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technical manual cmos 32 - bit single chip microcomputer s1c33e08
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requir - ing high level reliability, such as medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this mate - rial will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. the epson s1c33e08 incorporates mp3 technology of which thomson sa in france holds the patent. manufacturers using the epson s1c33e08 to develop mp3 products must pay royalties to thomson sa in order to procure the license for the mp3 technology. ? seiko epson corporation 2007, all rights reserved.
devices s1 c 33209 f 00e1 packing specifications 00 : besides tape & reel 0a : tcp bl 2 directions 0b : tape & reel back 0c : tcp br 2 directions 0d : tcp bt 2 directions 0e : tcp bd 2 directions 0f : tape & reel front 0g : tcp bt 4 directions 0h : tcp bd 4 directions 0j : tcp sl 2 directions 0k : tcp sr 2 directions 0l : tape & reel left 0m : tcp st 2 directions 0n : tcp sd 2 directions 0p : tcp st 4 directions 0q : tcp sd 4 directions 0r : tape & reel right 99 : specs not fixed specification package d: die form; f: qfp, b: bga model number model name c: microcomputer, digital products product classification s1: semiconductor development tools s5u1 c 33000 h2 1 packing specifications 00: standard packing version 1: version 1 tool type hx : ice dx : evaluation board ex : rom emulation board mx : emulation memory for external rom tx : a socket for mounting cx : compiler package sx : middleware package corresponding model number 33l01: for s1c33l01 tool classification c: microcomputer use product classification s5u1: development tool for semiconductor products 00 00 configuration of product number

i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock s1c33e08 technical manual i s1c33e08 specifications i.1 overvie w i.2 block diagra m i.3 pin d escriptio n i.4 power suppl y i.5 cpu core and bus architecture i.6 memory ma p i.7 electrical characteristic s i.8 basic external wiring diagra m i.9 precautions on mountin g ii bus modules ii.1 high-speed dma (hsdma ) ii.2 intelligent dma (idma ) ii.3 sram controller (sramc ) ii.4 sdram controller (sdramc ) iii peripheral modules 1 (system) iii.1 clock management unit (cmu) iii.2 interrupt controller (itc ) iii.3 real-time clock (rtc ) iii.4 misc registers iv peripheral modules 2 (timers) iv. 1 16 -bit timers (t16 ) iv. 2 watchdog timer (wdt ) v peripheral modules 3 (interface) v. 1 general-purpose serial interface (efsio ) v. 2 serial peripheral interface (spi) v. 3 direction control serial interface (dcsio) v. 4 card interface (card ) v. 5 i 2 s interface (i 2 s) vi peripheral modules 4 (ports) vi.1 general-purpose i/o ports (gpio ) vi.2 extended general-purpose i/o ports (egpio ) vii peripheral modules 5 (analog) vii.1 a/d converter (adc ) viii peripheral modules 6 (lcd) viii.1 lcd controller (lcdc) viii.2 ivram and ivram arbiter ix peripheral modules 7 (usb) ix.1 usb function controller (usb) x peripheral modules 8 (mp3) x.1 mp3 decoder (mp3) appendix a i/o map b differences between c 33 pe core and other c33 core c development tools d boot e summary of precautions f supplementary description for clock control

preface s1c33e08 technical manual epson i application this manual describes the hardware functions and control registers of the s 1c33e08 or seiko epson s risc-type 32 -bit microcomputer, and precautions to observe when designing the application system for the microcomputer. since this manual is written for those who design applications and circuits, knowledge of embedded-type micro - computers and the functionality and control of general peripheral circuits is required to understand the contents of this manual. organization of the manual i. s 1c33e08 specifications this chapter outlines the s 1c33e08 and describes the pin functions, and electrical characteristics. also noise protection and other precautions to be taken when mounting the chip on the circuit board are included. ii. bus module this chapter describes the modules to control dma and the bus. iiiCx peripheral modules these chapters describe each peripheral module embedded in the s 1c33e08. appendix provides a list of control registers built into the s 1c33e08 and other additional information. notational conventions for control bits and addresses this manual describes some control bits as follows: example: 16 -bit timer run/stop control bits prun x (d0/0x300786 + 8? x ) x in this example represents a timer number ( 0 to 5 ). timer 0 to timer 5 have control bits for each timer that have the same functions as other timers. this manual uses x to describe two or more control bits (or addresses) in a bit name (or an expression). therefore, x should be substituted with 0 to 5 in this example to obtain the actual bit names and addresses. timer 0 : prun0 (d0/0x300786) ? 0x300786 + 8 0 = 0x300786 timer 1 : prun1 (d0/0x30078e) ? 0x300786 + 8 1 = 0x30078e timer 2 : prun2 (d0/0x300796) ? 0x300786 + 8 2 = 0x300796 timer 3 : prun3 (d0/0x30079e) ? 0x300786 + 8 3 = 0x30079e timer 4 : prun4 (d0/0x3007a6) ? 0x300786 + 8 4 = 0x3007a6 timer 5 : prun5 (d0/0x3007ae) ? 0x300786 + 8 5 = 0x3007ae x is used for not only timer numbers, but also memory block numbers, a/d converter channel numbers and others.
contents ii epson s1c33e08 technical manual contents i s1c33e08 specification s i.1 overview ..................................................................................................................... i-1- 1 i.2 block diagram ........................................................................................................... i-2- 1 i.3 pin d escription .......................................................................................................... i-3- 1 i.3.1 pin arrangement .......................................................................................................... i-3- 1 i.3.1.1 qfp package pin arrangement (s1c33e08f00a) ....................................... i-3- 1 i.3.1.2 pfbga package pin arrangement (s1c33e08b00a) .................................. i-3- 2 i.3.2 pin functions ............................................................................................................... i-3- 3 i.3.3 switching over the multiplexed pin functions ............................................................. i-3- 9 i.3.3.1 pin function select bits ................................................................................. i-3- 9 i.3.3.2 list of port function select registers ........................................................... i-3-1 2 0x3003a0 : p00Cp03 port function select register (pp0_03_cfp) ....................................... i-3-1 3 0x3003a1 : p04Cp07 port function select register (pp0_47_cfp) ....................................... i-3-1 4 0x3003a2 : p10Cp13 port function select register (pp1_03_cfp) ....................................... i-3-1 5 0x3003a3 : p14Cp17 port function select register (pp1_47_cfp) ....................................... i-3-1 6 0x3003a4 : p20Cp23 port function select register (pp2_03_cfp) ....................................... i-3-1 7 0x3003a5 : p24Cp27 port function select register (pp2_47_cfp) ....................................... i-3-1 8 0x3003a6 : p30Cp33 port function select register (pp3_03_cfp) ....................................... i-3-1 9 0x3003a7 : p34Cp36 port function select register (pp3_46_cfp) ....................................... i-3-2 0 0x3003a8 : p40Cp43 port function select register (pp4_03_cfp) ....................................... i-3-2 1 0x3003a9 : p44Cp47 port function select register (pp4_47_cfp) ....................................... i-3-2 2 0x3003 aa: p50Cp53 port function select register (pp5_03_cfp) ....................................... i-3-2 3 0x3003 ab: p54Cp57 port function select register (pp5_47_cfp) ....................................... i-3-2 4 0x3003 ac: p60Cp63 port function select register (pp6_03_cfp) ...................................... i-3-2 5 0x3003 ad: p64Cp67 port function select register (pp6_47_cfp) ...................................... i-3-2 6 0x3003 ae: p70Cp73 port function select register (pp7_03_cfp) ....................................... i-3-2 7 0x3003 af: p74 port function select register (pp7_4_cfp) ................................................. i-3-2 8 0x3003b0 : p80Cp83 port function select register (pp8_03_cfp) ....................................... i-3-2 9 0x3003b1 : p84Cp85 port function select register (pp8_45_cfp) ....................................... i-3-3 0 0x3003b2 : p90Cp93 port function select register (pp9_03_cfp) ....................................... i-3-3 1 0x3003b3 : p94Cp97 port function select register (pp9_47_cfp) ....................................... i-3-3 2 0x300c20 : pa0 Cpa3 port function select register (ppa_03_cfp) ....................................... i-3-3 3 0x300c21 : pa4 port function select register (ppa_4_cfp) ................................................. i-3-3 4 0x300c22 : pb0Cpb3 port function select register (ppb_03_cfp) ...................................... i-3-3 5 0x300c24 : pc0Cpc3 port function select register (ppc_03_cfp) ..................................... i-3-3 6 0x300c25 : pc4Cpc7 port function select register (ppc_47_cfp) ..................................... i-3-3 7 i.3.4 input/output cells and input/output characteristics ................................................... i-3-3 8 i.3.5 package ...................................................................................................................... i-3-4 1 i.3.5.1 qfp24-144 pin package ................................................................................ i-3-4 1 i.3.5.2 pfbga-180 pin package ............................................................................... i-3-4 3 i.3.5.3 thermal resistance of the package ............................................................. i-3-4 5 i.3.6 pad layout .................................................................................................................. i-3-4 6 i.4 power supply ............................................................................................................. i-4- 1 i.4.1 power supply pins ....................................................................................................... i-4- 1 i.4.2 operating voltage (v dd , v ss ) ........................................................................................ i-4- 2 i.4.3 power supply for pll (plv dd , plv ss ) .......................................................................... i-4- 2 i.4.4 power supply for i/o interface (v ddh ) .......................................................................... i-4- 2 i.4.5 power supply for analog circuits (av dd ) ..................................................................... i-4- 2 i.4.6 precautions on power supply ...................................................................................... i-4- 3
contents s1c33e08 technical manual epson iii i.5 cpu core and bus architecture .............................................................................. i-5- 1 i.5.1 features of the c33 pe core ....................................................................................... i-5- 1 i.5.2 cpu registers ............................................................................................................. i-5- 2 i.5.3 instruction set .............................................................................................................. i-5- 3 i.5. 4 trap table ..................................................................................................................... i-5- 7 i.5. 5 power-down mode ....................................................................................................... i-5- 9 i.5.6 debug mode ................................................................................................................ i-5-1 0 i.5.7 bus architecture .......................................................................................................... i-5-1 1 i.5.7.1 32-bit high-speed bus .................................................................................. i-5-1 1 i.5.7.2 sapb bus ..................................................................................................... i-5-1 2 i.5.7.3 external bus ................................................................................................ i-5-1 2 i.5. 8 chip id ........................................................................................................................ i-5-1 3 i.6 memory map .............................................................................................................. i-6- 1 i.6.1 boot address and gate rom ..................................................................................... i-6- 3 i.6.2 area 0 (a0ram) ........................................................................................................... i-6- 3 i.6.3 area 1 (specific rom for firmware) ........................................................................... i-6- 4 i.6.4 area 2 (debug area) ................................................................................................... i-6- 4 i.6.5 area 3 (ivram) ............................................................................................................ i-6- 4 i.6.6 area 3 (dst ram) ....................................................................................................... i-6- 4 i.6.7 area 6 (i/o area) .......................................................................................................... i-6- 5 i.6.8 external memory areas .............................................................................................. i-6- 5 i.7 electrical characteristics .......................................................................................... i-7- 1 i.7.1 absolute maximum rating ........................................................................................... i-7- 1 i.7.2 recommended operating conditions .......................................................................... i-7- 1 i.7.3 dc characteristics ....................................................................................................... i-7- 2 i.7.4 current consumption ................................................................................................... i-7- 3 i.7.5 a/d converter characteristics ...................................................................................... i-7- 5 i.7.6 oscillation characteristics ............................................................................................ i-7- 6 i.7.7 pll characteristics ...................................................................................................... i-7- 7 i.7.8 ac characteristics ....................................................................................................... i-7- 8 i.7.8.1 symbol description ........................................................................................ i-7- 8 i.7.8.2 ac characteristics measurement condition .................................................. i-7- 8 i.7.8.3 sramc ac characteristic tables .................................................................. i-7- 9 i.7.8.4 sramc ac characteristic timing charts ..................................................... i-7-1 0 i.7.8.5 sdram interface ac characteristics ........................................................... i-7-1 1 i.7.8.6 lcdc ac characteristics ............................................................................. i-7-1 4 i.7.9 usb dc and ac characteristics ................................................................................. i-7-2 7 i.8 basic external wiring diagram ................................................................................ i-8- 1 i.9 precautions on mounting ......................................................................................... i-9- 1
contents iv epson s1c33e08 technical manual ii bus m odule s ii.1 high-speed dma (hsdma) ..................................................................................... ii-1- 1 ii.1.1 functional outline of hsdma ..................................................................................... ii-1- 1 ii.1.2 i/o pins of hsdma ..................................................................................................... ii-1- 5 ii.1.3 programming control information ............................................................................... ii-1- 6 ii.1.3.1 standard mode and advanced mode ........................................................... ii-1- 6 ii.1.3.2 sequential access time for idma and hsdma ........................................... ii-1- 7 ii.1.3.3 setting the registers in dual-address mode ................................................ ii-1- 8 ii.1.3.4 setting the registers in single-address mode ............................................ ii-1-1 1 ii.1.4 enabling/disabling dma transfer ............................................................................... ii-1-1 4 ii.1.5 trigger source ............................................................................................................ ii-1-1 5 ii.1.6 operation of hsdma ................................................................................................. ii-1-1 6 ii.1.6.1 operation in dual-address mode ................................................................ ii-1-1 6 ii.1.6.2 operation in single-address mode .............................................................. ii-1-2 0 ii.1.7 interrupt function of hsdma ..................................................................................... ii-1-2 4 ii.1.8 hsdma operating clock ............................................................................................ ii-1-2 5 ii.1.9 details of control registers ....................................................................................... ii-1-2 6 0x301120C0x301150 : hsdma ch. x transfer counter registers (phs x _cnt) ...................... ii-1-2 8 0x301122C0x301152 : hsdma ch. x control registers ........................................................... ii-1-2 9 0x301124C0x301154: hsdma ch. x low-order source address setup registers (phs x _sadr) ................................................................................. ii-1-3 0 0x301126C0x301156 : hsdma ch. x high-order source address setup registers ................ ii-1-3 1 0x301128C0x301158 : hsdma ch. x low-order destination address setup registers (phs x _dadr) ................................................................................. ii-1-3 3 0x30112aC0x30115 a: hsdma ch. x high-order destination address setup registers ........ ii-1-3 4 0x30112cC0x30115 c: hsdma ch. x enable registers (phs x _en) ....................................... ii-1-3 6 0x30112eC0x30115 e: hsdma ch. x trigger flag registers (phs x _tf) ................................ ii-1-3 7 0x301162C0x301192 : hsdma ch. x control registers (phs x _advmode) for adv mode .... ii-1-3 8 0x301164C0x301196 : hsdma ch. x source address setup registers (phs x _ad_sadr) for adv mode ................................................... ii-1-4 0 0x301168C0x30119 a: hsdma ch. x destination address setup registers (phs x _adv_dadr) for adv mode ................................................. ii-1-4 2 0x30119 c: hsdma std/adv mode select register (phs_cntlmode) ............................. ii-1-4 4 0x30119 e: dma sequential access time register (phs_acctime) .................................... ii-1-4 5 ii.1.10 precautions .............................................................................................................. ii-1-4 6 ii.2 intelligent dma (idma) ............................................................................................ ii-2- 1 ii.2.1 functional outline of idma ......................................................................................... ii-2- 1 ii.2.2 programming control information ............................................................................... ii-2- 3 ii.2.2.1 setting the base address ............................................................................. ii-2- 3 ii.2.2.2 control information ....................................................................................... ii-2- 3 ii.2.3 idma invocation .......................................................................................................... ii-2- 8 ii.2.4 operation of idma ..................................................................................................... ii-2-1 1 ii.2.4.1 single transfer mode ................................................................................... ii-2-1 1 ii.2.4.2 successive transfer mode ........................................................................... ii-2-1 2 ii.2.4.3 block transfer mode .................................................................................... ii-2-1 3 ii.2.4.4 cause-of-interrupt processing by trigger type ............................................ ii-2-1 4 ii.2.5 linking ........................................................................................................................ ii-2-1 5 ii.2.6 interrupt function of intelligent dma .......................................................................... ii-2-1 6 ii.2.7 details of control registers ....................................................................................... ii-2-1 7 0x301100 : idma base address register 0 (pidmabase) ..................................................... ii-2-1 8 0x301102 : idma base address register 1 ............................................................................. ii-2-1 8
contents s1c33e08 technical manual epson v 0x301104 : idma start register (pidma_start) ................................................................... ii-2-1 9 0x301105 : idma enable register (pidma_en) ...................................................................... ii-2-2 0 ii.2.8 precautions ................................................................................................................ ii-2-2 1 ii.3 sram controller (sramc) ..................................................................................... ii-3- 1 ii.3.1 overview of the sramc ............................................................................................. ii-3- 1 ii.3.2 sramc pins ............................................................................................................... ii-3- 2 ii.3.3 external memory area (areas 4, 5, 7 to 22) ............................................................... ii-3- 3 ii.3.3.1 chip enable signals ...................................................................................... ii-3- 4 ii.3.3.2 area condition settings ................................................................................ ii-3- 4 ii.3.4 connection of external devices and bus operation ................................................... ii-3- 7 ii.3.4.1 connecting external devices ....................................................................... ii-3- 7 ii.3.4.2 data configuration in memory ...................................................................... ii-3- 7 ii.3.4.3 external bus operation ................................................................................. ii-3- 8 ii.3.5 sramc operating clock and bus clock .................................................................... ii-3- 9 ii.3.5.1 operating clock of the sramc .................................................................... ii-3- 9 ii.3.5.2 generation of the bus clock ........................................................................ ii-3-1 0 ii.3.5.3 external output of the bus clock ................................................................. ii-3-1 0 ii.3.6 bus access timing chart ........................................................................................... ii-3-1 1 ii.3.6.1 sram read/write timings with no external #wait ................................... ii-3-1 1 ii.3.6.2 sram read/write timings with external #wait ......................................... ii-3-1 3 ii.3.6.3 sram read/write timings with #ce4/#ce11 setup time ......................... ii-3-1 4 ii.3.6.4 sram read timings with #ce9 output disable time ................................. ii-3-1 5 ii.3.7 control register details ............................................................................................. ii-3-1 6 0 x 301500 : bclk and setup time control register (psramc_bclk_setup ) ......................... ii-3-1 7 0x301504 : wait control register (psramc_swait) ............................................................. ii-3-1 8 0x301508 : device size setup register (psramc_slv_size) .............................................. ii-3-2 0 0x30150 c: device type set up register (psramc_a0_bsl ) ................................................. ii-3-2 1 0x301510 : area location set up register (psramc_ als ) ..................................................... ii-3-2 2 ii.3.8 precautions ................................................................................................................ ii-3-2 3 ii.4 sdram controller (sdramc) ................................................................................ ii-4- 1 ii.4.1 sd ram interface ........................................................................................................ ii-4- 1 ii.4.1.1 overview of the sdram interface ................................................................ ii-4- 1 ii.4.1.2 sdramc pins .............................................................................................. ii-4- 2 ii.4.1.3 configuration of sdram .............................................................................. ii-4- 3 ii.4.1.4 sdramc operating clock and sdram clock ............................................. ii-4- 8 ii.4.1.5 control and operation of sdram interface ................................................. ii-4-1 0 ii.4.2 instruction/data queue buffers .................................................................................. ii-4-1 8 ii.4.2.1 overview ...................................................................................................... ii-4-1 8 ii.4.2.2 iqb (instruction queue buffer) .................................................................... ii-4-1 8 ii.4.2.3 dqb (data queue buffer) ............................................................................ ii-4-1 9 ii.4.2.4 operations using iqb/dqb .......................................................................... ii-4-2 0 ii.4.3 bus arbiter ................................................................................................................. ii-4-2 1 ii.4.3.1 overview ...................................................................................................... ii-4-2 1 ii.4.3.2 controlling the bus arbiter ........................................................................... ii-4-2 1 ii.4.4 control register details ............................................................................................. ii-4-2 2 0x301600 : sdram initial register (psdramc_ini) .............................................................. ii-4-2 3 0x301604 : sdram configuration register (psdramc_ctl) ............................................... ii-4-2 5 0x301608 : sdram refresh register (psdramc_ref) ........................................................ ii-4-2 7 0x301610 : sdram application configuration register (psdramc_app) ............................ ii-4-2 9 ii.4.5 precautions ................................................................................................................ ii-4-3 1
contents vi epson s1c33e08 technical manual iii p eripheral modules 1 (system ) iii.1 clock management unit (cmu) ............................................................................. iii-1- 1 iii.1.1 overview of the cmu ................................................................................................ iii-1- 1 iii.1.2 reset input and initial reset ..................................................................................... iii-1- 2 iii.1.2.1 initial reset pin ........................................................................................... iii-1- 2 iii.1.2.2 initial reset status ..................................................................................... iii-1- 2 iii.1.2.3 power-on reset .......................................................................................... iii-1- 3 iii.1.2.4 precautions to be taken during initial reset ............................................... iii-1- 4 iii.1.3 nmi input .................................................................................................................. iii-1- 5 iii.1.4 selecting the system clock source .......................................................................... iii-1- 6 iii.1.5 controlling the oscillator circuit ................................................................................ iii-1- 7 iii.1.5.1 osc3 oscillator circuit ............................................................................... iii-1- 7 iii.1.5.2 setting the osc3 divider ............................................................................ iii-1- 8 iii.1.5.3 osc1 oscillator circuit ............................................................................... iii-1- 8 iii.1.6 controlling the pll ................................................................................................... iii-1-1 0 iii.1.6.1 on/off control of the pll .......................................................................... iii-1-1 0 iii.1.6.2 selecting the pll input clock ................................................................... iii-1-1 0 iii.1.6.3 setting the frequency multiplication rate ................................................. iii-1-1 1 iii.1.6.4 other pll settings .................................................................................... iii-1-1 2 iii.1.6.5 power supply for pll ................................................................................ iii-1-1 3 iii.1.7 control of the sscg ................................................................................................ iii-1-1 4 iii.1.7.1 turning the sscg on/off .......................................................................... iii-1-1 4 iii.1.7.2 setting ss modulation parameters ............................................................ iii-1-1 5 iii.1.8 setting the main system clock (mclk) ................................................................... iii-1-1 6 iii.1.9 controlling clock supply .......................................................................................... iii-1-1 7 iii.1.9.1 mclk clock supply to each module ......................................................... iii-1-1 7 iii.1.9.2 automatic clock control in halt mode ..................................................... iii-1-1 7 iii.1.9.3 clock supply to the lcdc ........................................................................ iii-1-1 8 iii.1.9.4 clock supply to the sdramc .................................................................. iii-1-1 9 iii.1.9.5 clock supply to the sramc ...................................................................... iii-1-1 9 iii.1.9.6 clock supply to the gpio .......................................................................... iii-1-2 0 iii.1.9.7 clock supply to the efsio ....................................................................... iii-1-2 0 iii.1.9.8 clock supply to the usb ........................................................................... iii-1-2 0 iii.1.9.9 clock supply to the rtc ........................................................................... iii-1-2 1 iii.1.10 setting the external clock output (cmu_clk) ..................................................... iii-1-2 2 iii.1.11 standby modes ...................................................................................................... iii-1-2 3 iii.1.11.1 halt mode .............................................................................................. iii-1-2 3 iii.1.11.2 sleep mode ........................................................................................... iii-1-2 3 iii.1.11.3 precautions .............................................................................................. iii-1-2 5 iii.1.12 clock setup procedure .......................................................................................... iii-1-2 6 iii.1.12.1 changing the clock source from osc3 to pll ....................................... iii-1-2 6 iii.1.12.2 changing the clock source from pll to osc3, then turning off the pll ..................................................................... iii-1-2 7 iii.1.12.3 changing the clock source from osc3 or pll to osc1, then turning off osc3 and pll ......................................................... iii-1-2 8 iii.1.12.4 changing the clock source from osc1 to osc3 ................................... iii-1-2 9 iii.1.12.5 changing the clock source from osc1 to pll ....................................... iii-1-3 0 iii.1.12.6 turning off osc3 during sleep ............................................................ iii-1-3 1 iii.1.12.7 sleep keeping oscillation on (without clock change) ......................... iii-1-3 2 iii.1.13 power-down control .............................................................................................. iii-1-3 3
contents s1c33e08 technical manual epson vii iii.1.14 details of control registers ................................................................................... iii-1-3 4 0x301b00 : gated clock control register 0 (pcmu_gatedclk0) ....................................... iii-1-3 5 0x301b04 : gated clock control register 1 (pcmu_gatedclk1) ....................................... iii-1-3 7 0x301b08 : system clock control register (pcmu_clkcntl) ............................................. iii-1-4 0 0x301b0 c: pll control register (pcmu_pll) ..................................................................... iii-1-4 4 0x301b10 : sscg macro control register (pcmu_sscg) ................................................... iii-1-4 6 0x301b14 : clock option register (pcmu_opt) .................................................................... iii-1-4 7 0x301b24 : clock control protect register (pcmu_protect) ............................................. iii-1-4 9 iii.1.15 precautions ............................................................................................................ iii-1-5 0 iii.2 interrupt controller (itc) ....................................................................................... iii-2- 1 iii.2.1 outline of interrupt functions .................................................................................... iii-2- 1 iii.2.1.1 maskable interrupts .................................................................................... iii-2- 1 iii.2.1.2 causes of interrupt and intelligent dma ..................................................... iii-2- 4 iii.2.1.3 nonmaskable interrupt (nmi) ..................................................................... iii-2- 4 iii.2.1.4 interrupt processing by the cpu ................................................................ iii-2- 4 iii.2.1.5 clearing standby mode by interrupts ......................................................... iii-2- 4 iii.2.2 trap table .................................................................................................................. iii-2- 6 iii.2.3 itc operating clock .................................................................................................. iii-2- 7 iii.2.4 control of maskable interrupts .................................................................................. iii-2- 8 iii.2.4.1 structure of the interrupt controller ............................................................ iii-2- 8 iii.2.4.2 processor status register (psr) ............................................................... iii-2- 8 iii.2.4.3 cause-of-interrupt flag and interrupt enable register ............................... iii-2- 9 iii.2.4.4 interrupt priority register and interrupt levels .......................................... iii-2-1 0 iii.2.5 idma invocation ....................................................................................................... iii-2-1 1 iii.2.6 hsdma invocation ................................................................................................... iii-2-1 3 iii.2.7 details of control registers ..................................................................................... iii-2-1 4 0x300260 : port input 0C1 interrupt priority register (pint_pp01l) ...................................... iii-2-1 6 0x300261 : port input 2C3 interrupt priority register (pint_pp23l) ...................................... iii-2-1 7 0x300262 : key input interrupt priority register (pint_pk01l) .............................................. iii-2-1 8 0x300263 : hsdma ch.0C1 interrupt priority register (pint_phsd01l) .............................. iii-2-1 9 0x300264 : hsdma ch.2C3 interrupt priority register (pint_phsd23l) .............................. iii-2-2 0 0x300265 : idma interrupt priority register (pint_pdm) ....................................................... iii-2-2 1 0x300266 : 16 -bit timer 0C1 interrupt priority register (pint_p16t01) ................................. iii-2-2 2 0x300267 : 16 -bit timer 2C3 interrupt priority register (pint_p16t23) ................................. iii-2-2 3 0x300268 : 16 -bit timer 4C5 interrupt priority register (pint_p16t45) ................................. iii-2-2 4 0x300269 : lcdc, serial i/f ch.0 interrupt priority register (pint_plcdc_psi00) ............. iii-2-2 5 0x30026 a: serial i/f ch.1 , a/d interrupt priority register (pint_psi01 _pad) ..................... iii-2-2 6 0x30026 b: rtc interrupt priority register (pint_prtc) ...................................................... iii-2-2 7 0x30026 c: port input 4C5 interrupt priority register (pint_pp45l) ...................................... iii-2-2 8 0x30026 d: port input 6C7 interrupt priority register (pint_pp67l) ...................................... iii-2-2 9 0x30026 e: serial i/f ch.2 , spi interrupt priority register (pint_psi02_pspi) .................... iii-2-3 0 0x300270 : key input, port input 0C3 interrupt enable register (pint_ek01_ep03) ............. iii-2-3 1 0x300271 : dma interrupt enable register (pint_edma) ..................................................... iii-2-3 2 0x300272 : 16 -bit timer 0C1 interrupt enable register (pint_e16t01) ................................. iii-2-3 3 0x300273 : 16 -bit timer 2C3 interrupt enable register (pint_e16t23) ................................. iii-2-3 4 0x300274 : 16 -bit timer 4C5 interrupt enable register (pint_e16t45) ................................. iii-2-3 5 0x300276 : serial i/f ch.0C1 interrupt enable register (pint_esif01) ................................. iii-2-3 6 0x300277 : port input 4C7 , rtc, a/d interrupt enable register (pint_ep47 _ertc_ead) .. iii-2-3 7 0x300278 : lcdc interrupt enable register (pint_elcdc) .................................................. iii-2-3 8 0x300279 : serial i/f ch.2 , spi interrupt enable register (pint_esif2_espi) ..................... iii-2-3 9 0x300280 : key input, port input 0C3 interrupt cause flag register (pint_fk01_fp03) ...... iii-2-4 0 0x300281 : dma interrupt cause flag register (pint_fdma) .............................................. iii-2-4 2 0x300282 : 16 -bit timer 0C1 interrupt cause flag register (pint_f16t01) .......................... iii-2-4 3 0x300283 : 16 -bit timer 2C3 interrupt cause flag register (pint_f16t23) .......................... iii-2-4 4
contents viii epson s1c33e08 technical manual 0x300284 : 16 -bit timer 4C5 interrupt cause flag register (pint_f16t45) .......................... iii-2-4 5 0x300286 : serial i/f ch.0C1 interrupt cause flag register (pint_fsif01) .......................... iii-2-4 6 0x300287 : port input 4C7 , rtc, a/d interrupt cause flag register (pint_fp47 _frtc_fad) ................................................................................ iii-2-4 7 0x300288 : lcdc interrupt cause flag register (pint_flcdc) ........................................... iii-2-4 8 0x300289 : serial i/f ch.2 , spi interrupt cause flag register (pint_fsif2_fspi) .............. iii-2-4 9 0x300290 : port input 0C3, hsdma ch.0C1, 16 -bit timer 0 idma request register (pidmareq_rp03_rhs_r16t0) .................................................................. iii-2-5 0 0x300291 : 16 -bit timer 1C4 idma request register (pidmareq_r16t14) ........................ iii-2-5 1 0x300292 : 16 -bit timer 5 , serial i/f ch.0 idma request register (pidmareq_r16t5_rsif0) ........................................................................... iii-2-5 2 0x300293 : serial i/f ch.1 , a/d, port input 4C7 idma request register (pidmareq_rsif1_rad_rp47) ................................................................... iii-2-5 3 0x300294 : port input 0C3, hsdma ch.0C1, 16 -bit timer 0 idma enable register (pidmaen_dep03_dehs_de16t0) .............................................................. iii-2-5 4 0x300295 : 16 -bit timer 1C4 idma enable register (pidmaen_de16t14) ........................... iii-2-5 5 0x300296 : 16 -bit timer 5 , serial i/f ch.0 idma enable register (pidmaen_de16t5_desif0) ......................................................................... iii-2-5 6 0x300297 : serial i/f ch.1 , a/d, port input 4C7 idma enable register (pidmaen_desif1_dead_dep47) ............................................................... iii-2-5 7 0x300298 : hsdma ch.0C1 trigger set-up register (phsdma_htgr1) .............................. iii-2-5 8 0x300299 : hsdma ch.2C3 trigger set-up register (phsdma_htgr2) .............................. iii-2-5 8 0x30029 a: hsdma software trigger register (phsdma_hsofttgr) ............................... iii-2-6 0 0x30029 b: lcdc, serial i/f ch.2, spi idma request register (pidmareq_rlcdc_rsif2_rspi) ............................................................... iii-2-6 1 0x30029 c: lcdc, serial i/f ch.2 , spi idma enable register (pidmaen_delcdc_desif2_despi) .......................................................... iii-2-6 2 0x30029 f: flag set/reset method select register (prst_reset) ..................................... iii-2-6 3 0x3002a0 : port input 8C9 interrupt priority register (pint_pp89l) ...................................... iii-2-6 4 0x3002a1 : port input 10C11 interrupt priority register (pint_pp1011l) .............................. iii-2-6 5 0x3002a2 : port input 12C13 interrupt priority register (pint_pp1213l) .............................. iii-2-6 6 0x3002a3 : port input 14C15 interrupt priority register (pint_pp1415l) .............................. iii-2-6 7 0x3002a4 : i 2 s interrupt priority register (pint_pi 2s) ........................................................... iii-2-6 8 0x3002a6 : port input 8C15 interrupt enable register (pint_ep815) .................................... iii-2-6 9 0x3002a7 : i 2 s interrupt enable register (pint_ei 2s) ........................................................... iii-2-7 0 0x3002a9 : port input 8C15 interrupt cause flag register (pint_fp815) ............................. iii-2-7 1 0x3002 aa: i 2 s interrupt cause flag register (pint_fi 2s) ................................................... iii-2-7 2 0x3002 ac: port input 8C15 idma request register (pidmareq_rp815) .......................... iii-2-7 3 0x3002 ad: i 2 s idma request register (pidmareq_ri2s) ................................................. iii-2-7 4 0x3002 ae: port input 8C15 idma enable register (pidmaen_dep815) ............................. iii-2-7 5 0x3002 af: i 2 s idma enable register (pidmaen_dei 2s) .................................................... iii-2-7 6 0x3003c4 : port input interrupt select register 3 (ppintsel_spt811) ............................... iii-2-7 7 iii.2.8 precautions .............................................................................................................. iii-2-7 8 iii.3 real-time clock (rtc) ........................................................................................... iii-3- 1 iii.3.1 overview of the rtc ................................................................................................. iii-3- 1 iii.3.2 rtc counters ........................................................................................................... iii-3- 2 iii.3.3 control of the rtc .................................................................................................... iii-3- 5 iii.3.3.1 controlling the operating clock .................................................................. iii-3- 5 iii.3.3.2 initial sequence of the rtc ........................................................................ iii-3- 6 iii.3.3.3 selecting 12/24-hour mode and setting the counters ................................ iii-3- 7 iii.3.3.4 starting, stopping, and resetting counters ............................................... iii-3- 7 iii.3.3.5 counter hold and busy flag ....................................................................... iii-3- 8 iii.3.3.6 reading from and writing to counters in operation ................................... iii-3- 9 iii.3.3.7 30-second correction ................................................................................. iii-3- 9 iii.3.4 rtc interrupts .......................................................................................................... iii-3-1 0
contents s1c33e08 technical manual epson ix iii.3.5 osc1 oscillator circuit ............................................................................................ iii-3-1 1 iii.3.5.1 input/output pins of the osc1 oscillator circuit ....................................... iii-3-1 1 iii.3.5.2 structure of the osc1 oscillator circuit .................................................... iii-3-1 1 iii.3.5.3 oscillation control ..................................................................................... iii-3-1 2 iii.3.6 details of control registers ..................................................................................... iii-3-1 3 0x301900 : rtc interrupt status register (prtcintstat) .................................................... iii-3-1 4 0x301904 : rtc interrupt mode register (prtcintmode) .................................................. iii-3-1 5 0x301908 : rtc control register (prtc_cntl0) ................................................................. iii-3-1 6 0x30190 c: rtc access control register (prtc_cntl1) .................................................... iii-3-1 8 0x301910 : rtc second register (prtcsec) ....................................................................... iii-3-1 9 0x301914 : rtc minute register (prtcmin) ......................................................................... iii-3-2 0 0x301918 : rtc hour register (prtchour) ........................................................................ iii-3-2 1 0x30191 c: rtc day register (prtcday) ............................................................................. iii-3-2 2 0x301920 : rtc month register (prtcmonth) ................................................................... iii-3-2 3 0x301924 : rtc year register (prtcyear) .......................................................................... iii-3-2 4 0x301928 : rtc days of week register (prtcdayweek) ................................................... iii-3-2 5 iii.3.7 precautions .............................................................................................................. iii-3-2 6 iii.4 misc registers ........................................................................................................ iii-4- 1 iii.4.1 rtc and usb wait control registers ....................................................................... iii-4- 1 iii.4.1.1 setting wait cycles for accessing the rtc ................................................ iii-4- 1 iii.4.1.2 settings for the usb ................................................................................... iii-4- 1 iii.4.2 debug port mux register ......................................................................................... iii-4- 2 iii.4.3 boot register ............................................................................................................ iii-4- 3 iii.4.4 pin control registers ................................................................................................ iii-4- 4 iii.4.4.1 pull-up control ............................................................................................ iii-4- 4 iii.4.4.2 driving bus signals low ............................................................................. iii-4- 4 iii.4.5 misc register operating clock .................................................................................. iii-4- 5 iii.4.6 details of control registers ...................................................................................... iii-4- 6 0x300010 : rtc wait control register (pmisc_rtcwt) ....................................................... iii-4- 7 0x300012 : usb wait control register (pmisc_usbwt) ....................................................... iii-4- 8 0x300014 : debug port mux register (pmisc_pmux) ........................................................... iii-4- 9 0x300016 : performance analyzer control register (pmisc_pac) ........................................ iii-4-1 0 0x300018 : boot register (pmisc_boot) .............................................................................. iii-4-1 1 0x30001 a: corom switch register (pmisc_corom) ........................................................ iii-4-1 2 0x300020 : misc protect register (pmisc_prot) ................................................................. iii-4-1 3 0x300c41 : bus signal low drive control register (pmisc_buslow) ................................ iii-4-1 4 0x300c42 : p0 pull-up control register (pmisc_pup0) ........................................................ iii-4-1 5 0x300c43 : p1 pull-up control register (pmisc_pup1) ........................................................ iii-4-1 6 0x300c44 : p2 pull-up control register (pmisc_pup2) ........................................................ iii-4-1 7 0x300c45 : p3 pull-up control register (pmisc_pup3) ........................................................ iii-4-1 8 0x300c46 : p4 pull-up control register (pmisc_pup4) ........................................................ iii-4-1 9 0x300c47 : p5 pull-up control register (pmisc_pup5) ........................................................ iii-4-2 0 0x300c48 : p6 pull-up control register (pmisc_pup6) ........................................................ iii-4-2 1 0x300c49 : p7 pull-up control register (pmisc_pup7) ........................................................ iii-4-2 2 0x300c4 a: p8 pull-up control register (pmisc_pup8) ....................................................... iii-4-2 3 0x300c4 b: p9 pull-up control register (pmisc_pup9) ....................................................... iii-4-2 4 0x300c4 c: pa pull-up control register (pmisc_pupa) ....................................................... iii-4-2 5 0x300c4 d: pb pull-up control register (pmisc_pupb) ...................................................... iii-4-2 6 iii.4.7 precautions .............................................................................................................. iii-4-2 7
contents x epson s1c33e08 technical manual iv peripheral m odules 2 (t imers ) iv. 1 16 -bit timers (t16) ................................................................................................. iv- 1- 1 iv. 1.1 configuration of 16 -bit timer ..................................................................................... iv- 1- 1 iv. 1.2 i/o pins of 16 -bit timers ............................................................................................ iv- 1- 3 iv. 1.3 uses of 16 -bit timers ................................................................................................ iv- 1- 4 iv. 1.4 16 -bit timer operating clock ..................................................................................... iv- 1- 5 iv. 1.5 control and operation of 16 -bit timer ....................................................................... iv- 1- 6 iv. 1.6 controlling clock output .......................................................................................... iv- 1-1 0 iv. 1.7 16 -bit timer interrupts and dma .............................................................................. iv- 1-1 3 iv. 1.8 details of control registers ..................................................................................... iv- 1-1 6 0x300780C0x3007a8 : 16 -bit timer x comparison data a setup registers (pt16_cr x a) .... iv- 1-1 7 0x300782C0x3007 aa: 16 -bit timer x comparison data b setup registers (pt16_cr x b) ... iv- 1-1 8 0x300784C0x3007 ac: 16 -bit timer x counter data registers (pt16_tc x ) ........................... iv- 1-1 9 0x300786C0x3007 ae: 16 -bit timer x control registers (pt16_ctl x ) .................................. iv- 1-2 0 0x3007d0C0x3007d4 : da16 ch. x registers (pda16_cr x a) ................................................ iv- 1-2 2 0x3007 dc: count pause register (pt16 _cnt_pause) ....................................................... iv- 1-2 3 0x3007 de: 16 -bit timer std/adv mode select register (pt16 _advmode) ....................... iv- 1-2 4 0x3007e0C0x3007ea: 16 -bit time r x clock control registers (pt16_clkctl _ x ) ............... iv- 1-2 5 iv. 1.9 precautions .............................................................................................................. iv- 1-2 6 iv. 2 watchdog timer (wdt) .......................................................................................... iv- 2- 1 iv. 2.1 configuration of the watchdog timer ....................................................................... iv- 2- 1 iv. 2.2 input/output pins of the watchdog timer ................................................................. iv- 2- 2 iv. 2.3 operating clock of the watchdog timer ................................................................... iv- 2- 3 iv. 2.4 control of the watchdog timer .................................................................................. iv- 2- 4 iv. 2.4.1 setting up the watchdog timer .................................................................. iv- 2- 4 iv. 2.4.2 starting/stopping the watchdog timer ...................................................... iv- 2- 5 iv. 2.4.3 resetting the watchdog timer ................................................................... iv- 2- 5 iv. 2.4.4 operation in standby mode ........................................................................ iv- 2- 5 iv. 2.4.5 clock output of the watchdog timer ......................................................... iv- 2- 6 iv. 2.4.6 external nmi output ................................................................................... iv- 2- 6 iv. 2.5 details of control registers ...................................................................................... iv- 2- 7 0x300660 : watchdog timer write-protect register (pwd_wp) ............................................. iv- 2- 8 0x300662 : watchdog timer enable register (pwd_en) ........................................................ iv- 2- 9 0x300664: watchdog timer comparison data setup register 0 (pwd_comp_low) ......... iv- 2-1 1 0x300666 : watchdog timer comparison data setup register 1 (pwd_comp_high) ........ iv- 2-1 1 0x300668 : watchdog timer count register 0 (pwd_cnt_low) ......................................... iv- 2-1 2 0x30066 a: watchdog timer count register 1 (pwd_cnt_high) ........................................ iv- 2-1 2 0x30066 c: watchdog timer control register (pwd_cntl) .................................................. iv- 2-1 3 iv. 2.6 precautions .............................................................................................................. iv- 2-1 4
contents s1c33e08 technical manual epson xi v peripheral m odules 3 ( i nterface ) v. 1 general-purpose serial interface ( efsio) ............................................................. v- 1- 1 v. 1.1 configuration of serial interfaces ................................................................................ v- 1- 1 v. 1.1.1 features of serial interfaces ......................................................................... v- 1- 1 v. 1.1.2 i/o pins of serial interface ............................................................................ v- 1- 2 v. 1.1.3 setting interface mode and transfer mode ................................................... v- 1- 3 v. 1.1.4 serial interface operating clock ................................................................... v- 1- 4 v. 1.1.5 standard mode and advanced mode ........................................................... v- 1- 5 v. 1.2 baud-rate timer (setting baud rate) ........................................................................ v- 1- 6 v. 1.3 clock-synchronized interface ..................................................................................... v- 1- 8 v. 1.3.1 outline of clock-synchronized interface ....................................................... v- 1- 8 v. 1.3.2 setting clock-synchronized interface ........................................................... v- 1- 9 v. 1.3.3 control and operation of clock-synchronized transfer ............................... v- 1-1 0 v. 1.4 asynchronous interface .............................................................................................. v- 1-1 7 v. 1.4.1 outline of asynchronous interface ............................................................... v- 1-1 7 v. 1.4.2 setting asynchronous interface ................................................................... v- 1-1 8 v. 1.4.3 control and operation of asynchronous transfer ........................................ v- 1-2 0 v. 1.5 irda interface ............................................................................................................. v- 1-2 5 v. 1.5.1 outline of irda interface ............................................................................... v- 1-2 5 v. 1.5.2 setting irda interface ................................................................................... v- 1-2 5 v. 1.5.3 control and operation of irda interface ....................................................... v- 1-2 7 v. 1.6 iso7816 interface (ch.1) ........................................................................................... v- 1-2 8 v. 1.6.1 outline of iso7816 interface ....................................................................... v- 1-2 8 v. 1.6.2 setting iso7816 interface ............................................................................ v- 1-2 9 v. 1.6.3 control and operation of iso7816 mode .................................................... v- 1-3 2 v. 1.7 serial interface interrupts and dma ........................................................................... v- 1-3 7 v. 1.8 details of control registers ....................................................................................... v- 1-4 0 0x300b00C0x300b20 : serial i/f ch. x transmit data registers ( pefsif x _txd) .................... v- 1-4 1 0x300b01C0x300b21 : serial i/f ch. x receive data registers ( pefsif x _rxd) .................... v- 1-4 2 0x300b02C0x300b22 : serial i/f ch. x status registers ( pefsif x _status) ......................... v- 1-4 3 0x300b03C0x300b23 : serial i/f ch. x control registers ( pefsif x _ctl) .............................. v- 1-4 5 0x300b04C0x300b24 : serial i/f ch. x irda registers ( pefsif x _irda) ................................. v- 1-4 7 0x300b05C0x300b25 : serial i/f ch. x baud-rate timer control registers ( pefsif x _brtrun) ....................................................................... v- 1-4 9 0x300b06C0x300b26 : serial i/f ch. x baud-rate timer reload data registers ( lsb) ( pefsif x _brtrdl) ........................................................................ v- 1-5 0 0x300b07 C0x300b27 : serial i/f ch. x baud-rate timer reload data registers ( msb) ( pefsif x _brtrdm) ....................................................................... v- 1-5 0 0x300b08 C0x300b28 : serial i/f ch. x baud-rate timer count data registers ( lsb) ( pefsif x _brtcdl) ........................................................................ v- 1-5 1 0x300b09 C0x300b29 : serial i/f ch. x baud-rate timer count data registers ( msb) ( pefsif x _brtcdm) ....................................................................... v- 1-5 1 0x300b1a : serial i/f ch.1 iso7816 mode control register (pefsif1_7816ctl) ................ v- 1-5 2 0x300b 1 b : serial i/f ch.1 iso7816 mode status register (pefsif1_7816 sta) .................. v- 1-5 4 0x300b 1 c : serial i/f ch.1 iso7816 mode fi/di ratio register ( lsb) (pefsif1 _fidil) ...... v- 1-5 5 0x300b 1 d : serial i/f ch.1 iso7816 mode fi/di ratio register ( msb) (pefsif1 _fidim) .... v- 1-5 5 0x300b 1 e : serial i/f ch.1 transmit time guard register (pefsif1 _ttgr) ......................... v- 1-5 7 0x300b 1 f : serial i/f ch.1 iso7816 mode output clock setup register (pefsif1 _clknum) ....................................................................... v- 1-5 8 0x300b4 f: serial i/f std/adv mode select register ( pefsif_adv) ................................... v- 1-5 9 v. 1.9 precautions ................................................................................................................ v- 1-6 0
contents xii epson s1c33e08 technical manual v. 2 serial peripheral interface (spi) ............................................................................. v- 2- 1 v. 2.1 outline of spi module ................................................................................................. v- 2- 1 v. 2.2 i/o pins of spi module ................................................................................................ v- 2- 2 v. 2.3 spi operating clock .................................................................................................... v- 2- 3 v. 2.4 setting spi module ..................................................................................................... v- 2- 4 v. 2.5 control of data transfer .............................................................................................. v- 2- 6 v. 2.6 spi interrupts and dma ............................................................................................. v- 2-1 0 v. 2.7 details of control registers ....................................................................................... v- 2-1 3 0x301700 : spi receive data register (pspi_rxd) ............................................................... v- 2-1 4 0x301704 : spi transmit data register (pspi_txd) ............................................................... v- 2-1 5 0x301708 : spi control register 1 (pspi_ctl1) ..................................................................... v- 2-1 6 0x30170c: spi control register 2 (pspi_ctl2) .................................................................... v- 2-1 8 0x301710 : spi wait register (pspi_wait) ............................................................................. v- 2-1 9 0x301714 : spi status register (pspi_stat) .......................................................................... v- 2-2 0 0x301718 : spi interrupt control register (pspi_int) ............................................................. v- 2-2 1 0x30171 c: spi receive data mask register (pspi_rxmk) .................................................. v- 2-2 3 v. 2.8 precautions ................................................................................................................ v- 2-2 4 v. 3 direction control serial interface (dcsio) ............................................................ v- 3- 1 v. 3.1 outline of dcsio ........................................................................................................ v- 3- 1 v. 3.2 i/o pins of dcsio ....................................................................................................... v- 3- 2 v. 3.3 dcsio operating clock .............................................................................................. v- 3- 3 v. 3.4 setting dcsio module ................................................................................................ v- 3- 4 v. 3.5 control of data transfer .............................................................................................. v- 3- 7 v. 3.6 dcsio interrupts and dma ........................................................................................ v- 3-1 1 v. 3.7 details of control registers ....................................................................................... v- 3-1 3 0x301800 : dcsio control register (pdcsio_ctl) ............................................................... v- 3-1 4 0x301804 : dcsio data load register (pdcsio_load) ....................................................... v- 3-1 5 0x301808 : dcsio receive data register (pdcsio_rcv) .................................................... v- 3-1 6 0x301814 : dcsio interrupt control register (pdcsio_int) ................................................. v- 3-1 7 0x301818 : dcsio status register (pdcsio_stat) ............................................................... v- 3-1 8 0x30181 c: dcsio port direction control register (pdcsio_dir) ........................................ v- 3-1 9 v. 3.8 precautions ................................................................................................................ v- 3-2 0 v. 4 card interface (card) ............................................................................................. v- 4- 1 v. 4.1 outline of the card interface ....................................................................................... v- 4- 1 v .4.2 card interface pins ...................................................................................................... v- 4- 2 v. 4.3 card area .................................................................................................................... v- 4- 3 v. 4.3.1 selecting the area ........................................................................................ v- 4- 3 v. 4.3.2 setting area access conditions .................................................................... v- 4- 3 v. 4.4 card interface control signals .................................................................................... v- 4- 4 v. 4.4.1 smartmedia interface ................................................................................... v- 4- 4 v. 4.4.2 compactflash interface ................................................................................ v- 4- 5 v. 4.4.3 pc card interface ......................................................................................... v- 4- 5 v. 4.5 card interface operating clock ................................................................................... v- 4- 7 v. 4.6 ecc generator ........................................................................................................... v- 4- 8 v. 4.7 details of control registers ....................................................................................... v- 4-1 1 0x300300 : card i/f area configuration register (pcardsetup) ......................................... v- 4-1 2 0x300302 : card i/f output port configuration register (pcardfuncsel05) ..................... v- 4-1 3 0x300310 : ecc trigger area select register (pecctrigsel) ............................................. v- 4-1 4 0x300311 : ecc reset/ready register (peccrstrdy) ........................................................ v- 4-1 5 0x300312 : ecc enable register (peccena) ........................................................................ v- 4-1 6 0x300313 : ecc mode register (peccmd) ............................................................................ v- 4-1 7
contents s1c33e08 technical manual epson xiii 0x300314 : area 0 ecc column parity data register (pecc0cp) ......................................... v- 4-1 8 0x300316 : area 0 ecc line parity register 0 (pecc0lpl) ................................................... v- 4-1 9 0x300317 : area 0 ecc line parity register 1 (pecc0lph) .................................................. v- 4-1 9 0x300318 : area 1 ecc column parity data register (pecc1cp) ......................................... v- 4-2 0 0x30031 a: area 1 ecc line parity register 0 (pecc1lpl) ................................................... v- 4-2 1 0x30031 b: area 1 ecc line parity register 1 (pecc1lph) .................................................. v- 4-2 1 v. 4.8 precautions ................................................................................................................ v- 4-2 2 v. 5 i 2 s interface ( i 2 s ) ...................................................................................................... v- 5- 1 v. 5.1 outline of i 2 s module .................................................................................................. v- 5- 1 v. 5.2 output pins of i 2 s module ........................................................................................... v- 5- 2 v. 5.3 i 2 s module operating clock ........................................................................................ v- 5- 3 v. 5.4 setting i 2 s module ...................................................................................................... v- 5- 4 v. 5.5 data output control .................................................................................................... v- 5- 9 v. 5.6 i 2 s interrupt ................................................................................................................ v- 5-1 1 v. 5.7 details of control registers ....................................................................................... v- 5-1 2 0x301c00 : i 2 s control register (pi2 s_control) ................................................................ v- 5-1 3 0x301c04 : i 2 s mclk divide ratio register (pi2 s_dv_mclk) .............................................. v- 5-1 6 0x301c08 : i 2 s audio clock divide ratio register (pi 2 s_dv_lrclk) .................................... v- 5-1 7 0x301c0 c: i 2 s start register (pi2 s_start) .......................................................................... v- 5-1 8 0x301c10 : i 2 s hsdma mode select register (pi2s_hsdmamd) ......................................... v- 5-1 9 0x301c14 : i 2 s fifo status register (pi2s_fifo_empty) ................................................... v- 5-2 0 0x301c20 : i 2 s fifo register (pi2s_fifo) ............................................................................. v- 5-2 1
contents xiv epson s1c33e08 technical manual vi peripheral m odules 4 ( port s ) vi.1 general-purpose i/o ports (gpio) ....................................................................... vi-1- 1 vi.1.1 structure of i/o port .................................................................................................. vi-1- 1 vi.1.2 selecting the i/o pin functions ................................................................................ vi-1- 1 vi.1.3 i/o control register and i/o modes ......................................................................... vi-1- 2 vi.1.4 input interrupt ........................................................................................................... vi-1- 3 vi.1.4.1 port input interrupt ..................................................................................... vi-1- 3 vi.1.4.2 key input interrupt ...................................................................................... vi-1- 5 vi.1.4.3 control registers of the interrupt controller ............................................... vi-1- 7 vi.1.5 i/o port operating clock ........................................................................................... vi-1- 9 vi.1.6 details of control registers ..................................................................................... vi-1-1 0 0x300380C0x300392 : p x port data registers (pp x _p x d) ..................................................... vi-1-1 1 0x30038 e: p7 port data register (pp7_p7d) ........................................................................ vi-1-1 2 0x300381C0x300393 : p x i/o control registers (pp x _ioc x ) ................................................. vi-1-1 3 0x3003a0C0x3003b3 : p x x port function select registers (pp x _ x x _cfp) ........................... vi-1-1 4 0x3003c0 : port input interrupt select register 1 (ppintsel_spt03) ................................. vi-1-1 5 0x3003c1 : port input interrupt select register 2 (ppintsel_spt47) ................................. vi-1-1 5 0x3003c4 : port input interrupt select register 3 (ppintsel_spt811) ............................... vi-1-1 5 0x3003c5 : port input interrupt select register 4 (ppintsel_spt1215) ............................. vi-1-1 5 0x3003c2: port input interrupt polarity select register 1 (ppintpol_spp07) .................... vi-1-1 7 0x3003c6 : port input interrupt polarity select register 2 (ppintpol_spp815) .................. vi-1-1 7 0x3003c3 : port input interrupt edge/level select register 1 (ppintel_sept07) ............... vi-1-1 8 0x3003c7 : port input interrupt edge/level select register 2 (ppintel_sept815) ............. vi-1-1 8 0x3003d0 : key input interrupt select register (pkintsel_sppk01) .................................. vi-1-1 9 0x3003d2 : key input interrupt (fpk 0 ) input comparison register (pkintcomp_scpk0) ... vi-1-2 0 0x3003d3 : key input interrupt (fpk 1 ) input comparison register (pkintcomp_scpk1) ... vi-1-2 0 0x3003d4 : key input interrupt (fpk0) input mask register (pkintcomp_smpk0) ............ vi-1-2 1 0x3003d5 : key input interrupt (fpk1) input mask register (pkintcomp_smpk1) ............ vi-1-2 1 vi.1.7 precautions .............................................................................................................. vi-1-2 2 vi.2 extended general-purpose i/o ports (egpio) ................................................... vi-2- 1 vi.2.1 structure of egpio port ........................................................................................... vi-2- 1 vi.2.2 selecting the i/o pin functions ................................................................................ vi-2- 1 vi.2.3 i/o control register and i/o modes ......................................................................... vi-2- 2 vi.2.4 egpio operating clock ............................................................................................ vi-2- 3 vi.2.5 details of control registers ...................................................................................... vi-2- 4 0x300c00C0x300c04 : p x i/o control registers (pp x _ioc ) ................................................... vi-2- 5 0x300c01C0x300c05 : p x port data registers (pp x _ data ) ................................................... vi-2- 6 0x300c20C0x300c25 : p x x port function select registers (pp x _cfp0/1 ) ............................. vi-2- 7
contents s1c33e08 technical manual epson xv vii peripheral m odules 5 ( analog ) vii.1 a/d converter (adc) ............................................................................................ vii-1- 1 vii.1.1 features and structure of a/d converter ................................................................ vii-1- 1 vii.1.2 input pins of a/d converter ..................................................................................... vii-1- 2 vii.1.3 a/d converter operating clock ............................................................................... vii-1- 3 vii.1.4 setting a/d converter .............................................................................................. vii-1- 4 vii.1.5 control and operation of a/d conversion ............................................................... vii-1- 9 vii.1.6 a/d converter interrupt and dma ........................................................................... vii-1-1 3 vii.1.7 details of control registers .................................................................................... vii-1-1 5 0x300520 : a/d clock control register (pad_clkctl) ......................................................... vii-1-1 6 0x300540 : a/d conversion result register (pad_add) ....................................................... vii-1-1 7 0x300542 : a/d trigger/channel select register (pad_trig_chnl) ................................... vii-1-1 8 0x300544 : a/d control/status register (pad_en_smpl_stat) .......................................... vii-1-2 0 0x300546 : a/d channel status flag register (pad_end) .................................................... vii-1-2 3 0x300548C0x300550 : a/d ch. x conversion result buffer registers (pad_ch x _buf) ........ vii-1-2 4 0x300558 : a/d upper limit value register (pad_upper) .................................................... vii-1-2 5 0x30055 a: a/d lower limit value register (pad_lower) ................................................... vii-1-2 6 0x30055 c: a/d conversion complete interrupt mask register (pad_ch04_intmask) ...... vii-1-2 7 0x30055 e: a/d converter mode select/internal status register (pad_advmode) ............. vii-1-2 8 vii.1.8 precautions ............................................................................................................. vii-1-2 9
contents xvi epson s1c33e08 technical manual viii peripheral m odules 6 ( lcd ) viii.1 lcd controller (lcdc) ...................................................................................... viii-1- 1 viii.1.1 overview ................................................................................................................ viii-1- 1 viii.1.2 block diagram ........................................................................................................ viii-1- 3 viii.1.3 output pins of the lcd controller ......................................................................... viii-1- 4 viii.1.4 system settings ..................................................................................................... viii-1- 6 viii.1.4.1 configuration of display data memory (vram) ...................................... viii-1- 6 viii.1.4.2 setting the lcdc clock ........................................................................... viii-1- 7 viii.1.5 setting the lcd panel ........................................................................................... viii-1- 9 viii.1.5.1 types of panels ....................................................................................... viii-1- 9 viii.1.5.2 stn panel timing parameters ............................................................... viii-1-1 0 viii.1.5.3 hr-tft panel timing parameters ......................................................... viii-1-1 2 viii.1.5.4 display modes ........................................................................................ viii-1-1 7 viii.1.5.5 look-up tables ....................................................................................... viii-1-2 0 viii.1.5.6 frame rates ........................................................................................... viii-1-2 6 viii.1.5.7 other settings ........................................................................................ viii-1-2 6 viii.1.6 display control ..................................................................................................... viii-1-2 7 viii.1.6.1 controlling lcd power up/down ........................................................... viii-1-2 7 viii.1.6.2 setting the display start address and line address offset ................... viii-1-2 8 viii.1.6.3 writing display data ............................................................................... viii-1-2 9 viii.1.6.4 inverting and blanking the display ......................................................... viii-1-2 9 viii.1.6.5 picture-in-picture plus ............................................................................ viii-1-2 9 viii.1.7 lcdc interrupt and dma ...................................................................................... viii-1-3 2 viii.1.8 power save ........................................................................................................... viii-1-3 4 viii.1.9 details of control registers .................................................................................. viii-1-3 5 0x301a00 : frame interrupt register (plcdc_int) .............................................................. viii-1-3 6 0x301a04 : status and power save configuration register (plcdc_ps) ............................. viii-1-3 7 0x301a10 : horizontal display register (plcdc_hd) ........................................................... viii-1-3 8 0x301a14 : vertical display register (plcdc_vd) ................................................................ viii-1-3 9 0x301a18 : mod rate register (plcdc_mr) ...................................................................... viii-1-4 0 0x301a20 : horizontal display start position register (plcdc_hdps) ................................ viii-1-4 1 0x301a24 : vertical display start position register (plcdc_vdps) .................................... viii-1-4 2 0x301a28 : fpline pulse setup register (plcdc_l) .......................................................... viii-1-4 3 0x301a2 c: fpframe pulse setup register (plcdc_f) .................................................... viii-1-4 4 0x301a30 : fpframe pulse offset register (plcdc_fo) .................................................. viii-1-4 5 0x301a40 : hr-tft special output register (plcdc_tso) ................................................ viii-1-4 6 0x301a44 : tft_ctl1 pulse register (plcdc_tc1) ........................................................... viii-1-4 7 0x301a48 : tft_ctl0 pulse register (plcdc_tc0) ........................................................... viii-1-4 8 0x301a4 c: tft_ctl2 register (plcdc_tc2) .................................................................... viii-1-4 9 0x301a60 : lcdc display mode register (plcdc_dmd) .................................................... viii-1-5 0 0x301a64 : iram select register (plcdc_iram) ................................................................ viii-1-5 3 0x301a70 : main window display start address register (plcdc_madd) ......................... viii-1-5 4 0x301a74 : main window line address offset register (plcdc_mladd) .......................... viii-1-5 5 0x301a80 : sub-window display start address register (plcdc_sadd) ............................ viii-1-5 6 0x301a88 : sub-window start position register (plcdc_ssp) ............................................ viii-1-5 7 0x301a8 c: sub-window end position register (plcdc_sep) ............................................. viii-1-5 8 0x301aa0 : look-up table data register 0 (plcdc_lut_03) .............................................. viii-1-5 9 0x301aa4 : look-up table data register 1 (plcdc_lut_47) .............................................. viii-1-6 0 0x301aa8 : look-up table data register 2 (plcdc_lut_8b) ............................................. viii-1-6 1 0x301 aac: look-up table data register 3 (plcdc_lut_cf) .......................................... viii-1-6 2 viii.1.10 precautions ......................................................................................................... viii-1-6 3
contents s1c33e08 technical manual epson xvii viii.2 ivram and ivram arbiter ................................................................................. viii-2- 1 viii.2.1 ivram ................................................................................................................... viii-2- 1 viii.2.2 ivram arbiter ........................................................................................................ viii-2- 2 viii.2.3 ivram arbiter operating clock ............................................................................. viii-2- 3 viii.2.4 details of the control register ............................................................................... viii-2- 4 0x301a64 : iram select register (plcdc_iram) ................................................................. viii-2- 4
contents xviii epson s1c33e08 technical manual ix peripheral m odules 7 ( usb ) ix.1 usb function controller (usb) ........................................................................... ix-1- 1 ix.1.1 outline of the usb function controller ..................................................................... ix-1- 1 ix.1.2 pins for the usb interface ........................................................................................ ix-1- 2 ix.1.3 usb operating clocks and dma registers .............................................................. ix-1- 3 ix.1.3. 1 controlling the usb clocks ........................................................................ ix-1- 3 ix.1.3. 2 setting the misc register ........................................................................... ix-1- 3 ix.1.3. 3 setting the itc and hsdma controllers .................................................... ix-1- 4 ix.1.4 functional description ............................................................................................. ix-1- 7 ix.1.4. 1 usb control ............................................................................................... ix-1- 8 ix.1.4. 2 fifo management .................................................................................... ix-1-2 5 ix.1.4. 3 port interface ............................................................................................. ix-1-2 8 ix.1.4. 4 snooze ...................................................................................................... ix-1-3 3 ix.1.5 registers .................................................................................................................. ix-1-3 4 ix.1.5.1 list of registers ......................................................................................... ix-1-3 4 ix.1.5.2 detailed description of registers .............................................................. ix-1-3 7 0x300900 : mainintstat (main interrupt status) ....................................................................... ix-1-3 7 0x 3009 01 : sie_intstat (sie interrupt status) ......................................................................... ix-1-3 8 0x 3009 02 : eprintstat (epr interrupt status) .......................................................................... ix-1-3 9 0x 3009 03 : dma_intstat (dma interrupt status) .................................................................... ix-1-4 0 0x 3009 04 : fifo_intstat (fifo interrupt status) .................................................................... ix-1-4 1 0x 3009 07 : ep0intstat (ep0 interrupt status) ......................................................................... ix-1-4 2 0x 3009 08 : epaintstat (epa interrupt status) ......................................................................... ix-1-4 3 0x 3009 09 : epbintstat (epb interrupt status) ......................................................................... ix-1-4 4 0x 30090a : epcintstat (epc interrupt status) ......................................................................... ix-1-4 5 0x 30090b : epdintstat (epd interrupt status) ........................................................................ ix-1-4 6 0x 3009 10 : mainintenb (main interrupt enable) ...................................................................... ix-1-4 7 0x 3009 11 : sie_intenb (sie interrupt enable) ........................................................................ ix-1-4 8 0x 3009 12 : eprintenb (epr interrupt enable) ......................................................................... ix-1-4 9 0x 3009 13 : dma_intenb (dma interrupt enable) ................................................................... ix-1-5 0 0x 3009 14 : fifo_intenb (fifo interrupt enable) ................................................................... ix-1-5 1 0x 3009 17 : ep0intenb (ep0 interrupt enable) ........................................................................ ix-1-5 2 0x 3009 18 : epaintenb (epa interrupt enable) ........................................................................ ix-1-5 3 0x 3009 19 : epbintenb (epb interrupt enable) ........................................................................ ix-1-5 4 0x 30091a : epcintenb (epc interrupt enable) ........................................................................ ix-1-5 5 0x 30091b : epdintenb (epd interrupt enable) ....................................................................... ix-1-5 6 0x 3009 20 : revisionnum (revision number) .......................................................................... ix-1-5 7 0x 3009 21 : usb_control (usb control) ................................................................................. ix-1-5 8 0x 3009 22 : usb_status (usb status) .................................................................................... ix-1-5 9 0x 3009 23 : xcvrcontrol (xcvr control) .................................................................................... ix-1-6 0 0x 3009 24 : usb_test (usb test) ............................................................................................ ix-1-6 1 0x 3009 25 : epncontrol (endpoint control) ............................................................................. ix-1-6 2 0x 3009 26 : eprfifo_clr (epr fifo clear) ............................................................................. ix-1-6 3 0x 30092 e: framenumber_h (frame number high) ............................................................ ix-1-6 4 0x 30092f : framenumber_l (frame number low) .............................................................. ix-1-6 5 0x 3009 30 C0x 3009 37 : ep0setup_0 (ep0 setup 0) Cep0setup_7 (ep0 setup 7 ) .................. ix-1-6 6 0x 3009 38 : usb_address (usb address) .............................................................................. ix-1-6 7 0x 3009 39 : ep0control (ep0 control) ..................................................................................... ix-1-6 8 0x 30093a : ep0controlin (ep0 control in) ............................................................................ ix-1-6 9 0x 30093b : ep0controlout (ep0 control out) .................................................................... ix-1-7 0 0x 30093f : ep0 maxsize (ep0 max packet size) ................................................................... ix-1-7 1 0x 3009 40 : epacontrol (epa control) ..................................................................................... ix-1-7 2 0x 3009 41 : epbcontrol (epb control) ..................................................................................... ix-1-7 3 0x 3009 42 : epccontrol (epc control) ..................................................................................... ix-1-7 4 0x 3009 43 : epdcontrol (epd control) ..................................................................................... ix-1-7 5 0x 3009 50 : epamaxsize_h (epa max packet size high) ..................................................... ix-1-7 6
contents s1c33e08 technical manual epson xix 0x 3009 51 : epamaxsize_l (epa max packet size low) ....................................................... ix-1-7 6 0x 3009 52 : epaconfig_0 (epa configuration 0) ..................................................................... ix-1-7 7 0x 3009 53 : epaconfig_1 (epa configuration 1) ..................................................................... ix-1-7 8 0x 3009 54 : epbmaxsize_h (epb max packet size high) ..................................................... ix-1-7 9 0x 3009 55 : epbmaxsize_l (epb max packet size low) ....................................................... ix-1-7 9 0x 3009 56 : epbconfig_0 (epb configuration 0) ..................................................................... ix-1-8 0 0x 3009 57 : epbconfig_1 (epb configuration 1) ..................................................................... ix-1-8 1 0x 3009 58 : epcmaxsize_h (epc max packet size high) ..................................................... ix-1-8 2 0x 3009 59 : epcmaxsize_l (epc max packet size low) ....................................................... ix-1-8 2 0x 30095a : epcconfig_0 (epc configuration 0) ..................................................................... ix-1-8 3 0x 30095b : epcconfig_1 (epc configuration 1) ..................................................................... ix-1-8 4 0x 30095c : epdmaxsize_h (epd max packet size high) .................................................... ix-1-8 5 0x 30095d : epdmaxsize_l (epd max packet size low) ...................................................... ix-1-8 5 0x 30095 e: epdconfig_0 (epd configuration 0) ..................................................................... ix-1-8 6 0x 30095f : epdconfig_1 (epd configuration 1) ..................................................................... ix-1-8 7 0x 3009 70 : epastartadrs_h (epa fifo start address high) ............................................... ix-1-8 8 0x 3009 71 : epastartadrs_l (epa fifo start address low) ................................................. ix-1-8 8 0x 3009 72 : epbstartadrs_h (epb fifo start address high) ............................................... ix-1-8 9 0x 3009 73 : epbstartadrs_l (epb fifo start address low) ................................................ ix-1-8 9 0x 3009 74 : epcstartadrs_h (epc fifo start address high) ............................................... ix-1-9 0 0x 3009 75 : epcstartadrs_l (epc fifo start address low) ................................................. ix-1-9 0 0x 3009 76 : epdstartadrs_h (epd fifo start address high) ............................................... ix-1-9 1 0x 3009 77 : epdstartadrs_l (epd fifo start address low) ................................................ ix-1-9 1 0x 3009 80 : cpu_joinrd (cpu join fifo read) .................................................................... ix-1-9 2 0x 3009 81 : cpu_joinwr (cpu join fifo write) .................................................................... ix-1-9 3 0x 3009 82 : enepnfifo_access (enable epn fifo access) ................................................. ix-1-9 4 0x 3009 83 : epnfifoforcpu (epn fifo for cpu) .................................................................. ix-1-9 5 0x 3009 84 : epnrdremain_h (epn fifo read remain high) ............................................. ix-1-9 6 0x 3009 85 : epnrdremain_l (epn fifo read remain low) ............................................... ix-1-9 6 0x 300986 : epnwrremain_h (epn fifo write remain high) ............................................. ix-1-9 7 0x 300987 : epnwrremain_l (epn fifo write remain low) ............................................... ix-1-9 7 0x 3009 88 : descadrs_h (descriptor address high) .............................................................. ix-1-9 8 0x 3009 89 : descadrs_l (descriptor address low) ............................................................... ix-1-9 8 0x 30098a : descsize_h (descriptor size high) .................................................................... ix-1-9 9 0x 30098b : descsize_l (descriptor size low) ..................................................................... ix-1-9 9 0x 30098f : descdoor (descriptor door) ................................................................................ ix-1-10 0 0x 3009 90 : dma_fifo_control (dma fifo control) ............................................................ ix-1-10 1 0x 3009 91 : dma_join (dma join fifo) ................................................................................ ix-1-10 2 0x 3009 92 : dma_control (dma control) ............................................................................... ix-1-10 3 0x 3009 94 : dma_config_0 (dma configuration 0) ................................................................ ix-1-10 4 0x 3009 95 : dma_config_1 (dma configuration 1) ................................................................ ix-1-10 5 0x 3009 97 : dma_latency (dma latency) ............................................................................. ix-1-10 6 0x 3009 98 : dma_remain_h (dma fifo remain high) ...................................................... ix-1-10 7 0x 3009 99 : dma_remain_l (dma fifo remain low) ....................................................... ix-1-10 7 0x 30099c : dma_count_hh (dma transfer byte counter high/high) .............................. ix-1-10 8 0x 30099d : dma_count_hl (dma transfer byte counter high/low) ................................ ix-1-10 8 0x 30099e : dma_count_lh (dma transfer byte counter low/high) ................................ ix-1-10 8 0x 30099f : dma_count_ll (dma transfer byte counter low/low) .................................. ix-1-10 8
contents xx epson s1c33e08 technical manual x peripheral m odules 8 ( mp3 ) x.1 mp3 decoder (mp3) ................................................................................................. x-1- 1 x.1.1 overview ..................................................................................................................... x-1- 1 x.1.2 composition of mp3 decoder system ........................................................................ x-1- 3 x.1.2.1 mp3 decoder bios ...................................................................................... x-1- 4 x.1.2.2 hardware resource requirements .............................................................. x-1- 5 x.1.3 usage of mp3 api functions ...................................................................................... x-1- 6 x.1.3.1 high-level mp3 api functions ..................................................................... x-1- 6 x.1.3.2 low-level mp3 api functions ..................................................................... x-1-1 1 x.1.4 mp3 format ............................................................................................................... x-1-1 2 x.1.4.1 mp3 file format .......................................................................................... x-1-1 2 x.1.4.2 mp3 bit stream format ............................................................................... x-1-1 3 x.1.5 details of mp3 decoder bios api ............................................................................ x-1-1 4 x.1.5.1 return values and event values ................................................................. x-1-1 4 x.1.5.2 c33mp3decopen open mp3 decoder ................................................... x-1-1 5 x.1.5.3 c33mp3decclose close mp3 decoder .................................................. x-1-1 8 x.1.5.4 c33mp3 decstart start playback ............................................................ x-1-1 9 x.1.5.5 c33mp3decstop stop playback ............................................................. x-1-2 1 x.1.5.6 c33mp3 decpause pause playback ........................................................ x-1-2 2 x.1.5.7 c33mp3decresume resume playback ................................................. x-1-2 3 x.1.5.8 c33mp3decresync resynchronization .................................................. x-1-2 4 x.1.5.9 transferdata (callback function) set mp3 data .................................... x-1-2 6 x.1.5.10 event (callback function) event handler ............................................. x-1-2 8 x.1.5.11 c33mp3calcstereoprocess stereo process ........................................ x-1-2 9 x.1.5.12 c33mp3calcstereoprocesslsf stereo process for lsf ..................... x-1-3 1 x.1.5.13 c33mp3calcantialias anti alias process ............................................. x-1-3 3 x.1.5.14 c33mp3calcidctlong inverse mdct calculation for long block ......... x-1-3 4 x.1.5.15 c33mp3 calcidctwindow window calculation ....................................... x-1-3 5 x.1.5.16 c33mp3 calcidctshort inverse mdct calculation for short block ........ x-1-3 6 x.1.5.17 c33mp3 calcsubbandsynthesisfdct fast-dct calculation ................. x-1-3 7 x.1.5.18 c33mp3 calcsubbandsynthesiswindow window calculation for sub-band synthesis .................................... x-1-3 8 x.1.5.19 c33mp3 calcsubbandsynthesiswindow2/4/8 window calculation for sub-band synthesis 2/4/8 ........................... x-1-3 9 x.1.6 performance .............................................................................................................. x-1-4 0 x.1.6.1 support formats .......................................................................................... x-1-4 0 x.1.6.2 cpu occupancy ratio ................................................................................ x-1-4 1
contents s1c33e08 technical manual epson xxi appendi x appendix a i/o map ..................................................................................................... ap-a- 1 0x300010C0x300020 misc register (1) .......................................................................... ap-a- 2 0x300260C0x3002 af interrupt controller ....................................................................... ap-a- 3 0x300300C0x30031b card interface .............................................................................. ap-a-1 1 0x300380C0x 3003d5 i/o ports ...................................................................................... ap-a-1 3 0x300520C0x 300 55e a/d converter .............................................................................. ap-a-2 4 0x300660C0x 300 66 c watchdog timer .......................................................................... ap-a-2 7 0x300780C0x3007ea 16- bit timer ................................................................................. ap-a-2 9 0x300900C0x30099f usb function controller .............................................................. ap-a-3 7 0x300b00C0x300b4f serial interface ............................................................................ ap-a-4 7 0x300c00C0x300c25 extended ports ............................................................................ ap-a-5 2 0x300c40C0x300c4d misc register (2) ......................................................................... ap-a-5 4 0x301100C0x301105 intelligent dma ............................................................................ ap-a-5 6 0x301120C0x30119e high -speed dma ........................................................................ ap-a-5 7 0x301500C0x301510 sram controller ......................................................................... ap-a-7 0 0x301600C0x301610 sdram controller ....................................................................... ap-a-7 1 0x301700C0x30171c spi ............................................................................................... ap-a-7 2 0x301800C0x30181c dcsio ......................................................................................... ap-a-7 3 0x301900C0x301928 real time clock .......................................................................... ap-a-7 4 0x301a00C0x301 aac lcd controller ............................................................................. ap-a-7 6 0x301b00C0x301b24 clock management unit .............................................................. ap-a-8 3 0x301c00C0x301c20 i 2 s interface ................................................................................. ap-a-8 7 appendix b differences between c 33 pe core and other c 33 core ......................... ap-b- 1 b .1 instructions .................................................................................................................. ap-b- 1 b .2 registers ...................................................................................................................... ap-b- 2 b .3 address space and other ........................................................................................... ap-b- 2 appendix c development tools ................................................................................. ap-c- 1 c. 1 major development tools ............................................................................................. ap-c- 1 c. 2 precautions on use of s5u1c33001c ........................................................................ ap-c- 2 appendix d boot ......................................................................................................... ap-d- 1 d. 1 boot mode .................................................................................................................. ap-d- 1 d. 2 nand flash boot ........................................................................................................ ap-d- 2 d. 2.1 configuration of nand flash boot system .................................................. ap-d- 2 d. 2.2 nand flash boot sequence ......................................................................... ap-d- 3 d. 2.3 nand flash data .......................................................................................... ap-d- 5 d. 3 nor flash/external rom boot ................................................................................... ap-d- 7 d. 3.1 configuration of nor flash/external rom boot system ............................. ap-d- 7 d. 3.2 nor flash/external rom boot sequence ................................................... ap-d- 7 d. 3.3 reset vector for nor flash/external rom boot .......................................... ap-d- 8 d. 4 spi-eeprom boot ...................................................................................................... ap-d- 9 d. 4.1 configuration of spi-eeprom boot system ................................................ ap-d- 9 d. 4.2 spi-eeprom boot sequence .................................................................... ap-d-1 0 d. 4.3 eeprom data ............................................................................................. ap-d-1 1 d. 5 pc rs232c boot ........................................................................................................ ap-d-1 2 d. 5.1 configuration of pc rs232c boot system ................................................. ap-d-1 2 d. 5.2 pc rs232c boot sequence ....................................................................... ap-d-1 3 d. 5.3 transfer data ................................................................................................ ap-d-1 4 d. 6 precautions ................................................................................................................. ap-d-1 5 appendix e summary of precautions ....................................................................... ap-e- 1 appendix f supplementary description for clock control .................................... ap-f- 1

i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 s1c33e08 technical manual i s1c33e08 specifications

i s1c33e08 specifications: overview s1c33e08 technical manual epson i-1-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.1 overview the s 1c33e08 is a high cost performance 32 -bit risc controller for specific applications that require an mp3 player, several general-purpose i/o ports, a powerful pwm timer/counter function, several serial interfaces includ - ing usb-fs device controller, an adc and a lcd display system, such as middle range electronic dictionaries and educational products with voice/music playback function. the s 1c33e08 consists of a 32 -bit risc cpu-core, an mp3 decoder supporting layer iii specifications, a generic dma controller, a usb-fs device controller, a pwm control timer/counter, several interfaces (sio including irda 1.0 and iso7816-3 protocol, spi, i 2 s and dcsio), an adc, ram/shared ivram and rtc implemented by epson soc design technology using 0.18 m mixed analog low cmos process. table i.1.1 product line model s1c33e08f00a ??? s1c33e08b00a ??? s1c33e08d00a ??? pa ck ag e qfp24-144pin pfbga-180pin die fo rm note : the epson s1c33e08 incorporates mp3 technology of which thomson sa in france holds the patent. manufacturers using the epson s1c33e08 to develop mp3 products must pay royalties to thomson sa in order to procure the license for the mp3 technology. the main functions and features of the s1c33e08 are outlined below. technology ? 0.18 m al-4 -layers mixed analog low power cmos process technology cpu ? epson original c33 pe 32 -bit risc cpu-core with amba bus optimized for soc ? max. 60 mhz operation ? internal 2-stage pipeline and 4 instruction queues ? instruction set: 128 instructions (16 -bit fixed length) ? basic instructions are compatible with the s1c33 32-bit risc cores. ? dual amba bus system for cpu and lcdc internal memories ? 8k-byte ram (1 k bytes are available when the mp3 decoder bios is used) ? 12 k-byte ivram (used as general-purpose ram, vram, or mp3 work area) ? 2k-byte dst ram (used as general-purpose ram or idma descriptor table ram) oscillator circuit / pll osc oscillator circuit ? crystal oscillation: 5 mhz min. to 48 mhz max. ? ceramic oscillation: 48 mhz, fixed ? external clock input: 5 mhz min. to 48 mhz max. ? a 48 mhz clock source with 0.25 % of accuracy should be connected for using the usb function. pll ? pll input frequency: 5 mhz min. to 50 mhz max. (osc3 1, 1/2, 1/3, ... 1/9, 1/10) ? pll output frequency: 20 mhz min. to 90 mhz max. ? multiplication rate: 1, 2, 4, 8, 10, 15 1 ? crystal oscillation: 32.768 khz typ. ? external clock input: 32.768 khz typ.
i s1c33e08 specifications: overview i-1-2 epson s1c33e08 technical manual high speed bus (hb) modules sramc (sram controller) ? 25-bit address lines and 8/16 -bit selectable data bus ? up to a 512m-byte (a[24:0 ]) address space is provided for each chip enable signal. ? max. 8 chip enable signals are available to connect external devices. ? programmable bus wait cycle (0 to 7 cycles) ? supports external wait signals. ? 4 gb physical address space is available. - the physical address space is divided into 23 areas: area 0 to area 22. - areas 0 to 4 and area 6 are system reserved. ? supports only little-endian access to each area. ? memory mapped i/o ? supports both a0 and bs (bus strobe) access type external devices. ? sram, rom, and flash rom direct access interfaces are built in. sdramc (sdram controller with sdram app and ahb local bus arbiter) ? supports sdram direct interface. ? supports only sdram devices with 16 -bit data bus. minimum configuration: 16m bits (2mb), 16-bit sdram 1 maximum configuration: 512m bits (64mb), 16-bit sdram 1 ? cas latency: 1, 2 or 3 programmable ? supports burst and single read/write. ? supports dqm (byte write) function. ? supports max. 4 sdram banks and bank active mode. ? incorporates a 12 -bit auto-refresh counter. ? intelligent self-refresh function for low power operation ? 2-stage 32 -bit data buffer and 8-stage 16-bit 2 -slot instruction buffer built-in ? supports up to 90 mhz sdram clock. - when the cpu clock is 48 mhz, the sdram clock can be set to 48 mhz. - when the cpu clock is 45 mhz, the sdram clock can be set to 90 mhz using the pll. ? arbitrates ownership of the external bus between the cpu, dmac, lcdc and sramc. dmac (direct memory access controller) ? 4 -ch. high speed hardware dma ? 128 -ch. intelligent dma (variable data transfer controller) with specific control table ivramarb (internal video ram arbiter) ? contains a 12kb sram (3,072 words 16 bits 2). ? arbitrates accesses from the lcdc and cpu. ? allows the cpu and lcdc to access ivram in minimum 2 cycles by 32-bit access. ? supports uma (unified memory access) for display. ? ivram is configurable as a 12 kb general-purpose ram in area 0 using a control register if it is not used as a video ram. peripheral bus (sapb) modules tcu (timer/counter unit with pwm outputs) ? 6-ch. 16-bit timer/counter ? supports pwm outputs with da16 (digital d/a) mode. ? contains a prescaler, which can divide the peripheral clock by 1 to 4,096 , to generate the operating clock for each channel. ? possible to invoke dma transfer. wdt (watchdog timer) ? 30 -bit watchdog timer to generate an nmi interrupt ? the watchdog timer overflow cycle (nmi interrupt cycle) is programmable. ? the watchdog timer overflow signal can be output outside the ic.
i s1c33e08 specifications: overview s1c33e08 technical manual epson i-1-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 adc (a/d converter) ? 5-ch. 10 -bit a/d converter ? upper/lower limit interrupt is available. ? each adc channel includes a data buffer. ? contains a prescaler, which can divide the peripheral clock by 2 to 256 , to generate the operating clock for adc. itc (interrupt controller) ? possible to invoke dma transfer ? dma controller interrupt: 5 types ? input interrupt: 18 types ? tcu interrupt: 12 types ? efsio interrupt: 9 types ? adc interrupt: 2 types ? rtc interrupt: 1 type ? spi interrupt: 3 types ? dcsio interrupt: 1 type ? usb interrupt: 2 types ? i 2 s interrupt: 1 type ? lcdc interrupt: 1 type gpio (general-purpose i/o ports) ? max. 82 ports in the qfp24-144pin model. * the s 1c33e08 gpio ports are shared with other peripheral function pins (efsio, pwm etc.). there - fore, the number of gpio ports depends on the peripheral functions used. usb (universal serial bus 2.0 compliant full-speed device controller) ? supports usb2.0 full speed (12m bps) mode. ? supports auto negotiation function. ? supports control, bulk, isochronous and interrupt transfers. ? supports 4 general-purpose end points and end point 0 (control). ? embedded 1k-byte programmable fifo ? supports 8 -bit local bus dma port. ? possible to invoke dma transfer. ? supports async. dma transfer. ? supports dma slave mode. ? fixed 48 mhz clock for usb-fs. ? supports snooze mode. rtc (real time clock) ? contains time counters (seconds, minutes, and hours) and calendar counters (days, days of the week, months, and year). ? bcd data can be read from and written to both counters. ? capable of controlling the starting and stopping of time clocks . ? 24-hour or 12-hour mode can be selected. ? a 30 -second correction function can be implemented in software. ? periodic interrupts are possible. card (serial input/output with direction control) ? provides smartmedia i/f signals (#smre, #smwe). ? provides 8- or 16 -bit nand flash i/f signals. ? ecc function is available when reading/writing from/to nand flash type devices. ? supports nand flash booting function. ? supports epson middleware fs33.
i s1c33e08 specifications: overview i-1-4 epson s1c33e08 technical manual efsio (extended serial interface with fifo buffer) ? 3 -ch. clock sync./async. serial interface ? contains fifo data buffers (4 receive data buffer and 2 transmit data buffer are available for each chan - nel). ? supports irda1.0 interface. ? contains a baud-rate generator (12-bit programmable timer). ? supports iso7816 mode (ch.1 only). - alternative msb or lsb - memory card interface compatible with iso 7816-3 t=0 & t=1 protocol - programmable baud-rate and guard-time generation - iso 7816 acknowledge and automatically repeat transmission ? possible to invoke dma transfer. spi (serial peripheral interface) ? 1 ch. spi that operates in either master or slave mode ? supports 1- to 32 -bit data transfer. ? data transfer timing (clock phase and polarity variations) is selectable from among 4 types. ? a 1 to 65,536 clocks of delay can be inserted between transfers. ? generates transmit data register empty and receive data register full interrupts. ? supports both mmc and sd-card capabilities. ? possible to invoke dma transfer. dcsio (direction control serial input/output port) ? 2-ch. input/output ports with a serial shifter ? input/output level detection to drive a state machine ? 1-wire or 2 -wire communication protocol is simulated with software. egpio (extended gpio) ? max. 17 configurable gpio ports are available in addition to the standard gpio ports. in die form, max. 91 ports are available. * the egpio ports are shared with other peripheral function pins. therefore, the number of egpio ports depends on the peripheral functions used. ? most ports have a pull-up resistor that can be enabled/disabled with the control register. ? possible to drive the ports low. cmu (extended clock management unit) ? controls clock supply to each peripheral module (static). ? manages reset and nmi inputs. ? switches the system clock source (mclk, sdram_clk, or rtc_clk). ? controls the mclk and rtc_clk oscillator circuits. ? turns on/off and controls frequency multiplication rate of the pll. ? controls clocks according to the standby mode (sleep and halt). ? controls divide ratios of the lcdc clock. ? manages the external bus clock. misc (misc. setting register) ? usb/rtc wait configuration registers ? debug port function select register ? boot mode configuration register i 2 s (inter-ic sound bus interface) ? supports universal audio i 2 s bus interface. ? operates as the master to generate the bit clock, word-select signal, data and master clock. ? generates the i 2 s interrupt signal. ? possible to invoke dma transfer.
i s1c33e08 specifications: overview s1c33e08 technical manual epson i-1-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 lcdc (stn/tft lcd controller with amba bus) vram: ? built-in a 12 kb ram usable as a display buffer or general-purpose ram (register selectable) ? supports the uma method allowing lcdc to access sdram (external vram) or ivram (internal vram). ? the external vram map (sdram) is configurable. ? the sub-window area can be located in ivram or external vram regardless of whether it contains the main window area or not. display support: ? 4- or 8 -bit monochrome lcd interface ? 4- or 8 -bit color lcd interface ? single-panel, single-drive passive displays ? 12 -bit generic hr-tft interface - 320 240 -dot sharp hr-tft panel, sii liquid tft panel, or some other tft panels ? typical resolutions - 320 240 (8 -bpp mode, external vram is required) bpp = bits per pixel - 320 240 (1-bpp mode) * note that the panel width must be a multiple of 16 bits per pixel. display modes: ? due to frame rate modulation, grayscale display is possible in up to 16 shades of gray when a mono - chrome passive lcd panel is used. - two-shade display in 1-bpp mode - four-shade display in 2-bpp mode - 16-shade display in 4-bpp mode ? a maximum of 64 k colors can be simultaneously displayed on a color passive lcd panel. - 256-color display in 8-bpp mode - 4k-color display in 12-bpp mode - 64k-color display in 16-bpp mode ? a maximum of 4096 colors can be simultaneously displayed on a tft panel. - two-color display in 1-bpp mode - four-color display in 2-bpp mode - 16-color display in 4-bpp mode - 256-color display in 8-bpp mode - 4k-color display in 12-bpp mode ? a look-up table, which consists of 6 bits 16 entries 3 colors, is provided. - in monochrome 1/2/4-bpp or color 8/12-bpp mode, the look-up table can be used or bypassed. - in color 1/2/4/16-bpp mode, the look-up table cannot be used (must be bypassed). display features: ? picture-in-picture plus (pip + ) picture-in-picture plus enables a secondary window (or sub-window) within the main display window. the sub-window may be positioned anywhere within the main window and is controlled through regis - ters. the sub-window retains the same color depth as the main window. the speed of generating a sub-window by hardware is faster than software. by using this pip + function, it can greatly speed the gui performance and cpu can have more performance to assign other processing. (e.g. voice etc.) ? 12 -bit generic hr-tft interface the 12 -bit generic hr-tft interface can support 320 240 sharp hr-tft panel, sii tft panel or some other tft panels. because the timing of fpfram, fpline, and tft_ctl 0C3 are not fixed for tft panels, they can be controlled by register setting. by different register settings, you can get your specified tft i/f signal timing. ? clock source the lcdc clock can be internally divided 48 mhz by 1 to 16 . the clock division register is located in cmu part.
i s1c33e08 specifications: overview i-1-6 epson s1c33e08 technical manual mp 3 decoder ? mp3 decoder bios provides mp3 decode and playback api functions. - main apis for playback: start playback, stop playback, pause playback, resume playback - main apis for decoding: stereo processing, anti alias processing, idct calculation, sub-band analysis ? sampling frequency: 32, 44.1, and 48 khz (mpeg1 audio layer-iii) 16, 22.05, and 24 khz (mpeg2 audio layer-iii lsf) * the higher the sampling frequency, the more the cpu occupancy rate during playback increases. the cpu clock frequency should be set as high as possible to perform parallel processing using the rtos, etc. ? bit-rate: 32 to 320 kbps (mpeg1 audio layer-iii, cbr/vbr/abr) 8 to 160 kbps (mpeg2 audio layer-iii lsf, cbr/vbr/abr) ? channel mode: stereo (joint stereo and dual channel) and monaural ? sound quality mode: high/middle/low * the sound quality mode affects the cpu occupancy rate. ? cpu occupancy rate: the cpu occupancy rate depends on the cpu clock frequency, sound quality mode, mp 3 data sampling frequency and bit-rate, however, the s1c33e08 is ca - pable of multitask operations under a real-time os such as the rtos even in mp 3 playback. example) when cpu clock = 48 mhz, sampling frequency = 44.1 khz and sound quality mode = middle, the mp 3 decode/playback processing occupies the cpu for about 18 ms in about 26 ms cycles (cpu occupancy rate: 70% or less). ? a built-in hardware mp3 accelerator * when using the mp 3 decoder bios (mp3 decoder module), a 7 kb internal ram area, 12 kb ivram, a 20 kb external ram area (min.), and a 40 -byte stack area are required. when using the mp3 calculation module only, a 40-byte stack area is required. operating voltage ? v dd (core): 1.70 to 1.90 v (typ. 1.8 v) when a ceramic resonator is used for the usb clock ? v dd (core): 1.65 to 1.95 v (typ. 1.8 v) when a crystal is used or an external clock is input ? plv dd : 1.65 to 1.95 v (typ. 1.8 v) ? v ddh (i/o): 2.70 to 3.60 v when the usb is not used (5-v tolerant i/o not supported) ? v ddh (i/o): 3.00 to 3.60 v (typ. 3.3 v) when the usb is used (5-v tolerant i/o not supported) operating frequency ? cpu: 60 mhz max. ? usb: 48 mhz fixed. ? sdramc: 90 mhz max. ? lcdc: 60 mhz max. ? other peripheral circuits: 60 mhz max. operating temperatures ? -40 to 85 c ( 0 to 70 c when a ceramic resonator is used for the usb clock)
i s1c33e08 specifications: overview s1c33e08 technical manual epson i-1-7 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 current consumption ? during sleep: 1.0 a typ. (operation clock = 48 mhz) ? during halt: 3.0 ma typ. (operation clock = 48 mhz) ? during execution: core 19.0 ma typ. (operation clock = 48 mhz) sramc 3.4 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) sdramc 5.4 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) dma 3.9 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) lcdc 5.3 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) usb 10.0 ma typ. (operation clock = 48 mhz, idle state with the clock supplied) adc 260.0 a typ. (idle state when adc is enabled) mp 3 decoder 8.0 ma typ. (when mp3 decoder is on playback) * by controlling the cpu clock through the clock-gear (cmu), c urrent consumption can be reduced. shipping form ? package: qfp24-144pin (16 mm 16 mm 1.0 mm and 0.4 mm pin pitch) pfbga- 180pin (12 mm 12 mm 1.2 mm and 0.8 mm ball pitch) ? die form: 168 pads with pad pitch 90 m
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i s1c33e08 specifications: block diagram s1c33e08 technical manual epson i-2-1 i block i.2 block diagram a0ram (ivram) (12kb) a0ram (8kb) area 0 specific ro m (mp3 decoder bios) a18m pll cmu sdramc register s sramc register s i 2 s dcsio lcdc register s rt c spi pe_e08_cpu (hardw are mp3 accelerator b uilt-in) lcdc area 1 area 6 ivram (12kb) ivram arbiter dqb dqb arbiter iqb dst ram (2kb) area 3 gate ro m (4 wo r ds) area 10 sdramc_ip mux exter nal memor y i/f a6dec (used as a ram or mp3 wo rk area) (the mp3 decoder bios requires a 20kb or more e xter nal ram area.) the mp3 decoder bios uses ivram (area 0) as an mp3 wo rk area. a6_x32 de vices dma gp register s tcu16 (6 ch.) wdt adc a6_x16 de vices gpio egpio efsio (3 ch.) itc card i/f misc register s usb a6_x8 de vices sd app1 < < < x32 < < cpu_ahb lcdc_ahb lcdc_amb a: master dma gp: master 2 s1c33pe_amb a: master 1 (used as a vram) sd app2 sdramc sramc (sapb bridge) hsdma idma dma gp registers dma gp external ram x32 x32 x32 x32 x32 x16 x16 x16 x32 figure i.2.1 s1c33e08 block diagram
i s1c33e08 specifications: block diagram i-2-2 epson s1c33e08 technical manual this page is blank.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3 pin description i.3.1 pin arrangement the s1c33e08 comes in a qfp24-144pin or pfbga-180pin plastic package. i.3.1.1 qfp package pin arrangement (s1c33e08f00a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 (p55/card0) #ce9 (p46/tft_ctl2) a18 (p45/fpdat11) a19 (p44/fpdat10) a20 (p43/fpdat9) a21 (p42/fpdat8) a22 v ss (card2/#dmareq0) p30 (card3/#dmareq1) p31 (card4/#dmareq2) p32 (card5/#dmareq3) p33 (sin0/#dmaack2) p00 (sout0/#dmaack3) p01 (#sclk0/#dmaend2) p02 (#srdy0/#dmaend3) p03 v ddh (sin1/i2s_sdo) p04 (sout1/i2s_ws) p05 (#sclk1/i2s_sck) p06 (#srdy1/i2s_mclk) p07 (tm0/sin0/#dmaend0) p10 (tm1/sout0/#dmaend1) p11 v dd (tm2/#sclk0/#dmaack0) p12 (tm3/#srdy0/#dmaack1) p13 (tm4/sin1) p14 (p15/tm5/sout1/tft_ctl0) dst0 (p16/dcsio0/#sclk1/tft_ctl3) dst1 (p17/dcsio1/#srdy1/tft_ctl2) dpco v ddh (p34) dsio (p36) dst2 (p35) dclk (#wait/excl2) p64 (sdi/fpdat8) p65 (sdo/fpdat9) p66 p25 (#sdwe) p24 (#sdcas) p23 (#sdras/tft_ctl1) v ddh p22 (#sdcs) sdclk (p21) p20 (sdcke) v ss d15 d14 d13 d12 v dd d11 d10 d9 d8 v ddh d7 d6 d5 d4 v dd d3 d2 d1 d0 v ss p63 (#srdy2/wdt_clk/#wdt_nmi) p62 (#sclk2/#adtrg/cmu_clk) p61 (sout2/dcsio1/excl1) p60 (sin2/dcsio0/excl0) usbvbus usbdp usbdm #nmi 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 #reset p97 (fpdat7) p96 (fpdat6) p95 (fpdat5) p94 (fpdat4) v ddh p93 (fpdat3) p92 (fpdat2) p91 (fpdat1) p90 (fpdat0) v ss mclko mclki v dd p85 (dcsio1) p84 (dcsio0/fpdat11) p83 (fpdrdy/tft_ctl1/bclk) p82 (fpshift) p81 (fpline) p80 (fpframe) p70 (ain0) p71 (ain1) p72 (ain2) p73 (ain3) p74 (ain4/excl5) av dd boot1 test0 plv dd vcp plv ss v ss rtc_clko rtc_clki v dd p67 (spi_clk/fpdat10) (dqml) p26 (dqmh) p27 a14 a15 a16 / dqml a17 / dqmh (p53/sda10) #ce7 a0 / #bsl v ss a1 a2 a3 a4 a5 v dd a6 a7 a8 a9 v ddh a10 (p47) a11 a12 a13 (p41/#sdras/excl3) a23 (p40/#sdcas/excl4) a24 v ss (p57) #ce10 #rd #wrl #wrh / #bsh (p56) #ce11 (bclk/#ce6/cmu_clk) p52 (p50/card0) #ce4 (p51/card1) #ce5 (p54/card1) #ce8 figure i.3.1.1.1 pin arrangement (qfp24-144pin)
i s1c33e08 specifications: pin description i-3-2 epson s1c33e08 technical manual i.3.1.2 pfbga package pin arrangement (s1c33e08b00a) top view bottom view a1 corner a1 corner index a b c d e f g h j j l m n p a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1 n.c. a18 p46 tft_ctl2 a22 p42 fpd at 8 p30 card2 #dmareq0 p33 card5 #dmareq3 p03 #srd y0 #dmaend3 p06 #sclk1 i2s_sck p10 tm0 sin0 #dmaend0 dst0 p15 tm5 sout1 tft_ctl0 dsio p34 dclk p35 pb3 fpd a t11 i2s_mclk card5 p67 spi_clk fpd a t10 n.c . a b c d e f g h j k l m n p a b c d e f g h j k l m n p 1 1 #ce8 p54 card1 #ce9 p55 card0 a20 p44 fpd a t10 a19 p45 fpd a t11 p00 sin0 #dmaa ck2 p01 sout0 #dmaa ck3 p04 sin1 i2s_sdo p11 tm1 sout0 #dmaend1 p13 tm3 #srd y0 #dmaa ck1 dpco p17 dcsio1 #srd y1 tft_ctl2 pb0 fpd at 8 i2s_sdo card2 p65 sdi fpd at 8 r tc_clki #ce4 p50 card0 #ce5 p51 card1 a21 p43 fpd at 9 p31 card3 #dmareq1 p02 #sclk0 #dmaend2 p05 sout1 i2s_ws p07 #srd y1 i2s_mclk p14 tm4 sin1 dst1 p16 dcsio0 #sclk1 tft_ctl3 p64 #w ait excl2 pb2 fpd a t10 i2s_sck card4 p66 sdo fpd at 9 r tc_clk o #ce11 p56 #wrh/ #bsh p52 bclk #ce6 cmu_clk p32 card4 #dmareq2 p12 tm2 #sclk0 #dmaa ck0 dst2 p36 pb1 fpd at 9 i2s_ws card3 test0 vcp #rd a23 p41 #sdras excl3 a11 p47 a8 a4 #ce10 p57 #wrl boot1 p73 ain3 p74 ain4 excl5 p24 #sdcas p22 #sdcs sdclk p21 d15 d8 d6 d4 d1 p63 #srd y2 wdt_clk #wdt_nmi usbvbus usbdp usbdm a13 a24 p40 #sdcas excl4 p81 fpline p71 ain1 p70 ain0 a10 a12 p82 fpshift p83 fpdrd y tft_ctl1 bclk p72 ain2 p80 fpframe a6 a9 p84 dcsio0 fpd a t11 p85 dcsio1 mclki a2 a3 a7 burnin mclko p26 dqml p25 #sd we p23 #sdras tft_ctl1 p20 sdcke d12 d9 d7 d3 d0 boot0 p60 sin2 dcsio0 excl0 #nmi #reset pa 4 fpd a t11 tft_ctl3 card1 a14 p27 dqmh d14 d13 d10 d11 d5 d2 p62 #sclk2 #adtrg cmu_clk p61 sout2 dcsio1 excl1 pa 2 fpd at 9 tft_ctl1 p97 fpd at 7 p96 fpd at 6 pa 3 fpd a t10 tft_ctl2 card0 a15 a0/ #bsl a16/ dqml p91 fpd at 1 p94 fpd at 4 pa 1 fpd at 8 tft_ctl0 pa 0 tft_ctl0 #ce7 p53 sd a10 a17/ dqmh a1 a5 p90 fpd at 0 p93 fpd at 3 p95 fpd at 5 p92 fpd at 2 2 3 4 5 6 7 8 9 10 plv dd 11 12 plv ss 13 n.c. v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh av dd n.c. 14 2 3 4 5 6 7 8 t op vie w 9 1 0 1 1 1 2 1 3 1 4 v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd v ss v ss v ss v ss v ss v ss v ss figure i.3.1.2.1 pin arrangement (pfbga-180pin)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.2 pin functions tables i. 3.2.1 to i.3.2.6 list the function of each pin on the s1c33e08. table i.3.2.1 power supply pin list function po wer supply (+) f or core (1.8 v) po wer supply (+) f or i/o (3.3 v) po wer supply (C); gnd po wer supply (+) f or pll (pl v dd = v dd ) po wer supply (C) f or pll (pl v ss = v ss ) po wer supply (+) f or analog system and ain0Cain4 (3.3 v, av dd = v ddh ) qfp 23,38,59,86,96,123 16,30,67,91,105,128 7,41,62,81,101,117,135 44 42 47 pin no. pin name v dd v ddh v ss pl v dd pl v ss av dd pfbga d7,e6,e7,f10,f11,g4, g11,h4,h5,k7,n2,n8 d8,e8,e9,f4,f5,g5,g10, h10,h11,k8,k9,l9 d4,d5,d6,d11,e5,e10, e11,j5,j10,j11,k5,k6, k10,k11,n3,n9 p5 p4 p6 table i.3.2.2 clock pin list i/o i o i o o pull- up/do wn C C C C C function high speed (osc3) oscillation input (cr ystal/ceramic oscillator or e xter nal cloc k input with v dd le v el) high speed (osc3) oscillation output real time cloc k (osc1) oscillation input (cr ystal/ceramic oscillator or e xter nal cloc k input with v dd le v el) real time cloc k (osc1) oscillation output pll analog monitor (used f or current monitor) qfp 60 61 39 40 43 pin no. pin name mclki mclk o r tc_clki r tc_clk o vcp pfbga p8 p9 p2 p3 n4 table i.3.2.3 external bus pin list i/o i /o i /o i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) i/ o (l) pull- up/do wn ? 2 ? 2 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function data b us (d7Cd0) d[15:8]: data b us (d15Cd8) pc[7:0]: extended general-pur pose i/o por ts address b us (a0) or b us strobe (lo w b yte) signal address b us (a10Ca1) a11: address b us (a11) (def ault) p47: general-pur pose i/o por t address b us (a15Ca12) address b us (a16) or sdram data (lo w b yte) input/output mask signal output address b us (a17) or sdram data (high b yte) input/output mask signal output a18: address b us (a18) (def ault) p46: general-pur pose i/o por t tft_ctl2: lcdc tft i/f control signal 2 output a19: address b us (a19) (def ault) p45: general-pur pose i/o por t fpd a t11: lcd data a20: address b us (a20) (def ault) p44: general-pur pose i/o por t fpd a t10: lcd data a21: address b us (a21) (def ault) p43: general-pur pose i/o por t fpd a t9: lcd data qfp 90C87, 85C82 100C97, 95C92 116 129, 127C124, 122C118 130 112,111, 132,131 113 114 2 3 4 5 pin no. pin name d[7:0] d[15:8] pc[7:0] a0 / #bsl a[10:1] a11 p47 a[15:12] a16 / dqml a17 / dqmh a18 p46 tft_ctl2 a19 p45 fpd a t11 a20 p44 fpd a t10 a21 p43 fpd at 9 pfbga g13,g14, g12,h14, h13,h12, j14,j13 e14,c12, d12,e13, f12,e12, f13,f14 b11 b7,c8, a8,d9, b8,d10, a9,c9, b9,c10 a7 a11,a12, b6,c7 c11 b10 b1 d2 c2 c3
i s1c33e08 specifications: pin description i-3-4 epson s1c33e08 technical manual i/o i/ o (h) i/ o (h) i/ o ( l) o o o ? 3 i/ o (h) i/ o (h) i /o (pu) i/ o (h) i/ o (h) i/ o (h) i/ o (h) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) pull- up/do wn 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function a22: address b us (a22) (def ault) p42: general-pur pose i/o por t fpd a t8: lcd data a23: address b us (a23) (def ault) p41: general-pur pose i/o por t #sdras: sdram ro w address strobe signal output excl3: 16-bit timer 3 ev ent counter input a24: address b us (a24) (def ault) p40: general-pur pose i/o por t #sdcas: sdram column address strobe signal output excl4: 16-bit timer 4 ev ent counter input read signal wr ite (lo w b yte) signal wr ite (high b yte) signal or b us strobe (high b yte) signal #ce10: chip enab le signal f or areas 10, 13 and 20 (def ault) p57: general-pur pose i/o por t #ce4: chip enab le signal f or areas 4 and 14 (def ault) p50: general-pur pose i/o por t card0: card i/f signal 0 output #ce5: chip enab le signal f or areas 5, 15 and 16 (def ault) p51: general-pur pose i/o por t card1: card i/f signal 1 output p52: general-pur pose i/o por t (def ault) bclk: bus cloc k output #ce6: chip enab le signal f or areas 6, 17 and 18 cmu_clk: cmu e xter nal cloc k output #ce7: chip enab le signal f or areas 7 and 19 (def ault) p53: general-pur pose i/o por t sd a10: sdram address bit 10 #ce8: chip enab le signal f or areas 8 and 21 (def ault) p54: general-pur pose i/o por t card1: card i/f signal 1 output #ce9: chip enab le signal f or areas 9 and 22 (def ault) p55: general-pur pose i/o por t card0: card i/f signal 0 output #ce11: chip enab le signal f or areas 11 and 12 (def ault) p56: general-pur pose i/o por t p20: general-pur pose i/o por t (def ault) sdcke: sdram cloc k enab le signal output sdclk: sdram cloc k output (def ault) p21: general-pur pose i/o por t p22: general-pur pose i/o por t (def ault) #sdcs: sdram chip enab le signal output p23: general-pur pose i/o por t (def ault) #sdras: sdram ro w address strobe signal output tft_ctl1: lcdc tft i/f control signal 1 output p24: general-pur pose i/o por t (def ault) #sdcas: sdram column address strobe signal output p25: general-pur pose i/o por t (def ault) #sd we: sdram wr ite signal output p26: general-pur pose i/o por t (def ault) dqml: sdram data (lo w b yte) input/output mask signal output p27: general-pur pose i/o por t (def ault) dqmh: sdram data (high b yte) input/output mask signal output qfp 6 133 134 137 138 139 136 142 143 141 115 144 1 140 102 103 104 106 107 108 109 110 pin no. pin name a22 p42 fpd at 8 a23 p41 #sdras excl3 a24 p40 #sdcas excl4 #rd #wrl #wrh / #bsh #ce10 p57 #ce4 p50 card0 #ce5 p51 card1 p52 bclk #ce6 cmu_clk #ce7 p53 sd a10 #ce8 p54 card1 #ce9 p55 card0 #ce11 p56 p20 sdcke sdclk p21 p22 #sdcs p23 #sdras tft_ctl1 p24 #sdcas p25 #sd we p26 dqml p27 dqmh pfbga c1 a6 c6 a5 c5 b4 b5 a3 b3 c4 a10 a2 b2 a4 d13 d14 c14 c13 b14 b13 a13 b12
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 table i.3.2.4 input/output port and peripheral circuit pin list i/o i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i/ o (h) i/ o (h) i/ o (h) i /o (hi-z) i /o (hi-z) i /o (hi-z) pull- up/do wn 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function p00: general-pur pose i/o por t (def ault) sin0: ser ial i/f ch.0 data input #dmaa ck2: hsdma ch.2 ac kno wledge signal output p01: general-pur pose i/o por t (def ault) sout0: ser ial i/f ch.0 data output #dmaa ck3: hsdma ch.3 ac kno wledge signal output p02: general-pur pose i/o por t (def ault) #sclk0: ser ial i/f ch.0 cloc k input/output #dmaend2: hsdma ch.2 end-of-transf er signal output p03: general-pur pose i/o por t (def ault) #srd y0: ser ial i/f ch.0 ready input/output #dmaend3: hsdma ch.3 end-of-transf er signal output p04: general-pur pose i/o por t (def ault) sin1: ser ial i/f ch.1 data input i2s_sdo: i 2 s send data signal p05: general-pur pose i/o por t (def ault) sout1: ser ial i/f ch.1 data output i2s_ws: i 2 s word select signal p06: general-pur pose i/o por t (def ault) #sclk1: ser ial i/f ch.1 cloc k input/output i2s_sck: i 2 s ser ial cloc k signal p07: general-pur pose i/o por t (def ault) #srd y1: ser ial i/f ch.1 ready input/output i2s_mclk: i 2 s master cloc k signal p10: general-pur pose i/o por t (def ault) tm0: 16-bit timer 0 output sin0: ser ial i/f ch.0 data input #dmaend0: hsdma ch.0 end-of-transf er signal output p11: general-pur pose i/o por t (def ault) tm1: 16-bit timer 1 output sout0: ser ial i/f ch.0 data output #dmaend1: hsdma ch.1 end-of-transf er signal output p12: general-pur pose i/o por t (def ault) tm2: 16-bit timer 2 output #sclk0: ser ial i/f ch.0 cloc k input/output #dmaa ck0: hsdma ch.0 ac kno wledge signal output p13: general-pur pose i/o por t (def ault) tm3: 16-bit timer 3 output #srd y0: ser ial i/f ch.0 ready input/output #dmaa ck1: hsdma ch.1 ac kno wledge signal output p14: general-pur pose i/o por t (def ault) tm4: 16-bit timer 4 output sin1: ser ial i/f ch.1 data input dst0: dst0 signal output f or deb ugging (def ault) p15: general-pur pose i/o por t tm5: 16-bit timer 5 output sout1: ser ial i/f ch.1 data output tft_ctl0: lcdc tft i/f control signal 0 output dst1: dst1 signal output f or deb ugging (def ault) p16: general-pur pose i/o por t dcsio0: dcsio por t #sclk1: ser ial i/f ch.1 cloc k input/output tft_ctl3: lcdc tft i/f control signal 3 output dpco: dpco signal output f or deb ugging (def ault) p17: general-pur pose i/o por t dcsio1: dcsio por t #srd y1: ser ial i/f ch.1 ready input/output tft_ctl2: lcdc tft i/f control signal 2 output p30: general-pur pose i/o por t (def ault) card2: card i/f signal 2 output #dmareq0: hsdma ch.0 request input p31: general-pur pose i/o por t (def ault) card3: card i/f signal 3 output #dmareq1: hsdma ch.1 request input p32: general-pur pose i/o por t (def ault) card4: card i/f signal 4 output #dmareq2: hsdma ch.2 request input qfp 12 13 14 15 17 18 19 20 21 22 24 25 26 27 28 29 8 9 10 pin no. pin name p00 sin0 #dmaa ck2 p01 sout0 #dmaa ck3 p02 #sclk0 #dmaend2 p03 #srd y0 #dmaend3 p04 sin1 i2s_sdo p05 sout1 i2s_ws p06 #sclk1 i2s_sck p07 #srd y1 i2s_mclk p10 tm0 sin0 #dmaend0 p11 tm1 sout0 #dmaend1 p12 tm2 #sclk0 #dmaa ck0 p13 tm3 #srd y0 #dmaa ck1 p14 tm4 sin1 dst0 p15 tm5 sout1 tft_ctl0 dst1 p16 dcsio0 #sclk1 tft_ctl3 dpco p17 dcsio1 #srd y1 tft_ctl2 p30 card2 #dmareq0 p31 card3 #dmareq1 p32 card4 #dmareq2 pfbga e2 f2 e3 f1 g2 f3 g1 g3 h1 h2 j4 j2 h3 j1 j3 k2 d1 d3 e4
i s1c33e08 specifications: pin description i-3-6 epson s1c33e08 technical manual i/o i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i (hi-z) i (hi-z) i (hi-z) i (hi-z) i (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (hi-z) pull- up/do wn 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function p33: general-pur pose i/o por t (def ault) card5: card i/f signal 5 output #dmareq3: hsdma ch.3 request input p60: general-pur pose i/o por t (def ault) sin2: ser ial i/f ch.2 data input dcsio0: dcsio por t excl0: 16-bit timer 0 ev ent counter input p61: general-pur pose i/o por t (def ault) sout2: ser ial i/f ch.2 data output dcsio1: dcsio por t excl1: 16-bit timer 1 ev ent counter input p62: general-pur pose i/o por t (def ault) #sclk2: ser ial i/f ch.2 cloc k input/output #adtrg: a/d con ve r ter tr igger input cmu_clk: cmu e xter nal cloc k output p63: general-pur pose i/o por t (def ault) #srd y2: ser ial i/f ch.2 ready input/output wdt_clk: w atchdog timer cloc k output #wdt_nmi: w atchdog timer nmi signal output p64: general-pur pose i/o por t (def ault) #w ait : w ait cycle request input excl2: 16-bit timer 2 ev ent counter input p65: general-pur pose i/o por t (def ault) sdi: spi data input fpd a t8: lcd data p66: general-pur pose i/o por t (def ault) sdo: spi data output fpd a t9: lcd data p67: general-pur pose i/o por t (def ault) spi_clk: spi cloc k fpd a t10: lcd data p70: general-pur pose i/o por t (def ault) ain0: a/d con ve r ter ch.0 input p71: general-pur pose i/o por t (def ault) ain1: a/d con ve r ter ch.1 input p72: general-pur pose i/o por t (def ault) ain2: a/d con ve r ter ch.2 input p73: general-pur pose i/o por t (def ault) ain3: a/d con ve r ter ch.3 input p74: general-pur pose i/o por t (def ault) ain4: a/d con ve r ter ch.4 input excl5: 16-bit timer 5 ev ent counter input p80: general-pur pose i/o por t (def ault) fpframe: lcd frame cloc k output p81: general-pur pose i/o por t (def ault) fpline: lcd line cloc k output p82: general-pur pose i/o por t (def ault) fpshift : lcd shift cloc k output p83: general-pur pose i/o por t (def ault) fpdrd y: lcd drd y/mod signal output tft_ctl1: lcdc tft i/f control signal 1 output bclk: bus cloc k output p84: general-pur pose i/o por t (def ault) dcsio0: dcsio por t fpd a t11: lcd data p85: general-pur pose i/o por t (def ault) dcsio1: dcsio por t p90: general-pur pose i/o por t (def ault) fpd a t0: lcd data p91: general-pur pose i/o por t (def ault) fpd a t1: lcd data p92: general-pur pose i/o por t (def ault) fpd a t2: lcd data p93: general-pur pose i/o por t (def ault) fpd a t3: lcd data p94: general-pur pose i/o por t (def ault) fpd a t4: lcd data qfp 11 77 78 79 80 34 35 36 37 52 51 50 49 48 53 54 55 56 57 58 63 64 65 66 68 pin no. pin name p33 card5 #dmareq3 p60 sin2 dcsio0 excl0 p61 sout2 dcsio1 excl1 p62 #sclk2 #adtrg cmu_clk p63 #srd y2 wdt_clk #wdt_nmi p64 #w ait excl2 p65 sdi fpd at 8 p66 sdo fpd at 9 p67 spi_clk fpd a t10 p70 ain0 p71 ain1 p72 ain2 p73 ain3 p74 ain4 excl5 p80 fpframe p81 fpline p82 fpshift p83 fpdrd y tft_ctl1 bclk p84 dcsio0 fpd a t11 p85 dcsio1 p90 fpd at 0 p91 fpd at 1 p92 fpd at 2 p93 fpd at 3 p94 fpd at 4 pfbga e1 l13 k12 j12 k14 k3 m2 m3 n1 n6 m6 n7 m5 n5 p7 l6 l7 m7 l8 m8 l10 l11 p10 m10 m11
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-7 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i/o i /o (hi-z) i /o (hi-z) i /o (hi-z) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) i /o (pu) pull- up/do wn 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 100k pu ? 1 function p95: general-pur pose i/o por t (def ault) fpd a t5: lcd data p96: general-pur pose i/o por t (def ault) fpd a t6: lcd data p97: general-pur pose i/o por t (def ault) fpd a t7: lcd data p a0: extended general-pur pose i/o por t (def ault) tft_ctl0: lcdc tft i/f control signal 0 output p a1: extended general-pur pose i/o por t (def ault) fpd a t8: lcd data tft_ctl0: lcdc tft i/f control signal 0 output p a2: extended general-pur pose i/o por t (def ault) fpd a t9: lcd data tft_ctl1: lcdc tft i/f control signal 1 output p a3: extended general-pur pose i/o por t (def ault) fpd a t10: lcd data tft_ctl2: lcdc tft i/f control signal 2 output card0: card i/f signal 0 output p a4: extended general-pur pose i/o por t (def ault) fpd a t11: lcd data tft_ctl3: lcdc tft i/f control signal 3 output card1: card i/f signal 1 output pb0: extended general-pur pose i/o por t (def ault) fpd a t8: lcd data i2s_sdo: i 2 s send data signal card2: card i/f signal 2 output pb1: extended general-pur pose i/o por t (def ault) fpd a t9: lcd data i2s_ws: i 2 s word select signal card3: card i/f signal 3 output pb2: extended general-pur pose i/o por t (def ault) fpd a t10: lcd data i2s_sck: i 2 s ser ial cloc k signal card4: card i/f signal 4 output pb3: extended general-pur pose i/o por t (def ault) fpd a t11: lcd data i2s_mclk: i 2 s master cloc k signal card5: card i/f signal 5 output qfp 69 70 71 C C C C C C C C C pin no. pin name p95 fpd at 5 p96 fpd at 6 p97 fpd at 7 pa 0 tft_ctl0 pa 1 fpd at 8 tft_ctl0 pa 2 fpd at 9 tft_ctl1 pa 3 fpd a t10 tft_ctl2 card0 pa 4 fpd a t11 tft_ctl3 card1 pb0 fpd at 8 i2s_sdo card2 pb1 fpd at 9 i2s_ws card3 pb2 fpd a t10 i2s_sck card4 pb3 fpd a t11 i2s_mclk card5 pfbga n10 n12 m12 p11 n11 l12 p12 p13 l2 l4 l3 m1 table i.3.2.5 usb interface pin list i/o i /o i /o i pull- up/do wn C C C function usb d+ pin usb d- pin usb vbus pin. allo ws input of 5 v qfp 75 74 76 pin no. pin name usbdp usbdm usbvbus pfbga m14 n14 l14 table i.3.2.6 other pin list i/o i i i /o i/ o (h) i/ o (l) i i i i pull- up/do wn 50k pu 50k pu 50k pu 50k pu 100k pu C C 50k pd 60k pd function initial reset input pin (with noise reduction circuit) nmi request input pin (with noise reduction circuit) dsio: ser ial input/output f or deb ugging (with noise reduction circuit) (def ault) p34: general-pur pose i/o por t dclk: dclk signal output f or deb ugging (def ault) p35: general-pur pose i/o por t dst2: dst2 signal output f or deb ugging (def ault) p36: general-pur pose i/o por t boot mode select signal 1 input boot mode select signal 0 input wa f er le v el bu r n-in test enab le input test -0 input qfp 72 73 31 33 32 46 C C 45 pin no. pin name #reset #nmi dsio p34 dclk p35 dst2 p36 boo t1 boo t0 burnin test0 pfbga n13 m13 k1 l1 k4 l5 k13 m9 m4
i s1c33e08 specifications: pin description i-3-8 epson s1c33e08 technical manual ?1 : these pins can have pull-ups enabled or disabled by setting the pin control registers. ?2 : these pins come with a bus hold latch. ?3 : the input/output direction of the #ce10 pin at initial reset depends on the configuration of the boot[1:0 ] pins. refer to appendix d boot for details. notes : ? the # prefixed to pin names indicates that input/output signals of the pin are active low. ? the pin names listed in boldface denote the default pin (signal) name. ? the i/o listed in boldface and uppercase denote the default input/output direction. ( ) for i/o indicates the following pin states: (h), (l): default output level. this is only indicated for signals whose level is fixed high or low when the chip is initially reset. (pu): the pin is pulled up at initial reset (register control pull- up is enabled). (hi-z): the pin is placed in high impedance state at initial reset (register control pull-up is disabled). ? the input level must be v dd only for the mclki and rtc_clki pins. input levels for other pins should be v ddh (or av dd ) level. ? the pa ? and pb ? port pins are not available in the qfp package. do not set these ports to a condition (input mode and pull-up off) that may place the port into floating status. ? the boot0 pin is not available in the qfp package. the boot0 signal is pulled down to low inside the package.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-9 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.3 switching over the multiplexed pin functions i.3.3.1 pin function select bits each pin is assigned one to four functions, as listed in table i. 3.3.1.1. when the chip is powered on or cold-reset, each pin defaults to function 0 except for the p21 /sdclk pin and debug pins. if any pin must be used for other than this default function, select the desired function by writing data to the corresponding pin function select bits. table i.3.3.1.1 list of pin function select bits pin function 0 mclki mclko rtc_clki rtc_clko vcp #reset #nmi boot1 boot0 burnin dsio dclk dst2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0/#bsl a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16/dqml a17/dqmh a18 a19 a20 pin function 1 p34 p35 p36 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 p47 p46 p45 p44 pin function 2 tft_ctl2 fpd a t11 fpd a t10 pin function 3 deb ug function function select bit cfp34[1:0] (d[1:0]/0x3003a7) cfp35[1:0] (d[3:2]/0x3003a7) cfp36[1:0] (d[5:4]/0x3003a7) cfpc0[1:0] (d[1:0]/0x300c24) cfpc1[1:0] (d[3:2]/0x300c24) cfpc2[1:0] (d[5:4]/0x300c24) cfpc3[1:0] (d[7:6]/0x300c24) cfpc4[1:0] (d[1:0]/0x300c25) cfpc5[1:0] (d[3:2]/0x300c25) cfpc6[1:0] (d[5:4]/0x300c25) cfpc7[1:0] (d[7:6]/0x300c25) cfp47[1:0] (d[7:6]/0x3003a9) cfp46[1:0] (d[5:4]/0x3003a9) cfp45[1:0] (d[3:2]/0x3003a9) cfp44[1:0] (d[1:0]/0x3003a9)
i s1c33e08 specifications: pin description i-3-10 epson s1c33e08 technical manual pin function 0 a21 a22 a23 a24 #rd #wrl #wrh/#bsh #ce10 #ce4 #ce5 p52 #ce7 #ce8 #ce9 #ce11 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p60 p61 p62 p63 p64 p65 p66 p67 p70 p71 p72 p73 p74 p80 p81 p82 p83 p84 p85 pin function 1 p43 p42 p41 p40 p57 p50 p51 bclk p53 p54 p55 p56 sin0 sout0 #sclk0 #srd y0 sin1 sout1 #sclk1 #srd y1 tm0 tm1 tm2 tm3 tm4 tm5 dcsio0 dcsio1 sdcke sdclk #sdcs #sdras #sdcas #sd we dqml dqmh card2 card3 card4 card5 sin2 sout2 #sclk2 #srd y2 #w ait sdi sdo spi_clk ain0 ain1 ain2 ain3 ain4 fpframe fpline fpshift fpdrd y dcsio0 dcsio1 pin function 2 fpd at 9 fpd at 8 #sdras #sdcas card0 card1 #ce6 sd a10 card1 card0 #dmaa ck2 #dmaa ck3 #dmaend2 #dmaend3 i2s_sdo i2s_ws i2s_sck i2s_mclk sin0 sout0 #sclk0 #srd y0 sin1 sout1 #sclk1 #srd y1 tft_ctl1 #dmareq0 #dmareq1 #dmareq2 #dmareq3 dcsio0 dcsio1 #adtrg wdt_clk excl2 fpd at 8 fpd at 9 fpd a t10 excl5 tft_ctl1 fpd a t11 pin function 3 excl3 excl4 cmu_clk #dmaend0 #dmaend1 #dmaa ck0 #dmaa ck1 tft_ctl0 tft_ctl3 tft_ctl2 excl0 excl1 cmu_clk #wdt_nmi bclk deb ug function dst0 dst1 dpco function select bit cfp43[1:0] (d[7:6]/0x3003a8) cfp42[1:0] (d[5:4]/0x3003a8) cfp41[1:0] (d[3:2]/0x3003a8) cfp40[1:0] (d[1:0]/0x3003a8) cfp57[1:0] (d[7:6]/0x3003ab) cfp50[1:0] (d[1:0]/0x3003aa) cfp51[1:0] (d[3:2]/0x3003aa) cfp52[1:0] (d[5:4]/0x3003aa) cfp53[1:0] (d[7:6]/0x3003aa) cfp54[1:0] (d[1:0]/0x3003ab) cfp55[1:0] (d[3:2]/0x3003ab) cfp56[1:0] (d[5:4]/0x3003ab) cfp00[1:0] (d[1:0]/0x3003a0) cfp01[1:0] (d[3:2]/0x3003a0) cfp02[1:0] (d[5:4]/0x3003a0) cfp03[1:0] (d[7:6]/0x3003a0) cfp04[1:0] (d[1:0]/0x3003a1) cfp05[1:0] (d[3:2]/0x3003a1) cfp06[1:0] (d[5:4]/0x3003a1) cfp07[1:0] (d[7:6]/0x3003a1) cfp10[1:0] (d[1:0]/0x3003a2) cfp11[1:0] (d[3:2]/0x3003a2) cfp12[1:0] (d[5:4]/0x3003a2) cfp13[1:0] (d[7:6]/0x3003a2) cfp14[1:0] (d[1:0]/0x3003a3) cfp15[1:0] (d[3:2]/0x3003a3) cfp16[1:0] (d[5:4]/0x3003a3) cfp17[1:0] (d[7:6]/0x3003a3) cfp20[1:0] (d[1:0]/0x3003a4) cfp21[1:0] (d[3:2]/0x3003a4) cfp22[1:0] (d[5:4]/0x3003a4) cfp23[1:0] (d[7:6]/0x3003a4) cfp24[1:0] (d[1:0]/0x3003a5) cfp25[1:0] (d[3:2]/0x3003a5) cfp26[1:0] (d[5:4]/0x3003a5) cfp27[1:0] (d[7:6]/0x3003a5) cfp30[1:0] (d[1:0]/0x3003a6) cfp31[1:0] (d[3:2]/0x3003a6) cfp32[1:0] (d[5:4]/0x3003a6) cfp33[1:0] (d[7:6]/0x3003a6) cfp60[1:0] (d[1:0]/0x3003a c) cfp61[1:0] (d[3:2]/0x3003a c) cfp62[1:0] (d[5:4]/0x3003a c) cfp63[1:0] (d[7:6]/0x3003a c) cfp64[1:0] (d[1:0]/0x3003ad) cfp65[1:0] (d[3:2]/0x3003ad) cfp66[1:0] (d[5:4]/0x3003ad) cfp67[1:0] (d[7:6]/0x3003ad) cfp70[1:0] (d[1:0]/0x3003ae) cfp71[1:0] (d[3:2]/0x3003ae) cfp72[1:0] (d[5:4]/0x3003ae) cfp73[1:0] (d[7:6]/0x3003ae) cfp74[1:0] (d[1:0]/0x3003af) cfp80[1:0] (d[1:0]/0x3003b0) cfp81[1:0] (d[3:2]/0x3003b0) cfp82[1:0] (d[5:4]/0x3003b0) cfp83[1:0] (d[7:6]/0x3003b0) cfp84[1:0] (d[1:0]/0x3003b1) cfp85[1:0] (d[3:2]/0x3003b1)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-11 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 pin function 0 p90 p91 p92 p93 p94 p95 p96 p97 pa0 pa1 pa2 pa3 pa4 pb0 pb1 pb2 pb3 usbdp usbdm usbvbus test0 pin function 1 fpd at 0 fpd at 1 fpd at 2 fpd at 3 fpd at 4 fpd at 5 fpd at 6 fpd at 7 tft_ctl0 fpd at 8 fpd at 9 fpd a t10 fpd a t11 fpd at 8 fpd at 9 fpd a t10 fpd a t11 pin function 2 tft_ctl0 tft_ctl1 tft_ctl2 tft_ctl3 i2s_sdo i2s_ws i2s_sck i2s_mclk pin function 3 card0 card1 card2 card3 card4 card5 deb ug function function select bit cfp90[1:0] (d[1:0]/0x3003b2) cfp91[1:0] (d[3:2]/0x3003b2) cfp92[1:0] (d[5:4]/0x3003b2) cfp93[1:0] (d[7:6]/0x3003b2) cfp94[1:0] (d[1:0]/0x3003b3) cfp95[1:0] (d[3:2]/0x3003b3) cfp96[1:0] (d[5:4]/0x3003b3) cfp97[1:0] (d[7:6]/0x3003b3) cfp a0[1:0] (d[1:0]/0x300c20) cfp a1[1:0] (d[3:2]/0x300c20) cfp a2[1:0] (d[5:4]/0x300c20) cfp a3[1:0] (d[7:6]/0x300c20) cfp a4[1:0] (d[1:0]/0x300c21) cfpb0[1:0] (d[1:0]/0x300c22) cfpb1[1:0] (d[3:2]/0x300c22) cfpb2[1:0] (d[5:4]/0x300c22) cfpb3[1:0] (d[7:6]/0x300c22) ? the set values 0 to 3 of the pin function select bits correspond to functions 0 to 3 , respectively. ? when trcmux (d0/0x300014 ) = 1 (default), the p15 Cp17 and p34 Cp36 pins are configured as debug-only pins and the function select bits are ineffective. to use the pin function other than debugging, set trcmux (d0/0x300014) to 0 before setting the function select bit. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) ? card0 to card5 are the output pins for card interfaces. the functions of respective pins can be selected according to the card interface used, as listed in table i. 3.3.1.2 . use the card i/f output port configuration register ( 0x300302 ) to select the functions of these pins. for details of the card interfaces and output signals, see section v. 4, card interface (card). table i. 3.3.1.2 relationship between ports and card interface signals pin name card0 card1 card2 card3 card4 card5 function 0 (default) #smrd #smwr #iord #io wr #oe #we function select bit cardio0 (d0/0x300302) cardio1 (d1/0x300302) cardio2 (d2/0x300302) cardio3 (d3/0x300302) cardio4 (d4/0x300302) cardio5 (d5/0x300302) function 1 #cfce1 #cfce2 #smrd #smwr #cfce1 #cfce2 #smrd, #smwr: output pins for smartmedia (nand flash) #cfce 1, #cfce2 : output pins for compactflash #iord, #iowr, #oe, #we: output pins for pc card ? cardio x : card x port function select bit in the card i/f output port configuration register (d x /0x300302)
i s1c33e08 specifications: pin description i-3-12 epson s1c33e08 technical manual i.3.3.2 list of port function select registers table i.3.3.2.1 list of port function select registers address 0x003003a0 0x003003a1 0x003003a2 0x003003a3 0x003003a4 0x003003a5 0x003003a6 0x003003a7 0x003003a8 0x003003a9 0x003003aa 0x003003ab 0x003003ac 0x003003ad 0x003003ae 0x003003af 0x003003b0 0x003003b1 0x003003b2 0x003003b3 0x00300c20 0x00300c21 0x00300c22 0x00300c24 0x00300c25 function selects p00Cp03 port pin functions. selects p 04Cp07 port pin functions. selects p 10Cp13 port pin functions. selects p14Cp17 port pin functions. selects p20Cp23 port pin functions. selects p24Cp27 port pin functions. selects p30Cp33 port pin functions. selects p34Cp36 port pin functions. selects p40Cp43 port pin functions. selects p44Cp47 port pin functions. selects p50Cp53 port pin functions. selects p54Cp57 port pin functions. selects p60Cp63 port pin functions. selects p64Cp67 port pin functions. selects p70Cp73 port pin functions. selects p74 port pin function. selects p80Cp83 port pin functions. selects p84Cp85 port pin functions. selects p90Cp93 port pin functions. selects p94Cp97 port pin functions. selects pa0Cpa3 port pin functions. * selects pa4 port pin function. * selects pb0Cpb3 port pin functions. * selects pc0Cpc3 port pin functions. selects pc4Cpc7 port pin functions. register name p00Cp03 port function select register (pp0_03_cfp) p04Cp07 port function select register (pp0_47_cfp) p10Cp13 port function select register (pp1_03_cfp) p14Cp17 port function select register (pp1_47_cfp) p20Cp23 port function select register (pp2_03_cfp) p24Cp27 port function select register (pp2_47_cfp) p30Cp33 port function select register (pp3_03_cfp) p34Cp36 port function select register (pp3_46_cfp) p40Cp43 port function select register (pp4_03_cfp) p44Cp47 port function select register (pp4_47_cfp) p50Cp53 port function select register (pp5_03_cfp) p54Cp57 port function select register (pp5_47_cfp) p60Cp63 port function select register (pp6_03_cfp) p64Cp67 port function select register (pp6_47_cfp) p70Cp73 port function select register (pp7_03_cfp) p74 port function select register (pp7_4_cfp) p80Cp83 port function select register (pp8_03_cfp) p84Cp85 port function select register (pp8_45_cfp) p90Cp93 port function select register (pp9_03_cfp) p94Cp97 port function select register (pp9_47_cfp) pa0Cpa3 port function select register (ppa_03_cfp) pa4 port function select register (ppa_4_cfp) pb0Cpb3 port function select register (ppb_03_cfp) pc0Cpc3 port function select register (ppc_03_cfp) pc4Cpc7 port function select register (ppc_47_cfp) siz e 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 * these ports are not available in the qfp24-144pin model. the following describes each port function select register. the port function select registers are mapped to addresses 0x3003a0 to 0x3003b3 and 0x300c20 to 0x300c25, and can be accessed in units of bytes.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-13 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a0: p00Cp03 port function select register (pp0_03_cfp) name address register name bit function setting init. r/w remarks cfp031 cfp030 cfp021 cfp020 cfp011 cfp010 cfp001 cfp000 d7 d6 d5 d4 d3 d2 d1 d0 p03 port extended function p02 port extended function p01 port extended function p00 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a0 (b) p00Cp03 port function select register (pp0_03_cfp) cfp03[1:0] function reserved #dmaend3 #srdy0 p03 cfp02[1:0] function reserved #dmaend2 #sclk0 p02 cfp01[1:0] function reserved #dmaack3 sout0 p01 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp00[1:0] function reserved #dmaack2 sin0 p00 this register selects the functions of ports p 00 to p03. d[7:6] cfp03[1:0]: p03 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmaend3 01 (r/w): #srdy0 00 (r/w): p03 (default) d[5:4] cfp02[1:0]: p02 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmaend2 01 (r/w): #sclk0 00 (r/w): p02 (default) d[3:2] cfp01[1:0]: p01 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmaack3 01 (r/w): sout0 00 (r/w): p01 (default) d[1:0] cfp00[1:0]: p00 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmaack2 01 (r/w): sin0 00 (r/w): p00 (default)
i s1c33e08 specifications: pin description i-3-14 epson s1c33e08 technical manual 0x3003a1: p04Cp07 port function select register (pp0_47_cfp) name address register name bit function setting init. r/w remarks cfp071 cfp070 cfp061 cfp060 cfp051 cfp050 cfp041 cfp040 d7 d6 d5 d4 d3 d2 d1 d0 p07 port extended function p06 port extended function p05 port extended function p04 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a1 (b) p04Cp07 port function select register (pp0_47_cfp) cfp07[1:0] function reserved i2s_mclk #srdy1 p07 cfp06[1:0] function reserved i2s_sck #sclk1 p06 cfp05[1:0] function reserved i2s_ws sout1 p05 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp04[1:0] function reserved i2s_sdo sin1 p04 this register selects the functions of ports p 04 to p07. d[7:6] cfp07[1:0]: p07 port extended function select bits 11 (r/w): reserved 10 (r/w): i2s_mclk 01 (r/w): #srdy1 00 (r/w): p07 (default) d[5:4] cfp06[1:0]: p06 port extended function select bits 11 (r/w): reserved 10 (r/w): i2s_sck 01 (r/w): #sclk1 00 (r/w): p06 (default) d[3:2] cfp05[1:0]: p05 port extended function select bits 11 (r/w): reserved 10 (r/w): i2s_ws 01 (r/w): sout1 00 (r/w): p05 (default) d[1:0] cfp04[1:0]: p04 port extended function select bits 11 (r/w): reserved 10 (r/w): i2s_sdo 01 (r/w): sin1 00 (r/w): p04 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-15 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a2: p10Cp13 port function select register (pp1_03_cfp) name address register name bit function setting init. r/w remarks cfp131 cfp130 cfp121 cfp120 cfp111 cfp110 cfp101 cfp100 d7 d6 d5 d4 d3 d2 d1 d0 p13 port extended function p12 port extended function p11 port extended function p10 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a2 (b) p10Cp13 port function select register (pp1_03_cfp) cfp13[1:0] function #dmaack1 #srdy0 tm3 p13 cfp12[1:0] function #dmaack0 #sclk0 tm2 p12 cfp11[1:0] function #dmaend1 sout0 tm1 p11 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp10[1:0] function #dmaend0 sin0 tm0 p10 this register selects the functions of ports p 10 to p13. d[7:6] cfp13[1:0]: p13 port extended function select bits 11 (r/w): #dmaack1 10 (r/w): #srdy0 01 (r/w): tm3 00 (r/w): p13 (default) d[5:4] cfp12[1:0]: p12 port extended function select bits 11 (r/w): #dmaack0 10 (r/w): #sclk0 01 (r/w): tm2 00 (r/w): p12 (default) d[3:2] cfp11[1:0]: p11 port extended function select bits 11 (r/w): #dmaend1 10 (r/w): sout0 01 (r/w): tm1 00 (r/w): p11 (default) d[1:0] cfp10[1:0]: p10 port extended function select bits 11 (r/w): #dmaend0 10 (r/w): sin0 01 (r/w): tm0 00 (r/w): p10 (default)
i s1c33e08 specifications: pin description i-3-16 epson s1c33e08 technical manual 0x3003a3: p14Cp17 port function select register (pp1_47_cfp) name address register name bit function setting init. r/w remarks cfp171 cfp170 cfp161 cfp160 cfp151 cfp150 cfp141 cfp140 d7 d6 d5 d4 d3 d2 d1 d0 p17 port extended function p16 port extended function p15 port extended function p14 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w when trcmux (d0/0x300014) is set to 1 (default), this register becomes ineffective and the port is configured for debugging. 003003a3 (b) p14Cp17 port function select register (pp1_47_cfp) cfp17[1:0] function tft_ctl2 #srdy1 dcsio1 p17 cfp16[1:0] function tft_ctl3 #sclk1 dcsio0 p16 cfp15[1:0] function tft_ctl0 sout1 tm5 p15 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp14[1:0] function reserved sin1 tm4 p14 this register selects the functions of ports p 14 to p17. d[7:6] cfp17[1:0]: p17 port extended function select bits 11 (r/w): tft_ctl2 10 (r/w): #srdy1 01 (r/w): dcsio1 00 (r/w): p17 (default) when trcmux (d 0/0x300014 ) = 1 (default), these control bits are ineffective and the p17 is configured as the dpco pin for debugging. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) d[5:4] cfp16[1:0]: p16 port extended function select bits 11 (r/w): tft_ctl3 10 (r/w): #sclk1 01 (r/w): dcsio0 00 (r/w): p16 (default) when trcmux (d 0/0x300014 ) = 1 (default), these control bits are ineffective and the p16 is configured as the dst 1 pin for debugging. d[3:2] cfp15[1:0]: p15 port extended function select bits 11 (r/w): tft_ctl0 10 (r/w): sout1 01 (r/w): tm5 00 (r/w): p15 (default) when trcmux (d 0/0x300014 ) = 1 (default), these control bits are ineffective and the p15 is configured as the dst 0 pin for debugging. d[1:0] cfp14[1:0]: p14 port extended function select bits 11 (r/w): reserved 10 (r/w): sin1 01 (r/w): tm4 00 (r/w): p14 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-17 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a4: p20Cp23 port function select register (pp2_03_cfp) name address register name bit function setting init. r/w remarks cfp231 cfp230 cfp221 cfp220 cfp211 cfp210 cfp201 cfp200 d7 d6 d5 d4 d3 d2 d1 d0 p23 port extended function p22 port extended function p21 port extended function p20 port extended function 0 0 0 0 0 1 0 0 r/w r/w r/w r/w 003003a4 (b) p20Cp23 port function select register (pp2_03_cfp) cfp23[1:0] function reserved tft_ctl1 #sdras p23 cfp22[1:0] function reserved #sdcs p22 cfp21[1:0] function reserved sdclk p21 1 ? 01 00 1 ? 01 00 1 ? 01 00 11 10 01 00 cfp20[1:0] function reserved sdcke p20 this register selects the functions of ports p 20 to p23. d[7:6] cfp23[1:0]: p23 port extended function select bits 11 (r/w): reserved 10 (r/w): tft_ctl1 01 (r/w): #sdras 00 (r/w): p23 (default) d[5:4] cfp22[1:0]: p22 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): #sdcs 00 (r/w): p22 (default) d[3:2] cfp21[1:0]: p21 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): sdclk (default) 00 (r/w): p21 d[1:0] cfp20[1:0]: p20 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): sdcke 00 (r/w): p20 (default)
i s1c33e08 specifications: pin description i-3-18 epson s1c33e08 technical manual 0x3003a5: p24Cp27 port function select register (pp2_47_cfp) name address register name bit function setting init. r/w remarks cfp271 cfp270 cfp261 cfp260 cfp251 cfp250 cfp241 cfp240 d7 d6 d5 d4 d3 d2 d1 d0 p27 port extended function p26 port extended function p25 port extended function p24 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a5 (b) p24Cp27 port function select register (pp2_47_cfp) cfp27[1:0] function reserved dqmh p27 cfp26[1:0] function reserved dqml p26 cfp25[1:0] function reserved #sdwe p25 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp24[1:0] function reserved #sdcas p24 this register selects the functions of ports p 24 to p27. d[7:6] cfp27[1:0]: p27 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): dqmh 00 (r/w): p27 (default) d[5:4] cfp26[1:0]: p26 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): dqml 00 (r/w): p26 (default) d[3:2] cfp25[1:0]: p25 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): #sdwe 00 (r/w): p25 (default) d[1:0] cfp24[1:0]: p24 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): #sdcas 00 (r/w): p24 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-19 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a6: p30Cp33 port function select register (pp3_03_cfp) name address register name bit function setting init. r/w remarks cfp331 cfp330 cfp321 cfp320 cfp311 cfp310 cfp301 cfp300 d7 d6 d5 d4 d3 d2 d1 d0 p33 port extended function p32 port extended function p31 port extended function p30 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a6 (b) p30Cp33 port function select register (pp3_03_cfp) cfp33[1:0] function reserved #dmareq3 card5 p33 cfp32[1:0] function reserved #dmareq2 card4 p32 cfp31[1:0] function reserved #dmareq1 card3 p31 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp30[1:0] function reserved #dmareq0 card2 p30 this register selects the functions of ports p 30 to p33. d[7:6] cfp33[1:0]: p33 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmareq3 01 (r/w): card5 00 (r/w): p33 (default) d[5:4] cfp32[1:0]: p32 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmareq2 01 (r/w): card4 00 (r/w): p32 (default) d[3:2] cfp31[1:0]: p31 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmareq1 01 (r/w): card3 00 (r/w): p31 (default) d[1:0] cfp30[1:0]: p30 port extended function select bits 11 (r/w): reserved 10 (r/w): #dmareq0 01 (r/w): card2 00 (r/w): p30 (default)
i s1c33e08 specifications: pin description i-3-20 epson s1c33e08 technical manual 0x3003a7: p34Cp36 port function select register (pp3_46_cfp) name address register name bit function setting init. r/w remarks C cfp361 cfp360 cfp351 cfp350 cfp341 cfp340 d7C6 d5 d4 d3 d2 d1 d0 reserved p36 port extended function p35 port extended function p34 port extended function C 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. when trcmux (d0/0x300014) is set to 1 (default), this register becomes ineffective and the port is configured for debugging. 003003a7 (b) p34Cp36 port function select register (pp3_46_cfp) cfp36[1:0] function C reserved p36 dst2 cfp35[1:0] function reserved p35 dclk 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp34[1:0] function reserved p34 dsio this register selects the functions of ports p 34 to p36. d[7:6] reserved d[5:4] cfp36[1:0]: p36 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p36 00 (r/w): dst2 (default) to use p 36 as a general-purpose i/o port, trcmux (d0/0x300014 ) must be set to 0 and cfp36[1:0] set to 01. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) d[3:2] cfp35[1:0]: p35 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p35 00 (r/w): dclk (default) to use p 35 as a general-purpose i/o port, trcmux (d0/0x300014 ) must be set to 0 and cfp35[1:0] set to 01. d[1:0] cfp34[1:0]: p34 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p34 00 (r/w): dsio (default) to use p 34 as a general-purpose i/o port, trcmux (d0/0x300014 ) must be set to 0 and cfp34[1:0] set to 01.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-21 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003a8: p40Cp43 port function select register (pp4_03_cfp) name address register name bit function setting init. r/w remarks cfp431 cfp430 cfp421 cfp420 cfp411 cfp410 cfp401 cfp400 d7 d6 d5 d4 d3 d2 d1 d0 p43 port extended function p42 port extended function p41 port extended function p40 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a8 (b) p40Cp43 port function select register (pp4_03_cfp) cfp43[1:0] function reserved fpdat9 p43 a21 cfp42[1:0] function reserved fpdat8 p42 a22 cfp41[1:0] function excl3 #sdras p41 a23 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp40[1:0] function excl4 #sdcas p40 a24 this register selects the functions of ports p 40 to p43. d[7:6] cfp43[1:0]: p43 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat9 01 (r/w): p43 00 (r/w): a21 (default) d[5:4] cfp42[1:0]: p42 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat8 01 (r/w): p42 00 (r/w): a22 (default) d[3:2] cfp41[1:0]: p41 port extended function select bits 11 (r/w): excl3 10 (r/w): #sdras 01 (r/w): p41 00 (r/w): a23 (default) d[1:0] cfp40[1:0]: p40 port extended function select bits 11 (r/w): excl4 10 (r/w): #sdcas 01 (r/w): p40 00 (r/w): a24 (default)
i s1c33e08 specifications: pin description i-3-22 epson s1c33e08 technical manual 0x3003a9: p44Cp47 port function select register (pp4_47_cfp) name address register name bit function setting init. r/w remarks cfp471 cfp470 cfp461 cfp460 cfp451 cfp450 cfp441 cfp440 d7 d6 d5 d4 d3 d2 d1 d0 p47 port extended function p46 port extended function p45 port extended function p44 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a9 (b) p44Cp47 port function select register (pp4_47_cfp) cfp47[1:0] function reserved p47 a11 cfp46[1:0] function reserved tft_ctl2 p46 a18 cfp45[1:0] function reserved fpdat11 p45 a19 11 10 01 00 11 10 01 00 11 10 01 00 1 ? 01 00 cfp44[1:0] function reserved fpdat10 p44 a20 this register selects the functions of ports p 44 to p47. d[7:6] cfp47[1:0]: p47 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p47 00 (r/w): a11 (default) d[5:4] cfp46[1:0]: p46 port extended function select bits 11 (r/w): reserved 10 (r/w): tft_ctl2 01 (r/w): p46 00 (r/w): a18 (default) d[3:2] cfp45[1:0]: p45 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat11 01 (r/w): p45 00 (r/w): a19 (default) d[1:0] cfp44[1:0]: p44 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat10 01 (r/w): p44 00 (r/w): a20 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-23 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003aa: p50Cp53 port function select register (pp5_03_cfp) name address register name bit function setting init. r/w remarks cfp531 cfp530 cfp521 cfp520 cfp511 cfp510 cfp501 cfp500 d7 d6 d5 d4 d3 d2 d1 d0 p53 port extended function p52 port extended function p51 port extended function p50 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003aa (b) p50Cp53 port function select register (pp5_03_cfp) cfp53[1:0] function reserved sda10 p53 #ce7 cfp52[1:0] function cmu_clk #ce6 bclk p52 cfp51[1:0] function reserved card1 p51 #ce5 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp50[1:0] function reserved card0 p50 #ce4 this register selects the functions of ports p 50 to p53. d[7:6] cfp53[1:0]: p53 port extended function select bits 11 (r/w): reserved 10 (r/w): sda10 01 (r/w): p53 00 (r/w): #ce7 (default) d[5:4] cfp52[1:0]: p52 port extended function select bits 11 (r/w): cmu_clk 10 (r/w): #ce6 01 (r/w): bclk 00 (r/w): p52 (default) d[3:2] cfp51[1:0]: p51 port extended function select bits 11 (r/w): reserved 10 (r/w): card1 01 (r/w): p51 00 (r/w): #ce5 (default) d[1:0] cfp50[1:0]: p50 port extended function select bits 11 (r/w): reserved 10 (r/w): card0 01 (r/w): p50 00 (r/w): #ce4 (default)
i s1c33e08 specifications: pin description i-3-24 epson s1c33e08 technical manual 0x3003ab: p54Cp57 port function select register (pp5_47_cfp) name address register name bit function setting init. r/w remarks cfp571 cfp570 cfp561 cfp560 cfp551 cfp550 cfp541 cfp540 d7 d6 d5 d4 d3 d2 d1 d0 p57 port extended function p56 port extended function p55 port extended function p54 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ab (b) p54Cp57 port function select register (pp5_47_cfp) cfp57[1:0] function reserved p57 #ce10 cfp56[1:0] function reserved p56 #ce11 cfp55[1:0] function reserved card0 p55 #ce9 11 10 01 00 11 10 01 00 1 ? 01 00 1 ? 01 00 cfp54[1:0] function reserved card1 p54 #ce8 this register selects the functions of ports p 54 to p57. d[7:6] cfp57[1:0]: p57 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p57 00 (r/w): #ce10 (default) d[5:4] cfp56[1:0]: p56 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): p56 00 (r/w): #ce11 (default) d[3:2] cfp55[1:0]: p55 port extended function select bits 11 (r/w): reserved 10 (r/w): card0 01 (r/w): p55 00 (r/w): #ce9 (default) d[1:0] cfp54[1:0]: p54 port extended function select bits 11 (r/w): reserved 10 (r/w): card1 01 (r/w): p54 00 (r/w): #ce8 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-25 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003ac: p60Cp63 port function select register (pp6_03_cfp) name address register name bit function setting init. r/w remarks cfp631 cfp630 cfp621 cfp620 cfp611 cfp610 cfp601 cfp600 d7 d6 d5 d4 d3 d2 d1 d0 p63 port extended function p62 port extended function p61 port extended function p60 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ac (b) p60Cp63 port function select register (pp6_03_cfp) cfp63[1:0] function #wdt_nmi wdt_clk #srdy2 p63 cfp62[1:0] function cmu_clk #adtrg #sclk2 p62 cfp61[1:0] function excl1 dcsio1 sout2 p61 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp60[1:0] function excl0 dcsio0 sin2 p60 this register selects the functions of ports p 60 to p63. d[7:6] cfp63[1:0]: p63 port extended function select bits 11 (r/w): #wdt_nmi 10 (r/w): wdt_clk 01 (r/w): #srdy2 00 (r/w): p63 (default) d[5:4] cfp62[1:0]: p62 port extended function select bits 11 (r/w): cmu_clk 10 (r/w): #adtrg 01 (r/w): #sclk2 00 (r/w): p62 (default) d[3:2] cfp61[1:0]: p61 port extended function select bits 11 (r/w): excl1 10 (r/w): dcsio1 01 (r/w): sout2 00 (r/w): p61 (default) d[1:0] cfp60[1:0]: p60 port extended function select bits 11 (r/w): excl0 10 (r/w): dcsio0 01 (r/w): sin2 00 (r/w): p60 (default)
i s1c33e08 specifications: pin description i-3-26 epson s1c33e08 technical manual 0x3003ad: p64Cp67 port function select register (pp6_47_cfp) name address register name bit function setting init. r/w remarks cfp671 cfp670 cfp661 cfp660 cfp651 cfp650 cfp641 cfp640 d7 d6 d5 d4 d3 d2 d1 d0 p67 port extended function p66 port extended function p65 port extended function p64 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ad (b) p64Cp67 port function select register (pp6_47_cfp) cfp67[1:0] function reserved fpdat10 spi_clk p67 cfp66[1:0] function reserved fpdat9 sdo p66 cfp65[1:0] function reserved fpdat8 sdi p65 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp64[1:0] function reserved excl2 #wait p64 this register selects the functions of ports p 64 to p67. d[7:6] cfp67[1:0]: p67 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat10 01 (r/w): spi_clk 00 (r/w): p67 (default) d[5:4] cfp66[1:0]: p66 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat9 01 (r/w): sdo 00 (r/w): p66 (default) d[3:2] cfp65[1:0]: p65 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat8 01 (r/w): sdi 00 (r/w): p65 (default) d[1:0] cfp64[1:0]: p64 port extended function select bits 11 (r/w): reserved 10 (r/w): excl2 01 (r/w): #wait 00 (r/w): p64 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-27 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003ae: p70Cp73 port function select register (pp7_03_cfp) name address register name bit function setting init. r/w remarks cfp731 cfp730 cfp721 cfp720 cfp711 cfp710 cfp701 cfp700 d7 d6 d5 d4 d3 d2 d1 d0 p73 port extended function p72 port extended function p71 port extended function p70 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ae (b) p70Cp73 port function select register (pp7_03_cfp) cfp73[1:0] function reserved ain3 p73 cfp72[1:0] function reserved ain2 p72 cfp71[1:0] function reserved ain1 p71 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp70[1:0] function reserved ain0 p70 this register selects the functions of ports p 70 to p73. d[7:6] cfp73[1:0]: p73 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): ain3 00 (r/w): p73 (default) d[5:4] cfp72[1:0]: p72 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): ain2 00 (r/w): p72 (default) d[3:2] cfp71[1:0]: p71 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): ain1 00 (r/w): p71 (default) d[1:0] cfp70[1:0]: p70 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): ain0 00 (r/w): p70 (default)
i s1c33e08 specifications: pin description i-3-28 epson s1c33e08 technical manual 0x3003af: p74 port function select register (pp7_4_cfp) name address register name bit function setting init. r/w remarks C cfp741 cfp740 d7C2 d1 d0 reserved p74 port extended function C 0 0 C r/w 0 when being read. 003003af (b) p74 port function select register (pp7_4_cfp) cfp74[1:0] function reserved excl5 ain4 p74 C 11 10 01 00 this register selects the function of port p 74. d[7:2] reserved d[1:0] cfp74[1:0]: p74 port extended function select bits 11 (r/w): reserved 10 (r/w): excl5 01 (r/w): ain4 00 (r/w): p74 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-29 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003b0: p80Cp83 port function select register (pp8_03_cfp) name address register name bit function setting init. r/w remarks cfp831 cfp830 cfp821 cfp820 cfp811 cfp810 cfp801 cfp800 d7 d6 d5 d4 d3 d2 d1 d0 p83 port extended function p82 port extended function p81 port extended function p80 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b0 (b) p80Cp83 port function select register (pp8_03_cfp) cfp83[1:0] function bclk tft_ctl1 fpdrdy p83 cfp82[1:0] function reserved fpshift p82 cfp81[1:0] function reserved fpline p81 1 ? 01 00 1 ? 01 00 1 ? 01 00 11 10 01 00 cfp80[1:0] function reserved fpframe p80 this register selects the functions of ports p 80 to p83. d[7:6] cfp83[1:0]: p83 port extended function select bits 11 (r/w): bclk 10 (r/w): tft_ctl1 01 (r/w): fpdrdy 00 (r/w): p83 (default) d[5:4] cfp82[1:0]: p82 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpshift 00 (r/w): p82 (default) d[3:2] cfp81[1:0]: p81 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpline 00 (r/w): p81 (default) d[1:0] cfp80[1:0]: p80 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpframe 00 (r/w): p80 (default)
i s1c33e08 specifications: pin description i-3-30 epson s1c33e08 technical manual 0x3003b1: p84Cp85 port function select register (pp8_45_cfp) name address register name bit function setting init. r/w remarks C cfp851 cfp850 cfp841 cfp840 d7C4 d3 d2 d1 d0 reserved p85 port extended function p84 port extended function C 0 0 0 0 C r/w r/w 0 when being read. 003003b1 (b) p84Cp85 port function select register (pp8_45_cfp) cfp85[1:0] function C reserved dcsio1 p85 cfp84[1:0] function reserved fpdat11 dcsio0 p84 11 10 01 00 1 ? 01 00 this register selects the functions of ports p 84 to p85. d[7:4] reserved d[3:2] cfp85[1:0]: p85 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): dcsio1 00 (r/w): p85 (default) d[1:0] cfp84[1:0]: p84 port extended function select bits 11 (r/w): reserved 10 (r/w): fpdat11 01 (r/w): dcsio0 00 (r/w): p84 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-31 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x3003b2: p90Cp93 port function select register (pp9_03_cfp) name address register name bit function setting init. r/w remarks cfp931 cfp930 cfp921 cfp920 cfp911 cfp910 cfp901 cfp900 d7 d6 d5 d4 d3 d2 d1 d0 p93 port extended function p92 port extended function p91 port extended function p90 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b2 (b) p90Cp93 port function select register (pp9_03_cfp) cfp93[1:0] function reserved fpdat3 p93 cfp92[1:0] function reserved fpdat2 p92 cfp91[1:0] function reserved fpdat1 p91 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp90[1:0] function reserved fpdat0 p90 this register selects the functions of ports p 90 to p93. d[7:6] cfp93[1:0]: p93 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat3 00 (r/w): p93 (default) d[5:4] cfp92[1:0]: p92 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat2 00 (r/w): p92 (default) d[3:2] cfp91[1:0]: p91 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat1 00 (r/w): p91 (default) d[1:0] cfp90[1:0]: p90 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat0 00 (r/w): p90 (default)
i s1c33e08 specifications: pin description i-3-32 epson s1c33e08 technical manual 0x3003b3: p94Cp97 port function select register (pp9_47_cfp) name address register name bit function setting init. r/w remarks cfp971 cfp970 cfp961 cfp960 cfp951 cfp950 cfp941 cfp940 d7 d6 d5 d4 d3 d2 d1 d0 p97 port extended function p96 port extended function p95 port extended function p94 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b3 (b) p94Cp97 port function select register (pp9_47_cfp) cfp97[1:0] function reserved fpdat7 p97 cfp96[1:0] function reserved fpdat6 p96 cfp95[1:0] function reserved fpdat5 p95 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp94[1:0] function reserved fpdat4 p94 this register selects the functions of ports p 94 to p97. d[7:6] cfp97[1:0]: p97 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat7 00 (r/w): p97 (default) d[5:4] cfp96[1:0]: p96 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat6 00 (r/w): p96 (default) d[3:2] cfp95[1:0]: p95 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat5 00 (r/w): p95 (default) d[1:0] cfp94[1:0]: p94 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): fpdat4 00 (r/w): p94 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-33 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x300c20: pa0Cpa3 port function select register (ppa_03_cfp) name address register name bit function setting init. r/w remarks cfpa31 cfpa30 cfpa21 cfpa20 cfpa11 cfpa10 cfpa01 cfpa00 d7 d6 d5 d4 d3 d2 d1 d0 pa3 port extended function pa2 port extended function pa1 port extended function pa0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c20 (b) pa0Cpa3 port function select register (ppa_03_cfp) cfpa3[1:0] function card0 tft_ctl2 fpdat10 pa3 cfpa2[1:0] function reserved tft_ctl1 fpdat9 pa2 cfpa1[1:0] function reserved tft_ctl0 fpdat8 pa1 1 ? 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfpa0[1:0] function reserved tft_ctl0 pa0 note : the pa0 to pa3 ports are not available in the qfp24-144pin package model. this register selects the functions of ports pa 0 to pa3. d[7:6] cfpa3[1:0]: pa3 port extended function select bits 11 (r/w): card0 10 (r/w): tft_ctl2 01 (r/w): fpdat10 00 (r/w): pa3 (default) d[5:4] cfpa2[1:0]: pa2 port extended function select bits 11 (r/w): reserved 10 (r/w): tft_ctl1 01 (r/w): fpdat9 00 (r/w): pa2 (default) d[3:2] cfpa1[1:0]: pa1 port extended function select bits 11 (r/w): reserved 10 (r/w): tft_ctl0 01 (r/w): fpdat8 00 (r/w): pa1 (default) d[1:0] cfpa0[1:0]: pa0 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): tft_ctl0 00 (r/w): pa0 (default)
i s1c33e08 specifications: pin description i-3-34 epson s1c33e08 technical manual 0x300c21: pa4 port function select register (ppa_4_cfp) name address register name bit function setting init. r/w remarks C cfpa41 cfpa40 d7C2 d1 d0 reserved pa4 port extended function C 0 0 C r/w 0 when being read. 00300c21 (b) pa4 port function select register (ppa_4_cfp) cfpa4[1:0] function card1 tft_ctl3 fpdat11 pa4 11 10 01 00 function C note : the pa4 port is not available in the qfp24-144pin package model. this register selects the function of port pa 4. d[7:2] reserved d[1:0] cfpa4[1:0]: pa4 port extended function select bits 11 (r/w): card1 10 (r/w): tft_ctl3 01 (r/w): fpdat11 00 (r/w): pa4 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-35 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x300c22: pb0Cpb3 port function select register (ppb_03_cfp) name address register name bit function setting init. r/w remarks cfpb31 cfpb30 cfpb21 cfpb20 cfpb11 cfpb10 cfpb01 cfpb00 d7 d6 d5 d4 d3 d2 d1 d0 pb3 port extended function pb2 port extended function pb1 port extended function pb0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c22 (b) pb0Cpb3 port function select register (ppb_03_cfp) cfpb3[1:0] function card5 i2s_mclk fpdat11 pb3 cfpb2[1:0] function card4 i2s_sck fpdat10 pb2 cfpb1[1:0] function card3 i2s_ws fpdat9 pb1 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfpb0[1:0] function card2 i2s_sdo fpdat8 pb0 note : the pb0 to pb3 ports are not available in the qfp24-144pin package model. this register selects the functions of ports pb 0 to pb3. d[7:6] cfpb3[1:0]: pb3 port extended function select bits 11 (r/w): card5 10 (r/w): i2s_mclk 01 (r/w): fpdat11 00 (r/w): pb3 (default) d[5:4] cfpb2[1:0]: pb2 port extended function select bits 11 (r/w): card4 10 (r/w): i2s_sck 01 (r/w): fpdat10 00 (r/w): pb2 (default) d[3:2] cfpb1[1:0]: pb1 port extended function select bits 11 (r/w): card3 10 (r/w): i2s_ws 01 (r/w): fpdat9 00 (r/w): pb1 (default) d[1:0] cfpb0[1:0]: pb0 port extended function select bits 11 (r/w): card2 10 (r/w): i2s_sdo 01 (r/w): fpdat8 00 (r/w): pb0 (default)
i s1c33e08 specifications: pin description i-3-36 epson s1c33e08 technical manual 0x300c24: pc0Cpc3 port function select register (ppc_03_cfp) name address register name bit function setting init. r/w remarks cfpc31 cfpc30 cfpc21 cfpc20 cfpc11 cfpc10 cfpc01 cfpc00 d7 d6 d5 d4 d3 d2 d1 d0 pc3 port extended function pc2 port extended function pc1 port extended function pc0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c24 (b) pc0Cpc3 port function select register (ppc_03_cfp) cfpc3[1:0] function reserved pc3 d11 cfpc2[1:0] function reserved pc2 d10 cfpc1[1:0] function reserved pc1 d9 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfpc0[1:0] function reserved pc0 d8 this register selects the functions of ports pc 0 to pc3. d[7:6] cfpc3[1:0]: pc3 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc3 00 (r/w): d11 (default) d[5:4] cfpc2[1:0]: pc2 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc2 00 (r/w): d10 (default) d[3:2] cfpc1[1:0]: pc1 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc1 00 (r/w): d9 (default) d[1:0] cfpc0[1:0]: pc0 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc0 00 (r/w): d8 (default)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-37 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 0x300c25: pc4Cpc7 port function select register (ppc_47_cfp) name address register name bit function setting init. r/w remarks cfpc71 cfpc70 cfpc61 cfpc60 cfpc51 cfpc50 cfpc41 cfpc40 d7 d6 d5 d4 d3 d2 d1 d0 pc7 port extended function pc6 port extended function pc5 port extended function pc4 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c25 (b) pc4Cpc7 port function select register (ppc_47_cfp) cfpc7[1:0] function reserved pc7 d15 cfpc6[1:0] function reserved pc6 d14 cfpc5[1:0] function reserved pc5 d13 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfpc4[1:0] function reserved pc4 d12 this register selects the functions of ports pc 4 to pc7. d[7:6] cfpc7[1:0]: pc7 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc7 00 (r/w): d15 (default) d[5:4] cfpc6[1:0]: pc6 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc6 00 (r/w): d14 (default) d[3:2] cfpc5[1:0]: pc5 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc5 00 (r/w): d13 (default) d[1:0] cfpc4[1:0]: pc4 port extended function select bits 11 (r/w): reserved 10 (r/w): reserved 01 (r/w): pc4 00 (r/w): d12 (default)
i s1c33e08 specifications: pin description i-3-38 epson s1c33e08 technical manual i.3.4 input/output cells and input/output characteristics table i.3.4.1 pin characteristics i/o cell name lliny llo ty lliny llo ty llo ty hibhp1ty hibhp1ty hibasp2ty hibhp1ty hibhy hbbh2bp1ty hbbh2bp1ty hbbh2bp2ty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbt2ahty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty input le vel tr ansparent C tr ansparent C C schmitt schmitt l vcmos schmitt schmitt schmitt schmitt schmitt l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl l vttl schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt i oh /i ol C C C C C C C C C C 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 2 ma 2 ma 2 ma pull-up/do wn C C C C C 50 k ? up 50 k ? up 100 k ? up 50 k ? up 50 k ? do wn 50 k ? up 50 k ? up 100 k ? up bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch bus-hold latch 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up i/o i o i o o i i i i i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o po wer sour ce v dd v dd v dd v dd pl v dd v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh remarks note 2 note 2 note 2 note 2 note 4 note 5 note 5 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 signal name mclki mclko rtc_clki rtc_clko vcp #reset #nmi boot1 boot0 burnin dsio (p34) dclk (p35) dst2 (p36) d0 d1 d2 d3 d4 d5 d6 d7 d8 (pc0) d9 (pc1) d10 (pc2) d11 (pc3) d12 (pc4) d13 (pc5) d14 (pc6) d15 (pc7) a0/#bsl a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 (p47) a12 a13 a14 a15 a16/dqml a17/dqmh a18 (p46/tft_ctl2) a19 (p45/fpdat11) a20 (p44/fpdat10) a21 (p43/fpdat9) a22 (p42/fpdat8) a23 (p41/#sdras/excl3) a24 (p40/#sdcas/excl4) #rd #wrl #wrh/#bsh #ce10 (p57) #ce4 (p50/card0) #ce5 (p51/card1)
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-39 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i/o cell name hbbh1bp2ty hbbh2bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh2ap2ty hbbh2ap2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2bp2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh2ap2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hibasp2ty hibasp2ty hibasp2ty hibasp2ty hibasp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty input le vel schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt l vcmos l vcmos l vcmos l vcmos l vcmos schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt i oh /i ol 2 ma 4 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 4 ma 4 ma 2 ma 2 ma 2 ma 2 ma 2 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 4 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma C C C C C 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma pull-up/do wn 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i i i i i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o po wer sour ce v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh av dd av dd av dd av dd av dd v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh remarks note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1, 3 note 1, 3 note 1, 3 note 1, 3 note 1, 3 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 signal name p52 (bclk/#ce6/cmu_clk) #ce7 (p53/sda10) #ce8 (p54/card1) #ce9 (p55/card0) #ce11 (p56) p00 (sin0/#dmaack2) p01 (sout0/#dmaack3) p02 (#sclk0/#dmaend2) p03 (#srdy0/#dmaend3) p04 (sin1/i2s_sdo) p05 (sout1/i2s_ws) p06 (#sclk1/i2s_sck) p07 (#srdy1/i2s_mclk) p10 (tm0/sin0/#dmaend0) p11 (tm1/sout0/#dmaend1) p12 (tm2/#sclk0/#dmaack0) p13 (tm3/#srdy0/#dmaack1) p14 (tm4/sin1) dst0 (p15/tm5/sout1/tft_ctl0) dst1 (p16/dcsio0/#sclk1/tft_ctl3) dpco (p17/dcsio1/#srdy1/tft_ctl2) p20 (sdcke) sdclk (p21) p22 (#sdcs) p23 (#sdras/tft_ctl1) p24 (#sdcas) p25 (#sdwe) p26 (dqml) p27 (dqmh) p30 (card2/#dmareq0) p31 (card3/#dmareq1) p32 (card4/#dmareq2) p33 (card5/#dmareq3) p60 (sin2/dcsio0/excl0) p61 (sout2/dcsio1/excl1) p62 (#sclk2/#adtrg/cmu_clk) p63 (#srdy2/wdt_clk/#wdt_nmi) p64 (#wait/excl2) p65 (sdi/fpdat8) p66 (sdo/fpdat9) p67 (spi_clk/fpdat10) p70 (ain0) p71 (ain1) p72 (ain2) p73 (ain3) p74 (ain4/excl5) p80 (fpframe) p81 (fpline) p82 (fpshift) p83 (fpdrdy/tft_ctl1/bclk) p84 (dcsio0/fpdat11) p85 (dcsio1) p90 (fpdat0) p91 (fpdat1) p92 (fpdat2) p93 (fpdat3) p94 (fpdat4) p95 (fpdat5) p96 (fpdat6) p97 (fpdat7)
i s1c33e08 specifications: pin description i-3-40 epson s1c33e08 technical manual i/o cell name hbbh1bp2ty hbbh2ap2ty hbbh2ap2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty hbbh1bp2ty C C C litst1y input le vel schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt schmitt C C C l vcmos i oh /i ol 2 ma 4 ma 4 ma 2 ma 2 ma 2 ma 2 ma 2 ma 2 ma C C C C pull-up/do wn 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up 100 k ? up C C C 60 k ? do wn i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i i po wer sour ce v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh v ddh remarks note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 note 1, 5 signal name pa0 (tft_ctl0) pa1 (fpdat8/tft_ctl0) pa2 (fpdat9/tft_ctl1) pa3 (fpdat10/tft_ctl2/card0) pa4 (fpdat11/tft_ctl3/card1) pb0 (fpdat8/i2s_sdo/card2) pb1 (fpdat9/i2s_ws/card3) pb2 (fpdat10/i2s_sck/card4) pb3 (fpdat11/i2s_mclk/card5) usbdp usbdm usbvbus test0 notes : 1 pull-ups can be enabled or disabled by setting the pin control registers. 2 this pin must be used in input voltage range 0 v vin v dd . 3 this pin must be used in input voltage range 0 v vin av dd . 4 this pin must be used in input voltage range 0 v vin plv dd . 5 these pins are not available in the qfp24-144 pin package model.
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-41 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.5 package i.3.5.1 qfp24-144 pin package 16 0.1 18 0.4 16 0.1 18 0.4 37 72 1 3 6 108 73 144 109 index 1.0 0.1 0.1 1.2 max 0.16 0.4 +0.10 C0.05 1 0.5 0.2 0 8 0.125 +0.05 C0.025 figure i.3.5.1.1 qfp24-144 pin package dimensions
i s1c33e08 specifications: pin description i-3-42 epson s1c33e08 technical manual pin 1 0 8 f 0 0 a 3 e 3 3 c 1 s f p a n a j (1) y x pkg center line x' y' (2) (15) 0.8 6.0 0.7 0.25 0.8 0.4 0.25 (16) (17) (18) 6.7 1.2 0.8 1.2 0.8 1.2 0.8 1.5 (mm) 6.7 (19) (20) (22) (23) (24) (25) (27) (28) (3) (4) (5) (6) (7) (9) (10) (11) (12) (13) (14) (21) (26) pkg center line (8) figure i.3.5.1.2 qfp24-144 pin package marking
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-43 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.5.2 pfbga-180 pin package top view bottom view a1 corner a1 corner index d e a a 1 e z d s d s s y p n m l k j h g f e d c b a symbol d e a a 1 e b x y s d s e z d z e min 11.8 11.8 0.25 0.38 dimension in millimeters nom 12.0 12.0 0.30 0.80 0.43 0.40 0.40 0.80 0.80 max 12.2 12.2 1.20 0.35 0.48 0.08 0.10 b m e z e s e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 figure i.3.5.2.1 pfbga-180 pin package dimensions
i s1c33e08 specifications: pin description i-3-44 epson s1c33e08 technical manual 3 3 e 0 8 0 0 a * c f j a p a n (1 ) y x pkg center lin e x' y' (2 ) (12 ) ( 13) (14) (15) (16) (17 ) (21 ) (22) (23) (24) (25 ) (18) (19) (20) (3 ) (4) (5 ) (6) (7 ) (8) (9 ) (10) (11 ) 3. 1 3. 4 3. 4 3.4 3.4 0. 1 0. 2 0. 5 0. 1 0. 9 0.5 0. 9 0.5 0. 9 0.5 1. 5 1. 5 (mm) pkg center lin e 0. 6 figure i.3.5.2.2 pfbga-180 pin package marking
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-45 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.3.5.3 thermal resistance of the package the chip temperature of lsi devices tends to increase with the power consumed on the chip. the chip temperature when encapsulated in a package is calculated from its ambient temperature (ta), the thermal resistance of the package ( ), and power dissipation (p d ). chip temperature (tj) = ta + (p d ) [ c] when used under normal operating conditions, make sure that the chip temperature (tj) is 100 c or less. thermal resistance of the qfp24-144 pin package 1. when mounted on a board (windless condition) thermal resistance ( j-a) = 33.3 c/w this value indicates the thermal resistance of the package when measured under a windless condition, with the sample mounted on a measurement board (size: 114 76 1.6 mm thick, fr4/4 layered board). 2. when suspended alone (windless condition) thermal resistance = 90C100 c/w this value indicates the thermal resistance of the package when measured under a windless condition, with the sample suspended alone. thermal resistance of the pfbga-180 pin package 1. when mounted on a board (windless condition) thermal resistance ( j-a) = 30 c/w this value indicates the thermal resistance of the package when measured under a windless condition, with the sample mounted on a measurement board (size: 114.5 101.5 1.6 mm thick, fr4/4 layered board). 2. when suspended alone (windless condition) thermal resistance = 165 c/w this value indicates the thermal resistance of the package when measured under a windless condition, with the sample suspended alone. note : the thermal resistance of the package varies significantly depending on how it is mounted on the board and whether forcibly air-cooled.
i s1c33e08 specifications: pin description i-3-46 epson s1c33e08 technical manual i.3.6 pad layout x y (0, 0) 4.70 mm 4.70 mm 1 5 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 125 45 50 55 60 65 70 75 80 130 135 140 145 150 155 160 165 168 pad opening (x y) 104 m 104 m: pad no. 1, 42, 43, 84, 85, 126, 127, 168 80 m 104 m: pad no. 2C41, 86C125 104 m 80 m: pad no. 44C83, 128C167 figure i.3.6.1 pad layout diagram
i s1c33e08 specifications: pin description s1c33e08 technical manual epson i-3-47 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 table i. 3.6.1 pad coordinate (unit: mm) no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p ad name #ce9 (p55/card0) a18 (p46/tft_ctl2) a19 (p45/fpd a t11) a20 (p44/fpd a t10) a21 (p43/fpd a t9) a22 (p42/fpd a t8) v ss p30 (card2/#dmareq0) p31 (card3/#dmareq1) p32 (card4/#dmareq2) p33 (card5/#dmareq3) p00 (sin0/#dmaa ck2) p01 (sout0/#dmaa ck3) p02 (#sclk0/#dmaend2) p03 (#srd y0/#dmaend3) v ddh p04 (sin1/i2s_sdo) p05 (sout1/i2s_ws) p06 (#sclk1/i2s_sck) p07 (#srd y1/i2s_mclk) p10 (tm0/sin0/#dmaend0) p11 (tm1/sout0/#dmaend1) v dd p12 (tm2/#sclk0/#dmaa ck0) p13 (tm3/#srd y0/#dmaa ck1) p14 (tm4/sin1) dst0 (p15/tm5/sout1/tft_ctl0) dst1 (p16/dcsio0/#sclk1/tft_ctl3) dpco (p17/dcsio1/#srd y1/tft_ctl2) v ddh v ddh dsio (p34) dst2 (p36) dclk (p35) pb0 (fpd a t8/i2s_sdo/card2) p64 (#w ait) pb1 (fpd a t9/i2s_ws/card3) v ss p65 (sdi/fpd a t8) pb2 (fpd a t10/i2s_sck/card4) p66 (sdo/fpd a t9) pb3 (fpd a t11/i2s_mclk/card5) p67 (spi_clk/fpd a t10) v dd rtc_clki rtc_clko v ss plv ss vcp plv dd p ad name test0 boot1 av dd p74 (ain4/excl5) p73 (ain3) p72 (ain2) p71 (ain1) p70 (ain0) p80 (fpframe) p81 (fpline) p82 (fpshift) p83 (fpdrd y/tft_ctl1/bclk) p84 (dcsio0/fpd a t11) p85 (dcsio1) v dd mclki mclko v ss burnin p90 (fpd a t0) p91 (fpd a t1) p92 (fpd a t2) p93 (fpd a t3) v ddh pa0 (tft_ctl0) p94 (fpd a t4) pa1 (fpd a t8/tft_ctl0) p95 (fpd a t5) pa2 (fpd a t9/tft_ctl1) p96 (fpd a t6) pa3 (fpd a t10/tft_ctl2/card0) p97 (fpd a t7) pa4 (fpd a t11/tft_ctl3/card1) #reset #nmi v dd usbdm usbdp n.c. usbvbus n.c. v ddh p60 (sin2/dcsio0/excl0) p61 (sout2/dcsio1/excl1) p62 (#sclk2/#adtrg/cmu_clk) p63 (#srd y2/wdt_clk/#wdt_nmi) boot0 v ss d0 d1 x -2.02 -1.80 -1.68 -1.58 -1.49 -1.40 -1.31 -1.22 -1.13 -1.04 -0.95 -0.86 -0.77 -0.68 -0.59 -0.50 -0.41 -0.32 -0.23 -0.14 -0.05 0.05 0.14 0.23 0.32 0.41 0.50 0.59 0.68 0.77 0.86 0.95 1.04 1.13 1.22 1.31 1.40 1.49 1.58 1.68 1.80 2.02 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 y -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.02 -1.80 -1.68 -1.58 -1.49 -1.40 -1.31 -1.22 x 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.02 1.80 1.68 1.58 1.49 1.40 1.31 1.22 1.13 1.04 0.95 0.86 0.77 0.68 0.59 0.50 y -1.13 -1.04 -0.95 -0.86 -0.77 -0.68 -0.59 -0.50 -0.41 -0.32 -0.23 -0.14 -0.05 0.05 0.14 0.23 0.32 0.41 0.50 0.59 0.68 0.77 0.86 0.95 1.04 1.13 1.22 1.31 1.40 1.49 1.58 1.68 1.80 2.02 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23
i s1c33e08 specifications: pin description i-3-48 epson s1c33e08 technical manual no. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 no. 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 p ad name d2 d3 v dd d4 d5 d6 d7 v ddh d8 d9 d10 d11 v dd d12 d13 d14 d15 v ss p20 (sdcke) sdclk (p21) p22 (#sdcs) v ddh p23 (#sdras/tft_ctl1) p24 (#sdcas) p25 (#sd we) v ss p26 (dqml) p27 (dqmh) a14 a15 a16/dqml a17/dqmh #ce7 (p53/sd a10) a0/#bsl p ad name v ss v ss a1 a2 a3 a4 a5 v dd v dd a6 a7 a8 a9 v ddh v ddh a10 a11 (p47) a12 a13 a23 (p41/#sdras/excl3) a24 (p40/#sdcas/ excl4) v ss v ss #ce10 (p57) #rd #wrl #wrh/#bsh #ce11 (p56) p52 (bclk/#ce6/cmu_clk) v dd #ce4 (p50/card0) #ce5 (p51/card1) #ce8 (p54/card1) v ddh x 0.41 0.32 0.23 0.14 0.05 -0.05 -0.14 -0.23 -0.32 -0.41 -0.50 -0.59 -0.68 -0.77 -0.86 -0.95 -1.04 -1.13 -1.22 -1.31 -1.40 -1.49 -1.58 -1.68 -1.80 -2.02 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 y 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.23 2.02 1.80 1.68 1.58 1.49 1.40 1.31 1.22 x -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 -2.23 y 1.13 1.04 0.95 0.86 0.77 0.68 0.59 0.50 0.41 0.32 0.23 0.14 0.05 -0.05 -0.14 -0.23 -0.32 -0.41 -0.50 -0.59 -0.68 -0.77 -0.86 -0.95 -1.04 -1.13 -1.22 -1.31 -1.40 -1.49 -1.58 -1.68 -1.80 -2.02
i s1c33e08 specifications: power supply s1c33e08 technical manual epson i-4-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.4 power supply this section explains the operating voltage of the s 1c33e08. i.4.1 power supply pins the s1c33e08 has the power supply pins shown in table i.4.1.1. table i.4.1.1 power supply pins function po wer supply (+) f or core (1.8 v) po wer supply (+) f or i/o (3.3 v) po wer supply (C); gnd po wer supply (+) f or pll (pl v dd = v dd ) po wer supply (C) f or pll (pl v ss = v ss ) po wer supply (+) f or analog system and ain0Cain4 (3.3 v, av dd = v ddh ) qfp 23,38,59,86,96,123 16,30,67,91,105,128 7,41,62,81,101,117,135 44 42 47 pin no. pin name v dd v ddh v ss pl v dd pl v ss av dd pfbga d7,e6,e7,f10,f11,g4, g11,h4,h5,k7,n2,n8 d8,e8,e9,f4,f5,g5,g10, h10,h11,k8,k9,l9 d4,d5,d6,d11,e5,e10, e11,j5,j10,j11,k5,k6, k10,k11,n3,n9 p5 p4 p6 i/o interface circuit cpu core internal logic circuits v dd 1.65 to 1.95 v (1.70 to 1.90 v ? 1 ) v ss gnd plv dd 1.65 to 1.95 v v ddh 2.70 to 3.60 v (3.00 to 3.60 v ? 2 ) plv ss gnd oscillator circuits pll ? 1 when the ceramic oscillator circuit is used ? 2 when the usb function controller is used analog circuits (a/d converter) av dd 2.70 to 3.60 v figure i.4.1.1 power supply system
i s1c33e08 specifications: power supply i-4-2 epson s1c33e08 technical manual i.4.2 operating voltage (v dd , v ss ) the core cpu and internal logic circuits operate with a voltage supplied between the v dd and v ss pins. the following operating voltage can be used: v dd = 1.65 v to 1.95 v (1.8 v 0.15 v, v ss = gnd) or v dd = 1.70 v to 1.90 v (1.8 v 0.10 v, v ss = gnd) when the ceramic oscillator circuit is used note : the s1c33e08 qfp package has six v dd pins and seven v ss pins; the pfbga package has 12 v dd pins and 16 v ss pins. be sure to supply the operating voltage to all the pins. do not open any of them. i.4.3 power supply for pll (plv dd , plv ss ) the pll power supply pins (plv dd , plv ss ) are provided separately from the v dd and v ss pins in order that the digital circuits do not affect the pll circuit. supply the same voltage level as the v dd to the plv dd pin. plv dd = v dd , plv ss = v ss noise on the pll power lines decrease the pll output precision, so use a stabilized power supply and make the board pattern with consideration given to that. i.4.4 power supply for i/o interface (v ddh ) the v ddh voltage is used for interfacing with external i/o signals. for the output interface of the s 1c33e08 , the v ddh voltage is used as high level and the v ss voltage as low level. the v ss pin is used for the ground common with v dd . the following voltage is enabled for v ddh : v ddh = 2.70 v to 3.60 v (v ss = gnd) when the usb function controller is not used or v ddh = 3.00 v to 3.60 v (3.3 v 0.3 v, v ss = gnd) when the usb function controller is used notes : ? the s1c33e08 qfp package has six v ddh pins; the pfbga package has 12 v ddh pins. be sure to supply the operating voltage to all the pins. do not open any of them. ? when an external clock is input to the mclki or rtc_clki pin, the clock signal level must be v dd . i.4.5 power supply for analog circuits (av dd ) the analog power supply pin (av dd ) is provided separately from the v dd and v ddh pins in order that the digital circuits do not affect the analog circuit (a/d converter). the av dd pin is used to supply an analog power voltage and the v ss pin is used as the analog ground. the following voltage is enabled for av dd : av dd = 2.70 v to 3.60 v (3.0/3.3 v 0.3 v, v ss = gnd) note : be sure to supply v ddh to the av dd pin when the analog circuit is not used. noise on the analog power lines decrease the a/d converting precision, so use a stabilized power supply and make the board pattern with consideration given to that.
i s1c33e08 specifications: power supply s1c33e08 technical manual epson i-4-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.4.6 precautions on power supply power-on sequence in order to operate the device normally, supply power in accordance with the following timing. v ddh , av dd v dd , plv dd osc3 #reset v dd min. t vdd t sta3 t rst figure i.4.6.1 power-on sequence (1) t vdd : elapsed time until the power supply stabilizes after power-on supply power in the following sequence (or simultaneously). power-on: v dd and plv dd (internal) v ddh and av dd (i/o) apply the input signal (2) t sta 3 : time at which osc 3 oscillation starts (3) t rst : minimum reset pulse width time at which the clock supplied to the chip stabilizes plus at least six clocks; keep the #reset signal low. power-off sequence shut off the power supply in the following sequence (or simultaneously). power-off: turn off the input signal av dd and v ddh (i/o) plv dd and v dd (internal) latch-up the cmos device may be in the latch-up condition. this is the phenomenon caused by conduction of the parasitic pnpn junction (thyristor) contained in the cmos ic, resulting in a large current between v dd and v ss and leading to breakage. latch-up occurs when the voltage applied to the input / output exceeds the rated value and a large current flows into the internal element, or when the voltage at the v dd pin exceeds the rated value and the internal element is in the breakdown condition. in the latter case, even if the application of a voltage exceeding the rated value is instantaneous, the current remains high between v dd and v ss once the device is in the latch-up condition. as this may result in heat generation or smoking, the following points must be taken into consideration: (1 ) the voltage level at the input / output must not exceed the range specified in the electrical characteristics. in other words, it must be below the power-supply voltage and above v ss . the power-on timing should also be taken into consideration. (2 ) abnormal noise must not be applied to the device. (3 ) the potential at the unused input should be fixed at v dd , v ddh , av dd , or v ss . (4) no outputs should be shorted.
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i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5 cpu core and bus architecture the s1c33e08 contains the c33 pe core as its core processor. the c 33 pe (processor element) core is a seiko epson original 32 -bit risc-type core processor for the s1c33 family microprocessors. based on the c 33 std core cpu features, some useful c33 adv core functions/ instructions were added and some of the infrequently used ones in general applications are removed to realize a high cost-performance core unit with high processing speed. the c 33 pe core has been designed with optimization for embedded applications (full rtl design) in mind to short development time and to reduce cost. as the principal instructions are object-code compatible with the c 33 std core cpu, the software assets that the user has accumulated in the past can be effectively utilized. for details of the c 33 pe core, refer to the s1c33 family c33 pe core manual. i.5.1 features of the c33 pe core processor type ? seiko epson original 32-bit risc processor ? 32-bit internal data processing ? contains a 32-bit 8-bit multiplier operating-clock frequency ? dc to 66 mhz or higher (depending on the processor model and process technology) instruction set ? code length 16 -bit fixed length ? number of instructions 125 ? execution cycle main instructions executed in one cycles ? extended immediate instructions immediate extended up to 32 bits ? multiplication instructions multiplications for 16 16 and 32 32 bits supported register set ? 32 -bit general-purpose registers ? 32 -bit special registers memory space and external bus ? instruction, data, and i/o coexisting linear space ? up to 4g bytes of memory space ? harvard architecture using separated instruction bus and data bus interrupts ? reset, nmi, and 240 external interrupts supported ? four software exceptions ? three instruction execution exceptions ? direct branching from vector table to interrupt handler routine power-down mode ? halt mode ? sleep mode
i s1c33e08 specifications: cpu core and bus architecture i-5-2 epson s1c33e08 technical manual i.5.2 cpu registers the c33 pe core contains 16 general-purpose registers and 8 special registers. r15 r14 r13 r12 r11 r10 r4 r5 r6 r7 r8 r9 r3 r2 r1 r0 bit 31 bit 0 general-purpose registers pc ttbr bit 31 #15 #11 #10 #8 #3 #2 #1 #0 #15 #14 #13 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 bit 0 ahr alr psr sp idir dbbr special registers figure i.5.2.1 registers
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.3 instruction set the c 33 pe core instruction set consists of the function-extended instruction set of the c33 std core cpu and the new instructions, in addition to the conventional s 1c33 -series instructions. some instructions of the c33 std core cpu are deleted. as the c 33 pe core is object-code compatible with the c33 std core cpu, software assets can be transported from the s1c33 series to the c33 pe model easily, with minimal modifications required. all of the instruction codes are fixed to 16 bits in length which, combined with pipelined processing, allows most important instructions to be executed in one cycle. for details, refer to the s1c33 family c33 pe core manual. table i.5.3.1 s1c33-series-compatible instructions classification ar ithmetic operation branch function addition between general-pur pose registers addition of a general-pur pose register and immediate addition of sp and immediate (with immediate z ero-e xtended) addition with carr y between general-pur pose registers subtraction between general-purpose registers subtraction of general-pur pose register and immediate subtraction of sp and immediate (with immediate z ero-e xtended) subtraction with carr y between general-pur pose registers ar ithmetic compar ison between general-pur pose registers ar ithmetic compar ison of general-pur pose register and immediate (with immediate z ero-e xtended) signed integer multiplication (16 bits 16 bits 32 bits) unsigned integer multiplication (16 bits 16 bits 32 bits) signed integer multiplication (32 bits 32 bits 64 bits) unsigned integer multiplication (32 bits 32 bits 64 bits) pc relativ e conditional jump branch condition: !z & !(n ^ v) dela y ed branching possib le pc relativ e conditional jump branch condition: !(n ^ v) dela y ed branching possib le pc relativ e conditional jump branch condition: n ^ v dela y ed branching possib le pc relativ e conditional jump branch condition: z | n ^ v dela y ed branching possib le pc relativ e conditional jump branch condition: !z & !c dela y ed branching possib le pc relativ e conditional jump branch condition: !c dela y ed branching possib le pc relativ e conditional jump branch condition: c dela y ed branching possib le pc relativ e conditional jump branch condition: z | c dela y ed branching possib le pc relativ e conditional jump branch condition: z dela y ed branching possib le pc relativ e conditional jump branch condition: !z dela y ed branching possib le pc relativ e jump dela y ed branching possib le absolute jump dela y ed branching possib le pc relativ e subroutine call dela y ed call possib le absolute subroutine call dela y ed call possib le subroutine retur n dela y ed retur n possib le retur n from interr upt or e xception handling retur n from the deb ug processing routine softw are e xception deb ug e xception add adc sub sbc cmp mlt.h mltu.h mlt.w mltu.w jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d jp jp.d call call.d ret ret.d reti retd int brk %rd,%rs %rd,imm6 %sp,imm10 %rd,%rs %rd,%rs %rd,imm6 %sp,imm10 %rd,%rs %rd,%rs %rd,sign6 %rd,%rs %rd,%rs %rd,%rs %rd,%rs sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 %rb sign8 %rb imm2 mnemonic
i s1c33e08 specifications: cpu core and bus architecture i-5-4 epson s1c33e08 technical manual classification data transf er system control immediate e xtension bit manipulation other function general-pur pose register (b yte) general-pur pose register (sign-e xtended) memor y (b yte) general-pur pose register (sign-e xtended) p ostincrement possib le stac k (b yte) general-pur pose register (sign-e xtended) general-pur pose register (b yte) memor y p ostincrement possib le general-pur pose register (b yte) stac k general-pur pose register (b yte) general-pur pose register (z ero-e xtended) memor y (b yte) general-pur pose register (z ero-e xtended) p ostincrement possib le stac k (b yte) general-pur pose register (z ero-e xtended) general-pur pose register (halfword) general-pur pose register (sign-e xtended) memor y (halfword) general-pur pose register (sign-e xtended) p ostincrement possib le stac k (halfword) general-pur pose register (sign-e xtended) general-pur pose register (halfword) memor y p ostincrement possib le general-pur pose register (halfword) stac k general-pur pose register (halfword) general-pur pose register (z ero-e xtended) memor y (halfword) general-pur pose register (z ero-e xtended) p ostincrement possib le stac k (halfword) general-pur pose register (z ero-e xtended) general-pur pose register (word) general-pur pose register immediate general-pur pose register (sign-e xtended) memor y (word) general-pur pose register p ostincrement possib le stac k (word) general-pur pose register general-pur pose register (word) memor y p ostincrement possib le general-pur pose register (word) stac k no operation hal t sleep extend operand in the f ollo wing instr uction t est a specified bit in memor y data clear a specified bit in memor y data set a specified bit in memor y data in ve rt a specified bit in memor y data byte wise sw ap on b yte boundar y in word push general-pur pose registers %rs C%r0 onto the stac k p op data f or general-pur pose registers %rd C%r0 off the stac k ld.b ld.ub ld.h ld.uh ld.w nop halt slp ext btst bclr bset bnot swap pushn popn %rd,%rs %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] [%rb ],%rs [%rb ]+,%rs [%sp+imm6 ],%rs %rd,%rs %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] %rd,%rs %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] [%rb ],%rs [%rb]+,%rs [%sp+imm6 ],%rs %rd,%rs %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] %rd,%rs %rd,sign6 %rd, [%rb ] %rd, [%rb]+ %rd,[%sp+imm6 ] [%rb ],%rs [%rb]+,%rs [%sp+imm6 ],%rs imm13 [%rb ],imm3 [%rb ],imm3 [%rb ],imm3 [%rb ],imm3 %rd,%rs %rs %rd mnemonic the symbols in the above table each have the meanings specified below. table i.5.3.2 symbol meanings symbol %rs %rd %ss %sd [ %rb ] [ %rb ]+ %sp imm2,imm4,imm3, imm5,imm6,imm10, imm13 sign6,sign8 description general-pur pose register , source general-pur pose register , destination special register , source special register , destination general-pur pose register , indirect addressing general-pur pose register , indirect addressing with postincrement stac k pointer unsigned immediate (numerals indicating bit length) ho we ve r, numerals in shift instr uctions indicate the number of bits shifted, while those in bit manipulation indicate bit positions . signed immediate (numerals indicating bit length)
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 table i.5.3.3 function extended instructions classification logical operation shift and rotate data transf er function logical and between general-pur pose registers logical and of general-pur pose register and immediate logical or between general-pur pose registers logical or of general-pur pose register and immediate exclusiv e or between general-pur pose registers exclusiv e or of general-pur pose register and immediate logical in v ersion between general-pur pose registers (1's complement) logical in v ersion of general-pur pose register and immediate (1's complement) logical shift to the r ight (bits 0C31 shifted as specified by the register) logical shift to the r ight (bits 0C31 shifted as specified by immediate) logical shift to the left (bits 0C31 shifted as specified by the register) logical shift to the left (bits 0C31 shifted as specified by immediate) ar ithmetic shift to the r ight (bits 0C31 shifted as specified by the register) ar ithmetic shift to the r ight (bits 0C31 shifted as specified by immediate) ar ithmetic shift to the left (bits 0C31 shifted as specified by the register) ar ithmetic shift to the left (bits 0C31 shifted as specified by immediate) rotate to the r ight (bits 0C31 rotated as specified by the register) rotate to the r ight (bits 0C31 rotated as specified by immediate) rotate to the left (bits 0C31 rotated as specified by the register) rotate to the left (bits 0C31 rotated as specified by immediate) special register (word) general-pur pose register general-pur pose register (word) special register extended function the v flag is cleared after the instr uction has been ex ecuted. f or rotate/shift operation, it has been made possib le to shift 9C31 bits . the number of special registers that can be used to load data has been increased. and or xor not srl sll sra sla rr rl ld.w %rd,%rs %rd,sign6 %rd,%rs %rd,sign6 %rd,%rs %rd,sign6 %rd,%rs %rd,sign6 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%rs %rd,imm5 %rd,%ss %sd,%rs mnemonic
i s1c33e08 specifications: cpu core and bus architecture i-5-6 epson s1c33e08 technical manual table i.5.3.4 instructions added to the c33 pe core classification branch system control coprocessor control other function pc relativ e jump dela y ed branching possib le set a specified bit in psr clear a specified bit in psr load data from coprocessor store data in coprocessor ex ecute coprocessor load c, v, z, and n flags from coprocessor byte wise sw ap on halfword boundar y in word push single general-pur pose register p op single general-pur pose register push special registers %ssCalr onto the stac k p op data f or special registers %sdCalr off the stac k jpr jpr.d psrset psrclr ld.c ld.c do.c ld.cf swaph push pop pushs pops %rb imm5 imm5 %rd,imm4 imm4,%rs imm6 %rd,%rs %rs %rd %ss %sd mnemonic table i.5.3.5 instructions removed classification ar ithmetic operation other function first step in signed integer division first step in unsigned integer division ex ecution of step division data correction f or the result of signed integer division 1 data correction f or the result of signed integer division 2 bitwise sw ap ev er y b yte in word multiply-accumulate operation 16 bits 16 bits + 64 bits 64 bits search f or bits whose v alue = 0 search f or bits whose v alue = 1 div0s div0u div1 div2s div3s mirror mac scan0 scan1 %rs %rs %rs %rs %rd,%rs %rs %rd,%rs %rd,%rs mnemonic
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-7 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.4 trap table the c33 pe core allows the base (starting) address of the trap table to be set by the ttbr register. after an initial reset, the ttbr register is set to 0xc00000. therefore, even when the trap table position is changed, it is necessary that at least the reset vector be written to the above address. bits 9 to 0 in the ttbr register are fixed at 0 . therefore, the trap table starting address always begins with a 1kb boundary address. table i.5.4.1 trap table idma ch. C C C C C C C C C C C C C C 1 2 3 4 C C 5 6 C C C C 7 8 C 9 10 C 11 12 C 13 14 C 15 16 C 17 18 C priority 1 C 4 3 C 2 5 6 C high lo w v ector number (he x address) 0(base) 1 2(base+8) 3(base+0c) 4C5 6(base+18) 0x60000 7(base+1c) 8C10 11(base+2c) 12(base+30) 13(base+34) 14(base+38) 15(base+3c) 16(base+40) 17(base+44) 18(base+48) 19(base+4c) 20(base+50) 21(base+54) 22(base+58) 23(base+5c) 24(base+60) 25(base+64) 26(base+68) 27C29 30(base+78) 31(base+7c) 32C33 34(base+88) 35(base+8c) 36C37 38(base+98) 39(base+9c) 40C41 42(base+a8) 43(base+a c) 44C45 46(base+b8) 47(base+bc) 48C49 50(base+c8) 51(base+cc) 52C55 exception/interrupt name (peripheral cir cuit) reset reser ve d ext e xception undefined instr uction e xception reser ve d address misaligned e xception deb ugging e xception nmi reser ve d illegal interr upt e xception softw are e xception 0 softw are e xception 1 softw are e xception 2 softw are e xception 3 po rt input interr upt 0 po rt input interr upt 1 po rt input interr upt 2 po rt input interr upt 3 ke y input interr upt 0 ke y input interr upt 1 high-speed dma ch.0 high-speed dma ch.1 high-speed dma ch.2 high-speed dma ch.3 intelligent dma reser ve d 16-bit timer 0 reser ve d 16-bit timer 1 reser ve d 16-bit timer 2 reser ve d 16-bit timer 3 reser ve d 16-bit timer 4 reser ve d 16-bit timer 5 reser ve d cause of e xception/interrupt lo w input to the reset pin C ext instr uction (illegal use) undefined instr uction C memor y access instr uction brk instr uction, etc. lo w input to the #nmi pin or w atchdog timer ov erflo w C occurrence of illegal interr upt from itc int instr uction int instr uction int instr uction int instr uction edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) rising or f alling edge rising or f alling edge high-speed dma ch.0, end of transf er high-speed dma ch.1, end of transf er high-speed dma ch.2, end of transf er high-speed dma ch.3, end of transf er intelligent dma, end of transf er C timer 0 compare-match b timer 0 compare-match a C timer 1 compare-match b timer 1 compare-match a C timer 2 compare-match b timer 2 compare-match a C timer 3 compare-match b timer 3 compare-match a C timer 4 compare-match b timer 4 compare-match a C timer 5 compare-match b timer 5 compare-match a C
i s1c33e08 specifications: cpu core and bus architecture i-5-8 epson s1c33e08 technical manual idma ch. C 23 24 C C 25 26 C 27 C C 28 29 30 31 C 33 C C 34 35 C 36 37 C 38 39 40 41 42 43 44 45 C 46 C priority high lo w v ector number (he x address) 56(base+e0) 57(base+e4) 58(base+e8) 59 60(base+f0) 61(base+f4) 62(base+f8) 63(base+fc) 64(base+100) 65(base+104) 66C67 68(base+110) 69(base+114) 70(base+118) 71(base+11c) 72(base+120) 73(base+124) 74C75 76(base+130) 77(base+134) 78(base+138) 79C80 81(base+144) 82(base+148) 83 84(base+150) 85(base+154) 86(base+158) 87(base+15c) 88(base+160) 89(base+164) 90(base+168) 91(base+16c) 92C93 94(base+178) 95C107 exception/interrupt name (peripheral cir cuit) ser ial interf ace ch.0 reser ve d ser ial interf ace ch.1 a/d con ve r ter rt c reser ve d po rt input interr upt 4 po rt input interr upt 5 po rt input interr upt 6 po rt input interr upt 7 reser ve d lcdc reser ve d ser ial interf ace ch.2 reser ve d spi reser ve d po rt input interr upt 8 spi po rt input interr upt 9 usb pdreq po rt input interr upt 10 usb po rt input interr upt 11 dcsio po rt input interr upt 12 po rt input interr upt 13 po rt input interr upt 14 po rt input interr upt 15 reser ve d i 2 s interf ace reser ve d cause of e xception/interrupt receiv e error receiv e b uff er full tr ansmit b uff er empty C receiv e error receiv e b uff er full tr ansmit b uff er empty result out of range (upper-limit and lo wer-limit) end of con v ersion 1/64 second, 1 second, 1 minuet, or 1 hour count up C edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) C end of frame C receiv e error receiv e b uff er full tr ansmit b uff er empty C receiv e dma request tr ansmit dma request C edge (r ising or f alling) or le v el (high or lo w) spi interr upt (d[1:0]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) usb dma request (d[3:2]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) usb interr upt (d[5:4]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) dcsio interr upt (d[7:6]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) C i 2 s fifo empty C notes : ? the mp3 decoder bios (mp3 decoder module) uses the hsdma ch.0 , ch.1 and i 2 s and their interrupts for output data requests. therefore, these dma channels and interrupts cannot be used in the user program. ? idma ch.19C22, 32, 47C53 are reserved.
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-9 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.5 power-down mode the c33 pe core supports two power-down modes: halt and sleep modes. halt mode program execution is halted at the same time that the c 33 pe core executes the halt instruction, and the processor enters halt mode. halt mode commonly turns off only the c 33 pe core operation. see section iii.1.11, standby modes, for details. sleep mode program execution is halted at the same time the c 33 pe core executes the slp instruction, and the processor enters sleep mode. sleep mode commonly turns off the c 33 pe core and on-chip peripheral circuit operations, thereby it significantly reduces the current consumption in comparison to the halt mode. see section iii. 1.11, standby modes, for details. canceling halt or sleep mode initial reset, maskable external interrupts, nmi, and debug exceptions are commonly used for canceling halt and sleep modes. the interrupt enable/disable status set in the processor does not affect the cancellation of halt or sleep mode even if an interrupt signal is used as the cancellation. in other words, interrupt signals are able to cancel halt and sleep modes even if the ie flag in psr or the interrupt enable bits in the interrupt controller (depending on the implementation) are set to disable interrupts. when the processor is taken out of halt or sleep mode using an interrupt that has been enabled (by the interrupt controller and ie flag), the corresponding interrupt handler routine is executed. therefore, when the interrupt handler routine is terminated by the reti instruction, the processor returns to the instruction next to halt or slp . when the interrupt has been disabled, the processor restarts the program from the instruction next to halt or slp after the processor is taken out of halt or sleep mode.
i s1c33e08 specifications: cpu core and bus architecture i-5-10 epson s1c33e08 technical manual i.5.6 debug mode the c33 pe core has debug mode to assist in software development by the user. the debug mode provides the following functions: ? instruction break a debug exception is generated before the set instruction address is executed. an instruction break can be set at three addresses. ? data break a debug exception is generated when the set address is accessed for read or write. a data break can be set at only one address. ? single step a debug exception is generated every instruction executed. ? forcible break a debug exception is generated by an external input signal. ? bus break a debug exception is generated when the data of the selected bus matches the set value. ? bus trace the value of the selected bus is traced. ? pc trace the status of instruction execution by the processor is traced. when a debug exception occurs, the processor performs the following processing: (1 ) suspends the instruction currently being executed. a debug exception is generated at the end of the e stage of the currently executed instruction, and is accepted at the next rise of the system clock. (2 ) saves the contents of the pc and r0 , in that order, to the addresses specified below. pc 0x00060008 r 0 0x0006000c (3 ) loads the debug exception vector located at the address 0 x 00060000 to pc and branches to the debug exception handler routine. in the exception handler routine, the retd instruction should be executed at the end of processing to return to the suspended instruction. when returning from the exception by the retd instruction, the processor restores the saved data in order of the r0 and the pc. neither hardware interrupts nor nmi interrupts are accepted during a debug exception.
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-11 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.7 bus architecture pe_e08_cpu lcdc area 6 ivram (12kb) ivram arbiter dqb dqb arbiter iqb dst ram (2kb) area 3 sdramc_ip mux exter nal memor y i/f a6dec sd app1 < < < x32 < < cpu_ahb lcdc_ahb lcdc_amb a: master dma gp: master 2 internal peripheral modules external de vices external bu s sapb bu s s1c33pe_amb a: master 1 sd app2 sdramc sramc (sapb bridge) hsdma idma dma gp registers dma gp x32 x32 x32 x32 x32 x16 x16 x16 x32 figure i.5.7.1 s1c33e08 bus architecture i.5.7.1 32-bit high-speed bus since the ivram (internal video ram) or an external sdram may be simultaneously accessed from the cpu and the lcdc, the s 1c33e08 adopts a dual 32 -bit high-speed bus system that consists of the cpu_ahb bus and lcdc_ahb bus to reduce bus occupancy by one bus master. the c 33 pe core, dmac, sramc, instruction/data caches in sdramc, ivram arbiter and dst ram in area 3 are connected to the cpu_ahb bus. usually the c33 pe core is the bus master of the cpu_ahb bus and the ownership of the bus is delegated to the dmac when a dma request is generated. the lcdc, ivram arbiter and lcdc data cache in sdramc are connected to the lcdc_ahb bus. the lcdc_ahb bus master is always the lcdc. the ivram arbiter is connected to both the cpu_ahb and lcdc_ahb buses and it arbitrates accesses to the ivram from the cpu and lcdc. the lcdc has higher priority than the cpu for the ivram access authorization as it must refresh the lcd display. for details of the ivram arbiter, see section viii. 2, ivram and ivram arbiter. likewise the sdramc is connected to the both buses allowing the cpu and lcdc to access the external sdram. also in this case the lcdc has higher priority. the bus arbiter in the sdramc arbitrates the ownership of the bus between the cpu and lcdc. for details of the bus arbiter, see section ii. 4.3, bus arbiter.
i s1c33e08 specifications: cpu core and bus architecture i-5-12 epson s1c33e08 technical manual i.5.7.2 sapb bus the sapb bus is used to access the internal peripheral modules located in area 6 . the sramc functions as a bridge between the cpu_ahb bus and sapb bus. i.5.7.3 external bus the s1c33e08 external bus is configured with a 25 -bit address bus and a 16 -bit data bus. the external sdram is accessed via the sdramc and other devices are accessed via the sramc. the bus arbiter in the sdramc arbitrates the access authorization for t he external bus. for more information on the external memory, see section i. 6, memory map, section ii.3, sram controller (sramc), and section ii.4, sdram controller (sdramc).
i s1c33e08 specifications: cpu core and bus architecture s1c33e08 technical manual epson i-5-13 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.5.8 chip id the s 1c33e08 has chip id bits shown below that allow the application software to identify cpu type, model, and chip version. core id bits (d[7:0]/0x20000) these bits provide an 8-bit id code that indicates the chip core type. id chip core type 0x02 c33 standard macro core (c33 std core) 0x03 c33 mini-macro core 0x04 c33 advanced macro core (c33 adv core) 0x05 c33 pe core 0x06 c33 pe little endian core the s 1c33e08 has adopted the c33 pe little endian core, so the chip core id is 0x06. product series id bits (d[ 7:0]/0x20001) these bits provide an 8-bit id code that indicates the product series of the s1c33 family. id product series 0x03 s1c333xx series 0x04 s1c334xx series 0x0 e s1c33exx series 0x15 s1c33lxx series the product series id of the s 1c33e08 is 0x0e. model id bits (d[7:0]/0x20002) these bits provide an 8-bit id code that indicates the model. the model id of the s 1c33e07/e08 is 0x07. version bits (d[ 7:0]/0x20003) these bits provide an 8 -bit id code that indicates the version number. 0x22 is a version number.
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i s1c33e08 specifications: memory map s1c33e08 technical manual epson i-6-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.6 memory map figure i. 6.1 shows a memory map of the entire address space of the s1c33e08 . figure i.6.2 shows a memory map of internal memory and the internal i/o space of the s1c33e08. area 13 0x02ff ffff 0x0200 0000 area 12 0x01ff ffff 0x0180 0000 area 11 0x017f ffff 0x0100 0000 area 10 0x00ff ffff 0x00c0 0000 area 9 0x00bf ffff 0x0080 0000 area 8 0x007f ffff 0x0060 0000 area 7 0x005f ffff 0x0040 0000 area 6 0x003f ffff 0x0030 0000 ip and peripherals (reserved for ip and peripherals) area 5 0x002f ffff 0x0020 0000 area 4 0x001f ffff 0x0010 0000 area 3 0x000f ffff 0x0008 0000 internal ram area area 2 0x0007 ffff 0x0006 0000 reserved for debugging area 1 0x0005 ffff 0x0002 0000 specific rom area (reserved) area 0 0x0001 ffff 0x0000 0000 area 22 0xffff ffff 0x8000 0000 area 21 0x7fff ffff 0x4000 0000 area 20 0x3fff ffff 0x2000 0000 area 19 0x1fff ffff 0x1000 0000 area 18 0x0fff ffff 0x0c00 0000 area 17 0x0bff ffff 0x0800 0000 area 16 0x07ff ffff 0x0600 0000 area 15 0x05ff ffff 0x0400 0000 area 14 0x03ff ffff 0x0300 0000 internal ram area external memory 16m bytes external memory 8m bytes external memory 8m bytes external memory 4m bytes external memory 4m bytes external memory 2m bytes external memory 2m bytes external memory 1m bytes external memory 1m bytes external memory 2g bytes external memory 1g bytes external memory 512m bytes external memory 256m bytes external memory 64m bytes external memory 64m bytes external memory 32m bytes external memory 32m bytes external memory 16m bytes #ce10 #ce11 #ce11 #ce10 #ce9 #ce8 #ce7 #ce5 #ce4 #ce9 #ce7 * #ce8 #ce10 #ce7 #ce6 #ce6 #ce5 #ce5 #ce4 (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) 4-word gate rom (reserved) (reserved) (reserved) (reserved) (reserved) internal areas external areas usable as memory space for smartmedia (nand flash), compactflash, or pc card. ? see note below. figure i.6.1 general memory map notes : area 22 is assigned to #ce9 in default settings. note that area 22 will be reassigned to #ce7 when the sdramc is enabled. a minimum 20 k bytes of external ram is required for using the mp3 decoder bios.
i s1c33e08 specifications: memory map i-6-2 epson s1c33e08 technical manual area 2 0x0007 ffff 0x0006 0000 reserved for debugging area 0 0x0001 ffff 0x0000 8000 0x0000 4fff 0x0000 2000 0x0000 1fff 0x0000 0000 a0ram (12kb) a0ram (8kb) (reserved) area 3 0x000f ffff 0x0008 4800 0x0008 47ff 0x0008 4000 0x0008 3fff 0x0008 3000 0x0008 2fff 0x0008 0000 ivram (12kb) dst ram (2kb) (reserved) (reserved) area 1 0x0005 ffff 0x0003 0000 0x0002 ffff 0x0002 0000 area 6 0x003f ffff 0x0030 2000 0x0030 1fff 0x0030 0000 ip and peripherals (reserved) specific rom (reserved for firmware) (reserved) internal i/o 0x301c00C0x301c20 0x301b00C0x301b24 0x301a00C0x301aac 0x301900C0x301928 0x301800C0x30181c 0x301700C0x30171c 0x301600C0x301610 0x301500C0x301510 0x301120C0x30119e 0x301100C0x301105 0x300c40C0x300c4d 0x300c00C0x300c25 0x300b00C0x300b4f 0x300a00C0x300aff 0x300900C0x30099f 0x300780C0x3007ea 0x300660C0x30066c 0x300520C0x30055e 0x300380C0x3003d5 0x300300C0x30031b 0x300260C0x3002af 0x300010C0x300020 i 2 s interface clock management unit lcd controller real time clock dcsio spi sdram controller sram controller high-speed dma intelligent dma misc register (2) extended ports serial interface usb dma area usb function controller 16-bit timer watchdog timer a/d converter i/o ports card interface interrupt controller misc register (1) internal areas the 12kb ivram can be moved to area 0 for use as a general-purpose ram (a part of the a0ram) if the lcdc is not using the ivram. an lcdc register is used to configure ivram. figure i.6.2 internal area map (when mp3 decoder bios is not used) area 2 0x0007 ffff 0x0006 0000 area 0 0x0001 ffff 0x0000 0400 0x0000 03ff 0x0000 0000 a0ram (1kb) reserved for mp3 decoder area 3 0x000f ffff 0x0008 4800 0x0008 47ff 0x0008 4000 0x0008 3fff 0x0008 3000 0x0008 2fff 0x0008 0000 ivram (12kb) dst ram (2kb) (reserved) (reserved) area 1 0x0005 ffff 0x0003 0000 0x0002 ffff 0x0002 0000 area 6 0x003f ffff 0x0030 2000 0x0030 1fff 0x0030 0000 ip and peripherals (reserved) specific rom (reserved for firmware) (reserved) reserved for debugging internal areas the mp3 decoder bios (mp3 decoder module) uses 7kb of a0ram (0x0400C0x1fff) and 12kb of ivram (located in area 0) as an mp3 work area. when using the mp3 calculation module only (when user's mp3 decoder routine is used), a0ram and ivram may be used in the user program. see figure i.6.2 figure i.6.3 internal area map (when mp3 decoder bios is used) the following describes the area configuration of the s 1c33e08.
i s1c33e08 specifications: memory map s1c33e08 technical manual epson i-6-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.6.1 boot address and gate rom when the chip is powered on or reset, the boot address is set to 0xc00000 (initial value of ttbr) by the c33 pe core. in the s 1c33e08 , a 4 -word gate rom is located at address 0xc00000 in area 10 (internal area), and the vectors written to it are used to start a boot sequence regardless whether an external memory is connected to area 10 or not. the vector written in the gate rom, which boots up the system, is determined by the input status of the boot pins. also the #ce 10 pin is used to set the boot mode. by setting these pins, the s1c33e08 boots up from a nand flash, spi-eeprom, pc (rs- 232 c), or an external nor-flash/rom. the boot sequence has been programmed in the specific rom located in area 1. tables i. 6.1.1 and i.6.1.2 list the pin configurations and the boot mode selected. for more information on boot, see appendix d, boot. table i.6.1.1 boot mode configuration (pfbga-180pin or die model) boo t1 pin 1 1 0 0 boot mode spi-eepr om pc rs232c nor flash/e xter nal ro m reser ve d large-page nand flash (> 1024 + 32 b ytes/page) small-page nand flash (< 1024 + 32 b ytes/page) boo t0 pin 1 0 1 0 #ce10 1 (input) 0 (input) output C 1 (input) 0 (input) boot code star t address 0x20010 in the inter nal r om (area 1) 0x2000c in the inter nal r om (area 1) C 0x20004 in the inter nal r om (area 1) mbr ex ecution address 0x0 in a0ram depending on the contents in 0xc00000 C 0x0 in a0ram table i.6.1.2 boot mode configuration (qfp-144pin model) boo t1 pin 1 0 boot mode nor flash/e xter nal ro m large-page nand flash (> 1024 + 32 b ytes/page) small-page nand flash (< 1024 + 32 b ytes/page) #ce10 output 1 (input) 0 (input) boot code star t address 0x2000c in the inter nal r om (area 1) 0x20004 in the inter nal r om (area 1) mbr ex ecution address depending on the contents in 0xc00000 0x0 in a0ram ? the qfp- 144 pin does not have the boot0 pin due to the limited number of pins available (boot 0 has been pulled down to v ss inside the ic). i.6.2 area 0 (a0ram) area 0 contains an 8k-byte high-speed ram (a0ram). its location address ranges from 0x0 to 0x1 fff. moreover, the s 1c33e08 has a built-in 12 k-byte ram (ivram) to be used as a video ram for the lcdc, which is located in area 3 by default. if ivram is not required for use as a video ram (e.g. when the lcdc is not used or when an external sdram is used as a video ram), ivram can be moved to area 0 to expand a0 ram into 20 k bytes. the lcdc provides the control bit iram (d 0 / 0 x 301 a 64 ) for this switch over. when iram = 0 (default), ivram is located in area 3 and when iram = 1 , ivram is located at 0x2000 to 0x4 fff in area 0 (immediately following 8 k-byte a0ram). ? iram : iram assign bit in the iram select register (d0/0x301a64) since a 0 ram (including ivram located in area 0 ) is accessed directly from the cpu without passing through the ahb bus, no wait cycles are inserted. a 0 ram is accessed in one cycle (with no wait cycle), regardless of whether accessed in units of bytes, half-words, or words. moreover, due to a harvard architecture, a 0 ram can be accessed simultaneously with the fetching of instructions from external memory (cache).
i s1c33e08 specifications: memory map i-6-4 epson s1c33e08 technical manual notes : ? a0 ram cannot contain idma control words or be specified as the source or destination of dma transfer. ? when the debug monitor s5u1c330m2d1 (mon33 ) is used to debug, addresses 0x0 to 0 xf are configured as an area for debugging. the s5u1c330m2d1 does not allow the user program to access this address range. when only the s 5u1c33001 h (icd33 ) is used for debugging, this area can be accessed by the user. ? the mp3 decoder bios (mp3 decoder module) uses 7 kb of a0 ram (0x0400C0x1 fff) and 12 kb of ivram (located in area 0 ) as an mp3 work area. when using the mp3 calculation module only (when user's mp 3 decoder routine is used), a0 ram and ivram may be used in the user program. i.6.3 area 1 (specific rom for firmware) area 1 contains a 64 k-byte mask rom. this rom is reserved for firmware to support booting and the mp3 decoder bios, therefore it does not contain a user program. the mp 3 decoder bios provides the mp3 data decoding and playback api functions. for details of the mp3 decoder, refer to section x. 1, mp3 decoder. i.6.4 area 2 (debug area) area 2 is a debugging-only area allocated for debugging resources. this area can only be accessed for writing in debug mode. make sure this area is not accessed from the user program or debugger. i.6.5 area 3 (ivram) 0x80000 to 0x82 fff in area 3 is allocated to the 12 k-byte ivram (internal video ram) by the default configuration. ivram can be used as a video ram for the lcdc. the lcdc and cpu access ivram through their respective 32 -bit ahb bus and the ivram arbiter that resolves bus conflicts between the lcdc and cpu. ivram located in area 3 can be accessed in a minimum of 2 -wait cycles. as described in section i. 6.2 , ivram can be located in area 0 for use as a high-speed general-purpose ram that allows no wait access when it is not used as a video ram. notes : ? a program cannot be executed in the ivram located in area 3. ? when using the mp3 decoder bios (mp3 decoder module), the ivram will be relocated to area 0 to be used as an mp3 work area by an api function. in this case, an external sdram must be used as the vram. i.6.6 area 3 (dst ram) 0x84000 to 0x847 ff in area 3 is allocated to the 2 k-byte dst ram (descriptor table ram). dst ram is provided for storing idma control words as a 0 ram cannot contain them. the memory space other than control words can be used as a general-purpose ram and may also be specified as the source and destination of dma transfer. dst ram can be accessed in a minimum of 2 -wait cycles. note : the upper 256 bytes (0x84700 to 0x847ff) in dst ram are reserved for use as the debugging area. the user program must be prohibited from accessing this area. however, specify 0x84780 for the debug ram address of the c33 das command in the debugger. c33 das 0x60000 0x84780 1
i s1c33e08 specifications: memory map s1c33e08 technical manual epson i-6-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.6.7 area 6 (i/o area) area 6 is allocated to the i/o area for s1c33e08 ip and peripheral circuits. although area 6 is one of the external memory areas, external memory cannot be accessed. for details of the internal peripheral circuits mapped to this area, see the description in chapters iii to ix. for details of a control register list, see i/o map in the appendix. i.6.8 external memory areas areas 4, 5 , and 7 to 22 can be used for external memory and other external devices. set up the sramc or sdramc according to specifications of the devices connected. although the internal address and internal data buses of the s 1c33e08 are both 32 bits wide, the maximum external data bus width is 16 bits (d[15:0 ]) and the maximum external address bus width is 25 bits (a[24:0 ]) due to the limited number of pins available. note : the mp3 decoder bios (mp3 decoder module) uses a minimum of 20kb area in the external ram. when using the mp3 calculation module only (when user's mp3 decoder routine is used), no external ram is required for the mp3 decoder bios.
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i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7 electrical characteristics i.7.1 absolute maximum rating item internal logic power voltage pll power voltage i/o power voltage analog power voltage input voltage analog input voltage high-level output current low-level output current storage temperature ( v ss =plv ss =0v ) symbol v dd plv dd v ddh av dd v i av in i oh i ol t stg rated value -0.3 to +2.5 -0.3 to +2.5 -0.3 to +4.0 -0.3 to +4.0 -0.3 to v dd h +0.5 -0.3 to av dd +0.3 -10 -40 10 40 -65 to +150 unit v v v v v v ma ma ma ma c condition 1 pin total of all pins 1 pin total of all pins ? i.7.2 recommended operating conditions item internal logic power voltage pll power voltage i/o power voltage analog power voltage input voltage analog input voltage cpu operating clock frequency bus operating clock frequency osc3 oscillation frequency osc3 external input clock frequency osc1 oscillation frequency operating temperature input rise time (normal input) input fall time (normal input) input rise time (schmitt input) input fall time (schmitt input) (v ss =plv ss =0v) symbol v dd plv dd v ddh av dd hv i lv i av in f cpu f bus f osc3 f eclk3 f osc1 ta t ri t fi t ri t fi max. 1.95 1.90 1.95 3.60 3.60 3.60 v ddh v dd av dd 60 60 48 48 C 85 70 50 50 5 5 unit v v v v v v v v v mhz mhz mhz mhz khz c c ns ns ms ms condition crystal or external clock ceramic oscillation when usb is not used when usb is used crystal or external clock ceramic oscillation typ. 1.80 1.80 1.80 C 3.30 C C C C C C C C 32.768 25 25 C C C C min. 1.65 1.70 1.65 2.70 3.00 2.70 v ss v ss v ss C C 5 2 C -40 0 C C C C ?
i s1c33e08 specifications: electrical characteristics i-7-2 epson s1c33e08 technical manual i.7.3 dc characteristics item input leakage current off-state leakage current high-level output voltage low-level output voltage high-level input voltage low-level input voltage positive trigger input voltage negative trigger input voltage hysteresis voltage pull-up resistor pull-down resistor high-level latching current low-level latching current high-level reversal current low-level reversal current input pin capacitance output pin capacitance i/o pin capacitance (unless otherwise specified: v ddh =2.7v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol i li i oz v oh v ol v ih v il v t+ v t- v h r pu r pd i bhh i bhl i bhho i bhlo c i c o c io max. 5 5 C 0.4 v ddh 0.8 2.7 1.8 C 288 144 346 144 -20 17 C C 8 8 8 unit a a v v v v v v v k ? k ? k ? k ? a a a a pf pf pf condition i oh =-1.7ma (2ma type), i oh =-3.5ma (4ma type), v dd =min. i ol =1.7ma (2ma type), i ol =3.5ma (4ma type), v dd =min. lvttl level, v ddh =max. lvttl level, v ddh =min. lvcmos schmitt lvcmos schmitt lvcmos schmitt v i =0v 100k ? type 50k ? type v i =v ddh 120k ? type 50k ? type pins with bus-hold latch, v i =1.9v, v ddh =min. pins with bus-hold latch, v i =0.8v, v ddh =min. pins with bus-hold latch, v i =0.8v, v ddh =max. pins with bus-hold latch, v i =1.9v, v ddh =max. f=1mhz, v ddh =0v f=1mhz, v ddh =0v f=1mhz, v ddh =0v typ. C C C C C C C C C 100 50 120 50 C C C C C C C min. -5 -5 v dd -0.4 C 2.0 v ss 1.2 0.5 0.2 50 25 60 25 C C -350 300 C C C ? note : see section i.3.4, input/output cells and input/output characteristics, for pin characteristics.
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.4 current consumption operating current item current consumption during cpu running (mclk=sdclk) current consumption during cpu running (mclk/sdclk) (mclk=1/2sdclk) ? 1 current consumption in halt mode current consumption in halt mode (operating cloc k=48mhz 1/n) ? 2 (unless otherwise specified: v ddh =3.3v, v dd =1.8v, v ss =0v, ta=25 c) symbol i dd1 i dd2 i dd3 i dd4 max. C C C C C C C C C C C C C C C C C C C C unit ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma condition 20mhz 25mhz 33mhz 48mhz 60mhz 24/48mhz 30/60mhz 40/80mhz 45/90mhz 20mhz 25mhz 33mhz 48mhz 60mhz 1/1 (=48mhz) 1/2 (=24mhz) 1/4 (=12mhz) 1/8 (=6mhz) 1/16 (=3mhz) 1/32 (=1.5mhz) typ. 8.0 10.0 13.0 19.0 23.5 10.0 14.0 20.0 21.0 1.3 1.6 2.1 3.0 4.0 3.0 2.2 1.8 1.6 1.5 1.4 min. C C C C C C C C C C C C C C C C C C C C ? 1 1 1 1 2 1 2 2 2 1 1 1 1 2 3 3 3 3 3 3 current consumption measurement condition: v ih =v ddh , v il =0 v, output pins are open, v dd power current only typ. value measurement condition: v ddh =av dd =3.3 v, v dd =1.8 v, ta=25 c typ. sample ? note) no. 1 2 3 osc3 on on on osc1 off off off cpu normal operation ? 3 normal operation ? 3 halt mode other peripheral circuits stopped pll ( 2) only is used when the osc3 frequency is 30mhz or more. others are stopped. stopped ?1 : the mclk (cpu operating clock) frequency is set to half of the sdclk (sdram clock). ?2 : the operating clock actually used is the mclk divided clock specified with the cmu_clksel regis - ter. the cmu_clksel register can be rewritten anytime necessary, note, however, that a hazard may occur on the clock output when the register is changed. the lower the operating frequency, the lower the current consumption is realized. however, it affects the clock frequency supplied to the peripheral circuits, therefore, it is necessary to control the clock supply (on/off) or to reset the prescaler. ?3 : the values of current consumption while the cpu was operating were measured when a test pro - gram consisting of 55 % load instructions, 23 % arithmetic operation instructions, 1 % mac instruction, 12 % branch instructions and 9 % ext instructions was executed continuously in the built-in rom. current consumption in sleep mode item current consumption in sleep mode (unless otherwise specified: v ddh =3.3v, v dd =1.8v, v ss =0v, ta=25 c) symbol i ds1 i ds2 max. C C unit a a condition 48mhz 32khz (system clock = osc1) typ. 1.0 2.0 min. C C ? current consumption measurement condition: v ih =v ddh , v il =0 v, output pins are open typ. value measurement condition: v ddh =av dd =3.3 v, v dd =1.8 v, ta=25 c typ. sample
i s1c33e08 specifications: electrical characteristics i-7-4 epson s1c33e08 technical manual peripheral circuit operating currents item sram controller operating current sdram controller operating current dma controller operating current lcd controller operating current usb controller operating current rtc operating current osc3 operating current sscg operating current pll operating current a/d converter operating current mp3 decoder operating current (unless otherwise specified: v ddh =av dd =3.3v, v dd =plv dd =1.8v, v ss =0v, ta=25 c) symbol i sr i sd i dma i lcd i usb i rtc i osc3 i sscg i pll i ad i mp 3 max. C C C C C C C C C C C unit ma ma ma ma ma a ma a ma a ma condition when sram clock is supplied. (48mhz) when sdram clock is supplied. (48mhz) when dma clock is supplied. (48mhz) when lcdc clock is supplied. (48mhz ) idle state when usb clock is supplied. (48mhz) osc1 oscillation (32khz) osc3 oscillation (48mhz) sscg input clock (48mhz) pll output clock (90mhz) when a/d converter is enabled when mp3 decoder is on playback typ. 3.4 5.4 3.9 5.3 10.0 2.0 1.3 400.0 2.1 260.0 8.0 min. C C C C C C C C C C C ? 4 4 4 4 4 4 4 4 5 6 7 ? note 4 ) v dd power current consumption in idle status when the clock is supplied 5 ) plv dd power current consumption 6 ) av dd power current consumption 7 ) except on stop or pause state
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.5 a/d converter characteristics item resolution conversion time zero scale error full scale error integral linearity error differential linearity error permissible signal source impedance analog input capacitance (unless otherwise specified: v ddh =av dd =2.7v to 3.6v, v dd =1.65v to 1.95v, v ss =0v, ta=-40 c to +85 c, st[1:0]=11) symbol C C e zs e fs e l e d C C max. C 1250 2 2 3 3 5 45 unit bit s lsb lsb lsb lsb k ? pf condition typ. 10 C C C C C C C min. C 10 -2 -2 -3 -3 C C ? 1 ? note 1 ) indicates the minimum value when a/d clock = 2mhz. indicates the maximum value when a/d clock = 16khz. a/d conversion error v[001]h = ideal voltage at zero-scale point (=0.5lsb) v'[001]h = actual voltage at zero-scale point v[3ff]h = ideal voltage at full-scale point (=1022.5lsb) v'[3ff]h = actual voltage at full-scale point 1lsb = 1lsb' = av dd - v ss 2 10 - 1 v'[3ff]h - v'[001]h 2 10 - 2 v'[001]h 3ff 3fe 3fd 003 002 001 000 v ss av dd integral linearity error e l = [lsb] v n ' - v n 1lsb' digital output (hex) analog input ideal conversion characteristic actual conversion characteristic v'[3ff]h v'[n]h v n ' v n v'[n-1]h n+1 n n-1 n-2 integral linearity error differential linearity error differential linearity error e d = - 1 [lsb] v'[n]h - v'[n-1]h 1lsb' digital output (hex) analog input ideal conversion characteristic actual conversion characteristic v[001]h (=0.5lsb) v'[001]h 004 003 002 001 000 v ss zero scale error zero scale error e zs = [lsb] (v'[001]h - 0.5lsb') - (v[001]h - 0.5lsb) 1lsb digital output (hex) analog input ideal conversion characteristic actual conversion characteristic v[3ff]h (=1022.5lsb) v'[3ff]h 3ff 3fe 3fd 3fc 3fb av dd full scale error full scale error e fs = [lsb] (v'[3ff]h + 0.5lsb') - (v[3ff]h + 0.5lsb) 1lsb digital output (hex) analog input ideal conversion characteristic actual conversion characteristic
i s1c33e08 specifications: electrical characteristics i-7-6 epson s1c33e08 technical manual i.7.6 oscillation characteristics oscillation characteristics change depending on conditions such as components used (oscillator, r f , r d , c g , c d ) and board pattern. use the following characteristics as reference values. in particular, when a ceramic or crystal oscillator is used, evaluate the components adequately under real operating conditions by mounting them on the board before the external register (r f , r d ) and capacitor (c g , c d ) values are finally decided. osc1 oscillation (crystal) item oscillation start time (unless otherwise specified: v dd =1.65v to 1.95v, v ss =0v, ta=25 c) symbol t sta1 max. 3 unit s condition typ. min. ? osc3 oscillation (crystal/ceramic) note : a crystal resonator that uses a fundamental should be used for the osc3 crystal oscillation circuit. item oscillation start time (unless otherwise specified: v dd =1.70v to 1.90v, v ss =0v, ta=25 c) symbol t sta3 max. 25 unit ms condition typ. min. ?
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-7 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.7 pll characteristics item input frequency output frequency output stabilization time (unless otherwise specified: plv dd =1.65v to 1.95v, plv ss =0v, ta=-40 c to +85 c) symbol f pllin f pllout t pll max. 50 90 200 unit mhz mhz s condition typ. min. 5 20 ? 1 2 ? note 1 ) input clock source divider: osc3 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10 2 ) multiplication rate: 1, 2, 4, 8, 10, 15
i s1c33e08 specifications: electrical characteristics i-7-8 epson s1c33e08 technical manual i.7.8 ac characteristics i.7.8.1 symbol description t cyc : bus-clock cycle time indicates the cycle time of the bus clock. i.7.8.2 ac characteristics measurement condition signal detection level: input signal high level v ih = v ddh - 0.4 v low level v il = 0.4 v output signal high level v oh = 1/2 v ddh low level v ol = 1/2 v ddh the following applies when osc 3 is external clock input: input signal high level v ih = 1/2 v dd low level v il = 1/2 v dd input signal waveform: rise time ( 10% 90 % v dd ) 5 ns fall time ( 90% 10 % v dd ) 5 ns output load capacitance: pins other than sdclk: c l = 50 pf sdclk pin: c l = 20 pf
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-9 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.8.3 sramc ac characteristic tables external clock input characteristics (note) these ac characteristics apply to input signals from outside the ic. the osc 3 input clock must be within v dd to v ss voltage range. item high-speed clock cycle time osc3 clock input duty osc3 clock input rise time osc3 clock input fall time bclk high-level output delay time bclk low-level output delay time (unless otherwise specified: v ddh =2.7v to 3.6v, v dd =1.65v to 1.95v, v ss =0v, ta=-40 c to +85 c) symbol t c3 t c3ed t if t ir t cd1 t cd2 max. 500 55 5 5 25 25 unit ns % ns ns ns ns min. 16.7 45 ? bclk clock output characteristics (note) these ac characteristic values are applied only when the high-speed oscillation circuit is used. item bclk clock output duty (unless otherwise specified: v ddh =2.7v to 3.6v, v dd =1.65v to 1.95v, v ss =0v, ta=-40 c to +85 c) symbol t cbd max. 60 unit % min. 40 ? bus access cycle item cmu_clk output dela y time address dela y time #ce x dela y time wr ite dela y time wr ite data dela y time wr ite data hold time read dela y time read data setup time read data hold time wr ite signal pulse width read signal pulse width read address access time chip enab le access time read signal access time #w ait setup time #w ait hold time (unless otherwise specified: v ddh =2.7v to 3.6v, v dd =1.65v to 1.95v, v ss =0v, external load=50pf, ta=-40 c to +85 c) symbol t cd t ad t ced t wr d t wrdd t wrdh t rdd t rds t rddh t wr w t rd w t ac c t cea c t rd ac t wt s t wt h max. 20 14 14 14 14 14 t cyc (1+wc)-26 t cyc (1+wc)-26 t cyc (1+wc)-26 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. -2 12 0 t cyc (1+wc)-14 t cyc (1+wc)-14 12 0 ?
i s1c33e08 specifications: electrical characteristics i-7-10 epson s1c33e08 technical manual i.7.8.4 sramc ac characteristic timing charts clock osc3 (high-speed clock) t c3 bclk (clock output) t c3 ( t cyc ) t c3h t c3ed = t c3h / t c3 t cbd = t cbh / t cyc bclk (clock output) t cyc t cbh t cd1 t cd2 t if t ir (1) when an external clock is input: (2) when the high-speed oscillation circuit is used for the operating clock: sram read cycle mclki cmu_clk (p52) a[24:0] #ce x #rd d[15:0] #wait t cd t cyc t ad t ced t rdd t rdd t ad t ced valid valid t rds t rddh t rdw t wt s t wt h sram write cycle mclki cmu_clk (p52) a[24:0] #ce x #wr x d[15:0] #wait t cd t cyc t ad t ced t wr d t wr d t ad t ced valid valid t wrdd t wt s t wrdh t wt h t wr w
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-11 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.8.5 sdram interface ac characteristics normal mode (sdclk = mclk, 60mhz max.) item address delay time address hold time sda10 delay time sda10 hold time #sdcs delay time #sdcs hold time #sdras signal delay time #sdras signal hold time #sdcas signal delay time #sdcas signal hold time dqmh, dqml signal delay time dqmh, dqml signal hold time sdcke signal delay time sdcke signal hold time #sdwe signal delay time #sdwe signal hold time read data setup time read data hold time write data delay time write data hold time (unless otherwise specified: v ddh =2.7v to 3.3v, v dd =1.65v to 1.95v, ta=-40 c to +85 c external load conditions: address bus/data bus=50pf, sdclk/control signals=20pf) symbol t ad t ah t a10d t a10h t csd t csh t rasd t rash t casd t cash t dqm d t dqm h t cked t ckeh t we d t we h t rds t rdh t wd d t wd h max. 10 10 10 10 10 10 10 10 11 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 4 0 1.5 ? double frequency mode (sdclk = 2 mclk, 90mhz max.) item address delay time address hold time sda10 delay time sda10 hold time #sdcs delay time #sdcs hold time #sdras signal delay time #sdras signal hold time #sdcas signal delay time #sdcas signal hold time dqmh, dqml signal delay time dqmh, dqml signal hold time sdcke signal delay time sdcke signal hold time #sdwe signal delay time #sdwe signal hold time read data setup time read data hold time write data delay time write data hold time (unless otherwise specified: v ddh =2.7v to 3.3v, v dd =1.65v to 1.95v, ta=-40 c to +85 c external load conditions: address bus/data bus=30pf, sdclk/control signals=20pf) symbol t ad t ah t a10d t a10h t csd t csh t rasd t rash t casd t cash t dqm d t dqm h t cked t ckeh t we d t we h t rds t rdh t wd d t wd h max. 8 8 8 8 8 8 8 8 8 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 4 0 1.5 ? note : all the signals change at the rising edge of the sdram clock.
i s1c33e08 specifications: electrical characteristics i-7-12 epson s1c33e08 technical manual sdram access cycle (write) (read) (column) (bank, row) bank active (column) t we h t cash sdclk sdcke a[24:0] sda10 #sdcs #sdras #sdcas #sdwe d[15:0] dqmh/ dqml t ad t ah t a10h read nop h valid valid valid t a10d t csd t csh t we d t we d t wd d t we h t dqm d t wd h t dqmh valid valid valid valid valid valid idle nop write t rasd t rash t casd t rdh t rds ? read: cas latency = 2 , burst length = 2 write: single write sdram mode-register-set cycle t cash sdclk sdcke a[24:0] sda10 #sdcs #sdras #sdcas #sdwe d[15:0] dqmh/ dqml mode register set t ad t ah nop nop h valid t a10d t a10h t csd t csh t we d t we h valid nop t rasd t rash t casd
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-13 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 sdram auto-refresh cycle sdclk sdcke a[24:0] sda10 #sdcs #sdras #sdcas #sdwe d[15:0] dqmh/ dqml t cash auto refresh nop nop h t csd t csh t we d t we h nop t rasd t rash t casd ? a precharge cycle is necessary before entering the auto refresh mode. sdram self-refresh cycle sdclk sdcke a[24:0] sda10 #sdcs #sdras #sdcas #sdwe d[15:0] dqmh/ dqml t csd t csh t we d exit self refresh mode enter self refresh mode t rasd t casd t cked ? a precharge cycle is necessary before entering the self refresh mode.
i s1c33e08 specifications: electrical characteristics i-7-14 epson s1c33e08 technical manual i.7.8.6 lcdc ac characteristics conditions: v ddh = 2.7v to 3.6v ta = - 40 c to 85 c trise and tfall for all outputs should be < 5 ns (10% ~ 90%) c l = 60 pf (lcd panel interface) power up/down timing #reset psave[1:0] bits (d[1:0]/0x301a04) fp signals lcd power active inactive inactive t 1 t 4 t 3 t 2 11 00 00 symbol t 1 t 2 t 3 t 4 max. 1 1 unit frame frame frame frame parameter power save inactive to fpline, fpframe, fpshift, fpdat, fpdrdy active fpline, fpframe, fpshift, fpdat, fpdrdy active to lcd power on power save active to lcd power off power save active to fpline, fpframe, fpshift, fpdat, fpdrdy inactive typ. min. 1 1 note) any i/o port can be used for controlling the power supply to the lcd panel. note, however, that the t 2 and t 3 timing conditions must be satisfied when controlling the signal.
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-15 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 4 -bit single monochrome panel timing fpframe fpline fpdrdy (mod) fpdat[7:4] vdp vndp fpline fpdrdy (mod) fpshift fpdat7 fpdat6 fpdat5 fpdat4 line 1 1-1 1-5 1-317 1-2 1-6 1-318 1-3 1-7 1-319 1-4 1-8 1-320 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel for this timing diagram fpsmask (d 29/0x301a60) is set to 1 vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-16 epson s1c33e08 technical manual frame pulse line pulse fpdrdy (mod) sync timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 line pulse shift pulse fpdat[7:4] data timing note : for this timing diagram fpsmask (d29/0x301a60) is set to 1. 4 -bit single monochrome panel ac timing symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width mod delay from line pulse rising edge shift pulse falling edge to line pulse rising edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse falling edge shift pulse period shift pulse width low shift pulse width high fpdat[7:4] setup to shift pulse falling edge fpdat[7:4] hold from shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 1 note 4 note 5 t 14 +2 4 2 2 2 2 23 note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 2 (ts) 5 . t 7min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 11 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-17 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 8 -bit single monochrome panel timing fpframe fpline fpdrdy (mod) fpdat[7:0] vdp vndp fpline fpdrdy (mod) fpshift fpdat7 fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 line 1 1-1 1-9 1-313 1-2 1-10 1-314 1-3 1-11 1-315 1-4 1-12 1-316 1-5 1-13 1-317 1-6 1-14 1-318 1-7 1-15 1-319 1-8 1-16 1-320 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel for this timing diagram fpsmask (d 29/0x301a60) is set to 1 vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-18 epson s1c33e08 technical manual frame pulse line pulse fpdrdy (mod) sync timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 line pulse shift pulse fpdat[7:0] data timing note : for this timing diagram fpsmask (d29/0x301a60) is set to 1. 8 -bit single monochrome panel ac timing symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width mod delay from line pulse rising edge shift pulse falling edge to line pulse rising edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse falling edge shift pulse period shift pulse width low shift pulse width high fpdat[7:0] setup to shift pulse falling edge fpdat[7:0] hold from shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 1 note 4 note 5 t 14 +4 8 4 4 4 4 23 note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 4 (ts) 5 . t 7min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 13 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-19 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 4-bit single color panel timing fpframe fpline fpdrdy (mod) fpdat[7:4] vdp vndp fpline fpdrdy (mod) fpshift fpdat7 fpdat6 fpdat5 fpdat4 line 1 1-r1 1-g2 1-b31 9 1-g1 1-b2 1-r320 1-b1 1-r3 1-g320 1-r2 1-g3 1-b3 1-r4 1-g4 1-b4 1-b32 0 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-20 epson s1c33e08 technical manual frame pulse line pulse fpdrdy (mod) sync timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 line pulse shift pulse fpdat[7:4] data timing 4 -bit single color panel ac timing symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width mod delay from line pulse rising edge shift pulse falling edge to line pulse rising edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse falling edge shift pulse period shift pulse width low shift pulse width high fpdat[7:4] setup to shift pulse falling edge fpdat[7:4] hold from shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 1 note 4 note 5 t 14 +0.5 1 0.5 0.5 0.5 0.5 23 (24) note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 1.5 (ts) 5 . t 7min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 10.5 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-21 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 8-bit single color panel timing (format 1) fpframe fpline fpdat[7:0] vdp vndp fpline fpshift fpshift2 fpdat7 fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 line 1 1-r1 1-g1 1-r236 1-b1 1-r2 1-b23 6 1-g2 1-b2 1-g237 1-r3 1-g3 1-r238 1-b3 1-r4 1-b23 8 1-g4 1-b4 1-g239 1-r5 1-g5 1-r240 1-b5 1-r6 1-b24 0 1-g6 1-r7 1-b7 1-g8 1-r9 1-b9 1-g10 1-r11 1-b6 1-g7 1-r8 1-b8 1-g9 1-r10 1-b10 1-g11 1-b11 1-g12 1-r13 1-b13 1-g14 1-r15 1-b15 1-g16 1-r12 1-b12 1-g13 1-r14 1-b14 1-g15 1-r16 1-b16 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-22 epson s1c33e08 technical manual frame pulse line pulse sync timing t 2 t 1 t 6b t 6a t 8 t 9 t 7a t 7b t 14 t 11 t 10 t 12 t 13 t 12 t 13 t 4 t 3 line pulse shift pulse 2 shift pulse fpdat[7:0] data timing 1 2 8 -bit single color panel ac timing (format 1) symbol t 1 t 2 t 3 t 4 t 6a t 6b t 7a t 7b t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width shift pulse falling edge to line pulse rising edge shift pulse 2 falling edge to line pulse rising edge shift pulse 2 falling edge to line pulse falling edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse rising, shift pulse 2 falling edge shift pulse 2, shift pulse period shift pulse 2, shift pulse width low shift pulse 2, shift pulse width high fpdat[7:0] setup to shift pulse 2, shift pulse falling edge fpdat[7:0] hold from shift pulse 2, shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 note 4 note 5 note 6 note 7 t 14 +2 4 2 2 1 1 23 (25) note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6amin = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + t 13 - t 10 + 1 (ts) 5 . t 6bmin = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + t 13 + 1 (ts) 6 . t 7amin = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 11 (ts) 7 . t 7amin = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 11 - t 10 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-23 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 8-bit single color panel timing (format 2) fpframe fpline fpdrdy (mod) fpdat[7:0] vdp vndp fpline fpdrdy (mod) fpshift fpdat7 fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 line 1 1-r1 1-b3 1-g238 1-g1 1-r4 1-b23 8 1-b1 1-g4 1-r239 1-r2 1-b4 1-g239 1-g2 1-r5 1-b23 9 1-b2 1-g5 1-r240 1-r3 1-b5 1-g240 1-g3 1-r6 1-g6 1-b6 1-r7 1-g7 1-b7 1-r8 1-g8 1-b8 1-b24 0 line 2 line 3 line 1 line 2 line 4 line 239 line 240 hdp hndp ? diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel vdp = vertical display period = vdpcnt[ 9:0] + 1 (lines) vdpcnt[ 9:0] (d[9:0]/0x301a14) vndp = vertical non-display period = vtcnt[ 9:0 ] - vdpcnt[9:0] (lines) vtcnt[ 9:0] (d[25:16]/0x301a14) hdp = horizontal display period = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[ 6:0] (d[6:0]/0x301a10) hndp = horizontal non-display period = (htcnt[ 6:0] - hdpcnt[6:0]) 8 (ts) htcnt[ 6:0] (d[22:16]/0x301a10)
i s1c33e08 specifications: electrical characteristics i-7-24 epson s1c33e08 technical manual frame pulse line pulse fpdrdy (mod) sync timing 2 1 t 2 t 1 t 5 t 6 t 8 t 9 t 7 t 14 t 11 t 10 t 12 t 13 t 4 t 3 line pulse shift pulse fpdat[7:0] data timing 8 -bit single color panel ac timing (format 2) symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 max. unit (note 1) ts ts ts ts ts ts ts ts ts ts parameter frame pulse setup to line pulse falling edge frame pulse hold from line pulse falling edge line pulse period line pulse width mod delay from line pulse rising edge shift pulse falling edge to line pulse rising edge shift pulse falling edge to line pulse falling edge line pulse falling edge to shift pulse falling edge shift pulse period shift pulse width low shift pulse width high fpdat[7:0] setup to shift pulse falling edge fpdat[7:0] hold from shift pulse falling edge line pulse falling edge to shift pulse rising edge typ. min. note 2 9 note 3 9 1 note 4 note 5 t 14 +2 2 (3) 1 1 1 1 23 note) 1 . ts = pixel clock period 2 . t 1min = t 3min - 9 (ts) 3 . t 3min = (htcnt[ 6:0] + 1) 8 (ts) 4 . t 6min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 1 (ts) 5 . t 7min = (htcnt[ 6:0] - hdpcnt[6:0]) 8 + 10 (ts)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-25 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 12 -bit generic hr-tft panel timing (1 ) generic hr-tft panel horizontal timing d1 d2 d3 d319 d320 fpframe (sps) fpline (lp) fpline (lp) fpshift (clk) fpdat[11:0] tft_ctl3 (spl) tft_ctl1 (cls) tft_ctl0 (ps) tft_ctl2 (rev) t 7 t 5 t 3 t 2 t 1 t 9 t 4 t 6 t 8 ? example timing for a 320 240 panel symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 max. 440 unit (note 1) ts ts ts ts ts ts ts ts parameter fpline start position total horizontal period fpline width fpshift period horizontal display start position horizontal display period fpline rising edge to tft_ctl3 rising edge tft_ctl3 pulse width fpline rising edge to tft_ctl2 change typ. note 2 note 3 note 4 1 note 5 note 6 59 1 11 min. 400 note) 1 . ts = pixel clock period 2 . t 1typ = fplst[ 9:0] + 1 (ts) fplst[9:0] (d[25:16]/0x301a28) 3 . t 2typ = (htcnt[ 6:0] + 1) 8 (ts) htcnt[6:0] (d[22:16]/0x301a10) 4 . t 3typ = fplwd[ 6:0] + 1 (ts) fplwd[ 6:0] (d[6:0]/0x301a28) 5 . t 5typ = hdpscnt[ 9:0] + 1 (ts) hdpscnt[9:0] (d[9:0]/0x301a20) 6 . t 6typ = (hdpcnt[ 6:0] + 1) 8 (ts) hdpcnt[6:0] (d[6:0]/0x301a10) (2 ) generic hr-tft panel vertical timing line 1 line 2 line 239 line 240 fpdat[11:0] fpframe (sps) t 2 t 4 t 3 t 1 ? example timing for a 320 240 panel symbol t 1 t 2 t 3 t 4 max. 330 unit lines lines lines lines parameter total vertical period vertical display start position vertical display period vertical sync pulse width typ. note 1 note 2 note 3 2 min. 245 note) 1 . t 1typ = vtcnt[ 9:0] + 1 (lines) vtcnt[9:0] (d[25:16]/0x301a14) 2 . t 2typ = vdpscnt[ 9:0 ] (lines) vdpscnt[9:0] (d[9:0]/0x301a24) 3 . t 3typ = vdpcnt[ 9:0] + 1 (lines) vdpcnt[9:0] (d[9:0]/0x301a14)
i s1c33e08 specifications: electrical characteristics i-7-26 epson s1c33e08 technical manual (3 ) generic hr-tft panel control signal offset timings fpline (lp) tft_ctl1 (cls) tft_ctl0 (ps) tft_ctl2 (rev) stop0 delay start1 stop1 start0 ? when fplst[9:0] (d[25:16]/0x301a28) = 0x0 start 1 = ctl1st[7:0] (ts) ctl1st[7:0] (d[7:0]/0x301a44) stop 1 = ctl1stp[7:0] + 1 (ts) ctl1stp[7:0] (d[23:16]/0x301a44) start 0 = ctl0st[7:0] (ts) ctl0st[7:0] (d[7:0]/0x301a48) stop 0 = ctl0stp[7:0] + 1 (ts) ctl0stp[7:0] (d[23:16]/0x301a48) delay = ctl 2 dly[7:0] (ts) ctl2 dly[7:0] (d[7:0]/0x301a4c)
i s1c33e08 specifications: electrical characteristics s1c33e08 technical manual epson i-7-27 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.7.9 usb dc and ac characteristics input levels item vbus input high (driven) high (floating) low differential input sensitivity differential common mode range (unless otherwise specified: v dd =3.0v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol v bus v ih v ihz v il v di v cm max. 5.25 C 3.6 0.8 C 2.5 unit v v v v v v condition |dp - dm| include v di range typ. C C C C C C min. 4.40 2.0 2.7 C 0.2 0.8 ? 1 2 2 2 ? note 1 ) refer to section 7.2.1 in the usb2.0 specification for the conditions. 2 ) refer to section 7.1.4 in the usb2.0 specification for the conditions. output levels item low high (driven) output signal crossover voltage (unless otherwise specified: v dd =3.0v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol v ol v oh v crs max. 0.3 3.6 2.0 unit v v v condition typ. C C C min. 0.0 2.8 1.3 ? 3 3 4 ? note 3 ) refer to section 7.1.1 in the usb2.0 specification for the conditions. 4 ) refer to figures 7-8 and 7-9 in the usb2.0 specification for the conditions. terminations item bus pull-up resistor on upstream facing port (idle bus) bus pull-up resistor on upstream facing port (receiving) (unless otherwise specified: v dd =3.0v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol r pui v pua max. 1.575 3.090 unit k ? k ? condition typ. C C min. 0.9 1.425 ? 5 5 ? note 5 ) refer to ecn in the usb2.0 specification for the conditions. driver characteristics max. 20 20 111.11 44 typ. C C C C C min. 4 4 90 28 125 item rise time fall time differential rise and fall time matching driver output resistance vbus input impedance vbus resistor ratio (unless otherwise specified: v dd =3.0v to 3.6v, v dd =1.65v to 1.95v, ta=-40 c to +85 c) symbol t fr t ff t frfm z drv z vbus unit ns ns % ? k ? condition t fr /t ff r1 + r2 r1 : r2 1 : 2 (nominal) ? 4 4 ? note 4 ) refer to figures 7-8 and 7-9 in the usb2.0 specification for the conditions.
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i s1c33e08 specifications: basic external wiring diagram s1c33e08 technical manual epson i-8-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.8 basic external wiring diagram x'tal1 c g1 c d1 rf 1 rd 1 crystal resonator gate capacitor drain capacitor feedback resistor drain resistor 32.768 khz 12 pf ? 4 12 pf ? 4 10 m ? ? 4 0 ? ? 4 x'tal2 or ce c g2 c d2 rf 2 rd 2 resonator gate capacitor drain capacitor feedback resistor drain resistor crystal 3 pf 4 pf 1 m ? 0 ? ceramic ? 1 (6 pf) (6 pf) 22 k ? 47 ? note : ? 1 cstcw48m0x11 ??? ? 2 oscillation characteristics vary depending on conditions (components used, board pattern, etc.). the values in the above table are shown only for reference and not guaranteed. in particular, ceramic oscillation is extremely sensitive to influence of external components and printed-circuit boards. before using a ceramic resonator, please be sure to contact murata manufacturing co., ltd. for further information on conditions of use for ceramic resonators. furthermore, this chip supports only 48-mhz ceramic resonators. do not use ceramic resonators with any other frequency. ? 3 capacitance built into the ceramic resonator ? 4 oscillation characteristics vary depending on conditions (components used, board pattern, etc.). the values in the above table are shown only for reference and not guaranteed. ? 2, ? 3 ? 2, ? 3 ? 2 ? 2 s1c33e08 [the potential of the substrate (back of the chip) is v ss .] external bus hsdma a[24:1], a0/#bsl d[15:0] #rd #wrl #wrh/#bsh #cexx #wait bclk #nmi cmu_clk wdt_clk #wdt_nmi sdclk sdcke sda10 dqmh dqml #sdcs #sdras #sdcas #sdwe #dmareqx #dmaackx #dmaendx fpframe fpline fpdat[11:0] fpshift fpdrdy tft_ctl[3:0] usbdp usbdm usbvbus sinx soutx #sclkx #srdyx sdi sdo spi_clk dcsio0 dcsio1 #smrd #smwr #iord #iowr #oe #we #cfce1 #cfce2 i2s_sdo i2s_ws i2s_scl i2s_mclk #adtrg ainx exclx tmx pxx sdram lcd panel card i 2 s a/d input timer input/output i/o usb spi dcsio serial i/o debug interface v dd plv dd v ddh av dd boot1 boot0 mclki mclko rtc_clki rtc_clko #reset vcp test0 burnin v ss dst[2:0] dpco dclk dsio 1.8 v 3.0/3.3 v rd 2 rd 1 c d2 x'tal2 or ce rf 2 c g2 c d1 x'tal1 rf 1 c g1 + +
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i s1c33e08 specifications: precautions on mounting s1c33e08 technical manual epson i-9-1 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 i.9 precautions on mounting the following shows the precautions when designing the board and mounting the ic. oscillation circuit ? oscillation characteristics change depending on conditions such as components used (oscillator, r f , r d , c g , c d ) and board pattern. in particular, when a ceramic or crystal oscillator is used, evaluate the components adequately under real operating conditions by mounting them on the board before the external register (r f , r d ) and capacitor (c g , c d ) values are finally decided. ? disturbances of the oscillation clock due to noise may cause a malfunction. to prevent this, the following points should be taken into consideration. in particular, the latest devices are more sensitive to noise, as they are more finely processed. the measures against noise for the rtc_clko pin, and the components and lines connected to this pin is most essential, and similar measures must also be taken for the rtc_clki pin. the measures for the rtc_clki and rtc_clko pins are described below. we recommend taking measures similar to those for the high-speed oscillation system, including the mclki and mclko pins and the components and lines connected to these pins. (1 ) components that are connected to the rtc_clki and rtc_clko pins, such as oscillators, resistors, and capacitors, should be connected in the shortest line. (2 ) whenever possible, configure digital signal lines with at least three millimeters clearance from the rtc_clki and rtc_clko pins and the components and lines connected to these pins. in particular, signals that are switched frequently must not be placed near these pins, components, and lines. the same applies to all layers on the multi-layered board as the distance between the layers is around 0.1 to 0.2 mm. furthermore, do not configure digital signal lines in parallel with these components and lines when arranging them on the same or another layer of the board. such an arrangement is strictly prohibited, even with clearance of three millimeters or more. also, avoid arranging digital signal lines across these components and signal lines. (3 ) shield the rtc_clki and rtc_clko pins and lines connected to those pins as well as the adjacent layers of the board using v ss . as shown in the figure on the right, shield the wired layers as much as possible. whenever possible, make the whole adjacent layers the ground layers, or ensure there is adequate shielding to a radius of five millimeters around the above pins and lines. as described in ( 2 ), do not configure digital signal lines in parallel with components and lines even if such precautionary measures are taken, and avoid configuring signal lines that are switched frequently across components and lines on other layers. (4 ) when an external clock is supplied to the rtc_clki or mclki pin, the clock source should be connected to the rtc_clki or mclki pin in the shortest line. furthermore, do not connect anything else to the rtc_clko or mclko pin. (5 ) after taking the above precautions, check the output clock waveform while operating the actual application program in the actual device. to do this, measure the output of the cmu_clk pins with an oscilloscope. check the waveform quality at the osc 3 or pll output clock by measuring the cmu_clk output. ensure that the frequencies are as designed and that there is no noise or jitters. check the waveform quality at the osc 1 clock by measuring the cmu_clk output (after switching the system clock source to osc 1 ). scale up the ranges around the rising and falling edges of the clock pulse to ensure that there is no noise, such as clock and spike, in the 100 ns ranges. rtc_clki rtc_clko v ss sample v ss pattern rtc_clki and rtc_clko
i s1c33e08 specifications: precautions on mounting i-9-2 epson s1c33e08 technical manual if conditions ( 1 ) to (3 ) are not satisfied, the osc3 or pll output may be jittery and the osc1 output may be noisy. when the osc 3 or pll output is jittery, the operating frequency will be lowered. when the osc1 output is noisy, operation of the rtc using the osc 1 clock and the cpu core after the system clock is switched to osc1 will be unstable. reset circuit ? the power-on reset signal which is input to the #reset pin changes depending on conditions (power rise time, components used, board pattern, etc.). decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. ? in order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the #reset pin in the shortest line. power supply circuit ? sudden power supply variation due to noise may cause malfunction. consider the following points to prevent this: (1 ) the power supply should be connected to the v dd , v ddh , v ss , av dd , plv dd and plv ss pins with patterns as short and large as possible. in particular, the power supply for av dd affects a/d conversion precision. (2 ) when connecting between the v dd and v ss pins with a bypass capacitor, the pins should be connected as short as possible. v dd v ss bypass capacitor connection example v dd v ss a/d converter ? when the a/d converter is not used, the power supply pin av dd for the analog system should be connected to v ddh . arrangement of signal lines ? in order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. ? when a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. do not arrange a high- speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. p70 (ain0) large current signal line high-speed signal line large current signal line high-speed signal line prohibited pattern rtc_clko, mclko rtc_clki, mclki v ss
i s1c33e08 specifications: precautions on mounting s1c33e08 technical manual epson i-9-3 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 usb the i/o block of the usb function controller incorporated in t his chip has the following features: the dp and dm pins can be connected directly to the usb connect or. the vbus level is detected by means of a 2/3 resistive division internally in the chip, thus allowing for direct input of a 5 v-level signal. the receiver does not enter a floating state even when the usb cable is disconnected from the usb connector. when the usb cable is disconnected, the vbus pin is tied to v ss , so that leakage current will be the only source that drains power in the usb i/o block. precautions on vbus be sure to not apply 6 v (max.) or more to the vbus pin as the ic may be destroyed. it is especially necessary to suppress overshoot on the input voltage and to prevent the host power source becoming unstable when the usb cable is plugged into the connector. to do this, connect a 1 f or more capacitor near the usb connector for decoupling the vbus signal. choose a ceramic capacitor for decoupling. usb connector vbus pin usbvbus pin 1 f or more in addition to the above, verify the vbus state completely on the actual circuit board using an oscilloscope or other device. overshoot and other symptoms are more likely to occur when using a long usb cable and connecting it to the host side connector. precautions on dp and dm when designing a printed circuit board, observe the following precautions to ensure that both dp and dm signals are properly routed: ? to prevent signal skew and to stabilize differential impedance, the dp and dm signal lines must be routed in parallel and in the same length, with the pins and connector connected in the shortest distance possible. crossed wiring of these signals should be avoided as much as possible. ? the periphery of these signal lines must be enclosed by a gnd pattern, and with the gnd pattern also created for the internal layer immediately below that. in particular, the routing of high-speed digital signal lines parallel to or across these signal lines should be avoided as much as possible. we recommend that you verify the eye pattern on the actual circuit board. sample eye diagram
i s1c33e08 specifications: precautions on mounting i-9-4 epson s1c33e08 technical manual noise-induced erratic operations if erratic ic operations appear to be attributable to noise, consider the following five points. ( 1 ) test0 pin if this pin is exposed to high-level noise, the entire ic enters test mode or a high-impedance state and becomes inoperable. in such cases, the ic will not be restored, even when the pin is returned to a low level. therefore, always make sure the test 0 pin is connected to gnd on the circuit board. although the ic contains internal pull-down resistors, it is susceptible to noise because these resistors are high impedance (approximately 50 to 100 k ? ). ( 2 ) dsio pin exposure of this pin to low-level noise causes the ic to enter debug mode. in debug mode, the clock is output from the dclk pin and the dst2 pin is high, indicating that the ic is in debug mode. in product versions, it is recommended that the dsio pin be pulled high by connecting it directly to v dd or through a resistor of 10 k ? or less. although the ic contains internal pull-up resistors, it is susceptible to noise because these resistors are high impedance (approximately 50 to 100 k ?). for details, refer to the s1c33 family application note. ( 3 ) #reset pin low-level noise on this pin resets the ic. however, the ic may not always be reset normally, depending on the input waveform. due to circuit design, this situation tends to occur when the reset input is in the high state, with high impedance. for details, refer to the s1c33 family application note. ( 4 ) #nmi pin low-level noise on this pin causes an nmi interrupt. due to the circuit design, this situation tends to occur when the #nmi pin is in the high state, with high impedance. lower the impedance of #nmi when it is held high, or incorporate corrective measures into the software to protect against erratic operations. ( 5 ) v dd , v ss , and v ddh power supplies if noise lower than the rated voltage enters one of these power-supply lines, the ic may operate erratically. take corrective measures in board design; for example, by using solid patterns for power supply lines, adding decoupling capacitors to eliminate noise, or incorporating surge/noise counteracting devices into the power supply lines. to confirm the above, use an oscilloscope capable of observing higher-frequency waveforms of 200 mhz. the generation of fast noise may not be observed with a low-frequency oscilloscope. if potential noise-induced erratic operations are detected through waveform observations using an oscilloscope, connect the suspected pin to the gnd or power supply with low impedance ( 1 k ? or less) and check once again. if erratic operations are no longer detected or occur at reduced frequency, or if different symptoms of erratic operations are observed, said pin may with reasonably certainty be considered to be the source of the erratic operations. the test 0 , dsio, #reset, and #nmi input circuits described above are designed to detect the edges of the input signal (#nmi can be changed to level sense mode), so that even spike noise may result in erratic operations. among the digital signal circuits, these pins are most susceptible to noise. in the design of the circuit board, take the following two points into consideration to protect the signal from noise. (a) the most important measure is to lower the signal-driving impedance, as described in each item above. connect pins to the power supply or gnd, with impedance of 1 k ? or less, preferably 0 ? . in addition, limit the length of the connected signal lines to approximately 5 cm. (b) parallel routing of said signal lines with other digital lines on the board is undesirable, since the noise generated when the signal changes from high to low or vice versa may adversely affect signals. the signal may be subject to the most noise when signal lines are laid between multiple signal lines whose states change simultaneously. take corrective measures by shortening the parallel distance (to several cm) or separating signal lines (2 mm or more).
i s1c33e08 specifications: precautions on mounting s1c33e08 technical manual epson i-9-5 i overview block pin power cpu map e char wiring mount ii preface hsdma idma sramc sdramc iii preface cmu itc rtc misc iv preface t16 wdt v preface efsio spi dcsio card i2s vi preface gpio egpio vii preface adc viii preface lcdc ivram ix preface usb ap i/omap differ gnu33 reference refer to chapter 4, the basic s1c33 chip board circuit, in the s1c33 family application note for more detailed precautions on the power supply, oscillation, reset, memory, port, and debug. other the 0.18 m fine-pattern process is employed to manufacture this series of products. although the product is designed to meet eiaj and mil standards regarding basic ic reliability, please pay careful attention to the following points when actually mounting the chip on a board. since all the oscillator input/output pins are constructed to use the internal 0.18 m transistors directly, the pins are susceptible to mechanical damage during the board-mounting process. moreover, the pins may also be susceptible to electrical damage caused by such disturbances (listed below) whose electrical strength, varying gradually with time, could exceed the absolute maximum rated voltage ( 2.5 v) of the ic: (1 ) electromagnetic induction noise from the utility power supply in the reflow process during board-mounting, rework process after board-mounting, or individual characteristic evaluation (experimental confirmation), and (2 ) electromagnetic induction noise from the tip of a soldering ir on especially when using a soldering iron, make sure that the ic gnd and soldering iron gnd are at the same potential before soldering.
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i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual ii bus modules

ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1 high-speed dma (hsdma) ii.1.1 functional outline of hsdma the s 1c33e08 contains four channels of hsdma (high-speed dma) circuits that support dual-address transfer and single-address transfer methods. since the control registers required for the hsdma function are implemented with logic circuits (not located in a memory), hsdma requests for data transfer can respond to insta ntaneously. notes : ? channels 0 to 3 are configured in the same way and have the same functionality. signal and control bit names are assigned channel numbers 0 to 3 to distinguish them from other chan - nels. in this manual, however, channel numbers 0 to 3 are designated with an x except where they must be distinguished, as the explanation is the same for all channels. ? the mp3 decoder bios (mp3 decoder module) uses hsdma ch.0 and ch.1 , therefore, these two channels cannot be used while the mp 3 decoder is active. dual-address transfer in this method, a source address and a destination address for dma transfer can be specified and a dma trans - fer is performed in two phases. the first phase reads data at the source address into the on-chip temporary reg - ister. the second phase writes the temporary register data to the destination address. unlike idma (intelligent dma), which has transfer information in memory, this dma method does not sup - port a dma link function but allows high-speed data transfers because it is not necessary to read transfer infor - mation from a memory. memory, i/o data transfer (1) (1) transfer data is read from the source memory or i/o device. (2) transfer data is written to the destination memory or i/o device. (2) destination memory, i/o source hsdma ch.0 ch.1 ch.2 ch.3 itc end of dma dma acknowledge dma request #dmareq x sramc/ sdramc #dmaend x #dmaack x address bus cpu-ahb bus dma data transfer request signal transfer count end signal dma data transfer acknowledge signal hardware/software trigger data bus figure ii.1.1.1 dual-address transfer method the features of dual-address transfer are outlined below. ? source external memory and internal memory except areas 0 and 1 ? destination external memory and internal memory except areas 0 and 1 ? transfer data size 8, 16, or 32 bits ? trigger 1 . software trigger (register control) 2 . hardware trigger (external trigger input, causes of interrupts) ? transfer mode 1. single transfer (one unit of data is transferred by one trigger) 2 . successive transfer (specified number of data are transferred by one trigger) 3 . block transfer (data block of the specified size is transferred by one trigger) ? transfer address control the source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. in successive or block transfers, the address can be reset to the initial value upon completion of transfer. ? #dmaend output goes low at the last access of data transfer by each trigger. ? #dmaack output goes low when a dma request is accepted.
ii bus modules: high-speed dma (hsdma) ii-1-2 epson s1c33e08 technical manual note : a0ram (area 0), specific rom (area 1), and ivram (area 0) cannot be specified as the source or destination for dma transfer. while ivram (area 3), dst ram (area 3), and the internal pe - ripheral i/o registers (area 6) can be used for dual-address transfer. timing chart of dual-address mode ( 1) sram address #ce (src) #ce (dst) #rd #wr ? #dmaack #dmaend source address read cycle write cycle destination address figure ii.1.1.2 #dmaack/#dmaend signal output timing (sram, standard settings) ( 2) sdram sdclk address #sdcs (src) #sdcs (dst) #sdras #sdcas #sd we #dmaa ck #dmaend ras cas read cycle wr ite cycle ras cas a ctv read a ctv writ figure ii.1.1.3 #dmaack/#dmaend signal output timing (sdram, standard settings) note : two or more access cycles are generated when the device size of the external memory is smaller than the transfer data size. in this case, the #dmaack/#dmaend signal is asserted over these cycles.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 single-address transfer in this method, data transfers that are normally accomplished by executing data read and write operations back- to-back are executed on the external bus collectively at one time, thus further speeding up the transfer opera - tion. the #dmaack x and #dmaend x signals are used to control data transfer. unlike dual-address transfer, this method does not allow memory to memory data transfer but data transfers can be performed in minimum cycles. external i/o #rd/#wr data transfer external memory or external i/o hsdma ch.0 ch.1 ch.2 ch.3 itc end of dma dma acknowledge dma request #dmareq x sramc #dmaend x #dmaack x address bus cpu-ahb bus dma data transfer request signal transfer count end signal bus control signals dma data transfer acknowledge signal hardware/software trigger data bus figure ii.1.1.4 single-address transfer method the features of single-address transfer are outlined below. ? source/destination 1 . between an external i/o and an external memory (except sdram) 2 . between an external i/o and another external i/o ? transfer data size 8, 16, or 32 bits ? trigger 1 . software trigger (register control) 2 . hardware trigger (external trigger input, causes of interrupts) ? transfer mode 1. single transfer (one unit of data is transferred by one trigger) 2 . successive transfer (specified number of data are transferred by one trigger) 3 . block transfer (data block of the specified size is transferred by one trigger) ? transfer address control the source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. in successive or block transfers, the address can be reset to the initial value upon completion of transfer. ? #dmaend output goes low at the last access of data transfer by each trigger. ? #dmaack output output for accessing the external i/o in every cycle during transfer. notes : ? a 0 ram (area 0 ), specific rom (area 1 ), area 2 , ivram (area 0 or area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) cannot be used for single-address transfer. ? single-address mode does not allow data transfer between memory devices. an external logic circuit is required to perform single-address transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram.
ii bus modules: high-speed dma (hsdma) ii-1-4 epson s1c33e08 technical manual timing chart of single-address mode ( 1) sram address #ce #rd #wr ? #dmaack #dmaend memory address read/write cycle figure ii.1.1.5 #dmaack/#dmaend signal output timing (sram, standard settings) ( 2) sdram the single-address mode does not support sdram.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.2 i/o pins of hsdma table ii. 1.2.1 lists the i/o pins used for hsdma. table ii. 1.2.1 i/o pins of hsdma pin name #dmareq0 #dmareq1 #dmareq2 #dmareq3 #dmaa ck0 #dmaa ck1 #dmaa ck2 #dmaa ck3 #dmaend0 #dmaend1 #dmaend2 #dmaend3 i/o i i i i o o o o o o o o function dma transf er request input pin f or hsdma ch.0 dma transf er request input pin f or hsdma ch.1 dma transf er request input pin f or hsdma ch.2 dma transf er request input pin f or hsdma ch.3 dma ac kno wledge signal output pin f or hsdma ch.0 dma ac kno wledge signal output pin f or hsdma ch.1 dma ac kno wledge signal output pin f or hsdma ch.2 dma ac kno wledge signal output pin f or hsdma ch.3 end-of-transf er signal output pin f or hsdma ch.0 end-of-transf er signal output pin f or hsdma ch.1 end-of-transf er signal output pin f or hsdma ch.2 end-of-transf er signal output pin f or hsdma ch.3 #dmareq x (dma request input pin) this pin is used to input a dma request signal from an external peripheral circuit. one data transfer opera - tion is performed by this trigger (either the rising edge or the falling edge of the signal can be selected). the #dmareq0 to #dmareq3 pins correspond to channel 0 to channel 3 , respectively. in addition to this external input, software trigger or a cause of interrupt can be selected for the hsdma trigger source using the register in the interrupt controller. #dmaack x (dma acknowledge signal output pin) this signal is output to indicate that a dma request has been a cknowledged by the dma controller. in single-address mode, the i/o device that is the source or destination of transfer outputs data to the external bus or takes in data from the external data synchronously with this signal. the #dmaack 0 to #dmaack3 pins correspond to channel 0 to channel 3 , respectively. this signal is also output in dual-address mode. see figures ii. 1.1.2, ii.1.1.3 and ii.1.1.5 for the waveform of the #dmaack x signal. #dmaend x (end-of-transfer signal output pin) this signal is output to indicate that the number of data transfer operations that is set in the control register have been completed. the #dmaend 0 to #dmaend3 pins correspond to channel 0 to channel 3 , respectively. note : the control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state is set to other than the hsdma. be - fore the hsdma signals assigned to these pins can be used, the functions of these pins must be switched for the hsdma by setting each corresponding port function select register. for details of pin functions and how to switch over, see section i.3.3, switching over the multi - plexed pin functions.
ii bus modules: high-speed dma (hsdma) ii-1-6 epson s1c33e08 technical manual ii.1.3 programming control information the hsdma operates according to the control information set i n the registers. note that some control bits change their functions according to the address mode. the following explains how to set the contents of control information. before using hsdma, make each the set - tings described below. ii.1.3.1 standard mode and advanced mode the hsdma in the s 1c33e08 is extended from that of the c33 std models. the s1c33e08 hsdma has two operating modes, the standard (std) mode of which functions are compatible with the existing c 33 std models and an advanced (adv) mode allowing use of the extended functions. table ii. 1.3.1.1 shows differences between standard mode and advanced mode. table ii. 1.3.1.1 differences between standard mode and advanced mode function source/destination address bit width w ord (32-bit) data transf er address decrement function with initialization ad v anced mode 32 bits available available standar d mode 28 bits unavailable unavailable to configure the hsdma in advanced mode, set hsdmaadv (d 0/0x30119 c) to 1 . the control registers (0x301162C0x30119 a) for the extended functions are enabled to write after this setting. at initial reset, hsd - maadv (d 0/0x30119c) is set to 0 and the hsdma enters standard mode. ? hsdmaadv : standard/advanced mode select bit in the hsdma std/adv mode select register (d0/0x30119c) the following descriptions unless otherwise specified are common contents for both modes. the extended func - tions in advanced mode are explained assuming that hsdmaadv (d 0/0x30119c) has been set to 1. notes : ? be sure to use the control registers for advanced mode when the hsdma is set to advanced mode. ? the standard or advanced mode currently set is applied to all the hsdma channels. it cannot be selected for each channel individually.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.3.2 sequential access time for idma and hsdma the dmac (idma and hsdma) has a higher priority for use of the ahb bus than the cpu, therefore the cpu must wait for use of the ahb bus while a dma transfer is in progress until it has completed in default settings. furthermore, the lcdc will be unable to read display data from the sdram if a dma transfer between sdram addresses starts. to avoid a problem, such as degradation in graphics performance, caused by dma, a dma trans - fer that exceeds a specified number of cycles (or sequential access time) can be temporarily suspended to release the bus ownership to the cpu or lcdc. the sequential access time can be set to unlimited or 64 to 940 cycles (in 64 mclk cycle increments) using dmaacctime[3:0] (d[3:0]/0x30119e). ? dmaacctime[3:0] : idma and hsdma sequential access time setup bits in the dma sequential access time register (d[3:0]/0x30119e) table ii. 1.3.2.1 setting the sequential access time dmaa cctime3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 dma sequential access time 960 cycles 896 cycles 832 cycles 768 cycles 704 cycles 640 cycles 576 cycles 512 cycles 448 cycles 384 cycles 320 cycles 256 cycles 192 cycles 128 cycles 64 cycles unlimited dmaa cctime2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 dmaa cctime1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 dmaa cctime0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0000 = unlimited) when unlimited is selected, the ahb bus will not be released until a dma transfer has been completed after it starts. specifying a number of cycles allows a dma transfer to be temporarily suspended when the specified cycles of data transfer have been executed to release the bus. the cpu or lcdc can perform a bus access during the sus - pended status. after that, the dmac resumes the data transfer that was being suspended.
ii bus modules: high-speed dma (hsdma) ii-1-8 epson s1c33e08 technical manual ii.1.3.3 setting the registers in dual-address mode make sure that the hsdma channel is disabled (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before setting the control information. ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) address mode the address mode select bit dualm x (d15/0x301122 + 0x10? x ) should be set to 1 (dual-address mode). this bit is set to 0 (single-address mode) at initial reset. ? dualm x : ch. x address mode select bit in the hsdma ch. x control register (d15/0x301122 + 0x10? x ) transfer mode a transfer mode should be set using d xmod[1:0] (d[15:14]/0x30112a + 0x10? x). ? d x mod[1:0] : ch. x transfer mode select bits in the hsdma ch. x high-order destination address setup register (d[15:14]/0x30112a + 0x10? x ) the following three transfer modes are available: single transfer mode (d xmod[1:0] (d[15:14]/0x30112a + 0x10? x) = 00 , default) in this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the specified size. if data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. successive transfer mode (d xmod[1:0] (d[15:14]/0x30112a + 0x10? x) = 01) in this mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 each time data is transferred. block transfer mode (d xmod[1:0] (d[15:14]/0x30112a + 0x10? x) = 10) in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ). if a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. transfer data size standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) datsize x (d14/0x301126 + 0x10? x) is used to set the unit size of data to be transferred. a half-word size ( 16 bits) is assumed if this bit is 1 and a byte size (8 bits) is assumed if this bit is 0 (default). ? datsize x : ch. x transfer data size select bit in the hsdma ch. x high-order source address setup register (d14/0x301126 + 0x10? x ) advanced mode (hsdmaadv (d 0/0x30119c) = 1) in advanced mode, wordsize x (d0/0x301162 + 0x10? x ) is provided to select word size (32 bits) in addition to half-word size and byte size that can be selected using datsize x (d14/0x301126 + 0x10? x). ? wordsize x : ch. x transfer data size select bit in the hsdma ch. x control register for adv mode (d0/0x301162 + 0x10? x ) table ii. 1.3.3.1 transfer data size selectable in advanced mode w ordsize x 1 0 0 t ransfer data siz e word (32 bits) half-word (16 bits) byte (8 bits) da tsize x x 1 0
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 block length when using block transfer mode (d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) = 10 ), the data block length (in units of the selected transfer data size) should be set using blklen x[7:0] (d[7:0]/0x301120 + 0x10? x). ? blklen x [7:0] : ch. x block length bits in the hsdma ch. x transfer counter register (d[7:0]/0x301120 + 0x10? x ) note : when performing data transfer in block transfer mode, the block size must not be set to 0. in single transfer and successive transfer modes, blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ) is used as bits 7C 0 of the transfer counter. transfer counter block transfer mode in block transfer mode, up to 16 bits of transfer count can be specified using tc x_l[7:0 ] (d[15:8]/0x301120 + 0x10? x ) and tc x_h[7:0] (d[7:0]/0x301122 + 0x10? x). ? tc x _l[7:0] : ch. x transfer counter [7:0] bits in the hsdma ch. x transfer counter register (d[15:8]/0x301120 + 0x10? x ) ? tc x _h[7:0] : ch. x transfer counter [15:8] bits in the hsdma ch. x control register (d[7:0]/0x301122 + 0x10? x ) single transfer and successive transfer modes in single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using blklen x [7:0 ] (d[7:0 ]/0x301120 + 0x10? x ), tc x _l[ 7:0 ] (d[15:8 ]/0x301120 + 0x10? x ) and tc x _h[ 7:0] (d[7:0]/0x301122 + 0x10? x ). note : the transfer count thus set is decremented according to the transfers performed. if the transfer count is set to 0, it is decremented to all fs by the first transfer performed. this means that you have set the maximum value that is determined by the number of bits available. source and destination addresses standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) in standard mode, a 28 -bit source address and a 28 -bit destination address for dma transfer can be speci - fied using s x adrl[ 15:0 ] (d[15:0 ]/0x301124 + 0x10 ? x ), s x adrh[ 11:0 ] (d[11:0 ]/0x301126 + 0x10 ? x ), d xadrl[15:0] (d[15:0]/0x301128 + 0x10? x) and d xadrh[11:0] (d[11:0]/0x30112a + 0x10? x). ? s x adrl[15:0] : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register (d[15:0]/0x301124 + 0x10? x ) ? s x adrh[11:0] : ch. x source address[27:16] in the hsdma ch. x high-order source address setup register (d[11:0]/0x301126 + 0x10? x ) ? d x adrl[15:0] : ch. x destination address[15:0] in the hsdma ch. x low-order destination address setup register (d[15:0]/0x301128 + 0x10? x ) ? d x adrh[11:0] : ch. x destination address[27:16] in the hsdma ch. x high-order destination address setup register (d[11:0]/0x30112a + 0x10? x ) advanced mode (hsdmaadv (d 0/0x30119c) = 1) in advanced mode, a 32 -bit source address and a 32 -bit destination address for dma transfer can be speci - fied using s x adrl[ 15:0 ] (d[15:0 ]/0x301164 + 0x10 ? x ), s x adrh[ 15:0 ] (d[15:0 ]/0x301166 + 0x10 ? x ), d xadrl[15:0] (d[15:0]/0x301168 + 0x10? x) and d xadrh[15:0] (d[15:0]/0x30116a + 0x10? x). ? s x adrl[15:0] : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register for adv mode (d[15:0]/0x301164 + 0x10? x ) ? s x adrh[15:0] : ch. x source address[31:16] in the hsdma ch. x high-order source address setup register for adv mode (d[15:0]/0x301166 + 0x10? x ) ? d x adrl[15:0] : ch. x destination address[15:0] in the hsdma ch. x low-order destination address setup register for adv mode (d[15:0]/0x301168 + 0x10? x ) ? d x adrh[15:0] : ch. x destination address[31:16] in the hsdma ch. x high-order destination address setup register for adv mode (d[15:0]/0x30116a + 0x10? x ) note : in advanced mode, be sure to use the control registers for advanced mode to set source/destina - tion addresses.
ii bus modules: high-speed dma (hsdma) ii-1-10 epson s1c33e08 technical manual address increment/decrement control standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) the source and/or destination addresses can be incremented or decremented when one data transfer is complet - ed. s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x ) (for source address) and d xin[1:0 ] (d[13:12]/0x30112 a + 0x10? x) (for destination address) are used to set this function. ? s x in[1:0] : ch. x source address control bits in the hsdma ch. x high-order source address setup register (d[13:12]/0x301126 + 0x10? x ) ? d x in[1:0] : ch. x destination address control bits in the hsdma ch. x high-order destination address setup register (d[13:12]/0x30112a + 0x10? x ) s xin[1:0]/d xin[1:0] = 00 : address fixed (default) the address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always read/write from/to the same address. s xin[1:0]/d xin[1:0] = 01 : address decremented without initialization the address is decremented by an amount equal to the specified data size when one data transfer is com - pleted. the address that has been decremented during transfer does not return to the initial value. s xin[1:0]/d xin[1:0] = 10 : address incremented with initialization the address is incremented by an amount equal to the specified data size when one data transfer is com - pleted. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the incremented address returns to the initial value when the block transfer is completed. s xin[1:0]/d xin[1:0] = 11 : address incremented without initialization the address is incremented by an amount equal to the specified data size when one data transfer is com - pleted. the address that has been incremented during transfer does not return to the initial value. advanced mode (hsdmaadv (d 0/0x30119c) = 1) the address control conditions set using s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x ) and d xin[1:0 ] (d[13:12]/ 0 x 30112 a + 0 x 10 ? x ) are effective in advanced mode. furthermore, advanced mode allows selection of address decremented with initialization. this condition can be selected using the s x id (d4/0x301162 + 0x10? x ) and d xid (d5/0x301162 + 0x10? x ). ? s x id : ch. x source address control bit in the hsdma ch. x control register for adv mode (d4/0x301162 + 0x10? x ) ? d x id : ch. x destination address control bit in the hsdma ch. x control register for adv mode (d5/0x301162 + 0x10? x ) when s x id (d4/0x301162 + 0x10? x ) and/or d x id (d5/0x301162 + 0x10? x ) are set to 0 (default), the condi - tions selected using s x in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 301126 + 0 x 10 ? x ) and/or d x in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 30112 a + 0 x 10 ? x ) are effective. when s x id (d4/0x301162 + 0x10? x ) and/or d x id (d5/0x301162 + 0x10? x ) are set to 1, address decremented with initialization is selected. s x id/d xid = 1 : address decremented with initialization the address is decremented by an amount equal to the specified data size when one data transfer is com - pleted. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the decremented address returns to the initial value when the block transfer is completed.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.3.4 setting the registers in single-address mode make sure that the hsdma channel is disabled (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before setting the control information. ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) address mode the address mode select bit dualm x (d15/0x301122 + 0x10? x ) should be set to 0 (single-address mode). this bit is set to 0 at initial reset. ? dualm x : ch. x address mode select bit in the hsdma ch. x control register (d15/0x301122 + 0x10? x ) transfer mode a transfer mode should be set using d xmod[1:0] (d[15:14]/0x30112a + 0x10? x). ? d x mod[1:0] : ch. x transfer mode select bits in the hsdma ch. x high-order destination address setup register (d[15:14]/0x30112a + 0x10? x ) table ii. 1.3.4.1 transfer mode d x mod1 1 1 0 0 d x mod0 1 0 1 0 mode in v alid bloc k transf er mode successiv e transf er mode single transf er mode refer to the explanation in section ii. 1.3.3, setting the registers in dual-address mode. direction of transfer the direction of data transfer should be set using d xdir (d14/0x301122 + 0x10? x). ? d x dir : ch. x transfer direction control bit in the hsdma ch. x control register (d14/0x301122 + 0x10? x ) memory write operations (data transfer from i/o device to memory) are specified by writing 1 and memory read operations (data transfer from memory to i/o device) are specified by writing 0. transfer data size standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) datsize x (d14/0x301126 + 0x10? x) is used to set the unit size of data to be transferred. a half-word size ( 16 bits) is assumed if this bit is 1 and a byte size (8 bits) is assumed if this bit is 0 (default). ? datsize x : ch. x transfer data size select bit in the hsdma ch. x high-order source address setup register (d14/0x301126 + 0x10? x ) advanced mode (hsdmaadv (d 0/0x30119c) = 1) in advanced mode, wordsize x (d0/0x301162 + 0x10? x ) is provided to select a word size (32 bits) in addi - tion to a half-word size and byte size that can be selected using datsize x (d14/0x301126 + 0x10? x). ? wordsize x : ch. x transfer data size select bit in the hsdma ch. x control register for adv mode (d0/0x301162 + 0x10? x ) table ii. 1.3.4.2 transfer data size selectable in advanced mode w ordsize x 1 0 0 t ransfer data siz e word (32 bits) half-word (16 bits) byte (8 bits) da tsize x x 1 0 datsize x (d14/0x301126 + 0x10? x ) and wordsize x (d0/0x301162 + 0x10? x ) are used to set the unit size of data to be transferred.
ii bus modules: high-speed dma (hsdma) ii-1-12 epson s1c33e08 technical manual block length when using block transfer mode (d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) = 10 ), the data block length (in units of the selected transfer data size) should be set using blklen x[7:0] (d[7:0]/0x301120 + 0x10? x). ? blklen x [7:0] : ch. x block length bits in the hsdma ch. x transfer counter register (d[7:0]/0x301120 + 0x10? x ) in single transfer and successive transfer modes, blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ) are used as bits 7 C0 of the transfer counter. note : when performing data transfer in block transfer mode, the block size must not be set to 0. transfer counter block transfer mode in block transfer mode, up to 16 bits of transfer count can be specified using tc x_l[7:0 ] (d[15:8]/0x301120 + 0x10? x ) and tc x_h[7:0] (d[7:0]/0x301122 + 0x10? x). ? tc x _l[7:0] : ch. x transfer counter [7:0] bits in the hsdma ch. x transfer counter register (d[15:8]/0x301120 + 0x10? x ) ? tc x _h[7:0] : ch. x transfer counter [15:8] bits in the hsdma ch. x control register (d[7:0]/0x301122 + 0x10? x ) single transfer and successive transfer modes in single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using blklen x [7:0 ] (d[7:0 ]/0x301120 + 0x10? x ), tc x _l[ 7:0 ] (d[15:8 ]/0x301120 + 0x10? x ) and tc x _h[ 7:0] (d[7:0]/0x301122 + 0x10? x ). memory address standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) in standard mode, s x adrl[ 15:0 ] (d[15:0 ]/0x301124 + 0x10? x ) and s x adrh[ 11:0 ] (d[11:0 ]/0x301126 + 0x10? x) are used to specify a 28-bit memory address. ? s x adrl[15:0] : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register (d[15:0]/0x301124 + 0x10? x ) ? s x adrh[11:0] : ch. x source address[27:16] in the hsdma ch. x high-order source address setup register (d[11:0]/0x301126 + 0x10? x ) advanced mode (hsdmaadv (d 0/0x30119c) = 1) in advanced mode, s x adrl[ 15:0 ] (d[15:0 ]/0x301164 + 0x10? x ) and s x adrh[ 15:0 ] (d[15:0 ]/0x301166 + 0x10? x) are used to specify a 32-bit memory address. ? s x adrl[15:0] : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register for adv mode (d[15:0]/0x301164 + 0x10? x ) ? s x adrh[15:0] : ch. x source address[31:16] in the hsdma ch. x high-order source address setup register for adv mode (d[15:0]/0x301166 + 0x10? x ) note : in advanced mode, be sure to use the control registers for advanced mode to set a memory ad - dress. in single-address mode, data transfer is performed between the memory connected to the system interface and an external i/o device. the i/o device is accessed directly by the #dmaack x signal, so it is unnecessary to specify an address. d xadrl[15:0 ] (d[15:0]/0x301168 + 0x10? x ) and d xadrh[15:0 ] (d[11:0]/0x30116 a + 0x10? x) are not used in single-address mode. address increment/decrement control standard mode (hsdmaadv (d 0/0x30119c) = 0 , default) the memory addresses can be incremented or decremented when one data transfer is completed. s x in[ 1:0] (d[13:12]/0x301126 + 0x10? x) is used to set this function. ? s x in[1:0] : ch. x source address control bits in the hsdma ch. x high-order source address setup register (d[13:12]/0x301126 + 0x10? x )
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table ii. 1.3.4.3 address control s x in1 1 1 0 0 s x in0 1 0 1 0 address contr ol increment without initialization increment with initialization decrement without initialization fix ed advanced mode (hsdmaadv (d 0/0x30119c) = 1) the address control condition set using s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) is effective in advanced mode. furthermore, advanced mode allows selection of address decremented with initialization. this condi - tion can be selected using the s xid (d4/0x301162 + 0x10? x). ? s x id : ch. x source address control bit in the hsdma ch. x control register for adv mode (d4/0x301162 + 0x10? x ) when s x id (d4/0x301162 + 0x10? x ) is set to 0 (default), the condition selected using s xin[1:0 ] (d[13:12]/ 0x301126 + 0x10? x ) is effective. when s x id (d4/0x301162 + 0x10? x ) is set to 1, address decremented with initialization is selected. refer to the explanation in section ii. 1.3.3, setting the registers in dual-address mode. d xin[1:0 ] (d[13:12]/0x30112 a + 0x10? x ) and d x id (d5/0x301162 + 0x10? x ) are not used in single-address mode.
ii bus modules: high-speed dma (hsdma) ii-1-14 epson s1c33e08 technical manual ii.1.4 enabling/disabling dma transfer the hsdma transfer is enabled by writing 1 to hs x_en (d0/0x30112c + 0x10? x). ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) however, the control information must always be set correctly before enabling a dma transfer. note that the control information cannot be set when hs x_en (d0/0x30112c + 0x10? x) = 1. when hs x_en (d0/0x30112c + 0x10? x) is set to 0, hsdma requests are no longer accepted. when a dma transfer is completed (transfer counter = 0 ), hs x _en (d0/0x30112 c + 0x10? x ) is reset to 0 to dis - able the following trigger inputs.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.5 trigger source a hsdma trigger source for each channel can be selected from among 15 types using hsd x s[ 3:0 ] (d[7:0 ]/ 0x300298, d[7:0]/0x300299 ). this function is supported by the interrupt controller. ? hsd0s[3:0] : ch.0 trigger set-up bits in the hsdma ch.0C1 trigger set-up register (d[3:0]/0x300298) ? hsd1s[3:0] : ch.1 trigger set-up bits in the hsdma ch.0C1 trigger set-up register (d[7:4]/0x300298) ? hsd2s[3:0] : ch.2 trigger set-up bits in the hsdma ch.2C3 trigger set-up register (d[3:0]/0x300299) ? hsd3s[3:0] : ch.3 trigger set-up bits in the hsdma ch.2C3 trigger set-up register (d[7:4]/0x300299) table ii. 1.5.1 shows the setting value and the corresponding trigger source. table ii. 1.5.1 hsdma trigger source v alue 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 ch.0 trigger sour ce softw are tr igger #dmareq0 input (f alling edge) #dmareq0 input (r ising edge) po rt 0 input po rt 4 input (reser v ed) 16-bit timer 0 compare b 16-bit timer 0 compare a 16-bit timer 4 compare b i 2 s left ser ial i/f ch.0 rx b uff er full ser ial i/f ch.0 tx b uff er empty a/d con v ersion completion po rt 8 input (spi interr upt) po rt 12 input ch.1 trigger sour ce softw are tr igger #dmareq1 input (f alling edge) #dmareq1 input (r ising edge) po rt 1 input po rt 5 input (reser v ed) 16-bit timer 1 compare b 16-bit timer 1 compare a 16-bit timer 5 compare b i 2 s r ight ser ial i/f ch.1 rx b uff er full ser ial i/f ch.1 tx b uff er empty a/d con v ersion completion po rt 9 input (usb pdreq) po rt 13 input ch.2 trigger sour ce softw are tr igger #dmareq2 input (f alling edge) #dmareq2 input (r ising edge) po rt 2 input po rt 6 input (reser v ed) 16-bit timer 2 compare b 16-bit timer 2 compare a (reser v ed) spi transmit dma request ser ial i/f ch.2 rx b uff er full ser ial i/f ch.2 tx b uff er empty a/d con v ersion completion po rt 10 input (usb interr upt) po rt 14 input ch.3 trigger sour ce softw are tr igger #dmareq3 input (f alling edge) #dmareq3 input (r ising edge) po rt 3 input po rt 7 input (reser v ed) 16-bit timer 3 compare b 16-bit timer 3 compare a (reser v ed) spi receiv e dma request (reser v ed) (reser v ed) a/d con v ersion completion po rt 11 input (dcsio interr upt) po rt 15 input by selecting a cause of interrupt with the hsdma trigger set-up register, the hsdma channel is invoked when the selected cause of interrupt occurs. the interrupt control bits (cause-of-interrupt flag, interrupt enable register, idma request register, interrupt priority register) do not affect this invocation. the cause of interrupt that invokes hsdma sets the cause-of-interrupt flag and hsdma does not reset the flag. consequently, when the dma trans - fer is completed (even if the transfer counter is not 0 ), an interrupt request to the cpu will be generated if the inter - rupt has been enabled. to generate an interrupt only when the transfer counter reaches 0 , disable the interrupt by the cause of interrupt that invokes hsdma and use the hsdma transfer completion interrupt. when software trigger is selected, the hsdma channel can be invoked by writing 1 to hst x (d x/0x30029a). ? hst x : ch. x software trigger bit in the hsdma software trigger register (d x /0x30029a) when the selected trigger occurs, the trigger flag is set to 1 to invoke the hsdma channel. the hsdma starts a dma transfer if it has been enabled and the trigger flag is cleared by the hardware at the same time. this makes it possible to queue the hsdma triggers that have been generated. the trigger flag can be read and cleared using hs x_tf (d0/0x30112e + 0x10? x). ? hs x _tf : ch. x trigger flag status/clear bit in the hsdma ch. x trigger flag register (d0/0x30112e + 0x10? x ) by writing 1 to this bit, the set trigger flag can be cleared if the dma transfer has not been started. when this bit is read, 1 indicates that the flag is set and 0 indicates that the flag is cleared. note : the following shows the priority order of channels when dma triggers with the same interrupt level occur in two or more hsdma and idma channels. priority channel high lo w hsdma ch.0 > ch.1 > ch.2 > ch.3 > idma softw are tr igger > idma hardw are tr igger
ii bus modules: high-speed dma (hsdma) ii-1-16 epson s1c33e08 technical manual ii.1.6 operation of hsdma an hsdma channel starts data transfer by the selected trigger source. make sure that transfer conditions and a trigger source are set and the hsdma channel is enabled before starting a dma transfer. ii.1.6.1 operation in dual-address mode in dual-address mode, both the source and destination addresses are accessed according to the bus condition set by the sramc and sdramc. hsdma has three transfer modes, in each of which data transfer operates differently. the following describes the operation of hsdma in each transfer mode. single transfer mode (dual-address mode) the channel for which d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) in control information is set to 00 oper - ates in single transfer mode. in this mode, a transfer operation invoked by one trigger is completed after trans - ferring one data unit of the size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ). if a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. ? d x mod[1:0] : ch. x transfer mode select bits in the hsdma ch. x high-order destination address setup register (d[15:14]/0x30112a + 0x10? x ) ? datsize x : ch. x transfer data size select bit in the hsdma ch. x high-order source address setup register (d14/0x301126 + 0x10? x ) ? wordsize x : ch. x transfer data size select bit in the hsdma ch. x control register for adv mode (d0/0x301162 + 0x10? x ) the operation of hsdma in single transfer mode is shown by the flow chart in figure ii. 1.6.1.1. start end data read from source (1 byte, 1 half word or 1 word) clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en data write to destination (1 byte, 1 half word or 1 word) transfer counter - 1 set cause-of-interrupt flag fhdm x transfer counter = 0 n y increment/decrement address ? ? : according to s x in/d x in or s x id/d x id settings figure ii.1.6.1.1 operation flow in single transfer mode
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared and then data of the size set in the control information is read from the source address. ? hs x _tf : ch. x trigger flag status/clear bit in the hsdma ch. x trigger flag register (d0/0x30112e + 0x10? x ) (2 ) the read data is written to the destination address. (3 ) the addresses are incremented or decremented according to the s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x)/ d x in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 30112 a + 0 x 10 ? x ) or s x id (d 4 / 0 x 301162 + 0 x 10 ? x )/d x id (d 5 / 0 x 301162 + 0 x 10 ? x ) settings. ? 1 ? s x in[1:0] : ch. x source address control bits in the hsdma ch. x high-order source address setup register (d[13:12]/0x301126 + 0x10? x ) ? d x in[1:0] : ch. x destination address control bits in the hsdma ch. x high-order destination address setup register (d[13:12]/0x30112a + 0x10? x ) ? s x id : ch. x source address control bit in the hsdma ch. x control register for adv mode (d4/0x301162 + 0x10? x ) ? d x id : ch. x destination address control bit in the hsdma ch. x control register for adv mode (d5/0x301162 + 0x10? x ) (4 ) the transfer counter is decremented. (5 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) ?1: in standard mode, s xid (d4/0x301162 + 0x10? x) and d xid (d5/0x301162 + 0x10? x ) are both fixed at 0.
ii bus modules: high-speed dma (hsdma) ii-1-18 epson s1c33e08 technical manual successive transfer mode (dual-address mode) the channel for which d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) in control information is set to 01 oper - ates in successive transfer mode. in this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 by one transfer executed. the operation of hsdma in successive transfer mode is shown by the flow chart in figure ii. 1.6.1.2. start end transfer counter - 1 transfer counter = 0 n y increments/decrements address ? ? : according to s x in/d x in or s x id/d x id settings data read from source (1 byte, 1 half word or 1 word) data write to destination (1 byte, 1 half word or 1 word) clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en set cause-of-interrupt flag fhdm x restores initial values to address ? ? : according to s x in/d x in or s x id/d x id settings figure ii.1.6.1.2 operation flow in successive transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared and then data of the size set in the control information is read from the source address. (2 ) the read data is written to the destination address. (3 ) the addresses are incremented or decremented according to the s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x)/ d x in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 30112 a + 0 x 10 ? x ) or s x id (d 4 / 0 x 301162 + 0 x 10 ? x )/d x id (d 5 / 0 x 301162 + 0 x 10 ? x ) settings. ? 1 (4 ) the transfer counter is decremented. (5 ) steps (1) to (4) are repeated until the transfer counter reaches 0. (6 ) the address returns to the initial value if s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x)/d xin[1:0 ] (d[13:12]/ 0x30112a + 0x10? x) is 10 or s xid (d4/0x301162 + 0x10? x)/d xid (d5/0x301162 + 0x10? x) is 1. ? 1 (7 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ?1: in standard mode, s xid (d4/0x301162 + 0x10? x) and d xid (d5/0x301162 + 0x10? x ) are both fixed at 0.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 block transfer mode (dual-address mode) the channel for which d x mod[ 1 : 0 ] (d[ 15 : 14 ]/ 0 x 30112 a + 0 x 10 ? x ) in control information is set to 10 operates in block transfer mode. in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ). if a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. the operation of hsdma in block transfer mode is shown by the flow chart in figure ii. 1.6.1.3. ? blklen x [7:0] : ch. x block length bits in the hsdma ch. x transfer counter register (d[7:0]/0x301120 + 0x10? x ) start end block size - 1 restores initial values to block size and address ? block size = 0 1-block transfer n y transfer counter - 1 transfer counter = 0 n y ? : according to s x in/d x in or s x id/d x id settings data read from source (1 byte, 1 half word or 1 word) data write to destination (1 byte, 1 half word or 1 word) increments/decrements address ? ? : according to s x in/d x in or s x id/d x id settings clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en set cause-of-interrupt flag fhdm x figure ii.1.6.1.3 operation flow in block transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared and then data of the size set in the control information is read from the source address. (2 ) the read data is written to the destination address. (3) the address is incremented or decremented and blklen x[7:0] (d[7:0]/0x301120 + 0x10? x) is decremented. (4 ) steps (1) to (3) are repeated until blklen x[7:0] (d[7:0]/0x301120 + 0x10? x) reaches 0. (5 ) the address returns to the initial value if s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x)/d xin[1:0 ] (d[13:12]/ 0x30112a + 0x10? x) is 10 or s xid (d4/0x301162 + 0x10? x)/d xid (d5/0x301162 + 0x10? x) is 1. ? 1 (6 ) the transfer counter is decremented. (7 ) steps (1) to (6) are repeated until the transfer counter reaches 0. (8 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ?1: in standard mode, s xid (d4/0x301162 + 0x10? x) and d xid (d5/0x301162 + 0x10? x ) are both fixed at 0.
ii bus modules: high-speed dma (hsdma) ii-1-20 epson s1c33e08 technical manual ii.1.6.2 operation in single-address mode in single-address mode, data read/write operations are performed simultaneously. the data transfer direction (read from i/o device write to memory or read from memory write to i/o device) is set using d x dir (d 14 / 0 x 301122 + 0x10? x ). ? d x dir : ch. x transfer direction control bit in the hsdma ch. x control register (d14/0x301122 + 0x10? x ) single-address mode has three transfer modes, in each of which data transfer operates differently. the following describes the operation of hsdma in single-address mode. #dmaack x signal output and bus operation when the hsdma circuit accepts the dma request, it outputs a low-level pulse from the #dmaack x pin and starts bus operation for the memory at the same time. the contents of this bus operation are as follows: ? data transfer from i/o device to memory (d xdir (d14/0x301122 + 0x10? x) = 1) the address that has been set in the memory address register is output to the address bus. a write operation is performed under the interface conditions set on the area to which the memory at the desti - nation of transfer belongs. the data bus is left floating. the external i/o device outputs the transfer data onto the data bus using the #dmaack x signal as the read sig - nal. the memory takes in this data using the write signal. ? data transfer from memory to an i/o device (d xdir (d14/0x301122 + 0x10? x) = 0 , default) the address that has been set in the memory address register is output to the address bus. a read operation is performed under the interface conditions set on the area to which the memory at the source of transfer belongs. the memory outputs the transfer data onto the data bus using the read signal. the external i/o device takes in the data from the data bus using the #dmaack x signal as the write signal. the number of bus operations for a dma transfer is decided according to the transfer data size and i/o device size as shown in the table below. table ii. 1.6.2.1 number of bus operations per dma transfer t ransfer data siz e 32 bits 32 bits 16 bits other number of b us operations 4 2 2 1 i/o de vice siz e 8 bits 16 bits 8 bits notes : ? a 0 ram (area 0 ), specific rom (area 1 ), area 2 , ivram (area 0 or area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) cannot be used for single-address transfer. ? single-address mode does not allow data transfer between memory devices. an external logic circuit is required to perform single-address transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. #dmaend x signal output when the transfer counter reaches 0 , the end-of-transfer signal is output from the #dmaend x pin indicating that a specified number of transfers has been completed. at the same time, the cause of interrupt (completion of hsdma) is generated.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 single transfer mode (single-address mode) the channel for which d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) in control information is set to 00 oper - ates in single transfer mode. in this mode, a transfer operation invoked by one trigger is completed after trans - ferring one data unit of the size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ). if a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. ? d x mod[1:0] : ch. x transfer mode select bits in the hsdma ch. x high-order destination address setup register (d[15:14]/0x30112a + 0x10? x ) ? datsize x : ch. x transfer data size select bit in the hsdma ch. x high-order source address setup register (d14/0x301126 + 0x10? x ) ? wordsize x : ch. x transfer data size select bit in the hsdma ch. x control register for adv mode (d0/0x301162 + 0x10? x ) the operation of hsdma in single transfer mode is shown by the flow chart in figure ii. 1.6.2.1. start end clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en transfer counter - 1 set cause-of-interrupt flag fhdm x transfer counter = 0 n y increment/decrement address ? ? : according to s x in or s x id settings data read from source and data write to destination (1 byte, 1 half word or 1 word) figure ii.1.6.2.1 operation flow in single transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared. data of the size set in the control information is read from the external memory or i/o device according to the specified di - rection and is written to the i/o device or external memory. ? 1 ? hs x _tf : ch. x trigger flag status/clear bit in the hsdma ch. x trigger flag register (d0/0x30112e + 0x10? x ) (2 ) the addresses are incremented or decremented according to the s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x) or s xid (d4/0x301162 + 0x10? x) settings. ? 2 ? s x in[1:0] : ch. x source address control bits in the hsdma ch. x high-order source address setup register (d[13:12]/0x301126 + 0x10? x ) ? s x id : ch. x source address control bit in the hsdma ch. x control register for adv mode (d4/0x301162 + 0x10? x ) (3 ) the transfer counter is decremented. (4 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x )
ii bus modules: high-speed dma (hsdma) ii-1-22 epson s1c33e08 technical manual ?1 : the data bus is placed in high-impedance state during reading from the i/o device. furthermore, the exter - nal memory read/write address is delivered from the memory address registers in the control information s x adrl and s x adrh. ? s x adrl : ch. x source address[15:0] in the hsdma ch. x low-order source address setup register (std mode: d[15:0]/0x301124 + 0x10? x , adv mode: d[15:0]/0x301164 + 0x10? x ) ? s x adrh : ch. x source address (high-order bits) in the hsdma ch. x high-order source address setup register (std mode: d[11:0]/0x301126 + 0x10? x , adv mode: d[15:0]/0x301166 + 0x10? x ) ?2: in standard mode, s xid (d4/0x301162 + 0x10? x ) is fixed at 0. successive transfer mode (single-address mode) the channel for which d xmod[1:0 ] (d[15:14]/0x30112 a + 0x10? x ) in control information is set to 01 oper - ates in successive transfer mode. in this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 by one transfer executed. the operation of hsdma in successive transfer mode is shown by the flow chart in figure ii. 1.6.2.2. start end transfer counter - 1 transfer counter = 0 n y increments/decrements address ? ? : according to s x in or s x id settings data read from source and data write to destination (1 byte, 1 half word or 1 word) clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en set cause-of-interrupt flag fhdm x restores initial values to address ? ? : according to s x in or s x id settings figure ii.1.6.2.2 operation flow in successive transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared. data of the size set in the control information is read from the external memory or i/o device according to the specified di - rection and is written to the i/o device or external memory. ? 1 (2 ) the addresses are incremented or decremented according to the s xin[1:0 ] (d[13:12]/0x301126 + 0x10? x) or s xid (d4/0x301162 + 0x10? x) settings. ? 2 (3 ) the transfer counter is decremented. (4 ) steps (1) to (3) are repeated until the transfer counter reaches 0. (5 ) the address returns to the initial value if s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) is 10 or s x id (d 4/ 0x301162 + 0x10? x) is 1. ? 2 (6 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ?1 : the data bus is placed in high-impedance state during reading from the i/o device. furthermore, the exter - nal memory read/write address is delivered from the memory address registers in the control information s x adrl and s x adrh. ?2: in standard mode, s xid (d4/0x301162 + 0x10? x ) is fixed at 0.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 block transfer mode (single-address mode) the channel for which d x mod[ 1 : 0 ] (d[ 15 : 14 ]/ 0 x 30112 a + 0 x 10 ? x ) in control information is set to 10 operates in block transfer mode. in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ). if a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. the operation of hsdma in block transfer mode is shown by the flow chart in figure ii. 1.6.2.3. ? blklen x [7:0] : ch. x block length bits in the hsdma ch. x transfer counter register (d[7:0]/0x301120 + 0x10? x ) start end block size - 1 restores initial values to block size and address ? block size = 0 1-block transfer n y transfer counter - 1 transfer counter = 0 n y ? : according to s x in or s x id settings increments/decrements address ? ? : according to s x in or s x id settings clear trigger flag hs x _tf to accept next trigger clear hsdma enable bit hs x _en set cause-of-interrupt flag fhdm x data read from source and data write to destination (1 byte, 1 half word or 1 word) figure ii.1.6.2.3 operation flow in block transfer mode (1 ) when a trigger is accepted, the trigger flag hs x _tf (d0/0x30112 e + 0x10? x ) is cleared. data of the size set in the control information is read from the external memory or i/o device according to the specified di - rection and is written to the i/o device or external memory. ?1 (2 ) the address is incremented or decremented and blklen x [ 7 : 0 ] (d[ 7 : 0 ]/ 0 x 301120 + 0 x 10 ? x ) is decremented. (3 ) steps (1) to (2) are repeated until blklen x[7:0] (d[7:0]/0x301120 + 0x10? x) reaches 0. (4 ) the address returns to the initial value if s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) is 10 or s x id (d 4/ 0x301162 + 0x10? x) is 1. ? 2 (5 ) the transfer counter is decremented. (6 ) steps (1) to (5) are repeated until the transfer counter reaches 0. (7 ) the hsdma enable bit hs x _en (d0/0x30112 c + 0x10? x ) is cleared and hsdma cause-of-interrupt flag in itc is set when the transfer counter reaches 0. ?1 : the data bus is placed in high-impedance state during reading from the i/o device. furthermore, the exter - nal memory read/write address is delivered from the memory address registers in the control information s x adrl and s x adrh. ?2: in standard mode, s xid (d4/0x301162 + 0x10? x ) is fixed at 0.
ii bus modules: high-speed dma (hsdma) ii-1-24 epson s1c33e08 technical manual ii.1.7 interrupt function of hsdma the dma controller can generate an interrupt when the transfer counter in each hsdma channel reaches 0. furthermore, channels 0 and 1 can invoke idma using their cause of interrupt. control registers of the interrupt controller table ii. 1.7.1 shows the control registers of the interrupt controller that are provided for each channel. table ii. 1.7.1 control registers of interrupt controller channel ch. 0 ch. 1 ch. 2 ch. 3 cause-of-interrupt fla g fhdm0(d0/0x300281) fhdm1(d1/0x300281) fhdm2(d2/0x300281) fhdm3(d3/0x300281) interrupt priority register phsd0l[2:0](d[2:0]/0x300263) phsd1l[2:0](d[6:4]/0x300263) phsd2l[2:0](d[2:0]/0x300264) phsd3l[2:0](d[6:4]/0x300264) interrupt enable register ehdm0(d0/0x300271) ehdm1(d1/0x300271) ehdm2(d2/0x300271) ehdm3(d3/0x300271) the hsdma controller sets the hsdma cause-of-interrupt flag to 1 when the transfer counter reaches 0 after completing a series of hsdma transfers. if the corresponding bit of the interrupt enable register is set to 1 at this time, an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit set to 0 . the hsdma cause-of-interrupt flag is always set to 1 when the data transfer in each channel is com - pleted no matter what value the interrupt enable register bit is set to. (this is true even when it is set to 0.) the interrupt priority register sets an interrupt priority level ( 0 to 7 ). an interrupt request to the cpu is accepted only when there is no other interrupt request of higher priority. furthermore, it is only when the psr's ie bit = 1 (interrupt enable) and the set value of il is smaller than the hsdma interrupt level which is set in the inter - rupt priority register that the cpu actually accepts a hsdma interrupt. for details about the interrupt control register and for the device operation when an interrupt occurs, refer to section iii. 2 , interrupt controller (itc). intelligent dma intelligent dma (idma) can be invoked by the end-of-transfer interrupt source of channels 0 and 1 of hs - dma. the following shows the idma channels set in hsdma: idma channel channel 0 end-of-transfer interrupt: 0x05 channel 1 end-of-transfer interrupt: 0x06 before idma can be invoked, the corresponding bits of the idma request and idma enable registers must be set to 1. settings of transfer conditions on the idma side are also required. table ii. 1.7.2 control bits for idma transfer channel ch. 0 ch. 1 idma request bit rhdm0(d4/0x300290) rhdm1(d5/0x300290) idma enable bit dehdm0(d4/0x300294) dehdm1(d5/0x300294) if the idma request and enable bits are set to 1 , idma is invoked through generation of a cause of interrupt. no interrupt request is generated at that point. an interrupt request is generated after the dma transfer is com - pleted. the registers can also be set so as not to generate an interrupt, with only a dma transfer performed. for details on idma transfers and interrupt control upon completion of idma transfer, refer to section ii. 2, intelligent dma (idma). trap vector the trap vector addresses for causes of interrupt in each channel are set by default as follows: channel 0 end-of-transfer interrupt: 0xc00058 channel 1 end-of-transfer interrupt: 0xc0005c channel 2 end-of-transfer interrupt: 0xc00060 channel 3 end-of-transfer interrupt: 0xc00064 note that the trap table base address can be modified using the ttbr register.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.1.8 hsdma operating clock the hsdma circuit is clocked by the dma_clk clock (= mclk) generated by the cmu. for details on how to control the clock, see section iii. 1, clock management unit (cmu). controlling the supply of the hsdma operating clock dma_clk is supplied to the dma controller with default settings. when dma transfer is not performed, the clock supply can be turned off using dma_cke (d 1/0x301b04 ) to reduce the amount of power consumed on the chip. ? dma_cke : dmac clock control bit in the gated clock control register 1 (d1/0x301b04) setting dma_cke (d 1/0x301b04 ) to 0 (initially 1 ) turns off the corresponding clock supply to the dma con - troller. clock state in standby mode the supply of dma_clk stops depending on type of standby mode. halt mode: dma_clk is supplied the same way as in normal mode (when dma_cke = 1). sleep mode: the supply of dma_clk stops. therefore, the dma controller also stops operating in sleep m ode.
ii bus modules: high-speed dma (hsdma) ii-1-26 epson s1c33e08 technical manual ii.1.9 details of control registers table ii. 1.9.1 list of hsdma registers address 0x00301120 0x00301122 0x00301124 0x00301126 0x00301128 0x0030112a 0x0030112c 0x0030112e 0x00301130 0x00301132 0x00301134 0x00301136 0x00301138 0x0030113a 0x0030113c 0x0030113e 0x00301140 0x00301142 0x00301144 0x00301146 0x00301148 0x0030114a 0x0030114c 0x0030114e 0x00301150 0x00301152 0x00301154 0x00301156 0x00301158 0x0030115a 0x0030115c 0x0030115e function sets ch.0 low-order transfer counter data and block length. sets ch.0 address mode and high-order transfer counter data. sets ch.0 low-order source address. sets ch.0 high-order source address, transfer data size, and source address inc/dec condition. sets ch.0 low-order destination address. sets ch.0 high-order destination address, transfer mode, and destination address inc/dec condition. enables ch.0 dma transfer. ch.0 trigger status sets ch.1 low-order transfer counter data and block length. sets ch.1 address mode and high-order transfer counter data. sets ch.1 low-order source address. sets ch.1 high-order source address, transfer data size, and source address inc/dec condition. sets ch.1 low-order destination address. sets ch.1 high-order destination address, transfer mode, and destination address inc/dec condition. enables ch.1 dma transfer. ch.1 trigger status sets ch.2 low-order transfer counter data and block length. sets ch.2 address mode and high-order transfer counter data. sets ch.2 low-order source address. sets ch.2 high-order source address, transfer data size, and source address inc/dec condition. sets ch.2 low-order destination address. sets ch.2 high-order destination address, transfer mode, and destination address inc/dec condition. enables ch.2 dma transfer. ch.2 trigger status sets ch.3 low-order transfer counter data and block length. sets ch.3 address mode and high-order transfer counter data. sets ch.3 low-order source address. sets ch.3 high-order source address, transfer data size, and source address inc/dec condition. sets ch.3 low-order destination address. sets ch.3 high-order destination address, transfer mode, and destination address inc/dec condition. enables ch.3 dma transfer. ch.3 trigger status register name hsdma ch.0 transfer counter register (phs0_cnt) hsdma ch.0 control register hsdma ch.0 low-order source address setup register (phs0_sadr) hsdma ch.0 high-order source address setup register hsdma ch.0 low-order destination address setup register (phs0_dadr) hsdma ch.0 high-order destination address setup register hsdma ch.0 enable register (phs0_en) hsdma ch.0 trigger flag register (phs0_tf) hsdma ch.1 transfer counter register (phs1_cnt) hsdma ch.1 control register hsdma ch.1 low-order source address setup register (phs1_sadr) hsdma ch.1 high-order source address setup register hsdma ch.1 low-order destination address setup register (phs1_dadr) hsdma ch.1 high-order destination address setup register hsdma ch.1 enable register (phs1_en) hsdma ch.1 trigger flag register (phs1_tf) hsdma ch.2 transfer counter register (phs2_cnt) hsdma ch.2 control register hsdma ch.2 low-order source address setup register (phs2_sadr) hsdma ch.2 high-order source address setup register hsdma ch.2 low-order destination address setup register (phs2_dadr) hsdma ch.2 high-order destination address setup register hsdma ch.2 enable register (phs2_en) hsdma ch.2 trigger flag register (phs2_tf) hsdma ch.3 transfer counter register (phs3_cnt) hsdma ch.3 control register hsdma ch.3 low-order source address setup register (phs3_sadr) hsdma ch.3 high-order source address setup register hsdma ch.3 low-order destination address setup register (phs3_dadr) hsdma ch.3 high-order destination address setup register hsdma ch.3 enable register (phs3_en) hsdma ch.3 trigger flag register (phs3_tf) siz e 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 address 0x00301162 0x00301164 0x00301166 0x00301168 0x0030116a 0x00301172 0x00301174 0x00301176 0x00301178 0x0030117a 0x00301182 0x00301184 0x00301186 0x00301188 0x0030118a 0x00301192 0x00301194 0x00301196 0x00301198 0x0030119a 0x0030119c 0x0030119e function selects ch.0 adv mode functions. sets ch.0 low-order source address for adv mode. sets ch.0 high-order source address for adv mode. sets ch.0 low-order destination address for adv mode. sets ch.0 high-order destination address for adv mode. selects ch.1 adv mode functions. sets ch.1 low-order source address for adv mode. sets ch.1 high-order source address for adv mode. sets ch.1 low-order destination address for adv mode. sets ch.1 high-order destination address for adv mode. selects ch.2 adv mode functions. sets ch.2 low-order source address for adv mode. sets ch.2 high-order source address for adv mode. sets ch.2 low-order destination address for adv mode. sets ch.2 high-order destination address for adv mode. selects ch.3 adv mode functions. sets ch.3 low-order source address for adv mode. sets ch.3 high-order source address for adv mode. sets ch.3 low-order destination address for adv mode. sets ch.3 high-order destination address for adv mode. selects standard or advanced mode. sets sequential access time for idma and hsdma. register name hsdma ch.0 control register (phs0_advmode) for adv mode hsdma ch.0 low-order source address setup register (phs0_ad_sadr) for adv mode hsdma ch.0 high-order source address setup register for adv mode hsdma ch.0 low-order destination address setup register (phs0_adv_dadr) for adv mode hsdma ch.0 high-order destination address setup register for adv mode hsdma ch.1 control register (phs1_advmode) for adv mode hsdma ch.1 low-order source address setup register (phs1_ad_sadr) for adv mode hsdma ch.1 high-order source address setup register for adv mode hsdma ch.1 low-order destination address setup register (phs1_adv_dadr) for adv mode hsdma ch.1 high-order destination address setup register for adv mode hsdma ch.2 control register (phs2_advmode) for adv mode hsdma ch.2 low-order source address setup register (phs2_ad_sadr) for adv mode hsdma ch.2 high-order source address setup register for adv mode hsdma ch.2 low-order destination address setup register (phs2_adv_dadr) for adv mode hsdma ch.2 high-order destination address setup register for adv mode hsdma ch.3 control register (phs3_advmode) for adv mode hsdma ch.3 low-order source address setup register (phs3_ad_sadr) for adv mode hsdma ch.3 high-order source address setup register for adv mode hsdma ch.3 low-order destination address setup register (phs3_adv_dadr) for adv mode hsdma ch.3 high-order destination address setup register for adv mode hsdma std/adv mode select register (phs_cntlmode) dma sequential access time register (phs_acctime) siz e 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 the following describes each hsdma control register. the hsdma control registers are mapped in the 16 -bit device area from 0x301120 to 0x30119 e, and can be ac - cessed in units of half-words or bytes. note : when setting the hsdma control registers, be sure to write a 0, and not a 1, for all reserved bits.
ii bus modules: high-speed dma (hsdma) ii-1-28 epson s1c33e08 technical manual 0x301120C0x301150: hsdma ch. x transfer counter registers (phs x _cnt) name address register name bit function setting init. r/w remarks tc x _l7 tc x _l6 tc x _l5 tc x _l4 tc x _l3 tc x _l2 tc x _l1 tc x _l0 blklen x 7 blklen x 6 blklen x 5 blklen x 4 blklen x 3 blklen x 2 blklen x 1 blklen x 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch. x transfer c ounter[7:0 ] (block transfer mode) ch. x transfer counter[15:8] (single/successive transfer mode) ch. x block lengt h (block transfer mode) ch. x transfer counter[7:0] (single/successive transfer mode) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w 00301120 | 00301150 (hw) hsdma ch. x transfer counter register (phs x _cnt) note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301120 hsdma ch.0 transfer counter register (phs0_cnt) 0x301130 hsdma ch.1 transfer counter register (phs1_cnt) 0x301140 hsdma ch.2 transfer counter register (phs2_cnt) 0x301150 hsdma ch.3 transfer counter register (phs3_cnt) d[15:8] tc x _l[7:0]: ch. x transfer counter bits set the data transfer count. (default: 0x00) in block transfer mode, tc x_l[7:0 ] is bits[7:0 ] of the transfer counter. in single or successive transfer mode, tc x_l[7:0] is bits[15:8 ] of the transfer counter. this counter is decremented each time a dma transfer in the corresponding channel is performed. when the counter reaches 0 , a cause of interrupt is generated. in single-address mode, the end-of-trans - fer signal is output from the #dmaend x pin at the same time. even when the counter is 0 , a dma request is accepted and the counter is decremented to 0xffff (or 0xffffff). be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing and reading to and from the counter. d[7:0] blklen x [7:0]: ch. x block length bits in block transfer mode, these bits are used to specify a transf er block size. (default: 0x00) a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0]. in single or successive transfer mode, these bits are used to specify the 8 low-order bits of the transfer counter. note : when performing data transfer in block transfer mode, the block size must not be set to 0.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301122C0x301152: hsdma ch. x control registers name address register name bit function setting init. r/w remarks C C dualm x d x dir C tc x _h7 tc x _h6 tc x _h5 tc x _h4 tc x _h3 tc x _h2 tc x _h1 tc x _h0 d15 d14 d13C8 d7 d6 d5 d4 d3 d2 d1 d0 ch. x address mode selection d) invalid s) ch. x transfer direction control reserved ch. x transfer counter[15:8] (block transfer mode) ch. x transfer counter[23:16] (single/successive transfer mode) 1 dual addr 0 single addr 1 memory wr 0 memory rd 0 C 0 C 0 0 0 0 0 0 0 0 r/w C r/w C r/w 0 when being read. 00301122 | 00301152 (hw) hsdma ch. x control register note: d) dual address mode s) single address mode note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301122 hsdma ch.0 control register 0x301132 hsdma ch.1 control register 0x301142 hsdma ch.2 control register 0x301152 hsdma ch.3 control register d15 dualm x : ch. x address mode select bit select an address mode. 1 (r/w): dual-address mode 0 (r/w): single-address mode (default) when 1 is written to dualm x , the hsdma channel enters dual-address mode that allows specifica - tion of source and destination addresses. when 0 is written, the hsdma channel enters single-address mode for high-speed data transfer between the external memory and an i/o device. d14 d x dir: ch. x transfer direction control bit control the direction of data transfer in single-address mode. 1 (r/w): memory write 0 (r/w): memory read (default) data transfer from an external i/o device to external memory (or an external/internal i/o) is performed by writing 1 to d x dir. data transfer from external memory (or an external/internal i/o) to an external i/o is performed by writing 0. this bit is effective only in single-address mode. d[13:8] reserved d[7:0] tc x _h[7:0]: ch. x transfer counter bits set the data transfer count. (default: 0x00) in block transfer mode, tc x_h[7:0 ] is bits[15:8 ] of the transfer counter. in single or successive transfer mode, tc x_h[7:0] is bits[23:16 ] of the transfer counter. this counter is decremented each time a dma transfer in the corresponding channel is performed. when the counter reaches 0 , a cause of interrupt is generated. in single-address mode, the end-of-trans - fer signal is output from the #dmaend x pin at the same time. even when the counter is 0 , a dma request is accepted and the counter is decremented to 0xffff (or 0xffffff). be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing and reading to and from the counter.
ii bus modules: high-speed dma (hsdma) ii-1-30 epson s1c33e08 technical manual 0x301124C0x301154: hsdma ch. x low-order source address setup registers (phs x _sadr) name address register name bit function setting init. r/w remarks s x adrl15 s x adrl14 s x adrl13 s x adrl12 s x adrl11 s x adrl10 s x adrl9 s x adrl8 s x adrl7 s x adrl6 s x adrl5 s x adrl4 s x adrl3 s x adrl2 s x adrl1 s x adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x source address[15:0] s) ch. x memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301124 | 00301154 (hw) hsdma ch. x low-order source address setup register (phs x _sadr) note: d) dual address mode s) single address mode note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301124 hsdma ch.0 low-order source address setup register (phs0_sadr) 0x301134 hsdma ch.1 low-order source address setup register (phs1_sadr) 0x301144 hsdma ch.2 low-order source address setup register (phs2_sadr) 0x301154 hsdma ch.3 low-order source address setup register (phs3_sadr) d[15:0] s x adrl[15:0]: ch. x source address[15:0] (for standard mode) in dual-address mode, these bits are used to specify a source address. in single-address mode, an exter - nal memory address at the destination or source of transfer is specified. use s xadrl[15:0] to set the 16 low-order bits of the address. be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing or reading to and from these registers. the address is incremented or decremented (as set by s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) or s x id (d4/0x301162 + 0x10? x )) according to the transfer data size each time a dma transfer in the cor - responding channel is performed. notes : ? the following areas cannot be used for dma transfer: dual-address mode: area 0, area 2 single-address mode: area 0, area 1, area 2, area 3, area 6 ? single-address mode does not allow data transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. ? use s x adrl[15:0] (d[15:0]/0x301164 + 0x10? x ) and s x adrh[15:0] (d[15:0]/0x301166 + 0x10? x ) for specifying an address in advanced mode.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301126C0x301156: hsdma ch. x high-order source address setup registers name address register name bit function setting init. r/w remarks C datsize x s x in1 s x in0 s x adrh11 s x adrh10 s x adrh9 s x adrh8 s x adrh7 s x adrh6 s x adrh5 s x adrh4 s x adrh3 s x adrh2 s x adrh1 s x adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved ch. x transfer data size d) ch. x source address control s) ch. x memory address control d) ch. x source address[27:16] s) ch. x memory address[27:16] C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. 00301126 | 00301156 (hw) 1 half word 0 byte hsdma ch. x high-order source address setup register note: d) dual address mode s) single address mode 11 10 01 00 s xin[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed C note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301126 hsdma ch.0 high-order source address setup register 0x301136 hsdma ch.1 high-order source address setup register 0x301146 hsdma ch.2 high-order source address setup register 0x301156 hsdma ch.3 high-order source address setup register d15 reserved d14 datsize x : ch. x transfer data size select bit select the data size to be transferred. 1 (r/w): half-word 0 (r/w): byte (default) the transfer data size is set to 16 bits by writing 1 to datsize x and set to 8 bits by writing 0. note : in advanced mode, this bit is effective when wordsize x (d0/0x301162 + 0x10? x ) = 0. the setting of this bit is ignored when wordsize x (d0/0x301162 + 0x10? x ) = 1 and the transfer data size is set to 32 bits. in standard mode, this bit is always effective regardless of the wordsize x (d0/0x301162 + 0x10? x ) setting. d[13:12] s x in[1:0]: ch. x source address control bits control the incrementing or decrementing of the memory address . table ii. 1.9.2 address control s x in1 1 1 0 0 s x in0 1 0 1 0 address contr ol increment without initialization increment with initialization decrement without initialization fix ed (default: 0b00) in dual-address mode, this setting applies to the source address. in single-address mode, this setting ap - plies to the external memory address. when fixed (00 ) is selected, the source address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always read from the same address. when increment without initialization (11 ) is selected, the source address is incremented by an amount equal to the data size set by datsize x (d14 ) or wordsize x (d0/0x301162 + 0x10? x ) when one data transfer is completed.
ii bus modules: high-speed dma (hsdma) ii-1-32 epson s1c33e08 technical manual when decrement without initialization (01 ) is selected, the source address is decremented in the same way. when increment with initialization (10 ) is selected, the source address is incremented by an amount equal to the data size set by datsize x (d14 ) or wordsize x (d0/0x301162 + 0x10? x ) when one data transfer is completed. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the incre - mented address returns to the initial value when the block transfer is completed. note : in advanced mode, these bits are effective when s x id (d4/0x301162 + 0x10? x ) = 0. the set - ting of these bits is ignored when s x id (d4/0x301162 + 0x10? x ) = 1 and decrement with ini - tialization is selected. in standard mode, this bit is always effective regardless of the s x id (d4/0x301162 + 0x10? x ) setting. d[11:0] s x adrh[11:0]: ch. x source address[27:16] (for standard mode) in dual-address mode, these bits are used to specify 12 high-order bits of source address. in single- address mode, 12 high-order bits of external memory address at the destination or source of transfer is specified. see s xadrl[15:0] (d[15:0]/0x301124 + 0x10? x) for more information.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301128C0x301158: hsdma ch. x low-order destination address setup registers (phs x _dadr) name address register name bit function setting init. r/w remarks d x adrl15 d x adrl14 d x adrl13 d x adrl12 d x adrl11 d x adrl10 d x adrl9 d x adrl8 d x adrl7 d x adrl6 d x adrl5 d x adrl4 d x adrl3 d x adrl2 d x adrl1 d x adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301128 | 00301158 (hw) hsdma ch. x low-order destination address setup register (phs x _dadr) note: d) dual address mode s) single address mode note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301128 hsdma ch.0 low-order destination address setup register (phs0_dadr) 0x301138 hsdma ch.1 low-order destination address setup register (phs1_dadr) 0x301148 hsdma ch.2 low-order destination address setup register (phs2_dadr) 0x301158 hsdma ch.3 low-order destination address setup register (phs3_dadr) d[15:0] d x adrl[15:0]: ch. x destination address[15:0] (for standard mode) in dual-address mode, these bits are used to specify a destinat ion address. use d xadrl[15:0] to set the 16 low-order bits of the address. be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing or reading to and from these registers. the address is incremented or decremented (as set by d x in[ 1:0 ] (d[13:12 ]/0x30112 a + 0x10? x ) or d xid (d5/0x301162 + 0x10? x)) according to the transfer data size each time a dma transfer in the cor - responding channel is performed. notes : ? in single-address mode, these bits are not used. ? the following areas cannot be specified for destination addresses: area 0 (a0ram), area 2 ? use d x adrl[15:0] (d[15:0]/0x301168 + 0x10? x ) and d x adrh[15:0] (d[15:0]/0x30116a + 0x10? x ) for specifying an address in advanced mode.
ii bus modules: high-speed dma (hsdma) ii-1-34 epson s1c33e08 technical manual 0x30112aC0x30115a: hsdma ch. x high-order destination address setup registers name address register name bit function setting init. r/w remarks d x mod1 d x mod0 d x in1 d x in0 d x adrh11 d x adrh10 d x adrh9 d x adrh8 d x adrh7 d x adrh6 d x adrh5 d x adrh4 d x adrh3 d x adrh2 d x adrh1 d x adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch. x transfer mode d) ch. x destination address control s) invalid d) ch. x destination address[27:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w 0030112a | 0030115a (hw) hsdma ch. x high-order destination address setup register note: d) dual address mode s) single address mode d xmod[1:0] mode invalid block successive single d xin[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed 11 10 01 00 11 10 01 00 note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x30112a hsdma ch.0 high-order destination address setup register 0x30113a hsdma ch.1 high-order destination address setup register 0x30114a hsdma ch.2 high-order destination address setup register 0x30115a hsdma ch.3 high-order destination address setup register d[15:14] d x mod[1:0]: ch. x transfer mode select bits select a transfer mode. table ii. 1.9.3 transfer mode d x mod1 1 1 0 0 d x mod0 1 0 1 0 mode in v alid bloc k transf er mode successiv e transf er mode single transf er mode (default: 0b00) in single transfer mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ). in successive transfer mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. in block transfer mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen x[7:0 ] (d[7:0]/0x301120 + 0x10? x ). d[13:12] d x in[1:0]: ch. x destination address control bits control the incrementing or decrementing of the memory address . table ii. 1.9.4 address control d x in1 1 1 0 0 d x in0 1 0 1 0 address contr ol increment without initialization increment with initialization decrement without initialization fix ed (default: 0b00) in dual-address mode, this setting applies to the destination a ddress. when fixed (00 ) is selected, the destination address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always written to the same address.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 when increment without initialization (11 ) is selected, the destination address is incremented by an amount equal to the data size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/ 0x301162 + 0x10? x) when one data transfer is completed. when decrement without initialization (01 ) is selected, the destination address is decremented in the same way. when increment with initialization (10 ) is selected, the destination address is incremented by an amount equal to the data size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/ 0x301162 + 0x10? x ) when one data transfer is completed. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the incremented address returns to the initial value when the block transfer is com - pleted. in single-address mode, these bits are not used. note : in advanced mode, these bits are effective when d x id (d5/0x301162 + 0x10? x ) = 0. the set - ting of these bits is ignored when d x id (d5/0x301162 + 0x10? x ) = 1 and decrement with ini - tialization is selected. in standard mode, this bit is always effective regardless of the d x id (d5/0x301162 + 0x10? x ) setting. d[11:0] d x adrh[11:0]: ch. x destination address[27:16] (for standard mode) in dual-address mode, these bits are used to specify 12 high-order bits of destination address. see d xadrl[15:0] (d[15:0]/0x301128 + 0x10? x) for more information. in single-address mode, these bits are not used.
ii bus modules: high-speed dma (hsdma) ii-1-36 epson s1c33e08 technical manual 0x30112cC0x30115c: hsdma ch. x enable registers (phs x _en) name address register name bit function setting init. r/w remarks C C hs x _en d15C1 d0 reserved ch. x enable 1 enable 0 disable C 0 C r/w 0 when being read. 0030112c | 0030115c (hw) hsdma ch. x enable register (phs x _en) note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x30112c hsdma ch.0 enable register (phs0_en) 0x30113c hsdma ch.1 enable register (phs1_en) 0x30114c hsdma ch.2 enable register (phs2_en) 0x30115c hsdma ch.3 enable register (phs3_en) d[15:1] reserved d0 hs x _en: ch. x enable bit enable a dma transfer. 1 (r/w): enable 0 (r/w): disable (default) dma transfer is enabled by writing 1 to this bit. hsdma is placed in a state ready to accept a dma request from the #dmareq x pin or by the se - lected trigger source. dma transfer is disabled by writing 0 to this bit. when dma transfers are completed (transfer counter = 0), hs x _en is cleared by the hardware. be sure to disable dma transfers (hs x_en = 0) before setting the transfer condition.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30112eC0x30115e: hsdma ch. x trigger flag registers (phs x _tf) name address register name bit function setting init. r/w remarks C C hs x _tf d15C1 d0 reserved ch. x trigger flag clear (writing) ch. x trigger flag status (reading) 1 clear 0 no operatio n 1 set 0 cleared C 0 C r/w 0 when being read. 0030112e | 0030115e (hw) hsdma ch. x trigger flag register (phs x _tf) note : the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x30112e hsdma ch.0 trigger flag register (phs0_tf) 0x30113e hsdma ch.1 trigger flag register (phs1_tf) 0x30114e hsdma ch.2 trigger flag register (phs2_tf) 0x30115e hsdma ch.3 trigger flag register (phs3_tf) d[15:1] reserved d0 hs x _tf: ch. x trigger flag clear/status bit these bits are used to check and clear the trigger flag status . 1 (r): trigger flag has been set 0 (r): trigger flag has been cleared (default) 1 (w): clear trigger flag 0 (w): has no effect the trigger flag is set when a trigger is input to the hsdma channel and is cleared when the hsdma channel starts a data transfer. by reading hs x _tf, the flag status can be checked. writing 1 to hs x_tf clears the trigger flag if the dma transfer has not been started.
ii bus modules: high-speed dma (hsdma) ii-1-38 epson s1c33e08 technical manual 0x301162C0x301192: hsdma ch. x control registers (phs x _advmode) for adv mode name address register name bit function setting init. r/w remarks C C C d x id s x id C wordsize x d15C6 d5 d4 d3C1 d0 reserved d) ch. x destination address control s) invalid d) ch. x source address control s) ch. x memory address control reserved ch. x transfer data size 1 decrement (with init.) 0 d xin[1:0] setting 1 decrement (with init.) 0 s xin[1:0] setting C 0 0 C 0 C r/w r/w C r/w 0 when being read. 0 when being read. 00301162 | 00301192 (hw) hsdma ch. x control register (phs x _advmode) for adv mode note: d) dual mode s) single mode 1 word 0 datsize x setting notes : ? this register is effective only in advanced mode (hsdmaadv (d0/0x30119c) = 1). ? the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301162 hsdma ch.0 control register (phs0 _advmode) 0x301172 hsdma ch.1 control register (phs1 _advmode) 0x301182 hsdma ch.2 control register (phs2 _advmode) 0x301192 hsdma ch.3 control register (phs3 _advmode) d[15:6] reserved d5 d x id: ch. x destination address control bit enable the address decrement function with initialization for destination address. 1 (r/w): decrement with initialization 0 (r/w): d xin[1:0 ] setting is effective (default) when this bit is set to 1 in dual-address mode, the destination address decrement function with initial - ization is enabled. the destination address is decremented by an amount equal to the data size set by datsize x (d14/0x301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ) when one data trans - fer is completed. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the ini - tial value when the specified number of transfers is completed. in block transfer mode, the decremented address returns to the initial value when the block transfer is completed. when this bit is set to 0, the condition set by d xin[1:0] (d[13:12]/0x30112a + 0x10? x ) is effective. in single-address mode, this bit is not used. d4 s x id: ch. x source address control bit enable the address decrement function with initialization for s ource address. 1 (r/w): decrement with initialization 0 (r/w): s xin[1:0 ] setting (default) in dual-address mode, this setting applies to the source address. in single-address mode, this setting ap - plies to the external memory address. when this bit is set to 1 , the address decrement function with initialization is enabled. the source/exter - nal memory address is decremented by an amount equal to the data size set by datsize x (d 14 / 0 x 301126 + 0x10? x ) or wordsize x (d0/0x301162 + 0x10? x ) when one data transfer is completed. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed. in block transfer mode, the decremented address returns to the initial value when the block transfer is completed. when this bit is set to 0, the condition set by s xin[1:0] (d[13:12]/0x301126 + 0x10? x ) is effective. d[3:1] reserved
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d0 wordsize x : ch. x transfer data size select bit select the data size to be transferred. 1 (r/w): word 0 (r/w): datsize x setting is effective (default) the transfer data size is set to 32 bits by writing 1 to this bit. when this bit is set to 0 , the size set by datsize x (d14/0x301126 + 0x10? x ) is effective.
ii bus modules: high-speed dma (hsdma) ii-1-40 epson s1c33e08 technical manual 0x301164C0x301196: hsdma ch. x source address setup registers (phs x _ad_sadr) for adv mode name address register name bit function setting init. r/w remarks s x adrl15 s x adrl14 s x adrl13 s x adrl12 s x adrl11 s x adrl10 s x adrl9 s x adrl8 s x adrl7 s x adrl6 s x adrl5 s x adrl4 s x adrl3 s x adrl2 s x adrl1 s x adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x source address[15:0] s) ch. x memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301164 | 00301194 (hw) hsdma ch. x low-order source address setup register (phs x _ad_sadr) for adv mode note: d) dual address mode s) single address mode s x adrh15 s x adrh14 s x adrh13 s x adrh12 s x adrh11 s x adrh10 s x adrh9 s x adrh8 s x adrh7 s x adrh6 s x adrh5 s x adrh4 s x adrh3 s x adrh2 s x adrh1 s x adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x source address[31:16] s) ch. x memory address[31:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301166 | 00301196 (hw) hsdma ch. x high-order source address setup register for adv mode note: d) dual address mode s) single address mode notes : ? this register is effective only in advanced mode (hsdmaadv (d0/0x30119c) = 1). ? the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301164 hsdma ch.0 low-order source address setup register (phs0_ad_sadr) 0x301166 hsdma ch.0 high-order source address setup register for adv mode 0x301174 hsdma ch.1 low-order source address setup register (phs1_ad_sadr) 0x301176 hsdma ch.1 high-order source address setup register for adv mode 0x301184 hsdma ch.2 low-order source address setup register (phs2_ad_sadr) 0x301186 hsdma ch.2 high-order source address setup register for adv mode 0x301194 hsdma ch.3 low-order source address setup register (phs3_ad_sadr) 0x301196 hsdma ch.3 high-order source address setup register for adv mode d[15:0]/0x301164C0x301194 s x adrl[15:0]: ch. x low-order source address[15:0] d[15:0]/0x301166C0x301196 s x adrh[15:0]: ch. x high-order source address[31:16] in dual-address mode, these bits are used to specify a 32 -bit source address. in single-address mode, a 32 -bit external memory address at the destination or source of transfer is specified. be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing or reading to and from these registers. the address is incremented or decremented (as set by s x in[ 1:0 ] (d[13:12 ]/0x301126 + 0x10? x ) or s x id (d4/0x301162 + 0x10? x )) according to the transfer data size each time a dma transfer in the cor - responding channel is performed.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 notes : ? the following areas cannot be used for dma transfer: dual-address mode: area 0, area 2 single-address mode: area 0, area 1, area 2, area 3, area 6 ? single-address mode does not allow data transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. ? use s x adrl[15:0] (d[15:0]/0x301124 + 0x10? x ) and s x adrh[11:0] (d[11:0]/0x301126 + 0x10? x ) for specifying an address in standard mode.
ii bus modules: high-speed dma (hsdma) ii-1-42 epson s1c33e08 technical manual 0x301168C0x30119a: hsdma ch. x destination address setup registers (phs x _adv_dadr) for adv mode name address register name bit function setting init. r/w remarks d x adrl15 d x adrl14 d x adrl13 d x adrl12 d x adrl11 d x adrl10 d x adrl9 d x adrl8 d x adrl7 d x adrl6 d x adrl5 d x adrl4 d x adrl3 d x adrl2 d x adrl1 d x adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301168 | 00301198 (hw) hsdma ch. x low-order destination address setup register (phs x _adv_dadr) for adv mode note: d) dual address mode s) single address mode d x adrh15 d x adrh14 d x adrh13 d x adrh12 d x adrh11 d x adrh10 d x adrh9 d x adrh8 d x adrh7 d x adrh6 d x adrh5 d x adrh4 d x adrh3 d x adrh2 d x adrh1 d x adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch. x destination address[31:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 0030116a | 0030119a (hw) hsdma ch. x high-order destination address setup register for adv mode note: d) dual address mode s) single address mode notes : ? this register is effective only in advanced mode (hsdmaadv (d0/0x30119c) = 1). ? the letter x in bit names, etc., denotes a channel number from 0 to 3. 0x301168 hsdma ch. 0 low-order destination address setup register (phs 0 _adv_dadr) 0x30116 a hsdma ch.0 high-order destination address setup register for adv mode 0x301178 hsdma ch. 1 low-order destination address setup register (phs 1 _adv_dadr) 0x30117 a hsdma ch.1 high-order destination address setup register for adv mode 0x301188 hsdma ch. 2 low-order destination address setup register (phs 2 _adv_dadr) 0x30118 a hsdma ch.2 high-order destination address setup register for adv mode 0x301198 hsdma ch. 3 low-order destination address setup register (phs 3 _adv_dadr) 0x30119 a hsdma ch.3 high-order destination address setup register for adv mode d[15:0]/0x301168C0x301198 d x adrl[15:0]: ch. x destination address[15:0] d[15:0]/0x30116aC0x30119a d x adrh[15:0]: ch. x destination address[31:16] in dual-address mode, these bits are used to specify a 32-bit destination address. be sure to disable dma transfers (hs x _en (d0/0x30112 c + 0x10? x ) = 0 ) before writing or reading to and from these registers. the address is incremented or decremented (as set by d x in[ 1:0 ] (d[13:12 ]/0x30112 a + 0x10? x ) or d xid (d5/0x301162 + 0x10? x)) according to the transfer data size each time a dma transfer in the cor - responding channel is performed.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-43 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 notes : ? in single-address mode, these bits are not used. ? the following areas cannot be specified for destination addresses: area 0 (a0ram), area 2 ? use d x adrl[15:0] (d[15:0]/0x301128 + 0x10? x ) and d x adrh[11:0] (d[11:0]/0x30112a + 0x10? x ) for specifying an address in standard mode.
ii bus modules: high-speed dma (hsdma) ii-1-44 epson s1c33e08 technical manual 0x30119c: hsdma std/adv mode select register (phs_cntlmode) name address register name bit function setting init. r/w remarks C hsdmaadv d15C1 d0 reserved standard mode/advanced mode select C 0 C r/w 0 when being read. 0030119c (hw) hsdma std/adv mode select register (phs_cntlmode) C 1 advanced mode 0 standar d mode d[15:1] reserved d0 hsdmaadv: standard/advanced mode select bit select standard or advanced mode. 1 (r/w): advanced mode 0 (r/w): standard mode (default) the hsdma in the s 1c33e08 is extended from that of the c33 std models. the s1c33e08 hsdma has two operating modes, standard (std) mode of which functions are compatible with the existing c33 std models and an advanced (adv) mode allowing use of the extended functions. table ii.1.9.5 shows differences between standard mode and advanced mode. table ii. 1.9.5 differences between standard mode and advanced mode function source/destination address bit width w ord (32-bit) data transf er address decrement function with initialization ad v anced mode 32 bits available available standar d mode 28 bits unavailable unavailable to configure the hsdma in advanced mode, set this bit to 1 . the control registers (0x301162C 0x30119 a) for the extended functions are enabled to write after this setting. notes : ? be sure to use the control registers for advanced mode when the hsdma is set to ad - vanced mode. ? standard or advanced mode currently set is applied to all the hsdma channels. it cannot be selected for each channel individually.
ii bus modules: high-speed dma (hsdma) s1c33e08 technical manual epson ii-1-45 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30119e: dma sequential access time register (phs_acctime) name address register name bit function setting init. r/w remarks C dmaacctime3 dmaacctime2 dmaacctime1 dmaacctime0 d15C4 d3 d2 d1 d0 reserved idma and hsdma sequential access time setup C 0 0 0 0 C r/w 0 when being read. 0030119e (hw) dma sequential access time register (phs_acctime) C 0 1 2 3 4 5 6 7 unlimited 64 cycles 128 cycles 192 cycles 256 cycles 320 cycles 384 cycles 448 cycles 8 9 a b c d e f 512 cycles 576 cycles 640 cycles 704 cycles 768 cycles 832 cycles 896 cycles 960 cycles d[15:4] reserved d[3:0] dmaacctime: idma and hsdma sequential access time setup bits sets the sequential access time for idma and hsdma. table ii. 1.9.6 setting the sequential access time dmaa cctime3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 dma sequential access time 960 cycles 896 cycles 832 cycles 768 cycles 704 cycles 640 cycles 576 cycles 512 cycles 448 cycles 384 cycles 320 cycles 256 cycles 192 cycles 128 cycles 64 cycles unlimited dmaa cctime2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 dmaa cctime1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 dmaa cctime0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0000 = unlimited) when unlimited is selected, the ahb bus will not be released until a dma transfer has been com - pleted after it starts. specifying a number of cycles allows a dma transfer to be temporarily suspended when the specified cycles of data transfer have been executed to release the bus. the cpu or lcdc can perform a bus access during the suspended status. after that, the dmac resumes the data transfer that was being suspended.
ii bus modules: high-speed dma (hsdma) ii-1-46 epson s1c33e08 technical manual ii.1.10 precautions ? when setting the transfer conditions, always make sure the dma controller is inactive (hs x _en (d0/0x30112c + 0x10? x) = 0). ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) ? after an initial reset, the cause-of-interrupt flag (fhdm x (d x /0x300281 )) becomes indeterminate. always be sure to reset the flag to prevent interrupts or idma requests from being generated inadvertently. ? fhdm x : hsdma ch. x cause-of-interrupt flag in the dma interrupt cause flag register (d x /0x300281) ? to prevent an interrupt from being generated repeatedly for the same source, be sure to reset the cause-of-inter - rupt flag before setting up the psr again or executing the reti instruction. ? hsdma is given higher priority over idma (intelligent dma) and the cpu. however, since hsdma and idma share the same circuit, hsdma cannot gain the bus ownership while an idma transfer is under way. requests for hsdma invocation that have occurred during an idma transfer are kept pending until the idma transfer is completed. a request for idma invocation or an interrupt request that has occurred during a hsdma transfer are accepted after completion of the hsdma transfer. ? in dual-address mode, a0 ram (area 0 ), specific rom (area 1 ), and ivram (area 0 ) cannot be specified as the source or destination for dma transfer. while ivram (area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) can be used for dual-address transfer. ? in single-address mode, a0 ram (area 0 ), specific rom (area 1 ), area 2 , ivram (area 0 or area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) cannot be used for dma transfer. ? single-address mode does not allow data transfer between memory devices. an external logic circuit is required to perform single-address transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. ? be sure to disable the hsdma before setting the chip in sleep mode (executing the slp instruction). halt mode can be set even if the hsdma is enabled.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2 intelligent dma (idma) ii.2.1 functional outline of idma the s 1c33e08 contains an intelligent dma (idma), a function that allows control information to be programmed in ram. up to 128 channels can be programmed, including 41 channels that are invoked by a cause of interrupt that occurs in some internal peripheral circuit. although an additional overhead for loading and storing control information in ram may be incurred, this intelligent dma supports such functions as successive transfers, block transfers, and linking to another idma. idma is invoked by a cause of interrupt that occurs in some internal peripheral circuit or a software trigger, thereby performing a data transfer according to the control information in ram. when the transfer is completed, idma can generate an interrupt or invoke another idma according to link settings. intelligent dma transfer memory, i/o (1) the control information stored in the memory is loaded into the idma temporary register. (2) transfer data is read from the source memory or i/o device. (3) transfer data is written to the destination memory or i/o device. (4) the updated control information in the idma temporary register is written back to the memory. (3) destination memory, i/o (2) (4) (1) source dst ram or external ram control information control information transfer data transfer idma itc dma request #dmareq x sramc load/store load/store (software trigger) address bus cpu_ahb bus dma control information data bus dma data transfer request signal dma data transfer acknowledge signal dma control information transfer request signal dma control information transfer acknowledge signal hardware trigger idma ch. number data bus figure ii.2.1.1 data and control information flow in intelligent dma transfer the features of idma are outlined below. ? controller equivalent to the hsdma dual-address transfer controller ? number of channels 128 channels ? control information programmable in the ram the information table can be stored in dst ram (area 3 ) or in the external ram. (a0ram cannot be used.) ? source external memory and internal memory except areas 0 and 1 ? destination external memory and internal memory except areas 0 and 1 ? transfer data size 8, 16, or 32 bits ? trigger 1 . software trigger (register control) 2 . hardware trigger (causes of interrupts) ? transfer mode 1. single transfer (one unit of data is transferred by one trigger) 2 . successive transfer (specified number of data are transferred by one trigger) 3 . block transfer (data block of the specified size is transferred by one trigger) ? transfer address control the source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. in successive or block transfers, the address can be reset to the initial value upon completion of transfer. ? programmable link function any channel can be linked with another to perform data transfer by multiple channels sequentially.
ii bus modules: intelligent dma (idma) ii-2-2 epson s1c33e08 technical manual s1c33e08 extended functions in the s 1c33e08 dma controller, some idma functions have been extended from those of the c33 std. table ii. 2.1.1 shows differences between c33 std idma and s1c33e08 idma. table ii. 2.1.1 differences between c33 std idma and s1c33e08 idma function source/destination address bit width tr ansf er counter (f or single/successive transfer) tr ansf er counter (f or block transfer) bloc k siz e setup bit width tr ansf er data siz e address decrement function with initialization control inf or mation siz e per channel control inf or mation base address s1c33e08 idma 32 bits 32 bits 20 bits 12 bits 32 bits, 16 bits, 8 bits available 4 words (128 bits) 32 bits (4-word alignment) c33 std idma 28 bits 24 bits 16 bits 8 bits 16 bits, 8 bits unavailable 3 words (96 bits) 28 bits (word alignment) note that the item layout in the control information has been changed along with this functional extension. furthermore, the control information is no longer placed in the area 0 built-in ram (a0ram).
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.2 programming control information the intelligent dma operates according to the control information prepared in ram. note that the control information must be placed in dst ram (area 3 ) or an external ram. a0 ram (area 0 ) cannot be used to store control information. the control information is 4 words (16 bytes) per channel in size, and must be located at continuous addresses beginning with the base address that is set in the software application as the starting address of channel 0. consequently, an area of 512 words (2,048 bytes) in ram is required in order for all of 128 channels to be used. note that the last 132 bytes in dst ram (area 3 ) are reserved for the debug circuits. therefore, up to 119 channels are available when using the on-chip debug functions. the following explains how to set the base address and the contents of control information. before using idma, make each the settings described below. ii.2.2.1 setting the base address set the starting address of control information (starting address of channel 0 ) to dbasel[ 15 : 0 ] (d[ 15 : 0 ]/ 0 x 301100 ) for 16 low-order bits and dbaseh[15:0] (d[15:0]/0x301102) for 16 high-order address bits. ? dbasel[15:0] : idma low-order base address bits in the idma base address register 0 (d[15:0]/0x301100) ? dbaseh[15:0] : idma high-order base address bits in the idma base address register 1 (d[15:0]/0x301102) when initially reset, the base address is set to 0x200003a0. notes : ? the control information must be placed in dst ram (area 3 ) or an external ram. a 0 ram (area 0 ) cannot be used to store control information. ? the address you set in the idma base address register must always be 4 -word units boundary address. ? be sure to disable dma transfers (idmaen (d0/0x301105 ) = 0 ) before setting the base address. writing to the idma base address register is ignored when the dma transfer is enabled (idmaen (d 0 / 0 x 301105 ) = 1 ). when the register is read, the read data is indeterminate. ? idmaen : idma enable bit in the idma enable register (d0/0x301105) ii.2.2.2 control information write the control information for the idma channels used to ram. the addresses at which the control information of each channel is placed are determined by the base address and a channel number. starting address of channel = base address + (channel number 16 [bytes]) note : the control information must be written only when the channel to be set does not start a dma transfer. if a dma transfer starts when the control information is being written to the ram, proper transfer cannot be performed. reading the control information can always be done.
ii bus modules: intelligent dma (idma) ii-2-4 epson s1c33e08 technical manual the contents of control information (4 words) in each channel are shown in the table below. table ii. 2.2.2.1 idma control information wo rd 1st 2nd 3rd 4th bit d31 d30C24 d23C18 d17C16 d15 d14C12 d11 d10C8 d7C6 d5C4 d3C1 d0 d31C12 d11C0 d31C0 d31C0 function idma link enab le 1 = enab led, 0 = disab led idma link field C data siz e control (do not set to 11.) da tsiz1 da tsiz0 setting contents 1 0 w ord (32 bits) 0 1 half-word (16 bits) 0 0 byte (8 bits) C source address control (do not set to others .) srinc2 srinc1 srinc0 setting contents 1 0 0 address decrement with initialization (address is reset in successiv e or b loc k transf er mode) 0 1 1 address increment without initialization (address is not reset) 0 1 0 address increment with initialization (address is reset in successiv e or b loc k transf er mode) 0 0 1 address decrement without initialization (address is not reset) 0 0 0 address fix ed C destination address control (do not set to others .) dsinc2 dsinc1 dsinc0 setting contents 1 0 0 address decrement with initialization (address is reset in successiv e or b loc k transf er mode) 0 1 1 address increment without initialization (address is not reset) 0 1 0 address increment with initialization (address is reset in successiv e or b loc k transf er mode) 0 0 1 address decrement without initialization (address is not reset) 0 0 0 address fix ed C tr ansf er mode (do not set to 11.) dmod1 dmod0 setting contents 1 0 bloc k transf er mode 0 1 successiv e transf er mode 0 0 single transf er mode C end-of-transf er interr upt enab le 1 = enab led, 0 = disab led tr ansf er counter (b loc k transf er mode) tr ansf er counter - 20 high-order bits (single or successiv e transf er mode) bloc k siz e (b loc k transf er mode) tr ansf er counter - 12 lo w-order bits (single or successiv e transf er mode) source address destination address name lnken lnkchn[6:0] reser ve d da tsiz[1:0] reser ve d srinc[2:0] reser ve d dsinc[2:0] reser ve d dmod[1:0] reser ve d dinten tc[19:0] blklen[11:0] sradr[31:0] dsadr[31:0] lnken: idma link enable (d 31/1 st word) if this bit remains set (= 1 ), the idma channel that is set in the idma link field is invoked after the completion of a dma transfer in this channel. dma transfers in multiple channels can be performed successively by merely triggering the first channel to be executed. there is no limit to the number of channels linked. set this link in order of the idma channels you want to be executed. if this bit is 0 , idma is completed by merely executing a dma transfer in this channel. lnkchn[6:0 ]: idma link field (d[30:24]/1 st word) if you want idma to be linked, set the channel numbers ( 0 to 127 ) to be executed next. the data in this field is valid only when lnken = 1.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 datsiz[ 1:0 ]: data size control (d[17:16]/1 st word) set the unit size of data to be transferred. table ii. 2.2.2.2 transfer data size da tsiz1 1 1 0 0 da tsiz0 1 0 1 0 t ransfer data siz e in v alid w ord (32 bits) half-word (16 bits) byte (8 bits) srinc[2:0 ]: source address control (d[14:12]/1 st word) set the source address control condition. ? srinc[ 2:0] = 000 : address fixed the source address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always read from the same address. ? srinc[ 2:0] = 011 : address increment without initialization (address is not reset) the source address is incremented by an amount equal to the data size set by datsiz when one data transfer is completed. the address that has been incremented during transfer does not return to the initial value. ? srinc[ 2:0] = 001 : address decrement without initialization (address is not reset) the source address is decremented by an amount equal to the data size set by datsiz when one data transfer is completed. the address that has been decremented during transfer does not return to the initial value. ? srinc[ 2:0] = 010 : address increment with initialization (address is reset in successive or block transfer mode) the source address is incremented by an amount equal to the data size set by datsiz when one data transfer is completed. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed (cnt = 0 ). in block transfer mode, the incremented address returns to the initial value when the block transfer is completed. ? srinc[ 2:0] = 100 : address decrement with initialization (address is reset in successive or block transfer mode) the source address is decremented by an amount equal to the data size set by datsiz when one data transfer is completed. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed (cnt = 0 ). in block transfer mode, the decremented address returns to the initial value when the block transfer is completed. ? srinc[ 2:0 ] = other than above: settings are prohibited note : in single transfer mode, the address does not return to the initial value even if a condition with address initialization is specified. dsinc[2:0 ]: destination address control (d[10:8]/1 st word) set the destination address control condition. ? dsinc[ 2:0] = 000 : address fixed the destination address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always written to the same address. ? dsinc[ 2:0] = 011 : address increment without initialization (address is not reset) the destination address is incremented by an amount equal to the data size set by datsiz when one data transfer is completed. the address that has been incremented during transfer does not return to the initial value.
ii bus modules: intelligent dma (idma) ii-2-6 epson s1c33e08 technical manual ? dsinc[ 2:0] = 001 : address decrement without initialization (address is not reset) the destination address is decremented by an amount equal to the data size set by datsiz when one data transfer is completed. the address that has been decremented during transfer does not return to the initial value. ? dsinc[ 2:0] = 010 : address increment with initialization (address is reset in successive or block transfer mode) the destination address is incremented by an amount equal to the data size set by datsiz when one data transfer is completed. in single transfer mode, the address that has been incremented during transfer does not return to the initial value. in successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed (cnt = 0 ). in block transfer mode, the incremented address returns to the initial value when the block transfer is completed. ? dsinc[ 2:0] = 100 : address decrement with initialization (address is reset in successive or block transfer mode) the destination address is decremented by an amount equal to the data size set by datsiz when one data transfer is completed. in single transfer mode, the address that has been decremented during transfer does not return to the initial value. in successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed (cnt = 0 ). in block transfer mode, the decremented address returns to the initial value when the block transfer is completed. ? dsinc[ 2:0 ] = other than above: settings are prohibited note : in single transfer mode, the address does not return to the initial value even if a condition with address initialization is specified. dmod[1:0 ]: transfer mode (d[5:4]/1 st word) use these bits to set the desired transfer mode. the transfer modes are outlined below (to be detailed later): ? dmod[ 1:0] = 00 : single transfer mode in this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by datsiz. if data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. ? dmod[ 1:0] = 01 : successive transfer mode in this mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 each time data is transferred. ? dmod[ 1:0] = 10 : block transfer mode in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen. if a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. ? dmod[ 1:0] = 11 : settings are prohibited dinten: end-of-transfer interrupt enable (d 0/1 st word) if this bit is left set (= 1 ), when the transfer counter reaches 0 , an interrupt request to the cpu is generated based on the cause-of-interrupt flag by which idma has been invoked. if this bit is 0 , no interrupt request to the cpu is generated even when the transfer counter has reached 0. tc[19:0 ]: transfer counter (d[31:12]/2 nd word) in block transfer mode, a transfer count can be specified using up to 20 bits. set this value here. in single transfer and successive transfer modes, a transfer count can be specified using up to 32 bits. set a 20 -bit high-order value here.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 blklen[11:0 ]: block size/transfer counter (d[11:0]/2 nd word) in block transfer mode, set the size of a block that is transferred in one operation (in units of datsiz). in single transfer and successive transfer modes, set an 12 -bit low-order value for the transfer count here. note : the transfer count and block size thus set is decremented according to the transfers performed. if the transfer count is set to 0, it is decremented to all fs by the first transfer performed. this means that you have set the maximum value that is determined by the number of bits available. sradr[31:0 ]: source address (d[31:0]/3 rd word) use these bits to set the starting address at the source of transfer. the content set here is updated according to the setting of srinc. dsadr[31:0 ]: destination address (d[31:0]/4 th word) use these bits to set the starting address at the destination of transfer. the content set here is updated according to the setting of dsinc. notes : ? area 0 (a0ram) and area 2 cannot be used for idma transfer and storing control information. ? since the control information is placed in ram, it can be rewritten. however, before rewriting the content of this information, make sure that no dma transfer is generated in the channel whose information you are going to rewrite.
ii bus modules: intelligent dma (idma) ii-2-8 epson s1c33e08 technical manual ii.2.3 idma invocation the triggers by which idma is invoked have the following three causes: 1 . cause of interrupt in internal peripheral circuits (hardware trigger) 2 . trigger in the software application 3. link setting enabling/disabling dma transfer the idma controller is enabled by writing 1 to the idma enable bit idmaen (d0/0x301105 ), and is ready to accept the triggers described above. however, before enabling a dma transfer, be sure to set the base address and the control information for the channel to be invoked correctly. if idmaen (d 0/0x301105 ) is set to 0 , no idma invocation request is accepted. ? idmaen : idma enable bit in the idma enable register (d0/0x301105) idma invocation by a cause of interrupt in internal peripheral circuits some internal peripheral circuits that have an interrupt generating function can invoke idma by a cause of interrupt in that circuit. the idma channel numbers corresponding to such idma invocation are predetermined. the relationship between the causes of interrupt that have this function and the idma channels is shown in table ii. 2.3.1. table ii. 2.3.1 interrupt causes used to invoke idma p eripheral cir cuit i/o por ts high-speed dma 16-bit timers 0C5 ser ial interf ace ch.0Cch.1 a/d con ve r ter i/o por ts lcdc ser ial interf ace ch.2 spi i/o por ts or por t mux interr upt i/o por ts i 2 s cause of interrupt po rt input 0 po rt input 1 po rt input 2 po rt input 3 ch.0, end of transf er ch.1, end of transf er timer 0 compar ison b timer 0 compar ison a timer 1 compar ison b timer 1 compar ison a timer 2 compar ison b timer 2 compar ison a timer 3 compar ison b timer 3 compar ison a timer 4 compar ison b timer 4 compar ison a timer 5 compar ison b timer 5 compar ison a ch.0 receiv e b uff er full ch.0 transmit b uff er empty ch.1 receiv e b uff er full ch.1 transmit b uff er empty end of a/d con v ersion po rt input 4 po rt input 5 po rt input 6 po rt input 7 end of frame ch.2 receiv e b uff er full ch.2 transmit b uff er empty receiv e dma request tr ansmit dma request po rt input 8 / spi po rt input 9 / usb pdreq po rt input 10 / usb int po rt input 11 / dcsio po rt input 12 po rt input 13 po rt input 14 po rt input 15 i 2 s idma enable bit dep0 (d0/0x300294) dep1 (d1/0x300294) dep2 (d2/0x300294) dep3 (d3/0x300294) dehdm0 (d4/0x300294) dehdm1 (d5/0x300294) de16tu0 (d6/0x300294) de16tc0 (d7/0x300294) de16tu1 (d0/0x300295) de16tc1 (d1/0x300295) de16tu2 (d2/0x300295) de16tc2 (d3/0x300295) de16tu3 (d4/0x300295) de16tc3 (d5/0x300295) de16tu4 (d6/0x300295) de16tc4 (d7/0x300295) de16tu5 (d0/0x300296) de16tc5 (d1/0x300296) desrx0 (d6/0x300296) destx0 (d7/0x300296) desrx1 (d0/0x300297) destx1 (d1/0x300297) deade (d2/0x300297) dep4 (d4/0x300297) dep5 (d5/0x300297) dep6 (d6/0x300297) dep7 (d7/0x300297) delcdc (d1/0x30029c) desrx2 (d2/0x30029c) destx2 (d3/0x30029c) despirx (d4/0x30029c) despitx (d5/0x30029c) dep8 (d0/0x3002ae) dep9 (d1/0x3002ae) dep10 (d2/0x3002ae) dep11 (d3/0x3002ae) dep12 (d4/0x3002ae) dep13 (d5/0x3002ae) dep14 (d6/0x3002ae) dep15 (d7/0x3002ae) dei2s (d0/0x3002af) idma request bit rp0 (d0/0x300290) rp1 (d1/0x300290) rp2 (d2/0x300290) rp3 (d3/0x300290) rhdm0 (d4/0x300290) rhdm1 (d5/0x300290) r16tu0 (d6/0x300290) r16tc0 (d7/0x300290) r16tu1 (d0/0x300291) r16tc1 (d1/0x300291) r16tu2 (d2/0x300291) r16tc2 (d3/0x300291) r16tu3 (d4/0x300291) r16tc3 (d5/0x300291) r16tu4 (d6/0x300291) r16tc4 (d7/0x300291) r16tu5 (d0/0x300292) r16tc5 (d1/0x300292) rsrx0 (d6/0x300292) rstx0 (d7/0x300292) rsrx1 (d0/0x300293) rstx1 (d1/0x300293) rade (d2/0x300293) rp4 (d4/0x300293) rp5 (d5/0x300293) rp6 (d6/0x300293) rp7 (d7/0x300293) rlcdc (d1/0x30029b) rsrx2 (d2/0x30029b) rstx2 (d3/0x30029b) rspirx (d4/0x30029b) rspitx (d5/0x30029b) rp8 (d0/0x3002a c) rp9 (d1/0x3002a c) rp10 (d2/0x3002a c) rp11 (d3/0x3002a c) rp12 (d4/0x3002a c) rp13 (d5/0x3002a c) rp14 (d6/0x3002a c) rp15 (d7/0x3002a c) ri2s (d0/0x3002ad) idma ch. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 24 25 26 27 28 29 30 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 these causes of interrupt are used in common for interrupt re quests and idma invocation requests. to invoke idma upon the occurrence of a cause of interrupt, set the corresponding bits of the idma request and idma enable registers shown in the table by writing 1 . then when a cause of interrupt occurs, an interrupt request to the cpu is kept pending and the corresponding idma channel is invoked. the cause-of-interrupt flag that has been set to 1 remains set until the dma transfer invoked by it is completed. if the following two conditions are met when one dma transfer is completed, an interrupt request is generated without resetting the cause-of-interrupt flag. ? the transfer counter has reached 0. ? dinten in control information is set to 1 (interrupt enabled). in this case, the idma request bit is cleared to 0 . therefore, if idma needs to be invoked when a cause of interrupt occurs next time, this register must be set up again. to prevent unwanted idma requests from being generated, this setting must be performed before enabling interrupts and after resetting the cause-of-interrupt flag. the idma enable bit is not cleared and remains set to 1. if the transfer counter is not 0 , the cause-of-interrupt flag is reset when the dma transfer is completed, so that no interrupt is generated. in this case, the idma request bit and idma enable bit are not cleared and remain set to 1. when dinten in control information has been set to 0 , the cause-of-interrupt flag is reset even if the transfer counter reaches 0 , so that no interrupt is generated. in this case, the idma request bit is not cleared but the idma enable bit is cleared. if the idma request register bit is left reset to 0 , the relevant cause of interrupt generates an interrupt request and not an idma request. the control registers (interrupt enable register and interrupt priority register) corresponding to the cause of interrupt do not affect idma invocation. idma can be invoked even if the interrupt enable bit in itc is set to 0 (interrupt disabled). however, these register must be set to enable the interrupt when generating the interrupt after completing the dma transfer.
ii bus modules: intelligent dma (idma) ii-2-10 epson s1c33e08 technical manual idma invocation by a trigger in the software application all idma channels for which control information is set, including those corresponding to causes of interrupt described above, can be invoked by a trigger in the software application. when the idma channel number to be invoked ( 0 to 127 ) is written to dchn[6:0 ] (d[6:0]/0x301104 ) and dstart (d 7/0x301104 ) is set to 1 after setting idmaen (d0/0x301105 ) to 1 , the specified idma channel starts a dma transfer. ? dchn[6:0] : idma channel number set-up bits in the idma start register (d[6:0]/0x301104) ? dstart : idma start control bit in the idma start register (d7/0x301104) dstart remains set (= 1 ) during a dma transfer and is reset to 0 in hardware when one dma transfer operation is completed. do not modify these bits during a dma transfer. if dinten is set to 1 (interrupt enabled), a cause of interrupt for the completion of idma transfer is generated when one dma transfer is completed. idma invocation by link setting if lnken in the control information is set to 1 (link enabled), the idma channel that is set in the idma link field lnkchn is invoked successively after a dma transfer in the link-enabled channel is completed. the interrupt request by the first channel is generated after transfers in all linked channels are completed if the interrupt conditions are met. to generate an interrupt at the end of an idma transfer, the dinten (end-of-transfer interrupt enable) bits in the idma control information for the first idma channel to be invoked and all the channels to be linked must be set to 1. idma invocation request during a dma transfer an idma invocation request to another channel that is generated during a dma transfer is kept pending until the dma transfer that was being executed at the time is completed. since an invocation request is not cleared, new requests will be accepted when the dma transfer under execution is completed. an idma invocation request to the same channel cannot be accepted while the channel is executing a dma transfer because the same cause of interrupt is used. therefore, an interval longer than the dma transfer period is required when invoking the same channel. idma invocation request when dma transfer is disabled an idma invocation request generated when idmaen (d 0/0x301105 ) is 0 (dma transfer disabled) is kept pending until idmaen (d 0/0x301105 ) is set to 1 . since an invocation request is not cleared, it is accepted when dma transfer is enabled. simultaneous generation of a software trigger and a hardware trigger when a software trigger and the hardware trigger for the same channel are generated simultaneously, the software trigger starts idma transfer. the idma transfer by the hardware trigger is executed after the dma transfer by the software trigger is completed.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.4 operation of idma idma has three transfer modes, in each of which data transfer operates differently. furthermore, a cause of interrupt is processed differently depending on the type of trigger. idma supports only dual-address transfers. it does not support single-address transfers. the following describes the operation of idma in each transfer mode and how a cause of interrupt is processed for each type of trigger. ii.2.4.1 single transfer mode the channels for which dmod in control information is set to 00 operate in single transfer mode. in this mode, a transfer operation invoked by one trigger is completed after transferring one data unit of the size set by datsiz. if a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. the operation of idma in single transfer mode is shown by the flow chart in figure ii. 2.4.1.1. start end calculates address of control information loads channel control information transfers one unit of data transfer counter - 1 saves channel control information idma interrupt processing (if interrupt is enabled) transfer counter = 0 a base address + (channel number 16) bn (4 words) :n = 1C4 c (data read from source of transfer) d (data write to destination of transfer) e fn (4 words) :n = 1C4 n trigger y a b1 b2 b3 b4 c d e f1 f2 f4 f3 figure ii.2.4.1.1 operation flow in single transfer mode (1 ) when a trigger is accepted, the address for control information is calculated from the base address and channel number. (2 ) control information is read from the calculated address into t he internal temporary register. (3 ) data of the size set in the control information is read from t he source address. (4 ) the read data is written to the destination address. (5 ) the address is incremented or decremented and the transfer c ounter is decremented. (6 ) the modified control information is written to ram. (7 ) in the case of a hardware trigger, the interrupt control bits are processed before completing idma. condition cause-of-interrupt flag idma request bit idma enable bit ________________________________________________________________________________________ transfer counter 0 : reset (0) not changed (1 ) not changed (1) transfer counter = 0, dinten = 1 : not changed (1) reset (0) not changed (1) transfer counter = 0, dinten = 0 : reset (0) not changed (1) reset (0)
ii bus modules: intelligent dma (idma) ii-2-12 epson s1c33e08 technical manual ii.2.4.2 successive transfer mode the channels for which dmod in control information is set to 01 operate in successive transfer mode. in this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. the transfer counter is decremented to 0 by one transfer executed. the operation of idma in successive transfer mode is shown by the flow chart in figure ii. 2.4.2.1. start end calculates address of control information loads channel control information transfers one unit of data transfer counter - 1 saves channel control information idma interrupt processing (if interrupt is enabled) transfer counter = 0 a base address + (channel number 16) bn (4 words) :n = 1C4 c (data read from source of transfer) d (data write to destination of transfer) e gn (4 words) :n = 1C4 n trigger y a b1 b2 b3 b4 c1 d1 e1 cn dn en f g1 g2 g3 g4 restores initial values to address ? f ? : according to srinc/dsinc settings figure ii.2.4.2.1 operation flow in successive transfer mode (1 ) when a trigger is accepted, the address for control information is calculated from the base address and channel number. (2 ) control information is read from the calculated address into t he internal temporary register. (3 ) data of the size set in the control information is read from t he source address. (4 ) the read data is written to the destination address. (5 ) the address is incremented or decremented and the transfer c ounter is decremented. (6 ) steps (3) to (5) are repeated until the transfer counter reaches 0. (7 ) if srinc and/or dsinc are 010 or 100 , the address is recycled to the initial value. (8 ) the modified control information is written to ram. (9 ) in the case of a hardware trigger, the interrupt control bits are processed before completing idma. condition cause-of-interrupt flag idma request bit idma enable bit ________________________________________________________________________________________ transfer counter 0 : reset (0) not changed (1 ) not changed (1) transfer counter = 0, dinten = 1 : not changed (1) reset (0) not changed (1) transfer counter = 0, dinten = 0 : reset (0) not changed (1) reset (0)
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.4.3 block transfer mode the channels for which dmod in control information is set to 10 operate in block transfer mode. in this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by blklen. if a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. the operation of idma in block transfer mode is shown by the flow chart in figure ii. 2.4.3.1. start end calculates address of control information loads channel control information transfers one unit of data block size - 1 restores initial values to block size and address ? idma interrupt processing (if interrupt is enabled) block size = 0 a base address + (channel number 16) bn (4 words) :n = 1C4 c (data read from source of transfer) d (data write to destination of transfer) e 1-block transfer f g n trigger y a b1 b2 b4 b3 c1 d1 e1 cn dn en f g h1 h2 h4 h3 transfer counter - 1 saves channel control information transfer counter = 0 hn (4 words) :n = 1C4 n y ? : according to srinc/dsinc settings figure ii.2.4.3.1 operation flow in block transfer mode (1 ) when a trigger is accepted, the address for control information is calculated from the base address and channel number. (2 ) control information is read from the calculated address into t he internal temporary register. (3 ) data of the size set in the control information is read from t he source address. (4 ) the read data is written to the destination address. (5 ) the address is incremented or decremented and blklen is decreme nted. (6 ) steps (3) to (5) are repeated until blklen reaches 0. (7 ) if srinc and/or dsinc are 010 or 100 , the address is recycled to the initial value. (8 ) the transfer counter is decremented. (9 ) the modified control information is written to ram. (10 ) in the case of a hardware trigger, the interrupt control bits are processed before completing idma. condition cause-of-interrupt flag idma request bit idma enable bit ________________________________________________________________________________________ transfer counter 0 : reset (0) not changed (1 ) not changed (1) transfer counter = 0, dinten = 1 : not changed (1) reset (0) not changed (1) transfer counter = 0, dinten = 0 : reset (0) not changed (1) reset (0)
ii bus modules: intelligent dma (idma) ii-2-14 epson s1c33e08 technical manual ii.2.4.4 cause-of-interrupt processing by trigger type when invoked by a cause of interrupt the cause-of-interrupt flag by which idma has been invoked remains set even during a dma transfer. if the transfer counter is decremented to 0 and dinten = 1 (interrupt enabled) when one dma transfer is completed, the cause of interrupt that has invoked idma is not reset and an interrupt request is generated. at the same time, the idma request bit is cleared to 0 . the idma enable bit is not cleared and remains set to 1. if the transfer counter is not 0 , the cause-of-interrupt flag is reset when the dma transfer is completed, so that no interrupt is generated. in this case, the idma request bit and idma enable bit are not cleared and remain set to 1. when dinten has been set to 0 (interrupt disabled), the cause-of-interrupt flag is reset even if the transfer counter reaches 0 , so that no interrupt is generated. in this case, the idma request bit is not cleared but the idma enable bit is cleared. 2 1 0 trigger by cause of interrupt data transfer transfer counter dinten idma request bit idma enable bit cause-of-interrupt flag interrupt request 1 0 figure ii.2.4.4.1 operation when invoked by cause of interrupt when idma is invoked by a cause of interrupt, the idma cause-of-interrupt flag fidma (d 4/0x300281 ) will not be set. ? fidma : idma cause-of-interrupt flag in the dma interrupt cause flag register (d4/0x300281) when invoked by a software trigger if the transfer counter is decremented to 0 and dinten = 1 (interrupt enabled) when one dma transfer is completed, fidma (d4/0x300281) is set, thereby generating an interrupt request. if the transfer counter is not 0 or dinten = 0 (interrupt disabled), fidma (d4/0x300281) is not set. if the cause-of-interrupt flag for the same channel is set during a software-triggered transfer, the idma invocation request by that cause-of-interrupt flag is kept pending. however, the cause-of-interrupt flag will be reset when the current execution is completed, so there will be no dma transfer by the cause-of-interrupt flag. 2 1 0 software trigger data transfer transfer counter dinten fidma (d4/0x300281) interrupt request 1 0 figure ii.2.4.4.2 operation when invoked by software trigger
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.5 linking if the idma channel number to be executed next is set in the idma link field lnkchn of control information and lnken is set to 1 (link enabled), dma successive transfer in that idma channel can be performed. an example of link setting is shown in figure ii. 2.5.1. ch.3 trigger after transfer tc = 0 lnken = 1 lnkchn = 5 dmod = 01 dinten = 1 tc = 1024 ch.5 tc = 7 lnken = 1 lnkchn = 7 dmod = 00 dinten = 1 tc = 8 ch.7 tc = 0 lnken = 0 lnkchn = 9 dmod = 10 dinten = 1 tc = 1 figure ii.2.5.1 example of link setting for the above example, idma operates as described below. for trigger in hardware (1 ) the idma channel 3 is invoked by a cause of interrupt and the dma transfer that is set is performed. since the idma is operating in successive transfer mode and the transfer counter is decremented to 0 and dinten is set to 1, the cause-of-interrupt flag by which the channel 3 has been invoked remains set. (2 ) next, a dma transfer is performed via the linked idma channel 5 . channel 5 is set for single transfer mode and the transfer counter in this transfer is decremented by 1. (3 ) finally, a dma transfer in idma channel 7 is performed. although the channel 7 is set for block transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers to be performed is 1. (4 ) since the cause-of-interrupt flag that has invoked idma channel 3 in (1 ) remains set, an interrupt is generated when the idma transfer (channel 7 ) in (3 ) is completed. the transfer result does not affect the cause-of- interrupt flag of channel 3. to generate an interrupt at the end of an idma transfer, the dinten (end-of-transfer interrupt enable) bits in the idma control information for the first idma channel to be invoked and all the channels to be linked must be set to 1. for trigger in the software application (1 ) the idma channel 3 is invoked by a software trigger dstart (d7/0x301104 ) and the dma transfer that is set is performed. since the idma is operating in successive transfer mode and the transfer counter is decremented to 0 and dinten is set to 1 , the idma cause-of-interrupt flag fidma (d4/0x300281 ) is set when the transfer is completed. ? dstart : idma start control bit in the idma start register (d7/0x301104) ? fidma : idma cause-of-interrupt flag in the dma interrupt cause flag register (d4/0x300281) (2 ) next, a dma transfer is performed in the linked idma channel 5 . the channel 5 is set for the single transfer mode and the transfer counter in this transfer is decremented by 1. (3 ) finally, a dma transfer in idma channel 7 is performed. although channel 7 is set for the block transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers to be performed is 1 . the completion of this transfer also causes fidma (d4/0x300281 ) to be set to 1. however, fidma (d 4/0x300281) has already been set when the transfer is completed in (1 ) above. (4 ) since fidma (d4/0x300281 ) is set, an interrupt request is generated here. in cases when idma has been invoked by a trigger in the software application, if the transfer counter in any one of the linked channels is decremented to 0 and dinten for that channel is set to 1 , an interrupt request for the completion of idma transfer is generated when a transfer operation in each of the linked channels is completed. the channel in which an interrupt request has been generated can be verified by reading out the transfer counter. transfer operations in each channel are performed as described earlier.
ii bus modules: intelligent dma (idma) ii-2-16 epson s1c33e08 technical manual ii.2.6 interrupt function of intelligent dma idma can generate an interrupt that causes invocation of idma and an interrupt for the completion of idma transfer itself. interrupt when invoked by a cause of interrupt if the corresponding bits of the idma request and interrupt enable registers are left set (= 1 ), assertion of an interrupt request is kept pending even when the enabled cause of interrupt has occurred and the idma channel assigned to that cause of interrupt is invoked. if the transfer counter is decremented to 0 and dinten = 1 (interrupt enabled) when one dma transfer is completed, the cause of interrupt that has invoked idma is not reset and an interrupt request is generated. at the same time, the idma request bit is cleared to 0 . the idma enable bit is not cleared and remains set to 1. if the transfer counter is not 0 , the cause-of-interrupt flag is reset when the dma transfer is completed, so that no interrupt is generated. in this case, the idma request bit and idma enable bit are not cleared and remain set to 1. when dinten has been set to 0 (interrupt disabled), the cause-of-interrupt flag is reset even if the transfer counter reaches 0 , so that no interrupt is generated. in this case, the idma request bit is not cleared but the idma enable bit is cleared. when idma is invoked by a cause of interrupt, the idma cause-of-interrupt flag fidma (d 4/0x300281 ) will not be set. for details about the causes of interrupt that can be used to invoke idma and the interrupt control registers, refer to the descriptions of the peripheral circuits in this manual. note that the priority levels of causes of interrupt are set by the interrupt priority register. refer to section iii. 2, interrupt controller (itc). however, when compared between idma and interrupt requests, idma is given higher priority over the other. consequently, even when a cause of interrupt occurring during an idma transfer has higher priority than the cause of interrupt that invoked the idma transfer, an interrupt request for it or a new idma invocation request is not accepted until after the current idma transfer is completed. software-triggered interrupts if the transfer counter is decremented to 0 and dinten = 1 (interrupt enabled) when one dma transfer operation is completed, fidma (d 4/0x300281 ) is set, thereby generating an interrupt request. if the transfer counter is not 0 or dinten = 0 (interrupt disabled), fidma (d4/0x300281) is not set. idma interrupt control register in the interrupt controller the following control bits are used to control an interrupt for the completion of idma transfer: ? fidma : idma cause-of-interrupt flag in the dma interrupt cause flag register (d4/0x300281) ? eidma : idma interrupt enable bit in the dma interrupt enable register (d4/0x300271) ? pdm[2:0] : idma interrupt level bits in the idma interrupt priority register (d[2:0]/0x300265) when a dma transfer in the idma channel invoked by a trigger in the software application or subsequent link is completed and the transfer counter is decremented to 0 , the cause-of-interrupt flag for the completion of idma transfer is set to 1 . however, this requires as a precondition that interrupt be enabled (dinten = 1 ) in the control information for that channel. if the interrupt enab le register bit remains set (= 1) when the flag is set, an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit cleared (= 0 ). use the interrupt priority register to set interrupt priority levels (0 to 7 ). an interrupt request to the cpu is accepted on condition that no other interrupt request of higher priority is generated. furthermore, it is only when the psr's ie bit = 1 (interrupt enabled) and the set value of il is smaller than the idma interrupt level which is set by the interrupt priority register that the cpu actually accepts an idma interrupt request. for details about these interrupt control registers, and for information on device operation when an interrupt occurs, refer to section iii.2, interrupt controller (itc). trap vector the trap vector address for an interrupt upon completion of idma transfer by default is set to 0xc00068. the trap table base address can be changed using the ttbr registers.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.7 details of control registers table ii. 2.7.1 list of idma registers address 0x00301100 0x00301102 0x00301104 0x00301105 function sets 16 low-order bits of idma base address. sets 16 high-order bits of idma base address. invokes an idma channel. enables idma. register name idma base address register 0 (pidmabase) idma base address register 1 idma start register (pidma_start) idma enable register (pidma_en) siz e 16 16 8 8 the following describes each idma control register. the idma control registers are mapped in the 16 -bit device area from 0x301100 to 0x301105 , and can be accessed in units of half-words or bytes. note : when setting the idma control registers, be sure to write a 0, and not a 1, for all reserved bits.
ii bus modules: intelligent dma (idma) ii-2-18 epson s1c33e08 technical manual 0x301100: idma base address register 0 (pidmabase) 0x301102: idma base address register 1 name address register name bit function setting init. r/w remarks dbasel15 dbasel14 dbasel13 dbasel12 dbasel11 dbasel10 dbasel9 dbasel8 dbasel7 dbasel6 dbasel5 dbasel4 dbasel3 dbasel2 dbasel1 dbasel0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idma base address low-order 16 bits (initial value: 0x200003a0) 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 r/w fix at 0. 00301100 (hw) idma base address register 0 (pidmabase) dbaseh15 dbaseh14 dbaseh13 dbaseh12 dbaseh11 dbaseh10 dbaseh9 dbaseh8 dbaseh7 dbaseh6 dbaseh5 dbaseh4 dbaseh3 dbaseh2 dbaseh1 dbaseh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idma base address high-order 16 bits (initial value: 0x200003a0) 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301102 (hw) idma base address register 1 specify the starting address of the control information to be placed in ram. at initial reset, the base address is set to 0x200003a0. d[15:0]/0x301100 dbasel[15:0]: idma low-order base address bits use dbasel to set the 16 low-order bits of the base address. d[15:0]/0x301102 dbaseh[15:0]: idma high-order base address bits use dbaseh to set the 16 high-order bits of the base address. in the s 1c33e08 idma, the dbaseh[15:12 ] bits have been added to extend the base address into 32 bits. notes : ? the control information must be placed in dst ram (area 3 ) or an external ram. a 0 ram (area 0 ) cannot be used to store control information. ? the address you set in the idma base address registers must always be 4 -word units boundary address. ? these registers cannot be read or written in bytes. the registers must be accessed in words for read/write operations to address 0x301100 , or in half-words for read/write operations to addresses 0x301100 and 0x301102 . write operations in half-words must be performed in order of 0x301100 and 0x301102 . read operations in half-words may be performed in any order. ? be sure to disable dma transfers (idmaen (d0/0x301105 ) = 0 ) before setting the base address. writing to the idma base address register is ignored when the dma transfer is enabled (idmaen (d 0 / 0 x 301105 ) = 1 ). when the register is read, the read data is indeterminate.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301104: idma start register (pidma_start) name address register name bit function setting init. r/w remarks 0 to 127 dstart dchn6 dchn5 dchn4 dchn3 dchn2 dchn1 dchn0 d7 d6 d5 d4 d3 d2 d1 d0 idma start idma channel number 1 idma start 0 stop 0 0 r/w r/w 00301104 (b) idma start register (pidma_start) d7 dstart: idma start control bit use this bit for software trigger and for monitoring the operation of idma. 1 (w): start idma 0 (w): has no effect 1 (r): operating (only when invoked by software trigger) 0 (r): idle (default) when dstart is set to 1 , it functions as a software trigger, invoking the idma channel that is set in the dchn register. d[6:0] dchn[6:0]: idma channel number setting bits set the channel numbers ( 0 to 127 ) to be invoked by software trigger. (default: 0) note : do not start an idma transfer and change the idma channel number simultaneously. when setting dchn[6:0], write 0 to dstart.
ii bus modules: intelligent dma (idma) ii-2-20 epson s1c33e08 technical manual 0x301105: idma enable register (pidma_en) name address register name bit function setting init. r/w remarks C C idmaen d7C1 d0 reserved idma enable (for software trigger) 1 enabled 0 disabled C 0 C r/w 0 when being read. 00301105 (b) idma enable register (pidma_en) d[7:1] reserved d0 idmaen: idma enable bit enable a idma transfer. 1 (r/w): enable 0 (r/w): disable (default) idma transfer is enabled by writing 1 to this bit and is disabled by writing 0.
ii bus modules: intelligent dma (idma) s1c33e08 technical manual epson ii-2-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.2.8 precautions ? the control information must be placed in dst ram (area 3 ) or an external ram. area 0 (a0 ram) and area 2 cannot be used for idma transfer and storing control information. ? the address you set in the idma base address registers must always be 4 -word units boundary address. ? be sure to disable dma transfers (idmaen (d0/0x301105 ) = 0 ) before setting the base address. writing to the idma base address register is ignored when the dma transfer is enabled (idmaen (d 0/0x301105 ) = 1 ). when the register is read, the read data is indeterminate. ? idmaen : idma enable bit in the idma enable register (d0/0x301105) ? do not start an idma transfer and change the idma channel number simultaneously. when setting dchn[6:0] (d[6:0]/0x301104), write 0 to dstart (d7/0x301104). ? dchn[6:0] : idma channel number set-up bits in the idma start register (d[6:0]/0x301104) ? dstart : idma start control bit in the idma start register (d7/0x301104) ? since the control information is placed in ram, it can be rewritten. however, before rewriting the content of this information, make sure that no dma transfer is generated in the channel whose information you are going to rewrite. ? since the c33 pe core performs look-ahead operations, do not specify another channel immediately after a software trigger has invoked a channel. ? be sure to disable the idma before setting the chip in sleep mode (executing the slp instruction). halt mode can be set even if the idma is enabled.
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ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3 sram controller (sramc) ii.3.1 overview of the sramc the sram controller (sramc) is a bus module connected to the cpu_ahb bus. the sramc manages the external memory space by dividing it into 19 areas. this module controls external bus signals according to bus conditions set for each area as it accesses the connected memor y or i/o device. the sramc functions and features are outlined below. ? supports a 32 -bit address bus and data bus. ? controls external memory space as 19 divided areas (areas 4 to 22). ? allows various conditions (e.g., device type, device size, number of wait cycles) to be set for each area. ? outputs 8 chip-enable signals (#ce4 to #ce11 ) corresponding to each external area. ? supports two interface modes: a0 and bsl (with bsl mode for external memory only). ? allows sram, rom, or flash memory to be connected directly to the external bus. ? allows wait states to be inserted from the external #wait pin (for sram type only). ? little endian
ii bus modules: sram controller (sramc) ii-3-2 epson s1c33e08 technical manual ii.3.2 sramc pins table ii. 3.2.1 lists the pins used by the sramc. table ii. 3.2.1 sramc pin list pin name a0/ #bsl a[24:1] d[15:0] #ce11 #ce10 #ce9 #ce8 #ce7 #ce6 #ce5 #ce4 #rd #wrl/ #wr #wrh/ #bsh bclk #w ait boo t[1:0] i/o o o i/o o i/o o o o o o o o o o o i i function address signal output pin / lo w-order b yte b us strobe signal output pin address signal output pins (e xter nal address b us) data signal input/output pins (e xter nal data b us) area 11/12 chip enab le signal output pin area 10/13/20 chip enab le signal output pin / boot mode select pin area 9/22 chip enab le signal output pin area 8/21 chip enab le signal output pin area 7/19 chip enab le signal output pin area 6/17/18 chip enab le signal output pin area 5/15/16 chip enab le signal output pin area 4/14 chip enab le signal output pin read signal output pin lo w-order b yte wr ite signal output pin (when accessing a0 interf aced area) / wr ite signal output pin (when accessing bsl interf aced area) high-order b yte wr ite signal output pin (when accessing a0 interf aced area) / high-order b yte b us strobe signal output pin (when accessing bsl interf aced area) bus cloc k output pin exter nal w ait request input pin boot mode select pins (boo t0 is not av ailab le in the qfp24-144pin pac kage model) notes : ? some control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state is set to other than the sramc. before the sramc signals assigned to these pins can be used, the functions of these pins must be switched for the sramc by setting each corresponding port function select register. for details on how to switch over the pin functions, see section i. 3.3, switching over the multiplexed pin functions. ? the bus control signals can be pulled high or forcibly driven low in software. for details on how to control, see section iii. 4, misc registers.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.3 external memory area (areas 4 , 5 , 7 to 22) the sramc supports an external memory space, which is divided into 19 areas as shown in figure ii.3.3.1. area 13 0x02ff ffff 0x0200 0000 area 12 ( ? 1) 0x01ff ffff 0x0180 0000 area 11 ( ? 1) 0x017f ffff 0x0100 0000 area 10 0x00ff ffff 0x00c0 0000 area 9 ( ? 1) 0x00bf ffff 0x0080 0000 area 8 0x007f ffff 0x0060 0000 area 7 ( ? 1, ? 2) 0x005f ffff 0x0040 0000 area 6 0x003f ffff 0x0030 0000 (reserved for internal peripherals) area 5 0x002f ffff 0x0020 0000 area 4 ( ? 1) 0x001f ffff 0x0010 0000 area 15 0x05ff ffff 0x0400 0000 area 14 ( ? 1) 0x03ff ffff 0x0300 0000 external memory 16m bytes external memory 8m bytes external memory 8m bytes external memory 4m bytes external memory 4m bytes external memory 2m bytes external memory 2m bytes external memory 1m bytes external memory 1m bytes area 18 0x0fff ffff 0x0c00 0000 area 17 0x0bff ffff 0x0800 0000 area 16 0x07ff ffff 0x0600 0000 external memory 64m bytes area 19 ( ? 1, ? 2) 0x13ff ffff 0x1000 0000 external memory 64m bytes area 20 0x23ff ffff 0x2000 0000 external memory 64m bytes area 21 0x43ff ffff 0x4000 0000 external memory 64m bytes area 22 ( ? 1, ? 2) 0x83ff ffff 0x8000 0000 external memory 64m bytes external memory 64m bytes external memory 32m bytes external memory 32m bytes external memory 16m bytes #ce4 #ce5 #ce6 ( ?3) #ce7 ( ?4) #ce 8 #ce9 #ce10 #ce11 ? 1 usable as memory space for smartmedia (nand flash), compactflash, or pc card. ? 2 usable as the sdram area. ? 3 external memory cannot be accessed. ? 4 area 22 is assigned to #ce9 in default settings. note that area 22 will be reassigned to #ce7 when the sdramc is enabled. figure ii.3.3.1 external memory space of the s1c33e08 areas 4, 5, 7 to 22 comprise an external memory area accessible from the sramc, to which external memory devices may be connected. the device type and size, and number of wait cycles may be set for each of these areas to be accessed.
ii bus modules: sram controller (sramc) ii-3-4 epson s1c33e08 technical manual ii.3.3.1 chip enable signals the s 1c33e08 provides 25 bits of an external address bus, 16 bits of an external data bus, and eight chip-enable pins (#ce4 to #ce11 ), allowing access to the 512mb address space. two or more areas are assigned to each chip-enable signal. table ii. 3 . 3 . 1 . 1 shows the relationship between the chip- enable pins and corresponding areas. table ii. 3.3.1.1 relationship between chip-enable pins and corresponding areas #ce pin #ce4 #ce5 #ce6 #ce7 #ce8 #ce9 #ce10 #ce11 corresponding area areas 4, 14 areas 5, 15, 16 areas 17, 18 areas 7, 19 areas 8, 21 areas 9, 22 areas 10, 13, 20 areas 11, 12 area area 4 area 5 area 17+18 area 7 area 8 area 9 area 10 area 11+12 siz e 1mb 1mb 128mb 2mb 2mb 4mb 4mb 16mb area area 14 area 15+16 C area 19 area 21 area 22 area 13 C siz e 16mb 64mb C 64mb 64mb 64mb 16mb C area C C C C C C area 20 C siz e C C C C C C 64mb C usable size of area in continuous address rang e the #ce x signal also becomes active when an address in any corresponding area is accessed. area 6 is allocated to the i/o area for s1c33e08 ip and peripheral circuits. although area 6 is one of external memory areas, external memory cannot be accessed. ii.3.3.2 area condition settings bus access conditions can be set by area for each #ce x signal. therefore, the same conditions for two or more areas accommodated by the respective #ce x signals will be set. this section describes the parameters to be set individually for each area and the relevant control bits. the sramc control registers are initialized by an initial reset. these registers should be set up back again in software to suit the external device configuration or specification as required. for details of bus cycle operation, see section ii. 3.6, bus access timing chart. note : the control register and control bit configurations are the same for all #ce4 to #ce11 areas. the control bit names begin with ce4 to ce11 to indicate the relevant areas, which in the description below are commonly represented by ce x for all areas. table ii. 3.3.2.1 area parameter settings setup item de vice type (#ce4C#ce11) de vice siz e (#ce4C#ce9, #ce11) static w ait cycle (#ce4C#ce11) #ce setup time (#ce4, #ce11) output disab le time (#ce9) content bsl a0 16 bits 8 bits inser t 7 w ait cycles : inser t 0 w ait cycles no setup time +1 bclk 7 cycles : 0 cycles contr ol bit settings ce x type = 1 ce x type = 0 (def ault) ce x size[1:0] = 01 (def ault) ce x size[1:0] = 10 ce x w ait[2:0] = 111 (def ault) : ce x w ait[2:0] = 000 ce x stup = 1 ce x stup = 0 (def ault) ce9hold[2:0] = 111 : ce9hold[2:0] = 000 (def ault) endian mode the s 1c33e08 supports little endian mode only. device type the sramc incorporates an sram-type bus interface, allowing a 0 (default) or bsl to be selected as the device type. to use a bsl-type device in the #ce x area, set ce xtype (d x - 4/0x30150c) to 1. ? ce x type : #ce x device type select bit in the device type setup register (d x - 4/0x30150c) table ii. 3.3.2.2 lists the bus control signal pins used in each device type.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table ii. 3.3.2.2 bus control signal pins used in a0 and bsl modes pin name #ce x #rd a0/#bsl #wrl/#wr #wrh/#bsh a0 (default) #ce x #rd unused #wrl #wrh bsl #ce x #rd #bsl #wr #bsh device size use ce xsize[1:0] (0x301508 ) to select a device size. ? ce4size[1:0] : #ce4 device size select bits in the device size setup register (d[1:0]/0x301508) ? ce5size[1:0] : #ce5 device size select bits in the device size setup register (d[3:2]/0x301508) ? ce6size[1:0] : #ce6 device size select bits in the device size setup register (d[5:4]/0x301508) ? ce7size[1:0] : #ce7 device size select bits in the device size setup register (d[7:6]/0x301508) ? ce8size[1:0] : #ce8 device size select bits in the device size setup register (d[9:8]/0x301508) ? ce9size[1:0] : #ce9 device size select bits in the device size setup register (d[11:10]/0x301508) ? ce11size[1:0] : #ce11 device size select bits in the device size setup register (d[15:14]/0x301508) table ii. 3.3.2.3 selection of device sizes ce x size1 1 1 0 0 ce xsize0 1 0 1 0 de vice siz e reser ve d 8 bits 16 bits reser ve d connected data bu s C d[7:0] d[15:0] C at an initial reset, the device size is initialized to 16 bits. note : the device size of the #ce10 area is determined by the contents in address 0xc00000 at system boot. the device size is set to 16 bits when the lsb of the 0xc00000 contents is 0 or 8 bits when it is 1. static wait cycle if the number of static wait cycles is specified, the chip enable and read/write signals are always prolonged for the number of specified cycles when the area is accessed. set up the wait cycle according to the specifications of the device connected to the area using ce x wait[2:0] (0x301504). ? ce4wait[2:0] : number of #ce4 static wait cycles setup bits in the wait control register (d[2:0]/0x301504) ? ce5wait[2:0] : number of #ce5 static wait cycles setup bits in the wait control register (d[6:4]/0x301504) ? ce6wait[2:0] : number of #ce6 static wait cycles setup bits in the wait control register (d[10:8]/0x301504) ? ce7wait[2:0] : number of #ce7 static wait cycles setup bits in the wait control register (d[14:12]/0x301504) ? ce8wait[2:0] : number of #ce8 static wait cycles setup bits in the wait control register (d[18:16]/0x301504) ? ce9wait[2:0] : number of #ce9 static wait cycles setup bits in the wait control register (d[22:20]/0x301504) ? ce10wait[2:0] : number of #ce10 static wait cycles setup bits in the wait control register (d[26:24]/0x301504) ? ce11wait[2:0] : number of #ce11 static wait cycles setup bits in the wait control register (d[30:28]/0x301504) table ii. 3.3.2.4 setting the static wait cycle ce x w ait2 1 1 1 1 0 0 0 0 number of wait cyc les 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle no w ait cycle ce x w ait1 1 1 0 0 1 1 0 0 ce x w ait0 1 0 1 0 1 0 1 0 at initial reset, the static wait conditions for all external areas are set to 7 cycles. the area to which an sram device is connected allows dynamic wait control using the #wait pin in addition to the static wait control. for details of bus cycle operation including wait cycles, see section ii. 3.6, bus access timing chart.
ii bus modules: sram controller (sramc) ii-3-6 epson s1c33e08 technical manual #ce4/#ce11 setup time normally a #ce signal is asserted one bclk clock cycle before the read/write signal becomes active. for the #ce 4 and #ce11 signals, this setup time can be removed to assert the #ce and read/write signals simultaneously. set ce xstup (d1, d2/0x301500) to 1 to remove the #ce setup time. ? ce4stup : #ce4 setup time select bit in the bclk and setup time control register (d1/0x301500) ? ce11stup : #ce11 setup time select bit in the bclk and setup time control register (d2/0x301500) at initial reset, #ce 4 and #ce11 signals are configured with one bclk setup time. for the bus cycle operations with or without a setup time, see section ii. 3.6, bus access timing chart. #ce9 output disable time in cases when a device having a long output disable time is connected, if a read cycle for that device is followed in the next access, contention for the data bus may occur. (due to the fact the read device's data bus is not placed in the high-impedance state.) the output disable time is provided to prevent such a data bus contention. this is accomplished by inserting a specified number of output disable cycles between a read cycle and the next bus operation. however, this setting is effective only for the #ce 9 area. the output disable time affects bus control signals such as #rd and #wrl/#wrh. check the specifications of the device to be connected before setting the output disable time. use ce 9hold[2:0] (d[6:4]/0x301500) to set the #ce9 output disable time. ? ce9hold[2:0] : #ce9 output disable time setup bits in the bclk and setup time control register (d[6:4]/0x301500) table ii. 3.3.2.5 setting the #ce9 output disable time ce9hold2 1 1 1 1 0 0 0 0 output disable cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle none ce9hold1 1 1 0 0 1 1 0 0 ce9hold0 1 0 1 0 1 0 1 0 at initial reset, the disable delay time is initialized to none (0 cycles). the following shows the conditions under which the output disable cycle is inserted. ? the output disable cycle is always inserted during read access. ? for read access where data size > device size, the output disable cycle is only inserted during the last access. ? no output disable cycle is inserted during write access. ? no output disable cycle is inserted during consecutive accesses to the same area.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.4 connection of external devices and bus operation ii.3.4.1 connecting external devices the following shows an example of connecting the s 1c33e08 and sram. s1c33e08 a[n:0] d[7:0] #ce x #rd #wrl sram a[n:0] i/o[7:0] #ce #oe #we figure ii.3.4.1.1 example of 8-bit sram connection with 8 -bit device size s1c33e08 a[n:1] d[15:0] #ce x #rd #wrl #wrh sram a[n-1:0] i/o[15:0] #ce #oe #wel #weh s1c33e08 a[n:1] d[15:0] #ce x #rd #wr #bsl #bsh sram a[n-1:0] i/o[15:0] #ce #oe #we #lb #ub figure ii.3.4.1.2 example of 16-bit sram connection with 16 -bit device size ii.3.4.2 data configuration in memory the s 1c33e08 sramc handles byte (8 -bit), halfword (16 -bit), and word (internal 32 -bit) data. to access data in memory, addresses aligned to the boundary of the data size must be specified. specifying other addresses generates address misaligned exceptions. instructions (e.g., stack manipulating and branch instructions) that rewrite the content of the stack pointer (sp) or program counter (pc) forcibly alter the address specified to a boundary address to prevent address misaligned exceptions. for details of address misaligned exceptions, refer to the c 33 pe core manual. table ii. 3.4.2.1 shows where each type of data is located in memory. table ii. 3.4.2.1 data locations in memory data type byte halfword w ord location byte boundar y (all addresses) halfword boundar y (a[0] = 0) w ord boundar y (a[1:0] = 0b00) all halfword and word data in memory are accessed in little endian mode. to increase memory efficiency, try locating the same type of data at contiguous addresses to reduce blank areas created by positioning at boundary addresses as much as possible.
ii bus modules: sram controller (sramc) ii-3-8 epson s1c33e08 technical manual ii.3.4.3 external bus operation the internal data bus size in the s 1c33e08 is 32 bits. note, however, that it has 16 external bus pins d[15:0 ]. depending on the device size and data size of the instruction executed, two or more bus operations may occur. table ii. 3.4.3.1 shows bus operation in a0 and bsl modes. for details on how to connect memory, see section ii. 3.4.1, connecting external devices. table ii. 3.4.3.1 bus operation de vice siz e 8 bits 16 bits data siz e byte half word w ord byte half word w ord r/w w r w r w r w r w r w r v alid signal #wrl #rd #wrl #rd #wrl #rd #wrl #wrh #rd #wrh #wrl #rd #wrh #wrl #rd d[15:8] pins C C C C C C C C C C C C C C C d[7:0] C d[7:0] d[7:0] pins d[7:0] d[7:0] d[7:0] d[15:8] d[7:0] d[15:8] d[7:0] d[15:8] d[23:16] d[31:24] d[7:0] d[15:8] d[23:16] d[31:24] d[7:0] C d[7:0] C access count 1 1 1st 2nd 1st 2nd 1st 2nd 3rd 4th 1st 2nd 3rd 4th 1 1 1 1 1 1 1st 2nd 1st 2nd a1 ? ? ? ? ? ? 0 0 1 1 0 0 1 1 ? ? ? ? ? ? 0 1 0 1 a0 ? ? 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 d[15:0] d[15:0] d[15:0] d[31:16] d[15:0] d[31:16] v alid signal C C C C C C #wr #bsl #wr #bsh #rd #bsl #rd #bsh #wr #bsh #bsl #rd #bsh #bsl #wr #bsh #bsl #rd #bsh #bsl d[15:8] pins C C C C C C C C C C C C C C C d[7:0] C d[7:0] d[7:0] pins C C C C C C C C C C C C C C d[7:0] C d[7:0] C d[15:0] d[15:0] d[15:0] d[31:16] d[15:0] d[31:16] a0 mode bsl mode
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.5 sramc operating clock and bus clock ii.3.5.1 operating clock of the sramc the sramc is clocked by the sramc_clk and sramc_sapb_clk clocks (= mclk) generated by the cmu. the bus control signals are generated synchronously with sramc_clk. the sramc_sapb_clk is used for the sramc control registers. for details on how to set and control the sramc operating clocks, see section iii. 1, clock management unit (cmu). controlling supply of the sramc operating clock the sramc operating clocks are supplied to the sramc with default settings. each clock supply can be controlled in the cmu. use the respective control bits to turn off any unnecessary clock supplies to reduce the amount of power consumed on the chip. 1 . sramc_sapb_clk the sramc_sapb_clk is used to operate the sramc control registers. to setup the registers, this clock is required. after the registers are set up, the clock supply can be stopped to reduce power consumption by setting sramsapb_cke (d7/0x301b04) to 0. ? sramsapb_cke : sramc sapb i/f clock control bit in the gated clock control register 1 (d7/0x301b04) 2. sramc_clk the sramc_clk is used for the sram interface. to access the external memories/devices and the peripheral control registers in area 6 , this clock is required. so this clock cannot be stopped in normal operation mode. however, the clock supply can be stopped in halt mode. by setting sramc_hcke (d26/0x301b04 ) to 0 , the sramc_clk stops when the cpu enters halt mode and it resumes when the cpu exits halt mode. ? sramc_hcke : sramc clock control (halt) bit in the gated clock control register 1 (d26/0x301b04) clock state in standby mode the supply of the sramc operating clock stops depending on the type of standby mode. halt mode: the operating clock is supplied the same way as in normal mode. it can be stopped by setting the cmu register. sleep mode: the clock supply stops. therefore, the sramc also stops operating in sleep mode.
ii bus modules: sram controller (sramc) ii-3-10 epson s1c33e08 technical manual ii.3.5.2 generation of the bus clock the sramc divides sramc_clk by a specified number to generate the bus clock (bclk). this divide-by ratio is set using the control bits shown below. setting the bus clock for areas other than #ce 9 ? bclk : bclk divide control bit in the bclk and setup time control register (d0/0x301500) setting the bus clock for the #ce 9 area ? ce9bclk : #ce9 area bclk divide control bit in the bclk and setup time control register (d7/0x301500) table ii. 3.5.2.1 bclk (sramc_clk divide-by ratio) settings bclk/ce9bclk 1 0 bclk frequenc y sramc_clk 1/2 sramc_clk 1 when initially reset, the bclk clock is set to sramc_clk 1/2. ii.3.5.3 external output of the bus clock the bclk output is an extended port function. therefore, before bclk can be output to external devices, the pin function must be switched for bclk output by using the function select register for the corresponding port. for details of the pins assigned to the bclk output function and how to switch the pin functions, see section i. 3.3, switching over the multiplexed pin functions.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.6 bus access timing chart ii.3.6.1 sram read/write timings with no external #wait 1 . sram read/write timings with no static wait cycles [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 4/#ce11 setup time: no setup time bclk a[24:0] #ce x #rd d[15:0] #wait valid valid figure ii.3.6.1.1 sram read timing with no static wait cycle bclk a[24:0] #ce x #wr ? d[15:0] #wait valid valid figure ii.3.6.1.2 sram write timing with no static wait cycle
ii bus modules: sram controller (sramc) ii-3-12 epson s1c33e08 technical manual 2 . sram read/write timings with static wait cycles [example settings] device size: 16 bits number of static wait cycles: 2 cycles #ce 4/#ce11 setup time: no setup time bclk a[24:0] #ce x #rd d[15:0] #wait valid valid static wait cycle figure ii.3.6.1.3 sram read timing with static wait cycle bclk a[24:0] #ce x #wr ? d[15:0] #wait valid valid static wait cycle figure ii.3.6.1.4 sram write timing with static wait cycle
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.6.2 sram read/write timings with external #wait a wait cycle can be inserted from the #wait pin only for sram-type devices. the external #wait signal is sampled on the rising edges of bclk at one clock before the read or write signal goes high. a wait state is entered while the #wait signal is sampled active (low), and subsequent operation resumes when the #wait signal is sampled inactive (high). [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 4/#ce11 setup time: no setup time bclk a[24:0] #ce x #rd d[15:0] #wait valid valid wait cycle figure ii.3.6.2.1 sram read timing with external #wait bclk a[24:0] #ce x #wr ? d[15:0] #wait valid valid wait cycle figure ii.3.6.2.2 sram write timing with external #wait
ii bus modules: sram controller (sramc) ii-3-14 epson s1c33e08 technical manual ii.3.6.3 sram read/write timings with #ce4/#ce11 setup time [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 4/#ce11 setup time: +1 bclk bclk a[24:0] #ce4/11 #rd d[15:0] #wait valid valid figure ii.3.6.3.1 sram read timing with #ce4/#ce11 setup time bclk a[24:0] #ce4/11 #wr ? d[15:0] #wait valid valid figure ii.3.6.3.2 sram write timing with #ce4/#ce11 setup time
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.6.4 sram read timings with #ce9 output disable time [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 9 output disable time: none bclk a[24:0] #ce9 #ce x #rd d[15:0] #wait valid valid read cycle for another area valid figure ii.3.6.4.1 sram read timing with no #ce9 output disable time [example settings] device size: 16 bits number of static wait cycles: 0 cycles #ce 9 output disable time: 1 cycle bclk a[24:0] #ce9 #ce x #rd d[15:0] #wait valid valid output disable time read cycle for another area valid figure ii.3.6.4.2 sram read timing with #ce9 output disable time
ii bus modules: sram controller (sramc) ii-3-16 epson s1c33e08 technical manual ii.3.7 control register details table ii. 3.7.1 sramc register list address 0x00301500 0x00301504 0x00301508 0x0030150c 0x00301510 function sets bclk and #ce4/#ce11 setup time. sets static wait cycle for each area. sets device size for each area. sets device type for each area. sets area 6 location. register name bclk and setup time control register (psramc_bclk_setup) wait control register (psramc_swait) device size setup register (psramc_slv_size) device type setup register (psramc_a0_bsl) area location setup register (psramc_als) siz e 32 32 32 32 32 each sramc control register is described below. the sramc control registers are mapped to the 32 -bit device area at addresses 0x301500 to 0x301510 , and can be accessed in units of words, halfwords, or bytes. note : when setting the sramc control registers, be sure to write a 0, and not a 1, for all reserved bits.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301500: bclk and setup time control register (psramc_bclk_setup) name address register name bit function setting init. r/w remarks C ce9bclk ce9hold2 ce9hold1 ce9hold0 C ce11stup ce4stup bclk d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce9 area bclk divide control #ce9 area output disable time reserved #ce11 setup time #ce4 setup time bclk divide control C 1 0 0 0 C 0 0 1 C r/w r/w C r/w r/w r/w 0 when being read. 0 when being read. 00301500 (w) bclk and setup time control register (psramc_bclk _setup) 1 no setup tim e 0 +1 bclk C 0 to 7 C 1 no setup tim e 0 +1 bclk 1 sramc_clk 1/2 0 sramc_clk 1 1 sramc_clk 1/2 0 sramc_clk 1 d[31:8] reserved d7 ce9bclk: #ce9 area bclk divide control bit the bclk clock for the #ce 9 area is independent of other areas and is generated from the sramc_clk clock by being divided by 1 or 2. ce9 bclk is used to select this divide-by ratio. 1 (r/w): sramc_clk 1/2 (default) 0 (r/w): sramc_clk 1 d[6:4] ce9hold[2:0]: #ce9 area output disable time setup bits these bits select the output disable time for accessing the #ce 9 area. table ii. 3.7.2 setting the #ce9 output disable time ce9hold2 1 1 1 1 0 0 0 0 output disable cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle none ce9hold1 1 1 0 0 1 1 0 0 ce9hold0 1 0 1 0 1 0 1 0 (default: 0b000 = none) when using a device that has a long output disable time, set a delay time to ensure that no contention for the data bus occurs during the bus operation immediately after a device is read. d3 reserved d2 ce11stup: #ce11 setup time select bit this bit selects the setup time (#ce active to #rd/#wr ? active) for the #ce11 signal. 1 (r/w): no setup time 0 (r/w): +1 bclk (default) d1 ce4stup: #ce4 setup time select bit this bit selects the setup time (#ce active to #rd/#wr ? active) for the #ce4 signal. 1 (r/w): no setup time 0 (r/w): +1 bclk (default) d0 bclk: bclk divide control bit the bclk clock is used for sram areas except the #ce 9 area and is generated from the sramc_clk clock by being divided by 1 or 2 . bclk is used to select this divide-by ratio. note that the bclk pin output clock will not be divided; it is always the same as the sramc_clk clock. 1 (r/w): sramc_clk 1/2 (default) 0 (r/w): sramc_clk 1 use ce 9bclk (d7) to set bclk for the #ce9 area.
ii bus modules: sram controller (sramc) ii-3-18 epson s1c33e08 technical manual 0x301504: wait control register (psramc_swait) name address register name bit function setting init. r/w remarks C ce11wait2 ce11wait1 ce11wait0 ce10wait3 ce10wait2 ce10wait1 ce10wait0 ce9wait3 ce9wait2 ce9wait1 ce9wait0 ce8wait3 ce8wait2 ce8wait1 ce8wait0 ce7wait3 ce7wait2 ce7wait1 ce7wait0 ce6wait3 ce6wait2 ce6wait1 ce6wait0 ce5wait3 ce5wait2 ce5wait1 ce5wait0 ce4wait3 ce4wait2 ce4wait1 ce4wait0 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved number of #ce11 static wait cycles reserved number of #ce10 static wait cycles reserved number of #ce9 static wait cycles reserved number of #ce8 static wait cycles reserved number of #ce7 static wait cycles reserved number of #ce6 static wait cycles reserved number of #ce5 static wait cycles reserved number of #ce4 static wait cycles C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C r/w C r/w C r/w C r/w C r/w C r/w C r/w C r/w 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301504 (w) wait control register (psramc_swait) C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 d31 reserved d[30:28] ce11wait[2:0]: number of #ce11 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 11 area. table ii. 3.7.3 setting the static wait cycle ce x w ait2 1 1 1 1 0 0 0 0 number of wait cyc les 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle no w ait cycle ce x w ait1 1 1 0 0 1 1 0 0 ce x w ait0 1 0 1 0 1 0 1 0 (default: 0b111 = 7 cycles) d27 reserved d[26:24] ce10wait[2:0]: number of #ce10 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 10 area. d23 reserved d[22:20] ce9wait[2:0]: number of #ce9 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 9 area. d19 reserved d[18:16] ce8wait[2:0]: number of #ce8 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 8 area.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d15 reserved d[14:12] ce7wait[2:0]: number of #ce7 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 7 area. d11 reserved d[10:8] ce6wait[2:0]: number of #ce6 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 6 area. d7 reserved d[6:4] ce5wait[2:0]: number of #ce5 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 5 area. d3 reserved d[2:0] ce4wait[2:0]: number of #ce4 static wait cycles setup bits these bits set the static wait cycle for accessing the #ce 4 area.
ii bus modules: sram controller (sramc) ii-3-20 epson s1c33e08 technical manual 0x301508: device size setup register (psramc_slv_size) name address register name bit function setting init. r/w remarks C ce11size1 ce11size0 C ce9size1 ce9size0 ce8size1 ce8size0 ce7size1 ce7size0 ce6size1 ce6size0 ce5size1 ce5size0 ce4size1 ce4size0 d31C16 d15 d14 d13C12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce11 device size reserved #ce9 device size #ce8 device size #ce7 device size #ce6 device size #ce5 device size #ce4 device size C 0 1 C 0 1 0 1 0 1 0 1 0 1 0 1 C r/w C r/w r/w r/w r/w r/w r/w 0 when being read. 0 when being read. 00301508 (w) device size setup register (psramc_slv _size) C (see below) C ce xsize[1:0] size reserved 8 bits 16 bits reserved 11 10 01 00 d[31:16] reserved d[15:14] ce11size[1:0]: device size select bits these bits select the device size for the #ce 11 area. table ii. 3.7.4 selection of device size ce x size1 1 1 0 0 ce xsize0 1 0 1 0 de vice siz e reser ve d 8 bits 16 bits reser ve d connected data bu s C d[7:0] d[15:0] C (default: 0b01 = 16 bits) d[13:12] reserved note : the device size of the #ce 10 area is determined by the contents in address 0xc00000 at system boot. the device size is set to 16 bits when the lsb of the 0xc00000 contents is 0 or 8 bits when it is 1. d[11:10] ce9size[1:0]: device size select bits these bits select the device size for the #ce 9 area. d[9:8] ce8size[1:0]: device size select bits these bits select the device size for the #ce 8 area. d[7:6] ce7size[1:0]: device size select bits these bits select the device size for the #ce 7 area. d[5:4] ce6size[1:0]: device size select bits these bits select the device size for the #ce 6 area. d[3:2] ce5size[1:0]: device size select bits these bits select the device size for the #ce 5 area. d[1:0] ce4size[1:0]: device size select bits these bits select the device size for the #ce 4 area.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30150c: device type setup register (psramc_a0_bsl) name address register name bit function setting init. r/w remarks C ce11type ce10type ce9type ce8type ce7type ce6type ce5type ce4type d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce11 device type #ce10 device type #ce9 device type #ce8 device type #ce7 device type #ce6 device type #ce5 device type #ce4 device type C 0 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0030150c (w) device type setup register (psramc_a0_bsl) C 1 bsl 0 a0 d[31:8] reserved d7 ce11type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce11 area. 1 (r/w): bsl 0 (r/w): a0 (default) table ii. 3.7.5 bus control signal pin functions in a0/bsl mode pin name #ce x #rd a0/#bsl #wrl/#wr #wrh/#bsh a0 (default) #ce x #rd unused #wrl #wrh bsl #ce x #rd #bsl #wr #bsh d6 ce10type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce10 area. 1 (r/w): bsl 0 (r/w): a0 (default) d5 ce9type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce9 area. 1 (r/w): bsl 0 (r/w): a0 (default) d4 ce8type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce8 area. 1 (r/w): bsl 0 (r/w): a0 (default) d3 ce7type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce7 area. 1 (r/w): bsl 0 (r/w): a0 (default) d2 ce6type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce6 area. 1 (r/w): bsl 0 (r/w): a0 (default) d1 ce5type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce5 area. 1 (r/w): bsl 0 (r/w): a0 (default) d0 ce4type: device type select bit this bit selects a device type (a 0 or bsl) for the #ce4 area. 1 (r/w): bsl 0 (r/w): a0 (default)
ii bus modules: sram controller (sramc) ii-3-22 epson s1c33e08 technical manual 0x301510: area location setup register (psramc_als) name address register name bit function setting init. r/w remarks C a6loc d31C1 d0 reserved area 6 location setup C 0 C r/w 0 when being read. 00301510 (w) area location setup register (psramc_als) C 1 external 0 internal d[31:1] reserved d0 a6loc: area 6 location setup bit this bit selects area 6 location from between external area or internal area. 1 (r/w): external 0 (r/w): internal (default) note : the s1c33e08 does not support an external device to be used for area 6. do not set a6loc to 1.
ii bus modules: sram controller (sramc) s1c33e08 technical manual epson ii-3-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.3.8 precautions the bclk pin output clock will not be divided regardless of how the bclk divide-by ratio is set using bclk (d0/0x301500 ); it is always the same as the sramc_clk clock. ? bclk : bclk divide control bit in the bclk and setup time control register (d0/0x301500)
ii bus modules: sram controller (sramc) ii-3-24 epson s1c33e08 technical manual this page is blank.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii. 4 sdram controller (sdramc) ii.4.1 sdram interface the sdram controller allows up to 64 mb of sdram to be connected directly to areas 7, 19 , and 22 . this section describes how to control the sdram interface, and how it operates. for instruction and data queue buffers to improve the sdram access performance and the bus arbiter to control sdram accesses from the cpu and lcdc, refer to section ii.4.2, instruction/data queue buffers, and section ii.4.3, bus arbiter, respectively. ii.4.1.1 overview of the sdram interface the following shows the main features and specifications of the sdram interface. ? up to 64mb sdram can be connected. ? three sdram areas (areas 7, 19, and 22 ) are reserved. sdram configuration examples - 32m 16-bit 1 chip (64mb) - 16m 16-bit 1 chip or 16m 8-bit 2 chips (32mb) - 8m 16-bit 1 chip or 8m 8-bit 2 chips (16mb) - 4m 16-bit 1 chip (8mb) - 2m 8-bit 2 chips (4mb) - 1m 16-bit 1 chip (2mb) ? data bus width: 16 bits ? cas latency: 1, 2, or 3 ? burst length: 2 ? supports 2 or 4 -bank sdram (ba1 and ba0 outputs). row address range: 2 k (sda10 Csda0), 4 k (sda11 Csda0), or 8 k (sda12 Csda0) column address range: 256 (sda7 Csda0), 512 (sda8 Csda0), or 1 k (sda9 Csda0) ? supports byte writes with the dqml and dqmh pins. ? supports bank interleaved access. ? incorporates a programmable 12 -bit auto refresh counter. the sdram can be refreshed as necessary, irrespective of the clock frequency used. ? intelligent self-refresh mode for low-power operation ? supports extended mode register set to program drive strength, temperature compensated self refresh, and partial array self refresh.
ii bus modules: sdram controller (sdramc) ii-4-2 epson s1c33e08 technical manual ii.4.1.2 sdramc pins table ii. 4.1.2.1 lists the pins used by the sdramc. table ii. 4.1.2.1 sdramc pin list pin name a[13:12] a[10:1] a[15:14] d[15:0] sd a10 sdcke sdclk #sdcs #sdras #sdcas #sd we dqml dqmh i/o o o o i/o o o o o o o o o o function address signal output pins (sd a[12:11]) address signal output pins (sd a[9:0]) bank select signal output pins (sdba[1:0]) data signal input/output pins (e xter nal data b us) address signal output pin (sd a10) sdram cloc k-enab le signal output pin sdram cloc k output pin sdram chip select signal output pin sdram ro w address strobe signal output pin sdram column address strobe signal output pin sdram wr ite signal output pin sdram data (to select lo w-order b yte) input/output mask signal output pin sdram data (to select high-order b yte) input/output mask signal output pin note : some control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state is set to other than the sdramc. before the sdramc signals assigned to these pins can be used, the functions of these pins must be switched for the sdramc by setting each corresponding port function select register. for details of pin functions and how to switch over, see section i.3.3, switching over the multiplexed pin functions.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.4.1.3 configuration of sdram sdram area the #ce 7 area (area 7 , area 19 , or area 22 ) is reserved for the sdramc. however, the #ce 7 area is configured for an sram area controlled with the sramc and the sdramc is disabled at initial reset. therefore, to use an sdram, the #ce 7 area must be configured as the sdram area by setting sdon (d4/0x301600 ) and appon (d1/0x301610) to 1. ? sdon : sdram controller enable bit in the sdram initial register (d4/0x301600) ? appon : sdapp control bit in the sdram application configuration register (d1/0x301610) note : when sdon (d4/0x301600) and appon (d1/0x301610) are set to 1, the #ce7 area external sram access conditions set in the sramc are disabled. setting sdram size and access conditions the table below lists the conditions related to sdram size and timing parameters that the sdramc can accommodate. table ii. 4.1.3.1 sdram setup items setup item sdram address configuration cas latency burst length t rp , t rcd t ras t rc , t rfc , t xsr content 32m 16 bits 1 16m 16 bits 1 8m 16 bits 1 4m 16 bits 1 1m 16 bits 1 (def ault) 16m 8 bits 2 8m 8 bits 2 2m 8 bits 2 3, 2 (def ault) or 1 2 (fix ed) 1 (def ault) to 4 cycles 1 (def ault) to 8 cycles 1 to 16 cycles (def ault: 15) contr ol bit settings addrc[2:0] (d[2:0]/0x301604) = 111 addrc[2:0] (d[2:0]/0x301604) = 011 addrc[2:0] (d[2:0]/0x301604) = 010 addrc[2:0] (d[2:0]/0x301604) = 001 addrc[2:0] (d[2:0]/0x301604) = 000 (def ault) addrc[2:0] (d[2:0]/0x301604) = 110 addrc[2:0] (d[2:0]/0x301604) = 101 addrc[2:0] (d[2:0]/0x301604) = 100 cas[1:0] (d[3:2]/0x301610) = 11, 10 (def ault) or 01 C t24ns[1:0] (d[13:12]/0x301604) = 00 (def ault) to 11 t60ns[2:0] (d[10:8]/0x301604) = 000 (def ault) to 111 t80ns[3:0] (d[7:4]/0x301604) = 0000 to 1110 (def ault) and 1111 sdram address configuration use addrc[ 2:0 ] (d[2:0]/0x301604 ) to select sdram size and chip configuration. this selection also sets up the bank size, column address size (page size), and row address size. ? addrc[2:0] : sdram address configuration bits in the sdram configuration register (d[2:0]/0x301604) table ii. 4.1.3.2 selecting sdram size sdram configuration 32m 16-bit 1 16m 8-bit 2 8m 8-bit 2 2m 8-bit 2 16m 16-bit 1 8m 16-bit 1 4m 16-bit 1 1m 16-bit 1 addrc2 1 1 1 1 0 0 0 0 addrc1 1 1 0 0 1 1 0 0 addrc0 1 0 1 0 1 0 1 0 bank 4 4 4 2 4 4 4 2 ro w 8k 4k 4k 2k 8k 4k 4k 2k column 1k 1k 512 512 512 512 256 256 memory siz e 64m b ytes 32m b ytes 16m b ytes 4m b ytes 32m b ytes 16m b ytes 8m b ytes 2m b ytes the relationship between the cpu addresses and the bank, colum n, and row addresses is shown below. a(m+n+p) bank address ro w address column address a(m+n+1) a(m+n) a(m+1) a(m) a1 a0 dqm figure ii.4.1.3.1 sdram address m: column address size (number of bits) 8 bits (256), 9 bits (512), or 10 bits (1k) n: row address size (number of bits) 11 bits (2k), 12 bits (4k), or 13 bits (8k) p: bank address size (number of bits) 1 bit (2 banks) or 2 bits (4 banks) when reading/writing byte data, the sdram controller decodes a 0 /bsl and wrh/bsh into dqml and dqmh. upper address bits that are not used (depending on memory size) are all set to 0s.
ii bus modules: sdram controller (sdramc) ii-4-4 epson s1c33e08 technical manual figures ii. 4.1.3.2 and ii.4.1.3.3 show examples of how to connect sdrams and figure ii.4.1.3.4 shows the area configuration and address ranges according to the sdram to be used. s1c33e08 a[15:14] a[13:12] sd a10 a[10:1] d[15:0] sdclk sdcke #sdcs #sdras #sdcas #sd we dqmh dqml sdram 32m 16 bits (4 banks) ba[1:0] a[12:11] a10 a[9:0] dq[15:0] clk cke #cs #ras #cas #we dqmu dqml figure ii.4.1.3.2 example of connecting 64-mb sdram s1c33e08 a[15:14] a12 sd a10 a[10:1] d[15:0] sdclk sdcke #sdcs #sdras #sdcas #sd we dqmh dqml sdram 8m 16 bits (4 banks) ba[1:0] a11 a10 a[9:0] dq[15:0] clk cke #cs #ras #cas #we dqmu dqml s1c33e08 a[15:14] a12 sd a10 a[10:1] d[15:8] d[7:0] sdclk sdcke #sdcs #sdras #sdcas #sd we dqmh dqml sdram 8m 8 bits (4 banks) 2 ba[1:0] a11 a10 a[9:0] dq[7:0] clk cke #cs #ras #cas #we dqm ba[1:0] a11 a10 a[9:0] dq[7:0] clk cke #cs #ras #cas #we dqm figure ii.4.1.3.3 example of connecting 16-mb sdram
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x005fffff 0x00500000 0x004fffff 0x00400000 bank 1 bank 0 area 7 area 19 1m 16-bit 1 = 2mb (addrc[2:0] = "000") area 7 (2mb, 0x00400000C0x005fffff) area 19 (256mb, 0x10000000C0x1fffffff) 0x1fffffff 0x10200000 0x101fffff 0x10100000 0x100fffff 0x10000000 mirror bank 1 bank 0 1m 16-bit 1 = 2mb (addrc[2:0] = "000") 0x005fffff 0x00400000 bank 0 bank 1 area 7 area 19 2m 8-bit 2 = 4mb (addrc[2:0] = "100") bank 1 cannot be accessed. 0x1fffffff 0x10400000 0x103fffff 0x10200000 0x101fffff 0x10000000 mirror bank 1 bank 0 2m 8-bit 2 = 4mb (addrc[2:0] = "100") 0x005fffff 0x00400000 area 7 area 19 4m 16-bit 1 = 8mb (addrc[2:0] = "001") banks 1C3 cannot be accessed. 0x1fffffff 0x10800000 0x107fffff 0x10600000 0x105fffff 0x10400000 0x103fffff 0x10200000 0x101fffff 0x10000000 mirror bank 3 bank 2 bank 1 bank 0 area 19 0x1fffffff 0x11000000 0x10ffffff 0x10c00000 0x10bfffff 0x10800000 0x107fffff 0x10400000 0x103fffff 0x10000000 mirror bank 3 bank 2 bank 1 bank 0 area 19 0x1fffffff 0x12000000 0x11ffffff 0x11800000 0x117fffff 0x11000000 0x10ffffff 0x10800000 0x107fffff 0x10000000 mirror bank 3 bank 2 bank 1 bank 0 4m 16-bit 1 = 8mb (addrc[2:0] = "001") 0x005fffff 0x00400000 area 7 8m 16-bit 1 = 16mb (addrc[2:0] = "010") or 8m 8-bit 2 = 16mb (addrc[2:0] = "101") upper half of bank 0 and banks 1C3 cannot be accessed. bank 0 8m 16-bit 1 = 16mb (addrc[2:0] = "010") or 8m 8-bit 2 = 16mb (addrc[2:0] = "101") 16m 16-bit 1 = 32mb (addrc[2:0] = "011") or 16m 8-bit 2 = 32mb (addrc[2:0] = "110") upper par t of bank 0 and banks 1C3 cannot be accessed. 16m 16-bit 1 = 32mb (addrc[2:0] = "011") or 16m 8-bit 2 = 32mb (addrc[2:0] = "110") bank 3 bank 2 bank 1 bank 3 bank 2 bank 1 bank 0 bank 0 0x005fffff 0x00400000 bank 3 bank 2 area 7 bank 1 bank 0 area 19 0x1fffffff 0x14000000 0x13ffffff 0x13000000 0x12ffffff 0x12000000 0x11ffffff 0x11000000 0x10ffffff 0x10000000 mirror bank 3 bank 2 bank 1 bank 0 32m 16-bit 1 = 64mb (addrc[2:0] = "111") upper par t of bank 0 and banks 1C3 cannot be accessed. 32m 16-bit 1 = 64mb (addrc[2:0] = "111") 0x005fffff 0x00400000 bank 3 bank 2 area 7 bank 1 bank 0 figure ii.4.1.3.4 sdram map
ii bus modules: sdram controller (sdramc) ii-4-6 epson s1c33e08 technical manual timing setup the following parameters can be set in conformity with sdram specifications before use. sdclk command sdba[1:0] sda[12:11, 9:0] sda10 dq[15:0] actv nop nop nop nop nop pre read ba ba ba row col row actv row ba row ba row row data data t rcd t rc t rp t ras cas latency nop actv ba bksel sdclk command sdcke sdba[1:0] sda[10] sda[12:11, 9:0] dq[15:0] self nop pall nop self refresh mode t rfc t xsr + 1 cycle t rp nop figure ii.4.1.3.5 sdram timing parameters ( 1 ) cas latency cas latency refers to the number of sdclk clocks until data is output from sdram after issuing the read command. for the sdramc s sdram interface, cas latency can be set from 1 to 3 using cas[1:0] (d[3:2]/0x301610). ? cas[1:0] : cas latency setup bits in the sdram application configuration register (d[3:2]/0x301610) table ii. 4.1.3.3 cas latency settings cas1 1 1 0 0 cas latenc y 3 2 1 reser ve d cas0 1 0 1 0 when initially reset, cas latency is initialized to 2. ( 2) t rc , t rfc , t xsr t rc : active to active command cycle time t rfc : auto-refresh cycle time t xsr : exit self refresh to active command period these timing parameters can be set from 1 to 16 cycles (in sdclk) using t80ns[3:0] (d[7:4]/0x301604). ? t80ns[3:0] : number of t rc , t rfc and t xsr cycles setup bits in the sdram configuration register (d[7:4]/0x301604)
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table ii. 4.1.3.4 t rc , t rfc and t xsr settings t80ns3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 t80ns2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 t rc , t rfc , t xsr 16 cycles 15 cycles 14 cycles 13 cycles 12 cycles 11 cycles 10 cycles 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle t80ns1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 t80ns0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 when initially reset, t rc , t rfc and t xsr are initialized to 15 cycles. ( 3) t ras t ras : active to precharge command period this timing parameter can be set from 1 to 8 cycles (in sdclk) using t60ns[2:0] (d[10:8]/0x301604). ? t60ns[2:0] : number of t ras cycles setup bits in the sdram configuration register (d[10:8]/0x301604) table ii. 4.1.3.5 t r as settings t60ns2 1 1 1 1 0 0 0 0 t60ns1 1 1 0 0 1 1 0 0 t ras 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle t60ns0 1 0 1 0 1 0 1 0 when initially reset, t ras is initialized to 1 cycle. ( 4) t rp , t rcd t rp : precharge to active command period t rcd : active to read or write delay time these timing parameters can be set from 1 to 4 cycles (in sdclk) using t 24 ns[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 301604 ). ? t24ns[1:0] : number of t rp and t rcd cycles setup bits in the sdram configuration register (d[13:12]/0x301604) table ii. 4.1.3.6 t r p and t rcd settings t24ns1 1 1 0 0 t24ns0 1 0 1 0 t rp , t rcd 4 cycles 3 cycles 2 cycles 1 cycle when initially reset, t rp and t rcd are initialized to 1 cycle.
ii bus modules: sdram controller (sdramc) ii-4-8 epson s1c33e08 technical manual ii.4.1.4 sdramc operating clock and sdram clock operating clock of the sdramc the sdramc is clocked by the following clocks generated by the cmu. for details on how to set and control the clocks, see section iii. 1, clock management unit (cmu). the sdramc operating clock supply to the sdramc is disabled by default setting. each clock supply can be controlled in the cmu. use the respective control bits to turn on only the required clocks to reduce the amount of power consumed on the chip. 1 . sdapp_cpu_clk clock this is the mclk clock used for interfacing between the cpu and sdramc. turn this clock on when using the sdramc. the clock supply can be controlled by sdapcpu_cke (d 6/0x301b00). ? sdapcpu_cke : sdramc cpu app clock control bit in the gated clock control register 0 (d6/0x301b00) furthermore, the sdapp_cpu_clk can automatically be stopped in halt mode. by setting sdapcpu_hcke (d 7/0x301b00 ) to 0 , the sdapp_cpu_clk stops when the cpu enters halt mode and it resumes when the cpu exits halt mode. ? sdapcpu_hcke : sdramc cpu app clock control (halt) bit in the gated clock control register 0 (d7/0x301b00) 2 . sdapp_lcdc_clk clock this is the mclk clock used for interfacing between the lcdc and sdramc. turn this clock on when using the sdram as the video ram. the clock supply can be controlled by sdaplcdc_cke (d 5/ 0x301b00). ? sdaplcdc_cke : sdramc lcdc app clock control bit in the gated clock control register 0 (d5/0x301b00) 3 . clocks for sdram interface and instruction/data queue buffers the sdramc inputs the osc_w clock (source clock for mclk) to operate the sdram interface. also this clock is used as sdclk (sdram synchronous clock). so the sdram can be accessed using a clock two times faster than the cpu clock when mclk is generated by dividing osc_w by 2. the osc_w clock supply can be controlled by sdapcpu_cke (d 6/0x301b00 ) and sdaplcdc_cke (d5/0x301b00). either one or both are set to 1, the osc_w clock is supplied to the sdramc. note : if the operating clock (sdclk) is stopped while the sdram is being accessed, a system failure may occur due to stoppage of the sdram operation in uncontrolled status. the following operations stop the sdclk, therefore, do not perform these operations when the sdram may be accessed. ? setting the s1c33e08 in sleep status ? switching the p21 port function from sdclk output to general-purpose input/output ? disabling the clock supply to the sdramc module besides the cpu, the dma controller (when dma transfer from/to the sdram is enabled) and the lcd controller (when sdram is configured as the vram for the lcdc) access the sdram. in this case, before performing an above operation, disable the dma transfer and the lcdc so that the sdram will not be accessed.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 4 . sdsapb_clk clock the sdsapb_clk is used to operate the sdramc control registers. to setup the registers, this clock is required. after the registers are set up, the clock supply can be stopped to reduce power consumption by setting sdsapb_cke (d4/0x301b00) to 0. ? sdsapb_cke : sdramc sapb i/f clock control bit in the gated clock control register 0 (d4/0x301b00) setting any of the clock control bits above (initially 0 ) to 1 turns on the corresponding clock supply to the sdramc. the sdramc operating clocks stop depending on the type of sta ndby mode. halt mode: the operating clock is supplied the same way as in normal mode. it can be stopped by setting the cmu register. sleep mode: the clock supply stops. therefore, the sdramc also stops operating in sleep mode. double frequency mode the sdramc supports double frequency mode in which the sdram can be operated with a clock two times faster than the cpu clock. for example, when the cpu runs with a 45 mhz clock, the sdram can be operated with a 90 mhz clock. to set the sdramc in double frequency mode: (1 ) configure mclk as osc_w 1/2. (2 ) set dbf (d5/0x301610) to 1. ? dbf : double frequency mode enable bit in the sdram application configuration register (d5/0x301610) note : the sdclk clock frequency is limited to 90 mhz, therefore, double frequency mode cannot be set when the cpu clock (mclk) is higher than 45 mhz. in this case (normal mode), a clock up to 60 mhz (cpu maximum operating frequency) can be used for the sdramc.
ii bus modules: sdram controller (sdramc) ii-4-10 epson s1c33e08 technical manual ii.4.1.5 control and operation of sdram interface initializing sdram to use sdram, it must be initialized by following the procedure below after switching power on. 1 . setting sdram interface pins switch over the pins shared with general-purpose input/output ports or other peripheral functions for sdram use by setting the relevant port function select register. for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. 2 . initializing the sdramc registers set up the sdramc registers in the following order: (1 ) sdram configuration register (0x301604) set sdram size/address-related parameters and access timing par ameters. (2 ) sdram refresh register (0x301608) set the auto-refresh and self-refresh counters. (3 ) sdram initial register (0x301600) set sdon (d 4) to 1 (sdramc enabled). (4 ) sdram application configuration register (0x301610) set cas latency and enable the sdapp and arbiter. also enable double frequency mode and instruction queue buffer if necessary. 3 . wait after sdram power-on after the power to sdram is turned on, the nop state (#sdcs = 1 ) must be maintained for a certain time (e.g., 100 s, 200 s or more). because this time varies with each sdram, refer to the specifications of the sdram being used. 4 . executing an sdram initial sequence in order to initialize the sdram, the pall (precharge all), ref (auto refresh), and mrs (mode register set) commands must be executed sequentially. note that the initialization sequence depends on the sdram. example 1 : pall ref ref mrs ( emrs) example 2 : pall mrs ref ref ( ref ref ref ref ref ref) refer to the specifications of the sdram to be used for the initialization sequence. each command can be executed using the control bit shown below. to execute the pall (precharge all) command: write 0x12 to the sdram initial register (0x301600); inipre (d1/0x301600) should be set to 1. then write any data to any address in the sdram. this dummy write is required as the trigger to send the pall command. ? inipre : pall command enable for initialization bit in the sdram initial register (d1/0x301600) to execute the ref (auto refresh) command: write 0x11 to the sdram initial register (0x301600); iniref (d0/0x301600) should be set to 1. then write any data to any address in the sdram. this dummy write is required as the trigger to send the ref command. ? iniref : ref command enable for initialization bit in the sdram initial register (d0/0x301600) when executing the ref command twice or more, insert the nop instruction between the executions. execute ref command execute nop execute ref command ( ref nop ref . . .) the sdram timing parameters set in the sdram configuration register ( 0x301604 ) is not effective in this manual initialization sequence. therefore, enough number of nop instructions must be executed to satisfy the sdram timings.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 to execute the mrs/emrs (mode register set/extended mode register set) command: write 0x14 to the sdram initial register (0x301600); inimrs (d2/0x301600) should be set to 1. then write any data to the specific address shown below according to the cas latency (mrs) or extended mode parameters (emrs). ? inimrs : mrs command enable for initialization bit in the sdram initial register (d2/0x301600) table ii. 4.1.5.1 data write address to execute the mrs/emrs command cpu address sdram address mrs cas latency = 1 cas latency = 2 cas latency = 3 emrs a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 1 0 0 0 0 0 0 0 0 see sdram specifications . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 ba1 mod e rese rv ed te st mode cas latency wb burst length bt mod e reser ve d ds p asr tcsr ba0 sd a12 sd a11 sd a10 sd a9 sd a8 sd a7 sd a6 sd a5 sd a4 sd a3 sd a2 sd a1 sd a0 for example, to execute an mrs command with 2 of cas latency specified, write data (any value) to address 0x10000442 (when the sdram is mapped to area 19 ) after writing 0x14 to the sdram initial register ( 0x301600). notes : ? the cas latency specified in the mrs command must be the same as the cas[1:0 ] (d[3:2]/ 0x301610 ) set value. ? cas[1:0] : cas latency setup bits in the sdram application configuration register (d[3:2]/0x301610) ? after the initial sequence commands are executed, the command enable bits must be set to 0 . write 0x10 to the sdram initial register (0x301600 ) after the last initialization command has been executed. ? the self-refresh function must be disabled until the sdram has finished initialization. 5. checking if the sdram has been initialized sden (d 3/0x301600 ) is reset to 0 after power-on, and is set to 1 upon completion of the initialization sequence shown above. make sure that sden (d 3/0x301600) is set to 1 before the sdram is accessed. in addition to being reset at power-on, sden (d 3/0x301600 ) is reset to 0 by writing 0 to sdon (d4/ 0x301600). ? sden : sdram initialize flag in the sdram initial register (d3/0x301600) ? sdon : sdram controller enable bit in the sdram initial register (d4/0x301600) sdram power sdclk command sdcke #sdcs #sdras #sdcas #sdwe dqmh/dqml sdon bit inipre bit iniref bit inimrs bit sden bit sda10 sdba[1:0] sda[12:11, 9:0] pall nop nop nop nop h h ref ref mrs cmd valid valid valid valid valid 100 s min. t rp t rfc t rfc v cc(min. ) nop figure ii.4.1.5.1 sdram power-up and initialization
ii bus modules: sdram controller (sdramc) ii-4-12 epson s1c33e08 technical manual sdram commands the sdram is controlled by commands that are comprised of a combination of high or low logic level signals. table ii. 4.1.5.2 lists the commands output by the sdram controller. table ii. 4.1.5.2 list of the supported sdram commands function deselect bank activ e bank precharge precharge all wr ite read mode register set nop a uto refresh self refresh entr y self refresh exit data wr ite/output enab le data wr ite/output disab le symbol C a ctv pre p all writ read mrs nop ref self C C C sdcke h h h h h h h h h h l l h h h dqm (dqmh/l) x x x x x x x x x x x l h sdb a[1:0] x v v x v v x x x x x x x sd a10 x v l h l l v x x x x x x sd a[12:11] sda[9:0] x v x x v v v x x x x x x #sdcs h l l l l l l l l l h x x #sdras x l l l h h l h l l x x x #sdcas x h h h l l l h l l x x x #sd we x h l l l h l h h h x x x command pins v = valid, x = don t care, l = low level, h = high level because all of these commands are output by the sdram controller as necessary, they do not need to be controlled by the user program, except for initializing the sdram. bus operations of sdram the external data bus of the s 1c33e08 is 16 bits wide. depending on the device size and data size of the instruction executed, two or more bus operations may occur. table ii. 4.1.5.3 shows bus operations in the sdram area. table ii. 4.1.5.3 bus operations de vice siz e 16 bits data siz e byte half word w ord r/w w r w r w r v alid signal dqml dqmh read dqmh/l read dqmh/l read little endian d[15:8] pins C d[7:0] C d[7:0] d[7:0] pins d[7:0] C d[7:0] C access count 1 1 1 1 1 1 1st 2nd 1st 2nd a1 ? ? ? ? ? ? 0 1 0 1 a0 0 1 0 1 ? ? ? ? ? ? d[15:0] d[15:0] d[15:0] d[31:16] d[15:0] d[31:16]
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 read cycle the sdramc always reads data from the sdram in bursts. the burst length is fixed at 2. figure ii. 4.1.5.2 shows an example of timing chart when reading out 2 -word data from the same row address. example of parameter settings: cas latency = 2, t rcd = 2 cycles, t ras = 4 cycles, t rp = 2 cycles sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] actv h nop pre nop read nop read ba ba row d(1-1) d(1-2) d(2-1) d(2-2) t rcd t rp cas latency cas latency row col1 ba col2 ba figure ii.4.1.5.2 burst read in the same page figure ii. 4.1.5.3 shows an example of a timing chart in cases where the row address is changed during burst read. example of parameter settings: cas latency = 2, t rcd = 2 cycles, t ras = 4 cycles, t rp = 2 cycles sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] actv h nop nop pre nop read ba ba row1 d (n) d (n+1) d (0) d (1) t rcd t rp t rcd t rp cas latency cas latency row1 coln ba actv nop pre nop read ba ba row2 row2 col0 ba figure ii.4.1.5.3 changing row address during burst read
ii bus modules: sdram controller (sdramc) ii-4-14 epson s1c33e08 technical manual write cycle when writing to the sdram, data are always written in a single operation. example of parameter settings: cas latency = 2, t rcd = 2 cycles, t ras = 4 cycles, t rp = 2 cycles sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] actv h nop pre nop read ba ba row1 d (n) d (n+1) d (m) t rcd t rp cas latency row1 coln ba writ pre ba colm ba figure ii.4.1.5.4 burst read to single write (same page) bank interleaved access multiple banks (up to four banks) can be activated at the same time. this makes it possible to access the sdram successively, one bank after another without issuing the actv (active) command. example of parameter settings: cas latency = 2, t rcd = 2 cycles, t ras = 4 cycles, t rp = 2 cycles sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] bank 1 bank 2 actv h nop nop actv read read read ba1 ba1 row2 d (n) d (n+1) t rp (bank 1 cannot be accessed) cas latency row2 row 1 row 1 active read precharge active read coln ba2 colm ba1 coll ba2 pre nop nop ba1 d (m) d (m+1) d (l) actv ba1 row3 row3 figure ii.4.1.5.5 bank interleaved access
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 sdram refresh the sdramc supports two sdram refresh modes: auto-refresh and self-refresh. auto-refresh the sdram controller incorporates a 12 -bit auto refresh counter. this counter continues counting on the sdclk clock edges, and when a specified count is reached, commands are sent to the sdram that precharges and auto-refreshes all banks. the counter is reset at that time, and starts counting for the next refresh period. the counter is also reset by self-refresh. the auto-refresh period is determined by the sdclk (mclk or double of mclk) clock frequency and the count value set in aurco[ 11:0] (d[11:0]/0x301608). ? aurco[11:0] : sdram auto-refresh counter bits in the sdram refresh register (d[11:0]/0x301608) for aurco[ 11:0 ] (d[11:0]/0x301608 ), set the appropriate value meeting the specifications of your sdram. the count value is obtained by the equation below. rfp aurco CCCCCCCC f clk - bl - cl - 2 t rp - t rcd - 3 rows rfp: maximum refresh period [s] rows: row address size f clk : sdclk clock frequency [hz] bl: burst length (= 2) cl: cas latency t rp : precharge command period [number of cycles] t rcd : active to read or write delay time [number of cycles] if rfp = 64 ms, rows = 4,096 , f clk = 20 mhz, cl = 2 , t rp = 2 , and t rcd = 2 , for example, the value to set is calculated as follows: 0.064 aurco CCCCCCCC 20,000,000 - 2 - 2 - 2 2 - 2 - 3 = 299 4,096 therefore, set any value equal to or less than 299 (0x12 b) for aurco[11:0] (d[11:0]/0x301608). sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] ref actv h l pall nop nop t rfc t rp figure ii.4.1.5.6 auto refresh
ii bus modules: sdram controller (sdramc) ii-4-16 epson s1c33e08 technical manual self-refresh self-refresh uses the sdram s self-refresh function and does not require clock pulses during the refresh period, thus helping to reduce the chip s power consumption. this self-refresh function is also used for data retention during power-down mode. to cause the sdram to be self-refreshed, set selen (d 23/0x301608 ) to 1 . this enables the sdram controller to send the self-refresh command (which sets the sdcke output to low) to the sdram. ? selen : sdram self-refresh enable bit in the sdram refresh register (d23/0x301608) the command is actually sent a certain time after accessing or auto-refreshing the sdram, so the sdram controller contains a self-refresh counter to count this time. the counter counts on sdclk clock edges, and when the designated count is reached, the sdram controller sends the self-refresh command to the sdram. when an sdram access or auto-refresh command is issued, the counter is reset and starts counting again. the designated value for the counter can be specified in a range of 1 to 127 by using the selco[6:0 ] (d[22:16]/ 0x301608). do not set the counter to 0 when the self-refresh function is enabled. ? selco[6:0] : sdram self-refresh counter bits in the sdram refresh register (d[22:16]/0x301608) when an sdram access occurs during self-refresh mode, sdcke is returned high and the sdram is taken out of self-refresh mode. after the sdram access has finished, the sdram controller sends another self- refresh command when the designated count is reached again. when the auto-refresh command is issued or an sdram access occurs, the counter will restart if the self- refresh command has not been sent to the sdram. therefore, the self-refresh counter value to be set must be smaller than the auto-refresh counter value. sdclk command sdcke #sdcs #sdras #sdcas #sdwe sdba[1:0] sda[10] sda[12:11, 9:0] dqmh/dqml dq[15:0] seldo self l pall nop self refresh mode enters self refresh mode exits self refresh mode t rp the sdram clock stops when sckon = 0. figure ii.4.1.5.7 self refresh during self-refresh (while sdcke = low), the seldo (d 25/0x301608 ) remains 1 . therefore, it is possible to determine whether or not self-refresh is in operation by readi ng this status register. ? seldo : sdram self-refresh status bit in the sdram refresh register (d25/0x301608) furthermore, sdram clock output during self-refresh can be turned off in order to reduce the chip s power consumption by setting the sckon (d 24/0x301608) to 0. ? sckon : sdram clock enable during self-refresh bit in the sdram refresh register (d24/0x301608)
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 power-down mode the s 1c33e08 supports two power-down modes for the c33 pe core (halt and sleep). halt mode ? the lcdc will be able to access the sdram in halt mode, if it is not disabled in normal mode. ? setting sdapcpu_cke (d6/0x301b00 ) and sdapcpu_hcke (d7/0x301b00 ) determines whether the cpu and dma will be able to access the sdram in halt mode or not. ? sdapcpu_cke : sdramc cpu app clock control bit in the gated clock control register 0 (d6/0x301b00) ? sdapcpu_hcke : sdramc cpu app clock control (halt) bit in the gated clock control register 0 (d7/0x301b00) table ii. 4.1.5.4 sdapp_cpu_clk clock status mode nor mal mode hal t mode sdapcpu_hcke x x x x 1 1 1 1 0 sdapcpu_cke 1 1 0 0 1 1 0 0 x sdaplcdc_cke 1 0 1 0 1 0 1 0 x sdram clock ( ? ) on (cpu , dma and lcdc) on (cpu and dma) on (lcdc) off (cannot be accessed) on (dma and lcdc) on (dma) on (lcdc) off (cannot be accessed) off (cannot be accessed) ? : ( ) indicates the modules that can access the sdram. note : to maintain data in the sdram during halt status with no sdram clock supplied, place the sdram in self-refresh mode by setting seldo (d25/0x301608) to 1 before stopping the sdram clock. sleep mode in sleep mode, the sdram can be turned off to reduce power consumption by the following procedure: 1 . if the cpu runs with the program stored in the sdram, it must be changed to a program located in the built-in ram or a memory other than the sdram. 2 . turn the sdram power off. 3 . switch the ports used for the sdram to general-purpose ports. 4 . drive the data and address buses to low. 5 . set sdon (d4/0x301600) to 0 to disable the sdramc. 6 . execute the slp instruction. ? sdon : sdram controller enable bit in the sdram initial register (d4/0x301600) perform the following procedure when the cpu wakes up: 1 . the cpu wakes up from sleep status. 2 . configure the port functions for sdram. 3 . release the data and address buses from forced low driving. 4 . turn the sdram power on. 5 . wait 100 or 200 s for the sdram be stabilize according to the sdram specification. 6 . set sdon (d4/0x301600) to 1 to enable the sdramc. 7 . initialize the sdramc.
ii bus modules: sdram controller (sdramc) ii-4-18 epson s1c33e08 technical manual ii.4.2 instruction/data queue buffers ii.4.2.1 overview the sdramc module contains the sdramc application unit that is an interface unit to connect between the c33 pe core (ahb bus) and the sdram interface unit described in section ii.4.1 . it generates the read, write, address, data, and handshake signals to drive the sdram interface unit. besides generating these signals, it also includes a data queue buffer and an instruction queue buffer to realize the instruction pre-fetch function and to increase the c33 pe core memory performance. sdram interface sdram queue buffer controller instruction queue buffer data queue buffer read/write control address register address to ahb bus data in data out read/write signals #wait address comparator sdramc application unit figure ii.4.2.1.1 instruction/data queue buffers ii.4.2.2 iqb (instruction queue buffer) this is a queue buffer to pre-fetch instructions and consists of 16 16 -bit d flip-flops. it is organized in 2 slots 8 16 bits as shown in the figure below. a[24:14] iqb address a[3:1] slot 0 slot 1 a[13:4] slot 0 address slot 1 address buf 0 buf 1 buf 2 buf 3 buf 4 buf 5 buf 6 buf 7 buf 0 buf 1 buf 2 buf 3 buf 4 buf 5 buf 6 buf 7 figure ii.4.2.2.1 structure of iqb iqb acts as an instruction cache located between the cpu and sdram when it is enabled by setting iqb (d 0/ 0x301610) to 1. ? iqb : instruction queue buffer enable bit in the sdram application configuration register (d0/0x301610) when the cpu attempts to fetch the first instruction from the sdram after iqb is enabled, the sdramc ap - plication unit pre-fetches 8 instructions from the sdram (including cpu aimed instructions) and stores them in iqb's slot 0 . the cpu then gets the needed instruction from iqb. after that, the cpu can get the subsequent instructions to be executed from iqb if iqb contains them (called as iqb hit). if iqb does not contain the instruc - tion to be executed next (called as iqb not hit), the sdramc application unit pre-fetches another 8 instruc - tions (including cpu aimed instructions) from the sdram and stores them in iqb's slot 1 , then the cpu gets the needed instruction from iqb's slot 1 . the two slots are used alternately like this and the cpu continues fetching instructions from iqb while the routine to be executed is located in the sdram. each slot can store 8 instructions, so iqb always stores the pre-fetched data beginning with a 4 -word (128 bits) boundary address.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 cpu aimed instruction address a[3:1] 000 001 010 011 100 101 110 111 slot 0, 1 buf 0 buf 1 buf 2 buf 3 buf 4 buf 5 buf 6 buf 7 cpu aimed instr uction iqb pre-f etched instr uction figure ii.4.2.2.2 instructions in slot when iqb is disabled (iqb (d 0/0x301610 ) = 0 ), the cpu can only fetch the instruction or data from the sdram through the data queue buffer described below. ii.4.2.3 dqb (data queue buffer) the dqb consists of two-stage 16 -bit buffers and is mainly used to store data read from the sdram and to decrease the sdram read latency. provided two stages, defined as buffer 0 and buffer 1 , correspond to two-burst reading for the sdram. when iqb (d 0/0x301610 ) is set to 1 to enable iqb, dqb acts as a data buffer in which data in the program is stored. when iqb (d 0/0x301610 ) is set to 0 to disable iqb, dqb acts as a pure read buffer in which all data read from the sdram are stored without distinction between instructions and data. note that dqb cannot be disabled. table ii. 4.2.3.1 lists the dqb status corresponding to the bus operation for the sdram. table ii. 4.2.3.1 dqb status corresponding to bus operation bus operation cpu instr uction f etch cpu v ector f etch cpu data read cpu data wr ite cpu stac k read cpu stac k wr ite dma data read dma data wr ite when iqb is disabled activ e activ e activ e inactiv e activ e inactiv e activ e inactiv e when iqb is enabled inactiv e activ e activ e inactiv e activ e inactiv e activ e inactiv e dqb status (active or inactive) the sdram interface always reads two successive half-word data beginning with a 32 -bit boundary address in burst reading. therefore, 16 -bit data at a word-boundary address (a[1:0 ] is corrected to 00 ) is always stored in buffer 0 , and the next read data at the subsequent half-word boundary address (a[1:0 ] = 10 ) is always stored in buffer 1. if dqb contains the needed data when the cpu reads data from the sdram, no sdram read cycle is generated and data is read from dqb.
ii bus modules: sdram controller (sdramc) ii-4-20 epson s1c33e08 technical manual ii.4.2.4 operations using iqb/dqb reading sdram data in order to judge the iqb/dqb hit or iqb/dqb not hit, the sdramc application unit has an address register that holds the address in which data is buffered into iqb/dqb and an address comparator for comparing between the cpu read address and the address register. the address comparator compares the sdram address being accessed from the cpu with the address data in the address register, and issues hit if they are matched or not hit if they are not matched. after an initial reset, the iqb/dqb and address register statuses are reset as empty. therefore, the cpu's first fetching/reading of the sdram always causes not hit. in the case of not hit: the internal wait signal is output to the c 33 pe core and the bus cycle enters a wait state. the sdramc application unit reads data from the sdram through the sdram interface and stores it into iqb or dqb. when the buffer is ready to read, the internal wait signal is negated and the bus cycle reads the data from the iqb or dqb. in the case of hit: no sdram access is generated and the cpu can fetch or read the instruction or data from iqb or dqb with no wait state inserted. writing data to sdram when the cpu writes data to the sdram, the internal wait signal input to the c 33 pe core is asserted until the sdram interface has finished writing to the sdram. if data is written to the address in which data has buffered in iqb or dqb, the related buffer data is flushed.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.4.3 bus arbiter ii.4.3.1 overview the sdramc contains a bus arbiter. when the lcdc uses the external sdram as the vram, the cpu and lcdc may access the sdram simultaneously. similarly, an external bus access from the sramc may occur while the lcdc is accessing the sdram. the bus arbiter arbitrates the ownership of the external bus in such cases. the priority of the bus masters is ( 1 ) lcdc, (2 ) dma, (3 ) cpu, and (4 ) sramc. note, however, that the lcdc cannot interrupt a long dma transfer unless the dma sequential access time is set using dmaacctime[ 3:0 ] (d [3:0]/0x30119e). ? dmaacctime[3:0] : idma and hsdma sequential access time setup bits in the dma sequential access time register (d[3:0]/0x30119e) ii.4.3.2 controlling the bus arbiter at initial reset, the bus arbiter is disabled. in this case, sdram requests from the cpu and bus requests from the sramc will be accepted but the lcdc cannot request to access the sdram. the bus arbiter must be enabled before the lcdc can access the sdram. set arbon (d 31/0x301610) to 1 to enable the bus arbiter. ? arbon : arbiter enable bit in the sdram application configuration register (d31/0x301610) when no sdram access from the lcdc occurs, such as when the lcdc uses ivram only, the bus arbiter can be disabled by setting arbon (d 31/0x301610) to 0 to reduce current consumption.
ii bus modules: sdram controller (sdramc) ii-4-22 epson s1c33e08 technical manual ii.4.4 control register details table ii. 4.4.1 sdramc register list address 0x00301600 0x00301604 0x00301608 0x00301610 function enables sdramc and controls initialization. sets sdram size and timing parameters. controls refresh. controls sdapp module. register name sdram initial register (psdramc_ini) sdram configuration register (psdramc_ctl) sdram refresh register (psdramc_ref) sdram application configuration register (psdramc_app) siz e 32 32 32 32 the following describes each sdramc control register. the sdramc control registers are mapped to the 32 -bit device area at addresses 0x301600 to 0x301610 , and can be accessed in units of words, half-words or bytes.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301600: sdram initial register (psdramc_ini) name address register name bit function setting init. r/w remarks C C sdon sden inimrs inipre iniref d31C5 d4 d3 d2 d1 d0 reserved sdram controller enable sdram initialize flag mrs command enable for init. pall command enable for init. ref command enable for init. C 0 0 0 0 0 C r/w r r/w r/w r/w 0 when being read. 00301600 (w) 1 initialized 0 not initialized 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled sdram initial register (psdramc_ini) d[31:5] reserved d4 sdon: sdram controller enable bit this bit enable the sdram controller. 1 (r/w): enable 0 (r/w): disable (default) when sdon is set to 1 , the sdram controller activates and outputs the sdram clock from the sdclk pin. before setting sdon to 1 , the sdramc clocks must be supplied to the sdram controller. d3 sden: sdram initialize flag this bit indicates that the sdram has finished initialization (mode register set). 1 (r): initialized 0 (r): not initialized (default) sden is reset to 0 after power-on, and is set to 1 upon completion of the initialization sequence. make sure that sden is set to 1 before the sdram is accessed. d2 inimrs: mrs command enable for initialization bit this bit enables to output the mrs (mode register set) command for initialization sequence. 1 (r/w): enable 0 (r/w): disable (default) in order to initialize the sdram, the pall (precharge all), ref (auto refresh), and mrs (mode register set) commands must be executed sequentially. note that the initialization sequence depends on the sdram. refer to the specifications of the sdram to be used for the initialization sequence. example 1 : pall ref ref mrs ( emrs) example 2 : pall mrs ref ref ( ref ref ref ref ref ref) to execute the mrs/emrs (mode register set/extended mode register set) command, write 0x14 to this register (inimrs should be set to 1 ). then write any data to a specific address shown below according to the cas latency (mrs) or extended mode parameters (emrs). table ii. 4.4.2 data write address to execute the mrs/emrs command cpu address sdram address mrs cas latency = 1 cas latency = 2 cas latency = 3 emrs a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 1 0 0 0 0 0 0 0 0 see sdram specifications . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 ba1 mod e rese rv ed te st mode cas latency wb burst length bt mod e reser ve d ds p asr tcsr ba0 sd a12 sd a11 sd a10 sd a9 sd a8 sd a7 sd a6 sd a5 sd a4 sd a3 sd a2 sd a1 sd a0 for example, to execute an mrs command with 2 of cas latency specified, write data (any value) to address 0x10000442 (when the sdram is mapped to area 19 ) after writing 0x14 to the sdram initial register ( 0x301600). note : the cas latency specified in the mrs command must be the same as the cas[1:0] (d[3:2]/ 0x301610) set value. ? cas[1:0] : cas latency setup bits in the sdram application configuration register (d[3:2]/0x301610)
ii bus modules: sdram controller (sdramc) ii-4-24 epson s1c33e08 technical manual d1 inipre: pall command enable for initialization bit this bit enables to output the pall (precharge all) command for initialization sequence. 1 (r/w): enable 0 (r/w): disable (default) to execute the pall (precharge all) command, write 0x12 to this register (inipre should be set to 1). then write any data to any address in the sdram. this dummy write is required as the trigger to send the pall command. see inimrs (d 2) for initialization sequence. d0 iniref: ref command enable for initialization bit this bit enables to output the ref (auto refresh) command for i nitialization sequence. 1 (r/w): enable 0 (r/w): disable (default) to execute the ref (auto refresh) command, write 0x11 to this register (iniref should be set to 1). then write any data to any address in the sdram. this dummy write is required as the trigger to send the ref command. see inimrs (d2) for initialization sequence. when executing the ref command twice or more, insert the nop instruction between the executions. execute ref command execute nop execute ref command ( ref nop ref . . .) notes : ? the sdram timing parameters set in the sdram configuration register (0x301604) is not effective in this manual initialization sequence. therefore, enough number of nop instructions must be executed to satisfy the sdram timings. ? after the initial sequence commands are executed, the command enable bits must be set to 0. write 0x10 to the sdram initial register (0x301600) after the last initialization command has been executed. ? the self-refresh function must be disabled until the sdram has finished initialization.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301604: sdram configuration register (psdramc_ctl) name address register name bit function setting init. r/w remarks C t24ns[1:0] = 0 to 3 1 to 4 cycles C t60ns[2:0] = 0 to 7 1 to 8 cycles t80ns[3:0] = 0 to 15 1 to 16 cycles C C t24ns1 t24ns0 C t60ns2 t60ns1 t60ns0 t80ns3 t80ns2 t80ns1 t80ns0 C addrc2 addrc1 addrc0 d31C14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved number of sdram t rp and t rcd cycles reserved number of sdram t ras cycles number of sdram t rc , t rfc and t xsr cycles reserved sdram address configuration C 0 0 C 0 0 0 1 1 1 0 C 0 0 0 C r/w C r/w r/w C r/w 0 when being read. 0 when being read. 0 when being read. 00301604 (w) 111 110 101 100 011 010 001 000 addrc[2:0] configuration 32m x 16 bits x 1 16m x 8 bits x 2 8m x 8 bits x 2 2m x 8 bits x 2 16m x 16 bits x 1 8m x 16 bits x 1 4m x 16 bits x 1 1m x 16 bits x 1 sdram configuration register (psdramc_ctl) d[31:14] reserved d[13:12] t24ns[1:0]: number of sdram t rp and t rcd setup bits these bits set t rp and t rcd sdram timing parameters. ? t rp precharge to active command period ? t rcd active to read or write delay time table ii. 4.4.3 t r p and t rcd settings t24ns1 1 1 0 0 t24ns0 1 0 1 0 t rp , t rcd 4 cycles 3 cycles 2 cycles 1 cycle (default: 0b00 = 1 cycle) d11 reserved d[10:8] t60ns[2:0]: number of sdram t ras setup bits these bits set t ras sdram timing parameters. ? t ras active to precharge command period table ii. 4.4.4 t r as settings t60ns2 1 1 1 1 0 0 0 0 t60ns1 1 1 0 0 1 1 0 0 t ras 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle t60ns0 1 0 1 0 1 0 1 0 (default: 0b000 = 1 cycle)
ii bus modules: sdram controller (sdramc) ii-4-26 epson s1c33e08 technical manual d[7:4] t80ns[3:0]: number of sdram t rc , t rfc , and t xsr setup bits these bits set t rc , t rfc , and t xsr sdram timing parameters. ? t rc active to active command cycle time ? t rfc auto-refresh cycle time ? t xsr exit self refresh to active command period table ii. 4.4.5 t rc , t rfc and t xsr settings t80ns3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 t80ns2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 t rc , t rfc , t xsr 16 cycles 15 cycles 14 cycles 13 cycles 12 cycles 11 cycles 10 cycles 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle t80ns1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 t80ns0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b1110 = 15 cycles) d3 reserved d[2:0] addrc[2:0]: sdram address configuration bits these bits selects sdram size and chip configuration. this selection also sets up the bank size, column address size (page size), and row address size. table ii. 4.4.6 selecting sdram size sdram configuration 32m 16-bit 1 16m 8-bit 2 8m 8-bit 2 2m 8-bit 2 16m 16-bit 1 8m 16-bit 1 4m 16-bit 1 1m 16-bit 1 addrc2 1 1 1 1 0 0 0 0 addrc1 1 1 0 0 1 1 0 0 addrc0 1 0 1 0 1 0 1 0 bank 4 4 4 2 4 4 4 2 ro w 8k 4k 4k 2k 8k 4k 4k 2k column 1k 1k 512 512 512 512 256 256 memory siz e 64m b ytes 32m b ytes 16m b ytes 4m b ytes 32m b ytes 16m b ytes 8m b ytes 2m b ytes (default: 0b000 = 2m bytes)
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301608: sdram refresh register (psdramc_ref) name address register name bit function setting init. r/w remarks C 0x0 to 0x7f C seldo sckon selen selco6 selco5 selco4 selco3 selco2 selco1 selco0 C aurco11 aurco10 aurco9 aurco8 aurco7 aurco6 aurco5 aurco4 aurco3 aurco2 aurco1 aurco0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved sdram self-refresh status sdram clock during self-refresh sdram self-refresh enable sdram self-refresh counter reserved sdram auto-refresh counter C 0 0 0 1 1 1 1 1 1 1 C 0 0 0 0 1 0 0 0 1 1 0 0 C r r/w r/w r/w C r/w 0 when being read. 0 when being read. 00301608 (w) 1 refresh mode 0 done 1 enabled 0 disabled 1 enabled 0 disabled sdram refresh register (psdramc_ref) C 0x0 to 0xfff d[31:26] reserved d25 seldo: sdram self-refresh status bit this bit indicates the sdram self-refresh status. 1 (r): in self-refresh mode 0 (r): not in self-refresh mode (default) seldo is 1 while the sdramc holds the sdcke pin low (i.e., the sdram is in self-refresh mode). otherwise, seldo = 0. before entering sleep mode, always be sure to read this bit using a program stored elsewhere (i.e., not in the sdram) to confirm that the sdram is in self-refresh mode. d24 sckon: sdram clock enable during self-refresh bit this bit selects whether to stop the sdram clock during self-re fresh or not. 1 (r/w): enable (not stopped) 0 (r/w): disable (stopped) (default) writing 0 to sckon causes the sdram clock output from the sdclk pin to stop and to remain off while the sdram is self-refreshed. this helps to reduce the chip's current consumption. if sckon = 1 , the sdram clock is always output from the sdclk pin even while the sdram is self-refreshed. d23 selen: sdram self-refresh enable bit this bit enable the sdram's self-refresh control function. 1 (r/w): enable 0 (r/w): disable (default) writing 1 to selen enables the sdramc to start self-refreshing the sdram (by setting sdcke output low). note that self-refreshing of the sdram actually begins a certain time after accessing or auto-refreshing the sdram. the duration of this elapsed time is defined by the number of clock cycles in selco[6:0] (d[22:16]). selen = 0 disables the self-refresh function.
ii bus modules: sdram controller (sdramc) ii-4-28 epson s1c33e08 technical manual d[22:16] selco[6:0]: sdram self-refresh counter bits these bits are used to set the self-refresh counter value. (default: 0x7f) if selen (d 23 ) is set to 1 (self-refresh-enabled), the self-refresh counter starts counting up on the sdclk clock edges beginning with 0 after accessing or auto-refreshing the sdram. when the count specified here is reached, the sdcke output is pulled low, causing the sdram to start self-refreshing. if an access to the sdram occurs during self-refresh mode, sdcke is returned high, thereby taking the sdram out of self-refresh mode. d[15:12] reserved d[11:0] aurco[11:0]: sdram auto-refresh counter bits these bits are used to set the auto refresh counter value. (default: 0x8c) the auto-refresh counter counts up on the sdclk clock edges beginning with 0 , and when the count specified here is reached, the sdram controller sends an auto-refresh command. the counter is reset at that point, and starts counting the next refresh period. the counter is also reset by self-refresh. the value calculated from the equation below is the maximum count that can be set. rfp aurco CCCCCCCC f clk - bl - cl - 2 t rp - t rcd - 3 rows rfp: maximum refresh period [s] rows: row address size f clk : sdclk clock frequency [hz] bl: burst length (= 2) cl: cas latency t rp : precharge command period [number of cycles] t rcd : active to read or write delay time [number of cycles]
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301610: sdram application configuration register (psdramc_app) name address register name bit function setting init. r/w remarks C arbon C dbf incr cas1 cas0 appon iqb d31 d30C6 d5 d4 d3 d2 d1 d0 arbiter enable reserved double frequency mode enable incr transfer enable cas latency setup sdapp control instruction queue buffer enable 0 C 0 0 1 0 0 0 r/w C r/w r/w r/w r/w r/w 0 when being read. 00301610 (w) 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled sdram application configuration register (psdramc_app) 1 on 0 off 1 enabled 0 disabled cas[1:0] cas latency 3 2 1 reserved 11 10 01 00 d31 arbon: arbiter enable bit this bit enables the bus arbiter. 1 (r/w): enable 0 (r/w): disable (default) when arbon is set to 1 , the bus arbiter is enabled and can arbitrate the sdram access requests from the cpu, lcdc, and sramc. when arbon is set to 0 , the bus arbiter is disabled. in this case, the lcdc cannot access the sdram. d[30:6] reserved d5 dbf: double frequency mode enable bit this bit enables double frequency mode. 1 (r/w): enable 0 (r/w): disable (default) when dbf is set to 1 , the sdramc can use the sdram clock (90 mhz max.) two times faster than the cpu clock ( 45 mhz max.). set dbf to 0 when the sdramc clock frequency is the same as the cpu operating clock (60 mhz max.). d4 incr: incr transfer enable bit this bit enables incr transfer. when incr is set to 1 , the sdramc will enhance the speed of data reading from the sdram by the lcdc and idma. 1 (r/w): enable 0 (r/w): disable (default) d[3:2] cas[1:0]: cas latency setup bits these bits set cas latency. cas latency refers to the number of sdclk clocks until data is output from sdram after issuing the read command. table ii. 4.4.7 cas latency settings cas1 1 1 0 0 cas latenc y 3 2 1 reser ve d cas0 1 0 1 0 (default: 0b10 = 2) d1 appon: sdram application unit control bit this bit turns the sdram application unit on and off. 1 (r/w): on 0 (r/w): off (default) appon must be set to 1 when using the sdramc.
ii bus modules: sdram controller (sdramc) ii-4-30 epson s1c33e08 technical manual d0 iqb: instruction queue buffer enable bit this bit enables the iqb (instruction queue buffer). 1 (r/w): enable 0 (r/w): disable (default) setting iqb to 1 enables iqb and instructions stored in the sdram are pre-fetched into the iqb. the iqb acts as a high-speed instruction cache for the cpu. in this case, dqb is used as a data read buffer. when iqb is set to 0 , iqb is disabled and dqb is used as an instruction/data buffer.
ii bus modules: sdram controller (sdramc) s1c33e08 technical manual epson ii-4-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ii.4.5 precautions if the operating clock (sdclk) is stopped while the sdram is being accessed, a system failure may occur due to stoppage of the sdram operation in uncontrolled status. the following operations stop the sdclk, therefore, do not perform these operations when the sdram may be accessed. ? setting the s1c33e08 in sleep status ? switching the p21 port function from sdclk output to general-purpose input/output ? disabling the clock supply to the sdramc module besides the cpu, the dma controller (when dma transfer from/to the sdram is enabled) and the lcd controller (when sdram is configured as the vram for the lcdc) access the sdram. in this case, before performing an above operation, disable the dma transfer and the lcdc so that the sdram will not be accessed.
ii bus modules: sdram controller (sdramc) ii-4-32 epson s1c33e08 technical manual this page is blank.
i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual iii peripheral modules 1 (system)

iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1 clock management unit (cmu) iii.1.1 overview of the cmu the clock management unit (cmu) controls the operating clock supplied to each functional module. the main functions of the cmu are outlined below. ? controls reset and nmi inputs ? selects the system clock source (osc3, pll, or osc1) ? controls on/off of the osc3 and osc1 oscillator circuits ? controls on/off and frequency multiplication rate of the pll ? controls sscg ? clock control corresponding to standby modes (sleep and halt) ? selects divide ratio of the main system clock ? selects an external bus clock ? controls on/off of clock supply for each functional module through system clock selection, oscillator circuit, and pll control, and main system clock divide ratio selection and clock on/off control for each functional module, the cmu enables the most suitable operating clock frequency to be selected for the processing involved, as well as to turn off unnecessary clock supply, which combined with standby mode, helps to significantly reduce power consumption on the chip. osc/pll/ sscg control osc3 oscillator (48 mhz) divider (1/1C1/32) divider (1/1C1/10) osc1 oscillator (32.768 khz) reset/nmi control pll x1Cx16 (20C90 mhz) clock switch nmi reset cmu #nmi #reset mclki mclko osc3 pllin_div osc oscsel mclkdiv cmu_clksel 11 clocks sleep wakeup, etc. halt osc_w osc3_div pll osc1 mclk clock on/off control to peripheral modules clock on/off control in halt mode power down control to ahb bus and some peripheral modules clock on/off control to sdramc to c33 pe core clock on/off control to lcdc cmu_clk clock on/off control to usb to rtc rtc_clki rtc_clko divider (1/1C1/16) 1/2 sscg figure iii.1.1.1 cmu block diagram note : the cmu control registers at addresses 0x301b00C0x301b14 are write-protected. before the cmu control registers can be rewritten, write protection of these registers must be removed by writing data 0x96 to the clock control protect register (0x301b24). note that since unnecessary rewrites to addresses 0x301b00C0x301b14 could lead to erratic system operation, the clock control protect register (0x301b24) should be set to other than 0x96 unless said cmu control registers must be rewritten.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-2 epson s1c33e08 technical manual iii.1.2 reset input and initial reset the cmu also has a function to generate an internal reset signa l from external reset input (#reset). iii.1.2.1 initial reset pin the #reset pin is used for initial reset input from outside the ic. set the #reset pin to 0 (low) to reset the ic. the #reset input signal is sampled with the osc 3 clock. therefore, the chip cannot be reset when the osc3 clock is not input or generated. moreover, to assert the internal reset signal #reset = 0 must be continuously detected at least three times in this sampling. the #reset signal should be held low for at least three osc 3 clock cycles to confirm that the chip is reset. also the internal reset signal is negated when #reset = 1 (high) is continuously detected three times. the s 1c33e08 is reset by the low state (= 0 ) on the internal reset signal, and starts operating when the reset signal is released back to high (= 1). osc3 clock #reset internal reset signal 3 cycles 2 cycles or less 3 cycles reset state figure iii.1.2.1.1 #reset sampling iii.1.2.2 initial reset status the c 33 pe core and internal peripheral circuits are initialized while the internal reset signal is kept 0 . the following shows the internal reset status: cpu ttbr: initialized to 0xc00000 cpu pc: the reset vector at address 0xc00000 is loaded to the pc. cpu psr: all the psr bits are reset to 0. other cpu registers: undefined cpu operating clock: the cpu operates with the osc3 1/1 clock. oscillator circuit: both the high-speed (osc 3 ) and low-speed (osc1 ) oscillator circuits are turned on (pll and sscg are turned off). clock supply to peripheral modules: all clocks are enabled except for the usb, sdramc, and lcdc. i/o pin status: initialized (see section i.3.2, pin functions. ) other peripheral modules: initialized or undefined (see each i/o map.) note : the s1c33e08 does not support a hot reset feature that maintains i/o pin status and the ttbr value.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.2.3 power-on reset when turning on the power for the chip, always be sure to cold reset the chip to ensure that it will start operating normally. since the #reset pin is a gate input, a power-on reset circuit should be configured external to the chip. initial reset (#reset = 0 ) causes the high-speed (osc3 ) oscillator circuit to start oscillating, and when the reset signal is released back high, the cpu starts operating with the osc 3 clock. the high-speed (osc3 ) oscillator circuit requires a finite time until its oscillation stabilizes after it starts operating. to confirm that the cpu is started, the initial reset can only be deasserted after this oscillation stabilization time elapses. note : the oscillation start time of the high-speed (osc3) oscillator circuit varies with the device used, board patterns, and operating environment. therefore, sufficient time should be provided before the reset signal is deasserted. power-on sequence to ensure that the chip will operate normally, observe the timing requirements given below when turning on the power for the chip. i/o power voltage v ddh , av dd internal power voltage v dd , plv dd osc3 #reset v dd min. t vdd t sta3 t rst figure iii.1.2.3.1 power-on sequence (1) t vdd : the time until the power supply for the chip stabilizes after being turned on. turn on the power supplies in order of the following (or at the same time): internal core power supply (v dd , plv dd ) i/o power supply (v ddh , av dd ) input signal applied (2) t sta 3 : osc 3 oscillation start time (3) t rst : minimum reset pulse width make sure #reset is held low (= 0 ) for at least 3 clock cycles after the osc3 clock supplied to the cmu has stabilized.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-4 epson s1c33e08 technical manual iii.1.2.4 precautions to be taken during initial reset core cpu when initially reset, all internal registers of the core cpu (except psr) become unstable. therefore, these registers must be initialized in a program. in particular, the stack pointer (sp) should always be initialized before accessing the stack. note that nmi requests are masked in hardware until data is written to the sp after initial reset, to prevent erratic operation. internal ram the content of internal ram becomes unstable when initially reset. internal ram must be initialized as required. high-speed (osc3 ) oscillator circuit when initially reset, the high-speed (osc 3 ) oscillator circuit starts oscillating, and when the reset signal is deasserted, the cpu starts operating with the osc 3 clock. to prevent erratic operation due to an instable clock when the chip is reset at power-on or while the high-speed (osc 3 ) oscillator circuit is idle, the reset signal should not be deasserted until after oscillation stabilizes. low-speed (osc 1 ) oscillator circuit when the chip is reset at power-on or while the low-speed (osc 1 ) oscillator circuit is idle, the low-speed (osc1 ) oscillator circuit also starts oscillating. the low-speed (osc1 ) oscillator circuit requires a longer time for oscillation to stabilize than the high-speed (osc 3 ) oscillator circuit. (see the electrical characteristics table.) to prevent erratic operation due to an instable clock, the osc 1 clock should not be used until after this stabilization time elapses. input/output ports and input/output pins initial reset initializes the control and data registers of the input/output ports, therefore, be set up back again in a program. other internal peripheral circuits the control and data registers of other peripheral circuits are initialized or made unstable by initial reset. therefore, these registers should be set up as required in a program. for details on how peripheral circuits are initialized by initial reset, see each i/o map or circuit description.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.3 nmi input the external nmi signal is input from the #nmi pin to the cmu, then forwarded to the cpu. for details about nmi exception handling by the cpu, refer to the s 1c33 family c33 pe core manual. notes : ? at least a 3 -system clock width of low pulse is required to generate nmi. after the nmi signal falls, maintain it at a low level for 3 or more clock cycles. ? nmi cannot be nested. the cpu keeps nmi input masked out until the reti instruction is executed after an nmi exception occurred.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-6 epson s1c33e08 technical manual iii.1.4 selecting the system clock source the cmu has the following three clock inputs, one of which can be selected as the source clock (osc) for the system. 1 . osc3 clock this clock is generated by the osc 3 oscillator circuit or supplied from an external source through the mclki pin. for details about the osc 3 oscillator circuit, see section iii.1.5.1, osc3 oscillator circuit. 2 . osc1 clock this is the source clock ( 32.768 khz, typ.) for the real time clock (rtc). when high-speed operation is unnecessary, this low-speed clock may be used to operate the system, thus helping to reduce power consumption on the chip. for details about the osc 1 oscillator circuit, see section iii.1.5.3, osc1 oscillator circuit. 3 . pll clock this is the pll output clock through the sscg module. the pll multiplies the osc 3 divided clock frequency by a given value to generate a clock for high-speed operation. the frequency multiplication rate can be set to one from 1 to 16 , note, however, that it depends on the osc3 divided clock frequency (maximum output frequency is 90 mhz). for details about the pll, see section iii. 1.6, controlling the pll. the clock source can be selected as shown in table iii. 1.4.1 by using oscsel[1:0] (d[3:2]/0x301b08). ? oscsel[1:0] : osc clock select bits in the system clock control register (d[3:2]/0x301b08) table iii. 1.4.1 selection of the system clock source oscsel1 1 1 0 0 oscsel0 1 0 1 0 cloc k sour ce pll osc3 osc1 osc3 (default: 0b00 = osc3) the clock source changed here is not reflected until after the cpu returns from sleep mode. therefore, the slp instruction must be executed once after setting oscsel[ 1:0 ] (d[3:2]/0x301b08 ). although the cpu returns from sleep mode to normal operation by an external interrupt from a port, for example, several functions are provided for use in clock source changes, thus automatically returning the cpu from sleep mode a certain time after slp instruction execution or leaving the osc 3 oscillator circuit turned on during sleep mode. section iii. 1 . 11 , standby modes, describes these methods of control in detail. note : when clock sources are changed, the cmu control registers must be set so that the cmu is supplied with a clock from the selected clock source upon returning from sleep mode immediately after the change. otherwise, the chip does not restart after the return from sleep mode.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.5 controlling the oscillator circuit iii.1.5.1 osc3 oscillator circuit the osc 3 oscillator circuit generates the main clock with which to operate the c 33 pe core and internal peripheral circuits. input/output pins of the osc3 oscillator circuit table iii. 1.5.1.1 lists the input/output pins of the osc3 oscillator circuit. table iii. 1.5.1.1 input/output pins of the osc3 oscillator circuit pin name mclki mclk o i/o i o function osc3 oscillator input pin: cr ystal/ceramic oscillator or e xter nal cloc k input osc3 oscillator output pin: cr ystal/ceramic oscillator (left open when using e xter nal cloc k input) structure of the oscillator circuit the osc 3 oscillator circuit accommodates a crystal/ceramic oscillator and external clock input. the core voltage v dd supplies power for this circuit. figure iii. 1.5.1.1 shows the structure of the osc3 oscillator circuit. oscillation circuit control signal sleep control oscillation circuit control signal sleep control v ss mclko mclki c d3 c g3 x'tal3 or ceramic osc3 mclko mclki external clock n.c. v ss v dd osc3 (1) crystal/ceramic oscillation circuit (2) external clock input r f r d figure iii.1.5.1.1 osc3 oscillator circuit for use as a crystal or ceramic oscillator circuit, connect a crystal (x tal3 ) or ceramic resonator and a feedback resistor (r f ), two capacitors (c g3 , c d3 ) and, if necessary, a drain resistor (r d ) to the mclki and mclko pins and v ss . to use an external clock, leave the mclko pin open and input a v dd -level clock (with a 50 % duty cycle) to the mclki pin. the range of oscillation frequencies is as follows: ? crystal oscillator: 5 mhz (min.) to 48 mhz (max.) ? ceramic oscillator: 48 mhz fixed ? external clock input: 5 mhz (min.) to 48 mhz (max.) ? a 48 mhz clock source with 0.25 % of accuracy should be connected for using the usb function. for details of oscillation characteristics and external clock input characteristics, see electrical characteristics. oscillation control cmu register control bit sosc 3 (d1/0x301b08) is used to control osc3 oscillation. ? sosc3 : high-speed oscillation (osc3) on/off control bit in the system clock control register (d1/0x301b08) setting this control bit to 0 causes the osc3 oscillator circuit to stop; setting it to 1 causes the osc3 oscillator circuit to start oscillating, thereby outputting a clock signal waveform. when initially reset, this bit is set to 1 for enabling osc3 oscillation. note : when the oscillator is made to start oscillating by setting sosc3 (d1/0x301b08) from 0 to 1, a finite time is required until oscillation stabilizes (see electrical characteristics). to prevent system malfunction, do not use the oscillator-derived clock until this oscillation stabilization time elapses.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-8 epson s1c33e08 technical manual iii.1.5.2 setting the osc3 divider an osc 3 divided clock can be used as the system clock when osc3 is selected as the system clock source. setting the system clock to the lowest frequency possible according to the processing can reduce current consumption. the osc 3 divider generates six kinds of clocks from osc3?1/1 to osc3?1/32 . select a divided clock from those six clocks using osc3div[2:0] (d[10:8]/0x301b08). ? osc3div[2:0] : osc3 clock divider select bits in the system clock control register (d[10:8]/0x301b08) table iii. 1.5.2.1 selecting an osc3 divided clock osc3div2 1 1 1 1 0 0 0 0 osc3div1 1 1 0 0 1 1 0 0 cmu_clk osc3?1/1 osc3?1/1 osc3?1/32 osc3?1/16 osc3?1/8 osc3?1/4 osc3?1/2 osc3?1/1 osc3div0 1 0 1 0 1 0 1 0 (default: 0b000 = osc3?1/1) a divided clock can be selected at any time. however, up to 32 osc3 clock cycles are required before the clocks are actually changed after altering the register values. iii.1.5.3 osc1 oscillator circuit the s 1c33e08 contains an oscillator circuit (osc1 ) used to generate a 32.768 khz (typ.) clock as the clock source for timekeeping operation of the rtc. the osc1 clock can also be used as a power-saving operating clock for the core system or peripheral circuits. input/output pins of the osc1 oscillator circuit table iii. 1.5.3.1 lists the input/output pins of the osc1 oscillator circuit. table iii. 1.5.3.1 input/output pins of the low-speed (osc1) oscillator circuit pin name r tc_clki r tc_clk o i/o i o function osc1 input pin: cr ystal oscillator or e xter nal cloc k input osc1 output pin: cr ystal oscillator output (left open when e xter nal cloc k is input) structure of the osc1 oscillator circuit the osc 1 oscillator circuit accommodates a crystal oscillator and external clock input. the core voltage v dd supplies power for this circuit. figure iii. 1.5.3.1 shows the structure of the osc1 oscillator circuit. low level oscillation circuit control signal oscillation circuit control signal osc1 rtc_clko rtc_clki external clock n.c. v ss v dd osc1 (1) crystal oscillation circuit v ss rtc_clko rtc_clki oscillation circuit control signal (3) when not used (2) external clock input v ss rtc_clko rtc_clki c d1 c g1 x'tal1 r f r d figure iii.1.5.3.1 osc1 oscillator circuit
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 for use as a crystal oscillator circuit, connect a crystal resonator x tal 1 ( 32 . 768 khz, typ.), feedback resistor (r f ), two capacitors (c g1 , c d1 ), and, if necessary, a drain resistor (r d ) to the rtc_clki and rtc_clko pins and v ss , as shown in figure iii. 1.5.3.1 (1). to use an external clock, leave the rtc_clko pin open and input a v dd level clock (whose duty cycle is 50 %) to the rtc_clki pin. do not input v ddh or other i/o level clocks. the oscillator frequency/input clock frequency is 32.768 khz (typ.). make sure the crystal resonator or external clock used in the rtc has this clock frequency. with any other clock frequencies, the rtc cannot be used for timekeeping purposes. for details of oscillation characteristics and the input characteristics of external clock, see electrical characteristics. when not using the osc 1 oscillator circuit, connect the rtc_clki pin to v ss and leave the rtc_clko pin open. oscillation control internal control bit sosc 1 (d0/0x301b08 ) of the cmu register is used to control osc1 oscillation. ? sosc1 : low-speed oscillation (osc1) on/off control bit in the system clock control register (d0/0x301b08) setting this control bit to 0 causes the osc1 oscillator circuit to stop; setting it to 1 causes the osc1 oscillator circuit to start oscillating, thereby outputting a clock signal waveform. when initially reset, this bit is set to 1, so that the osc1 oscillator circuit continues oscillating. note : when the oscillator is made to start oscillating by setting sosc1 (d0/0x301b08) from 0 to 1, a finite time (of up to 3 seconds) is required until oscillation stabilizes. to prevent system malfunction, do not use the oscillator-derived clock until this oscillation stabilization time elapses.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-10 epson s1c33e08 technical manual iii.1.6 controlling the pll the pll multiplies the osc 3 clock frequency by a given value to generate a source clock for high-speed operation. iii.1.6.1 on/off control of the pll pllpowr (d 0/0x301b0 c) can be used to turn the pll on or off. ? pllpowr : pll on/off control bit in the pll control register (d0/0x301b0c) setting pllpowr (d 0/0x301b0 c) to 1 initiates pll operation. when initially reset, pllpowr (d0/0x301b0c) is set to 0 (power-down mode), with the pll turned off. note : immediately after the pll is started by setting pllpowr (d0/0x301b0c) to 1, an output clock stabilization wait time is required (e.g., 200 s in the s1c33e08). when the clock source for the system is switched over to the pll, allow for this wait time after the pll has turned on. iii.1.6.2 selecting the pll input clock the pll input clock can be selected from among 10 kinds of osc3 divided clocks, osc3?1/1 to osc3?1/10, using pllindiv[3:0] (d[23:20]/0x301b08). ? pllindiv[3:0] : pll input clock source divider select bits in the system clock control register (d[23:20]/0x301b08) table iii. 1.6.2.1 selecting the pll input clock pllindiv3 1 1 0 0 0 0 0 0 0 0 pllindiv2 0 0 1 1 1 1 0 0 0 0 pll input c loc k osc3?1/10 osc3?1/9 osc3?1/8 osc3?1/7 osc3?1/6 osc3?1/5 osc3?1/4 osc3?1/3 osc3?1/2 osc3?1/1 osc3?1/8 pllindiv1 0 0 1 1 0 0 1 1 0 0 pllindiv0 1 0 1 0 1 0 1 0 1 0 other (default: 0b0111 = osc3?1/8) notes : ? the pll input clock can only be selected when the pll is turned off (pllpowr (d0/ 0x301b0 c) = 0 ) and the clock source is other than the pll (oscsel[1:0 ] (d[3:2]/0x301b08) = 0C2 ). if the pll input clock is changed while the system is operating with the pll clock, the system may operate erratically. ? for the range of the input clock frequency, see electrical characteristics.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.6.3 setting the frequency multiplication rate the pll frequency multiplication rate can be specified as shown in table iii. 1.6.3.1 by using plln[3:0 ] (d[7:4]/ 0x301b0c). ? plln[3:0] : pll multiplication rate setup bits in the pll control register (d[7:4]/0x301b0c) table iii. 1.6.3.1 pll frequency multiplication rates plln3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 plln2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 multiplication rate x16 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 plln1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 plln0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0000 = x1) pll output clock frequency = pll input clock frequency multiplication rate notes : ? the frequency multiplication rate must be set so that the pll output clock frequency does not exceed the upper-limit operating clock frequency. for the multiplication rates that can be set and the range of the output clock frequency, see electrical characteristics. ? the frequency multiplication rate can only be set when the pll is turned off (pllpowr (d0/ 0x301b0 c) = 0 ) and the clock source is other than the pll (oscsel[1:0 ] (d[3:2]/0x301b08) = 0C2 ). if the frequency multiplication rate is changed while the system is operating with the pll clock, the system may operate erratically.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-12 epson s1c33e08 technical manual iii.1.6.4 other pll settings v-divider to ensure that frequency f vco obtained by falls within the range of 100 to 400 mhz, set the proper w value by using pllv[ 1:0 ] (d[3:2]/0x301b0 c). lower value is better for low power consumption. ? pllv[1:0] : pll v-divider setup bits in the pll control register (d[3:2]/0x301b0c) table iii. 1.6.4.1 settings of the w value pll v1 1 1 0 0 pll v0 1 0 1 0 w 8 4 2 not allo we d (default: 0b01 = 2) vco kv constant (vc value) according to the range of f vco frequencies obtained by , set the vco kv circuit constant (vc value) by using pllvc[ 3:0] (d[15:12]/0x301b0c). ? pllvc[3:0] : pll vco kv setup bits in the pll control register (d[15:12]/0x301b0c) table iii. 1.6.4.2 settings of the vc value pll vc3 1 0 0 0 0 0 0 0 other pll vc2 0 1 1 1 1 0 0 0 f vco [mhz] 360 < f vco 400 320 < f vco 360 280 < f vco 320 240 < f vco 280 200 < f vco 240 160 < f vco 200 120 < f vco 160 100 f vco 120 not allowed pll vc1 0 1 1 0 0 1 1 0 pll vc0 0 1 0 1 0 1 0 1 (default: 0b0001) lpf resistance value (rs value) according to the input clock frequency, set the lpf resistance value (rs value) of the pll by using pllrs[3:0] (d[11:8]/0x301b0c). ? pllrs[3:0] : pll lpf resistance setup bits in the pll control register (d[11:8]/0x301b0c) table iii. 1.6.4.3 settings of the rs value pllrs3 1 1 other pllrs2 0 0 f refck [mhz] 5 f refck < 20 20 f refck 150 not allowed pllrs1 1 0 pllrs0 0 0 (default: 0b1000) lpf capacitance value (cs value) bits to set the lpf capacitance value (cs value) is provided in the cmu control registers, pllcs[ 1:0 ]/ (d[23:22]/0x301b0 c). however, do not alter the value of these bits, and leave them as initially set (0b00). ? pllcs[1:0] : pll lpf capacitance setup bits in the pll control register (d[23:22]/0x301b0c) charge pump current value (cp value) bits to set the charge pump current value (cp value) is provided in the cmu control registers, pllcp[ 4:0]/ (d[20:16]/0x301b0 c). however, do not alter the value of these bits, and leave them as initially set (0b10000). ? pllcp[4:0] : pll charge pump current setup bits in the pll control register (d[20:16]/0x301b0c)
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table iii. 1.6.4.4 example pll settings pll input c loc k 6 mhz 10 mhz 20 mhz 45 mhz pll output c loc k 90 mhz 60 mhz 80 mhz 40 mhz 80 mhz 40 mhz 90 mhz plln[3:0] x15, 0b1110 x10, 0b1001 x8, 0b0111 x4, 0b0011 x4, 0b0011 x2, 0b0001 x2, 0b0001 pll v[1:0] 0b01 0b01 0b01 0b10 0b01 0b10 0b01 pll vc[3:0] 0b0011 0b0001 0b0010 0b0010 0b0010 0b0010 0b0011 pllrs[3:0] 0b1010 0b1010 0b1010 0b1010 0b1000 0b1000 0b1000 note : the pll can only be set up when the pll is turned off (pllpowr (d0/0x301b0c) = 0) and the clock source is other than the pll (oscsel[1:0] (d[3:2]/0x301b08) = 0C2). if settings are changed while the system is operating with the pll clock, the system may operate erratically. iii.1.6.5 power supply for pll the power for pll is supplied from the plv dd and plv ss pins (separately from the core power supply) to prevent the effects of noise. make sure that the following voltages are supplied to the respective pins. plv dd pin: supply v dd level voltage. plv ss pin: connect to v ss level. for pin assignments, see section i. 3, pin description.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-14 epson s1c33e08 technical manual iii.1.7 control of the sscg the spread spectrum clock generator (sscg) is a circuit used to reduce electromagnetic interference (emi) noise by spreading the spectrum (or performing ss modulation) for the pll output clock signal. the ss modulation is effective for all operating clocks for the core and peripheral circuits (except the rtc that uses the osc 1 clock) when the pll output clock has been selected as the system clock source and only this case has the effect of reducing noise. note : when the osc3 or osc1 clock is selected as the system clock source, ss modulation is not performed for the operating clock (system clock). ? about spectrum spread (ss modulation) the sscg performs ss modulation by adjusting the width of the high section of the input clock. this adjustment is made by increasing or reducing the set value of the internal delay adjust circuit of the sscg. the maximum width within which the set value is changed constitutes the maximum frequency change width. the relevant control register is used to set the upper-limit value of this width. in the sscg, an interval timer adjusts the interval at which the set value changes. the relevant control register is also used to set this interval (frequency change cycle). 0 input clock cycle maximum frequency change width + C f requency change cycle figure iii.1.7.1 ss modulation iii.1.7.1 turning the sscg on/off the sscg can be turned on or off by using ssmcon (d 0/0x301b10). ? ssmcon : sscg macro on/off control bit in the sscg macro control register (d0/0x301b10) setting ssmcon (d 0/0x301b10 ) to 1 causes the sscg to start operating. when initially reset, ssmcon (d0/ 0x301b10) is initialized to 0 , with the sscg turned off (bypassed). notes : ? a stabilized clock must be supplied to the sscg module when turning the sscg on and off. the following shows the operation procedure. to turn the sscg on 1 . turn the pll on. 2 . wait more than the pll stabilization time. 3 . turn the sscg on. to turn the sscg off 1 . turn the sscg off. 2 . turn the pll off. ? the ss modulation is effective only for the pll output clock, and is not performed for other source clocks. when the pll output clock is not used for the system clock, turn the sscg off.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.7.2 setting ss modulation parameters as described in about spectrum spread (ss modulation) above, it is necessary to set the upper-limit value of the maximum frequency change width and the frequency change cycle. the maximum frequency change width should be set to the appropriate value according to the pll output clock frequency as shown in table iii. 1.7.2.1 using ssmcidt[3:0 ] (d[11:8 ]/0x301b10 ). the maximum frequency change width will be about 2 % of the pll output clock by setting the appropriate value. ? ssmcidt[3:0] : sscg macro maximum frequency change width setting bits in the sscg macro control register (d[11:8]/0x301b10) table iii. 1.7.2.1 maximum frequency change width settings ssmcidt2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ssmcidt1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 pll output c loc k frequency f [mhz] f 19.8 19.8 < f 21.2 21.2 < f 22.5 22.5 < f 24.2 24.2 < f 25.9 25.9 < f 28.4 28.4 < f 30.8 30.8 < f 34.2 34.2 < f 37.8 37.8 < f 43.1 43.1 < f 48.9 48.9 < f 58.5 58.5 < f 69.7 69.7 < f 90.0 C C ssmcidt3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 ssmcidt0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0000) ssmcitm[3:0] (d[15:12]/0x301b10 ) is used to set the frequency change cycle. however, always set it to 0b0001. ? ssmcitm[3:0] : sscg macro interval timer setting bits in the sscg macro control register (d[15:12]/0x301b10) notes : ? ssmcidt[3:0 ] (d[11:8]/0x301b10 ) must be set according to the pll output clock frequency as shown in table iii. 1 . 7 . 2 . 1 . using the sscg with an improper setting may cause a malfunction of the ic. ? when the pll is off, the initial values and the written values cannot be read correctly from ssmcidt[3:0 ] (d[11:8]/0x301b10 ) and ssmcitm[3:0 ] (d[15:12]/0x301b10 ) since the source clock is not supplied from the pll (different values are read out). the correct values can be read out when the pll is on.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-16 epson s1c33e08 technical manual iii.1.8 setting the main system clock (mclk) mclk is the main system clock for the c33 pe core and internal modules. the source clock osc for the system (selected by oscsel[ 1:0 ] (d[3:2]/0x301b08 )) is divided by 1 or 2 by a clock frequency divider, generating two kinds of clocks. select mclk from those two clocks using mclkdiv (d12/0x301b08). ? mclkdiv : mclk clock divider select bit in the system clock control register (d12/0x301b08) table iii. 1.8.1 selecting mclk mclkdiv 1 0 mclk osc?1/2 osc?1/1 (default: 0 = osc?1/1) when using the sdramc in double frequency mode (mclk : sdram clock = 1 : 2 ), mclk should be set to osc?1/2 (osc is used for the sdram clock). mclk can be selected at any time. however, up to 2 clock cycles are required before the clocks are actually changed after altering the register values.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.9 controlling clock supply to reduce power consumption on the chip, a function is provided to turn off clock supply independently for each functional module. iii.1.9.1 mclk clock supply to each module table iii. 1.9.1.1 lists the register bits used for on/off control of mclk clock supply to the internal modules. the modules listed here have one controllable clock path, so they can be turned on/off using the corresponding control bit only. see sections iii. 1.9.3 to iii.1.9.9 for controlling the lcdc, sdramc, sramc, gpio, efsio, usb, and rtc clocks. table iii. 1.9.1.1 mclk clock supply control bits module dst ram (area 3 ram) 16-bit timer 5 16-bit timer 4 16-bit timer 3 16-bit timer 2 16-bit timer 1 16-bit timer 0 extended gpio i 2 s dcsio watchdog timer spi card a/d converter itc dmac contr ol bit dstram_cke (d3) tm5_cke (d18) tm4_cke (d17) tm3_cke (d16) tm2_cke (d15) tm1_cke (d14) tm0_cke (d13) egpio_cke (d12) i2s_cke (d11) dcsio_cke (d10) wdt_cke (d9) spi_cke (d6) card_cke (d4) adc_cke (d3) itc_cke (d2) dma_cke (d1) contr ol register gated clock control register 0 (0x301b00) gated clock control register 1 (0x301b04) when initially reset, these control bits are set to 1 (on), with clocks supplied to each module. if any module is unused, set the corresponding control bit to 0 , thus turning the clock for that module off. notes : ? these clocks do not stop in halt mode. to stop supplying the clock in halt mode, the control bit should be set to 0 before executing the halt instruction. all these clocks stop in sleep mode. ? the clock supply to any module can only be stopped when the module is not operating or unused. if clock supply to any module is stopped when the module is being operated or used, the chip may hang. iii.1.9.2 automatic clock control in halt mode the clocks for the functions listed in table iii. 1.9.2.1 can be automatically stopped in halt mode by setting the control bits. table iii. 1.9.2.1 clock supply control bits to disable in halt mode function sdramc cpu_ahb bus i/f cpu_ahb bus control lcdc_ahb bus control gpio input/interrupt control sramc efsio baud rate timer misc registers contr ol bit sdapcpu_hcke (d7) cpuahb_hcke (d29) lcdcahb_hcke (d28) gpionstp_hcke (d27) sramc_hcke (d26) efsiobr_hcke (d25) misc_hcke (d24) contr ol register gated clock control register 0 (0x301b00) gated clock control register 1 (0x301b04) when initially reset, these control bits are set to 1 (on) to enable clock supply in halt mode. if any clock is unused in halt mode, set the corresponding control bit to 0 (off). the clock supply stops when the cpu enters halt mode. note : all these clocks stop in sleep mode regardless how these control bits are set.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-18 epson s1c33e08 technical manual iii.1.9.3 clock supply to the lcdc the cmu provides the clock paths with a control bit shown below for the lcdc. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) lcdc ahb bus interface clock (lcdc_ahbif_clk) the lcdc uses this clock (mclk) to access ivram (internal vram) or an sdram (external vram). this clock is required for displaying a screen on the lcd panel. lcdcahbif_cke (d 2/0x301b00 ) is used for clock supply control (default: off). ? lcdcahbif_cke : lcdc ahb bus interface clock control bit in the gated clock control register 0 (d2/0x301b00) (2 ) control register clock (lcdc_sapb_clk) this clock (mclk) is used to control the lcdc registers located in area 6 . this clock is required for accessing the lcdc registers and it can be stopped when not in use. lcdcsapb_cke (d 1/0x301b00 ) is used for clock supply control (default: off). ? lcdcsapb_cke : lcdc sapb bus interface clock control bit in the gated clock control register 0 (d1/0x301b00) (3 ) ivram arbiter clock (ivram_arb_clk) this clock (mclk) is used when the lcdc or cpu accesses ivram. when ivram is configured as a0 ram accessed by the cpu only, the clock supply can be stopped. ivramarb_cke (d19/0x301b04 ) is used for clock supply control (default: on). ? ivramarb_cke : ivram arbiter clock control bit in the gated clock control register 1 (d19/0x301b04) (4 ) lcd interface clock (lcdc_clk) this is the lcd interface clock (lcdc_clk) generated by dividing the osc 3 clock. the frequency divider generates 16 kinds of clocks from osc3?1/1 to osc3?1/16 . select a divided clock according to the frame rate using lcdcdiv[3:0] (d[19:16]/0x301b08). f lcdc frame rate = [hz] ht vt f lcdc : lcdc_clk frequency ht: horizontal total period (including non-display period) [pixels] vt: vertical total period (including non-display period) [pixels] ? lcdcdiv[3:0] : lcdc clock divider select bits in the system clock control register (d[19:16]/0x301b08) table iii. 1.9.3.1 selecting the lcdc clock lcdcdiv3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 lcdcdiv2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 lcdc_clk osc3?1/16 osc3?1/15 osc3?1/14 osc3?1/13 osc3?1/12 osc3?1/11 osc3?1/10 osc3?1/9 osc3?1/8 osc3?1/7 osc3?1/6 osc3?1/5 osc3?1/4 osc3?1/3 osc3?1/2 osc3?1/1 lcdcdiv1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 lcdcdiv0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0111 = osc3?1/8)
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 lcdc_cke (d 0/0x301b00 ) is used for clock supply control (default: off). ? lcdc_cke : lcdc main clock control bit in the gated clock control register 0 (d0/0x301b00) note : make sure that the lcd interface clock supply is stopped (lcdc_cke (d0/0x301b00) = 0) when changing the clock divide ratio using lcdcdiv[3:0] (d[19:16]/0x301b08). (5 ) lcdc_ahb bus clock (lcdc_ahbbus_clk) the lcdc_ahb bus clock (mclk) is always supplied in normal operation. however, it can be automatically turned off in halt mode (see section iii. 1.9.2 ) by setting lcdcahb_hcke (d28/0x301b04 ) to 0 (default: on). ? lcdcahb_hcke : lcdc_ahb bus clock control (halt) bit in the gated clock control register 1 (d28/0x301b04) note : the lcdc clock supply cannot be stopped while the lcd displays a screen. before the lcdc clock supply can be stopped, the lcdc must enter power save mode. iii.1.9.4 clock supply to the sdramc the cmu provides the clock paths with a control bit shown below for the sdramc. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) sdramc ahb bus interface clocks (sdapp_cpu_clk, sdapp_lcdc_clk) the sdramc uses these clocks (mclk) for the cpu_ahb bus and lcdc_ahb bus interface. these clocks are required for accessing sdram and queue buffers. sdapcpu_cke (d 6 / 0 x 301 b 00 ) and sdaplcdc_cke (d 5/0x301b00 ) are respectively used for clock supply control (default: off). ? sdapcpu_cke : sdramc cpu app clock control bit in the gated clock control register 0 (d6/0x301b00) ? sdaplcdc_cke : sdramc lcdc app clock control bit in the gated clock control register 0 (d5/0x301b00) furthermore, the cpu_ahb bus clock (sdapp_cpu_clk) can be automatically turned off in halt mode (see section iii.1.9.2 ) by setting sdapcpu_hcke (d7/0x301b00) to 0 (default: off). ? sdapcpu_hcke : sdramc cpu app clock control (halt) bit in the gated clock control register 0 (d7/0x301b00) (2 ) control register clock (sdsapb_clk) this clock (mclk) is used to control the sdramc registers located in area 6 . this clock is required for accessing the sdramc registers and it can be stopped when not in use. sdsapb_cke (d 4/0x301b00 ) is used for clock supply control (default: off). ? sdsapb_cke : sdramc sapb bus interface clock control bit in the gated clock control register 0 (d4/0x301b00) (3 ) sdram clock (sdip_clk) this clock (osc_w) is used in the sdram interface. by setting mclk to osc ?1/2 (= osc_w?1/2 ), the sdram bus can be driven in double frequency mode (sdram: 90 mhz max., cpu: 45 mhz). sdapcpu_cke (d 6/0x301b00 ) or sdaplcdc_cke (d5/0x301b00 ) shown in (1 ) above is used for clock supply control (default: off). iii.1.9.5 clock supply to the sramc the cmu provides the clock paths with a control bit shown below for the sramc. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) sramc clock (sramc_clk) the sramc controls the sapb bus and external bus, so the sramc clock (mclk) cannot be stopped while the ic is running. however, the sramc clock can be automatically turned off in halt mode (see section iii.1.9.2) by setting sramc_hcke (d26/0x301b04) to 0 (default: on). ? sramc_hcke : sramc clock control (halt) bit in the gated clock control register 1 (d26/0x301b04)
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-20 epson s1c33e08 technical manual (2 ) control register clock (sramsapb_clk) this clock (mclk) is used to control the sramc registers located in area 6 . this clock is required for accessing the sramc registers and it can be stopped when not in use. sramsapb_cke (d 7/0x301b04 ) is used for clock supply control (default: on). ? sramsapb_cke : sramc sapb bus interface clock control bit in the gated clock control register 1 (d7/0x301b04) iii.1.9.6 clock supply to the gpio the cmu provides the clock paths with a control bit shown below for the gpio. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) gpio clock (port_clk) this clock (mclk) is used for the gpio circuit and is required for accessing the gpio control registers. gpio_cke (d8/0x301b04 ) is used for clock supply control (default: on). ? gpio_cke : gpio normal clock control bit in the gated clock control register 1 (d8/0x301b04) (2 ) gpio no stop clock (port_nostop_clk) this clock (mclk) is used for reading input ports and generating input interrupts. this clock can be automatically turned off in halt mode (see section iii. 1.9.2 ) by setting gpionstp_hcke (d27/0x301b04) to 0 (default: on). ? gpionstp_hcke : gpio no stop clock control (halt) bit in the gated clock control register 1 (d27/0x301b04) note, however, that the gpio no stop clock is required in halt mode when using an input interrupt to cancel halt mode. iii.1.9.7 clock supply to the efsio the cmu provides the clock paths with a control bit shown below for the efsio. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) control register clock (efsiosapb_clk) this clock (mclk) is used to control the efsio registers located in area 6 . this clock is required for accessing the efsio registers and it can be stopped when not in use. efsiosapb_cke (d 5 / 0 x 301 b 04 ) is used for clock supply control (default: on). ? efsiosapb_cke : efsio sapb bus interface clock control bit in the gated clock control register 1 (d5/0x301b04) (2 ) efsio baud rate timer clock (efsio_baudrate_clk) this clock (mclk) is used as the source clock for the baud rate timer in efsio. this clock can be automatically turned off in halt mode (see section iii. 1. 9. 2 ) by setting efsiobr_hcke (d25 /0x 301 b04 ) to 0 (default: on). ? efsiobr_hcke : efsio baud rate clock control (halt) bit in the gated clock control register 1 (d25/0x301b04) iii.1.9.8 clock supply to the usb the cmu provides the clock paths with the control bit shown below for the usb module. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) usb clock (usb_clk) this clock (osc 3 = 48 mhz) is used for the usb interface module. usb_cke (d8/0x301b00 ) is used for clock supply control (default: off). ? usb_cke : usb ip 48 mhz clock control bit in the gated clock control register 0 (d8/0x301b00)
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 (2 ) control register clock (usbsapb_clk) this clock (mclk) is used to control the usb registers located in area 6 . this clock is required for accessing the usb registers and it can be stopped when not in use. usbsapb_cke (d 9/0x301b00 ) is used for clock supply control (default: off). ? usbsapb_cke : usb sapb bus interface clock control bit in the gated clock control register 0 (d9/0x301b00) iii.1.9.9 clock supply to the rtc the cmu provides the clock paths with a control bit shown below for the rtc. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1) 32.768 khz clock (osc1) this clock (osc 1 = 32.768 khz) is used for timekeeping operations of the rtc. the clock supply can be stopped only when the rtc is not used and the osc 1 clock is not used as the system clock. to stop the osc1 clock, turn the osc1 oscillator circuit off by setting sosc1 (d0/0x301b08) to 0 (default: on). ? sosc1 : low-speed oscillation (osc1) on/off control bit in the system clock control register (d0/0x301b08) (2 ) control register clock (rtcsapb_clk) this clock (mclk) is used to control the rtc registers located in area 6 . this clock is required for accessing the rtc registers and it can be stopped when not in use. rtcsapb_cke (d 0/0x301b04 ) is used for clock supply control (default: on). ? rtcsapb_cke : rtc sapb bus interface clock control bit in the gated clock control register 1 (d0/0x301b04)
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-22 epson s1c33e08 technical manual iii.1.10 setting the external clock output (cmu_clk) cmu_clk is an external output clock for the external devices. cmu_clk can be selected from 11 clocks using cmu_clksel[4:0] (d[28:24]/0x301b08). ? cmu_clksel[4:0] : cmu_clk output clock source select bits in the system clock control register (d[28:24]/0x301b08) table iii. 1.10.1 selecting cmu_clk cmu_clksel3 1 1 1 0 0 0 0 0 0 0 0 cmu_clksel2 0 0 0 1 1 1 1 0 0 0 0 cmu_clk osc3_div?1/32 osc3_div?1/16 osc3_div?1/8 osc3_div?1/4 osc3_div?1/2 osc3_div?1/1 lcdc_clk mclk pll osc1 osc3 reser ve d cmu_clksel4 0 0 0 0 0 0 0 0 0 0 0 other cmu_clksel1 1 0 0 1 1 0 0 1 1 0 0 cmu_clksel0 0 1 0 1 0 1 0 1 0 1 0 (default: 0b00000 = osc3) cmu_clk can be selected at any time. however, switching over the clocks creates hazards. when cmu_clk must be output to external devices, it is also necessary to select a port function. for details on how to control clock output and the port to be used, see section i. 3.3, switching over the multiplexed pin functions. note : settings other than those listed in table iii.1.10.1 are reserved for testing. do not set undescribed values to cmu_clksel[4:0] (d[28:24]/0x301b08) as undesired clocks may output.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.11 standby modes the s 1c33e08 supports two standby modes: halt and sleep. power consumption on the chip can be greatly reduced by placing the cpu in one of these standby modes. moreover, the cpu must be placed in sleep mode before clock sources for the system (osc 3 , osc1 , or pll) are switched over. iii.1.11.1 halt mode the cpu suspends program execution upon executing the halt instruction and enters halt mode. in halt mode, the cpu and a 0 ram (area 0 no-wait ram) stop operating. furthermore, the circuit for which the clock supply is automatically stopped in halt mode (see section iii. 1.9.2 ) stops operating. the other internal peripheral circuits remain in the state (idle or operating) hel d when the halt instruction was executed. the cpu is released from halt mode by initial reset, an nmi or other interrupt, or a forcible break from the debugger. halt mode is effective in reducing power consumption on the chip when running the cpu is unnecessary, such as when waiting for external input or responses from peripheral circuits. when the cpu is released from halt mode by an interrupt, it enters a program executable state by trap processing and executes an interrupt handling routine for the interrupt generated. in trap processing of the cpu, the address for the instruction next to halt is saved to the stack as a return address from the interrupt handling routine, so that the reti instruction in the interrupt handling routine branches to the instruction next to halt. the cpu is released from halt mode when the interrupt controller (itc) asserts the interrupt signal to be sent to the cpu. in other words, when a cause-of-interrupt flag of the interrupts that have been enabled by the interrupt enable bits in the itc is set to 1 , the cpu can be released from halt mode even if the psr is set to disable interrupts. however, in this case the cpu does not execute the interrupt handling routine. the #nmi signal releases the cpu from halt mode when it goes low level. iii.1.11.2 sleep mode the cpu suspends program execution upon executing the slp instruction and enters sleep mode. in sleep mode, the cpu stops operating and the cmu stops supplying a clock to each functional module. therefore, all peripheral circuits (except the oscillator circuit and rtc) stop operating. note that before the cmu actually stops clock output after initiating processing to enter sleep mode, up to 8 clock cycles of the source clock (osc) then selected are required. the cpu is reawaken from sleep mode by initial reset, rtc interrupt, nmi, or other interrupt from an external device (when wakeupwt = 1). when the cpu is reawaken from sleep mode by an interrupt, it enters a program executable state by trap processing and executes an interrupt handling routine for the interrupt generated. in trap processing of the cpu, the address for the instruction next to slp is saved to the stack as a return address from the interrupt handling routine, so that the reti instruction in the interrupt handling routine bra nches to the instruction next to slp. cause-of-interrupt flags in the interrupt controller (itc) cannot be set in sleep mode as the clock is not supplied to the itc in sleep mode. therefore, when the clock is not supplied to the itc, the interrupt signals from the interrupt sources that have been enabled to generate an interrupt are input to the cmu through the itc and used to wake up the cpu from a standby mode. in this case, the cause-of-interrupt flag is set after the clock has started supplying to the itc. the cpu can wake up from sleep mode by a cause of interrupt as described above even if the psr is set to disable interrupts, note however, that the cpu does not execute the interrupt handling routine. the #nmi signal releases the cpu from sleep mode when it goes l ow level.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-24 epson s1c33e08 technical manual notes : ? in sleep mode, there is a time lag between input of an interrupt signal for wakeup and the start of the clock supply to the itc, so a delay will occur until the interrupt controller (itc) sets the cause-of-interrupt flag. therefore, no interrupt will occur if the interrupt signal is deasserted before the clock is supplied to the itc, as the cause-of-interrupt flag in the itc is not set. furthermore, additional time is needed for the cpu to accept the interrupt request from the itc, the cpu may execute a few instructions that follow the slp instruction before it starts the interrupt processing. the same problem may occur when the cpu wakes up from sleep mode by nmi. no interrupt will occur if the #nmi signal is deasserted before the clock is supplied, as the nmi flag is not set. ? before setting the ic to sleep mode, the clock supply for the usb and lcdc must be disabled. stopping osc3 oscillation and waiting for oscillation stabilization at wakeup by default, neither the low-speed (osc 1 ) oscillator circuit nor the high-speed (osc3 ) oscillator circuit stops operating when in sleep mode. osc 3 oscillation can be made to stop during sleep mode by setting osc3off (d3/0x301b14). ? osc3off : osc3 disable during sleep in the clock option register (d3/0x301b14) setting osc 3 off (d3/0x301b14 ) to 1 causes osc3 oscillation to stop during sleep mode. in this case, the osc3 oscillator circuit starts oscillating when the cpu is reawaken from sleep mode. however, since the cpu may operate erratically if it starts operating with the osc 3 or pll clock before the oscillation stabilizes, an osc oscillation start wait timer is provided to keep the cpu waiting a while before it starts operating. the wait time can be set by using osctm[ 7:0] (d[15:8]/0x301b14 ) and tmhsp (d2/0x301b14). ? osctm[7:0] : osc oscillation stabilization-wait timer in the clock option register (d[15:8]/0x301b14) ? tmhsp : stabilization-wait timer high-speed mode select bit in the clock option register (d2/0x301b14) table iii. 1.11.2.1 oscillation stabilization wait time at wakeup tmhsp 1 0 osctm[7:0] 0x0 0x1 0x2 : 0xff 0x0 0x1 0x2 : 0xff time 0 800 ns 1.6 s : 0.204 ms 0 0.409 ms 0.819 ms : 104.5 ms number of c loc ks 0 16 32 : 4080 0 8192 16384 : 2m (the time shown here is an example when operating with a 20 mhz osc3.) sleep control when clock sources are switched over when the cpu reawakes from sleep mode, the clock sources (osc 3 , osc1 , or pll) also are switched over depending on how oscsel[ 1:0 ] (d[3:2]/0x301b08 ) is set. before the clock sources can be switched over, the cpu must be placed once in sleep mode, then released. therefore, a function is provided that automatically reawakes the cpu from sleep mode without using an interrupt, etc. to use this function, set wakeupwt (d0/0x301b14) to 0 . (by default, it is set to 1.) ? oscsel[1:0] : osc clock select bits in the system clock control register (d[3:2]/0x301b08) ? wakeupwt : wakeup-wait function enable bit in the clock option register (d0/0x301b14) when the slp instruction is executed with wakeupwt (d 0/0x301b14 ) set to 0 , the cpu automatically reawakes from sleep mode several 10 clock cycles after that time, then restarts with the source clock selected by oscsel[1:0] (d[3:2]/0x301b08 ) after the oscillation stabilization time described above has elapsed. the osc oscillation start wait timer configured using osctm[ 7:0 ] (d[15:8 ]/0x301b14 ) and tmhsp (d2/0x301b14 ) is effective even if wakeupwt (d0/0x301b14 ) is 0 . to restart the cpu in the shortest time possible, set osctm[7:0] (d[15:8]/0x301b14) to 0x0 and tmhsp (d2/0x301b14) to 1. when wakeupwt (d 0/0x301b14 ) is set to 1 , the cpu is reawaken from sleep mode by initial reset, rtc interrupt, nmi, or other interrupt from an external device. for details about clock switchover and sleep control procedures, see section iii. 1 . 12 , clock setup procedure.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.11.3 precautions interrupt the standby mode is released by an interrupt from the itc, nmi, or reset. note that the itc must be configured so that the interrupt to be used for releasing the standby mode can be generated to the cpu. when the clock has not been supplied to the itc, the interrupt signal from the interrupt source that has been enabled to interrupt is passed through the itc and is input to the cmu. this signal is used to release the standby mode and to start supplying clocks. the itc can operate with the supplied clock in halt mode, so the cause-of- interrupt flag is set immediately after the interrupt source asserts the interrupt signal and the itc requests an interrupt to the cpu without a delay. in sleep mode, the itc will be able to set the cause-of-interrupt flag and to request an interrupt to the cpu after the cmu starts supplying the clock to the itc. therefore, the delay in the interrupt request to the cpu after waking up from sleep mode may cause the cpu to execute a few instructions that follows the slp instruction before the cpu executes the interrupt processing. moreover, if the interrupt source deasserts the interrupt signal before the cmu starts supplying the clock to the itc, an interrupt does not occur since the cause-of-interrupt flag is not set. the ie and il[ 3:0 ] bits in the cpu's psr register do not affect the releasing of standby mode by an interrupt. for example, by setting the itc to enable the interrupt used for releasing and setting the ie bit to disable interrupts, the cpu can wake up from sleep mode without an interrupt processing. oscillator circuits when osc 3 oscillation is set to stop during sleep mode, the osc3 oscillator circuit starts oscillating upon exiting sleep mode. this is because the high-speed (osc 3 ) oscillator circuit requires a finite time before its oscillation stabilizes after starting operation. to restart the cpu using the osc 3 or pll as the source clock, osctm[ 7:0 ] (d[15:8 ]/0x301b14 ) and tmhsp (d2/0x301b14 ) must be properly set so that the cpu starts operating after this oscillation stabilization time elapses. when using the pll, note that the pll requires a lock-in time (e.g., 200 s in the s1c33e08 ) after osc3 oscillation has stabilized. the oscillation start time of the high-speed (osc 3 ) oscillator circuit varies with the device used, board patterns, and operating environment. therefore, the set time above should have a sufficient allowance. bus and dma when in standby mode, the bus module stops operating after the bus cycle in progress is completed. all chip enable signals become inactive. in halt mode, the sramc is active, so the bus clock signals can be output and the dma can also be run. in sleep mode, the sramc is inactive, so no bus clock signals are output, nor is the dma active. be sure to disable the hsdma and idma before setting the chip in sleep mode (executing the slp instruction). halt mode can be set even if the hsdma and/or idma are enabled. switching over the clock sources use the automatic sleep cancellation function when executing the slp instruction for switching over the clock sources. when the sleep mode is cancelled, the osc oscillation start wait timer that has been configured using osctm[ 7:0 ] (d[15:8 ]/0x301b14 ) starts operating with the clock source after switch over. use the switched clock frequency for calculating the oscillation wait time. other the status of the core cpu registers and input/output ports are retained even during standby mode. the contents of the control and data registers in internal peripheral circuits are also basically retained, but some contents are altered upon entering sleep mode. see the description of each peripheral circuit.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-26 epson s1c33e08 technical manual iii.1.12 clock setup procedure this section describes the procedure for setting up clocks or altering clock settings. when initially reset, the clocks are set to the following states: osc3 oscillator circuit: on pll: off osc1 oscillator circuit: on system clock source: osc 3 mclk: osc3?1/1 cmu_clk: osc 3?1/1 iii.1.12.1 changing the clock source from osc3 to pll 1 . clock control protect register (0x301b24) = 0x96 disable write protection of the clock control registers. 2 . pllpowr (d0/0x301b0c) = 0 turn off the pll. 3 . setting pll control register (0x301b0c) ? plln[3:0] (d[7:4]) = 0b0000C0b1111 set the frequency multiplication rate of the pll (x 1 to x16). ? pllv[1:0] (d[3:2]) = 0b01C0b11 set the w value of the pll ( 2, 4 or 8). ? pllvc[3:0] (d[15:12]) = 0b0001C0b1000 set the vco kv circuit constant. ? pllrs[3:0] (d[11:8]) = 0b1000 or 0b1010 set the lpf resistance value. 4 . pllpowr (d0/0x301b0c) = 1 turn on the pll. 5 . oscsel[1:0] (d[3:2]/0x301b08) = 0b11 select the pll for the clock source. 6 . setting the clock option register (0x301b14) ? osctm[7:0] (d[15:8]) = ? ? set appropriate values so that the wait timer exceeds the stabilization time ? osc3off (d3) = 0 of the pll output clock (e.g. 200 s in the s1c33e08 ). be aware that the ? tmhsp (d2) = ? wait timer operates with the pll clock. for details about the pll output ? wakeupwt (d0) = 0 stabilization time, see electrical characteristics. this setting causes the cpu to automatically exit sleep mode and restart after the set time has passed without waiting for an interrupt. 7 . stop any peripheral circuits that are operating, except the rtc. 8 . execute the slp instruction. the chip enters sleep mode and the cmu temporarily stops clock output. the cpu automatically reawakens from sleep mode after the set time has passed from execution of the slp instruction, and restarts using the pll as the clock source. 9 . newly setting the clock control registers again newly alter the mclk or cmu_clk settings, and set other clock control registers again, as required. 10 . clock control protect register (0x301b24) = other than 0x96 reenable write protection of the clock control registers.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.12.2 changing the clock source from pll to osc3 , then turning off the pll 1 . clock control protect register (0x301b24) = 0x96 disable write protection of the clock control registers. 2 . oscsel[1:0] (d[3:2]/0x301b08) = 0b00 select osc 3 for the clock source. 3 . setting the clock option register (0x301b14) ? osctm[7:0] (d[15:8]) = 0x0 ? osc3off (d3) = 0 ? tmhsp (d2) = 1 ? wakeupwt (d0) = 0 this setting causes the cpu to automatically exit sleep mode and restart in the shortest time possible (several 10 clock cycles) without waiting an interrupt. 4 . stop any peripheral circuits that are operating, except the rtc. 5 . execute the slp instruction. the chip enters sleep mode and the cmu temporarily stops clock output. the cpu automatically reawakes from sleep mode several 10 clock cycles after the slp instruction is executed, and restarts using osc3 as the clock source. 6 . pllpowr (d0/0x301b0c) = 0 turn off the pll. 7 . newly setting the clock control registers again newly alter the mclk or cmu_clk settings, and set other clock control registers again, as required. 8 . clock control protect register (0x301b24) = other than 0x96 reenable write protection of the clock control registers.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-28 epson s1c33e08 technical manual iii.1.12.3 changing the clock source from osc3 or pll to osc1 , then turning off osc 3 and pll 1 . clock control protect register (0x301b24) = 0x96 disable write protection of the clock control registers. 2 . sosc1 (d0/0x301b08) = 1 turn on the osc 1 oscillator circuit if turned off. 3 . oscsel[1:0] (d[3:2]/0x301b08) = 0b01 select osc 1 for the clock source. 4 . setting the clock option register (0x301b14) ? osctm[7:0] (d[15:8]) = ? ? set appropriate values so that the wait timer exceeds the stabilization time ? osc3off (d3) = 0 of osc1 oscillation (e.g., 3 seconds in the s1c33e08 ). be aware that the ? tmhsp (d2) = ? wait timer operates with the osc 1 clock. for details about the osc1 ? wakeupwt (d0) = 0 oscillation start time, see electrical characteristics. this setting causes the cpu to automatically exit sleep mode and restart after the set time has passed without waiting for an interrupt. 5 . stop any peripheral circuits that are operating. 6 . execute the slp instruction. the chip enters sleep mode and the cmu temporarily stops clock output. the cpu automatically reawakens from sleep mode after the set time has passed from execution of the slp instruction, and restarts using osc 1 as the clock source. 7 . pllpowr (d0/0x301b0c) = 0 turn off the pll. 8 . sosc3 (d1/0x301b08) = 0 turn off the osc 3 oscillator circuit. 9 . newly setting the clock control registers again newly alter the mclk or cmu_clk settings, and set other clock control registers again, as required. 10 . clock control protect register (0x301b24) = other than 0x96 reenable write protection of the clock control registers.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.12.4 changing the clock source from osc1 to osc3 1 . clock control protect register (0x301b24) = 0x96 disable write protection of the clock control registers. 2 . sosc3 (d1/0x301b08) = 1 turn on the osc 3 oscillator circuit if turned off. 3 . oscsel[1:0] (d[3:2]/0x301b08) = 0b00 select osc 3 for the clock source. 4 . setting the clock option register (0x301b14) ? osctm[7:0] (d[15:8]) = ? ? set appropriate values so that the wait timer exceeds the stabilization time ? osc3off (d3) = 0 of osc3 oscillation (e.g., 25 ms in the s1c33e08 ). be aware that the ? tmhsp (d2) = ? wait timer operates with the osc 3 clock. for details about the osc3 ? wakeupwt (d0) = 0 oscillation start time, see electrical characteristics. this setting causes the cpu to automatically exit sleep mode and restart after the set time has passed without waiting for an interrupt. 5 . stop any peripheral circuits that are operating, except the rtc. 6 . execute the slp instruction. the chip enters sleep mode and the cmu temporarily stops clock output. the cpu automatically reawakens from sleep mode after the set time has passed from execution of the slp instruction, and restarts using osc 3 as the clock source. 7 . newly setting the clock control registers again newly alter the mclk or cmu_clk settings, and set other clock control registers newly again, as required. 8 . clock control protect register (0x301b24) = other than 0x96 reenable write protection of the clock control registers.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-30 epson s1c33e08 technical manual iii.1.12.5 changing the clock source from osc1 to pll 1 . clock control protect register (0x301b24) = 0x96 disable write protection of the clock control registers. 2 . sosc3 (d1/0x301b08) = 1 turn on the osc 3 oscillator circuit if turned off. 3 . wait until osc3 oscillation stabilizes (only when osc3 has been turned on; e.g., 25 ms in the s1c33e08 ). for details about the osc3 oscillation start time, see electrical characteristics. 4 . pllpowr (d0/0x301b0c) = 0 turn off the pll. 5 . setting pll control register (0x301b0c) ? plln[3:0] (d[7:4]) = 0b0000C0b1111 set the frequency multiplication rate of the pll (x 1 to x16). ? pllv[1:0] (d[3:2]) = 0b01C0b11 set the w value of the pll ( 2, 4 or 8). ? pllvc[3:0] (d[15:12]) = 0b0001C0b1000 set the vco kv circuit constant. ? pllrs[3:0] (d[11:8]) = 0b1000 or 0b1010 set the lpf resistance value. 6 . pllpowr (d0/0x301b0c) = 1 turn on the pll. 7 . oscsel[1:0] (d[3:2]/0x301b08) = 0b11 select pll for the clock source. 8 . setting the clock option register (0x301b14) ? osctm[7:0] (d[15:8]) = ? ? set appropriate values so that the wait timer exceeds the stabilization time ? osc3off (d3) = 0 of the pll output clock (e.g. 200 s in the s1c33e08 ). be aware that the ? tmhsp (d2) = ? wait timer operates with the pll clock. for details about the pll output ? wakeupwt (d0) = 0 stabilization time, see electrical characteristics. this setting causes the cpu to automatically exit sleep mode and restart after the set time has passed without waiting for an interrupt. 9 . stop any peripheral circuits that are operating, except the rtc. 10 . execute the slp instruction. the chip enters sleep mode and the cmu temporarily stops clock output. the cpu automatically reawakens from sleep mode after the set time has passed from execution of the slp instruction, and restarts using the pll as the clock source. 11 . newly setting the clock control registers again newly alter the mclk or cmu_clk settings, and set other clock control registers again, as required. 12 . clock control protect register (0x301b24) = other than 0x96 reenable write protection of the clock control registers.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.12.6 turning off osc3 during sleep to turn off osc 3 oscillation during sleep mode when operating with osc3 or pll as the clock source, follow the control procedure described below. 1 . if the current clock source is pll, it must be changed to osc3 and the pll turned off (see note below). see section iii. 1.12.2, changing the clock source from pll to osc3 , then turning off the pll, for the procedure to change the clock source. stop pll even if the current clock source is osc 3. 2 . clock control protect register (0x301b24) = 0x96 disable write protection of the clock control registers. 3 . setting the clock option register (0x301b14) ? osctm[7:0] (d[15:8 ]) and tmhsp (d2) set the wait time until the oscillation stabilizes after exiting sleep mode. example: tmhsp = 1, osctm[7:0] = 0x40 (wait time = about 26 ms when osc3 = 20 mhz) ? osc3off (d3/0x301b14) = 1 turn off osc 3 oscillation when in sleep mode. ? wakeupwt (d0/0x301b14) = 1 set the cpu to awake from sleep mode by using an rtc interrupt, nmi, or other interrupt from an external device. 4 . clock control protect register (0x301b24) = other than 0x96 reenable write protection of the clock control registers. 5 . stop any peripheral circuits that are operating, except the rtc. 6 . execute the slp instruction. the chip enters sleep mode and the cmu temporarily stops cloc k output. the cpu is reawaken from sleep mode by an rtc interrupt, forced break from the debugger, nmi, or other interrupt from an external device. after the set oscillation start wait time elapses, the cpu restarts using the same clock source (osc3 ) that was selected before entering sleep mode. 7 . if the application needs pll as the clock source, change the clock source to pll after the cpu wakes up with the osc3 clock (see note below). see section iii. 1.12.1, changing the clock source from osc3 to pll, for the procedure to change the clock source. note : to turn the osc3 oscillation off in sleep mode, the conditions shown below must be satisfied before entering sleep mode and at wakeup from sleep mode. ? the cpu operates with osc3 as the clock source. ? the pll has been turned off. if both osc3 and pll turn on at wakeup from sleep mode and the cpu starts operating with pll as the clock source, the pll operation may become unstable. therefore, to set pll as the clock source, steps 1 and 7 above are required.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-32 epson s1c33e08 technical manual iii.1.12.7 sleep keeping oscillation on (without clock change) to enter sleep mode without a clock source change and turning off the oscillation, follow the control procedure described below. this is the control to reduce power consumption as much as possible by stopping the core and peripheral functions, with no restart time penalty. 1 . clock control protect register (0x301b24) = 0x96 disable write protection of the clock control registers. 2 . setting the clock option register (0x301b14) ? osctm[7:0] (d[15:8]) = 0x0 ? osc3off (d3) = 0 ? tmhsp (d2) = 1 ? wakeupwt (d0) = 1 this setting causes the cpu to exit sleep mode using an rtc interrupt, nmi, or other interrupt from an external device, and to restart in the shortest time possible (several 10 clock cycles). 3 . clock control protect register (0x301b24) = other than 0x96 reenable write protection of the clock control registers. 4 . stop any peripheral circuits that are operating, except the rtc. 5 . execute the slp instruction. the chip enters sleep mode and the cmu temporarily stops cloc k output. the cpu is brought out of sleep mode by an rtc interrupt, forced break from the debugger, nmi, or other interrupt from an external device, and it restarts using the clock source selected with oscsel[ 1:0 ] (d[3:2]/ 0x301b08).
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.1.13 power-down control the amount of current consumed on the chip varies significantly with the cpu operation mode, operating clock frequency, and peripheral circuit to be operated. the following summarizes points on how to reduce power consumption on the chip. 1 . reducing the operating clock frequency as much as possible the cmu allows one of the three available clock sources to be selected, and the system clock frequency to be set. (see iii.1.4 to iii.1.10.) reduce the operating clock frequency to as low a frequency as permitted for the intended processing content of the system. ? when the osc1 clock can suffice, turn off the pll and osc3, and use only osc1 to operate the system. ? when the osc3 clock can suffice (although high-speed processing is needed), turn off the pll and use osc3 to operate the system. ? when the pll is needed, use it with as small a frequency multiplication rate as possible. ? the divide ratios with which to generate mclk from the source clock can be selected. select the lowest divide ratios permitted for the intended processing content. ? some peripheral circuits may use the prescaler, while others have an exclusive clock control function incorporated in the module. for details, refer to the description of each peripheral circuit. 2 . turning off unnecessary clock supply the cmu allows clock supplies to be turned on or off independently for each functional module. (see iii. 1.9.) ? turn off clock supplies for unused functional modules. ? some peripheral circuits may use the prescaler, while others have an exclusive clock control function incorporated in the module. for details, refer to the description of each peripheral circuit. 3 . placing the cpu in standby mode place the cpu in standby mode by executing the halt or slp instruction as much as possible when, for example, waiting for key input. (see iii. 1.11.) ? optimum power saving effects may be obtained by placing the cpu in sleep mode whenever osc 3 oscillation is turned off. in such case, however, basically only the rtc can be used without other peripheral circuits. ? to wake cpu quickly from sleep mode with no oscillation stabilization time inserted, enter sleep mode after setting osc 3 so that it does not stop in sleep mode. the core and peripheral circuits other than rtc and osc3 cell unit enter power-down state. ? when peripheral circuits must be operated, use the halt instruction to place the cpu in halt mode. in halt mode, the cpu and a 0 ram all stop operating. furthermore, the circuit for which the clock supply is automatically stopped in halt mode (see section iii. 1.9.2) stops operating. 4 . turning off unnecessary external port pull-ups when input ports are driven to low level, their pull-up resistors consume some amount of current. use the pull- up control register to turn off unnecessary pull-ups. however, care should be taken to prevent the input ports from becoming left open (floating state).
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-34 epson s1c33e08 technical manual iii.1.14 details of control registers table iii. 1.14.1 list of cmu registers address 0x00301b00 0x00301b04 0x00301b08 0x00301b0c 0x00301b10 0x00301b14 0x00301b24 function control clock supply for functional modules 0 control clock supply for functional modules 1 set system clock set pll constant, on/off control control sscg set standby and wakeup conditions enable/disable write protection of clock control registers register name gated clock control register 0 (pcmu_gatedclk0 ) gated clock control register 1 (pcmu_gatedclk1 ) system clock control register (pcmu_clkcntl) pll control register (pcmu_pll) sscg macro control register (pcmu_sscg) clock option register (pcmu_opt) clock control protect register (pcmu_protect) siz e 32 32 32 32 32 32 32 the following describes each cmu control register. the cmu control registers are mapped to the 32 -bit device area at addresses 0x301b00 to 0x301b24 , and can be accessed in units of words, half-words or bytes. note : the cmu registers (0x301b00C0x301b14) are write-protected. before these register can be rewritten, write protection must be removed by writing data 0x96 to the clock control protect register (0x301b24). note that since unnecessary rewrites to addresses 0x301b00C0x301b14 could lead to erratic system operation, the clock control protect register (0x301b24) should be set to other than 0x96 unless said cmu control registers must be rewritten.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301b00: gated clock control register 0 (pcmu_gatedclk0) name address register name bit function setting init. r/w remarks C usbsapb_cke usb_cke sdapcpu_hcke sdapcpu_cke sdaplcdc_cke sdsapb_cke dstram_cke lcdcahbif_cke lcdcsapb_cke lcdc_cke d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved usb sapb i/f clock control usb ip 48 mhz clock control sdramc cpu app clock control (halt) sdramc cpu app clock control sdramc lcdc app clock control sdramc sapb i/f clock control dst ram clock control lcdc ahb i/f clock control lcdc sapb i/f clock control lcdc main clock control 1 on 0 off C 0 0 0 0 0 0 1 0 0 0 C r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00301b00 (w) gated clock control register 0 (pcmu _gatedclk0) protected C d[31:10] reserved d9 usbsapb_cke: usb sapb interface clock control bit controls clock (mclk) supply to the usb sapb bus interface. 1 (r/w): on 0 (r/w): off (default) d8 usb_cke: usb ip 48 mhz clock control bit controls clock (osc 3 = 48 mhz) supply to the usb module. 1 (r/w): on 0 (r/w): off (default) d7 sdapcpu_hcke: sdramc cpu app clock control (halt) bit controls clock (mclk) supply to the sdramc cpu_ahb bus interface in halt mode. 1 (r/w): on 0 (r/w): off (default) d6 sdapcpu_cke: sdramc cpu app clock control bit controls clock (mclk) supply to the sdramc cpu_ahb bus interface. 1 (r/w): on 0 (r/w): off (default) d5 sdaplcdc_cke: sdramc lcdc app clock control bit controls clock (mclk) supply to the sdramc lcdc_ahb bus interface. 1 (r/w): on 0 (r/w): off (default) d4 sdsapb_cke: sdramc sapb interface clock control bit controls clock (mclk) supply to the sdramc sapb bus interface. 1 (r/w): on 0 (r/w): off (default) d3 dstram_cke: dst ram clock control bit controls clock (mclk) supply to the dst ram in area 3. 1 (r/w): on (default) 0 (r/w): off d2 lcdcahbif_cke: lcdc ahb bus interface clock control bit controls clock (mclk) supply to the lcdc ahb bus interface. 1 (r/w): on 0 (r/w): off (default)
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-36 epson s1c33e08 technical manual d1 lcdcsapb_cke: lcdc sapb interface clock control bit controls clock (mclk) supply to the lcdc sapb bus interface. 1 (r/w): on 0 (r/w): off (default) d0 lcdc_cke: lcdc main clock control bit controls clock (lcdc_clk) supply to the lcdc module. 1 (r/w): on 0 (r/w): off (default)
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301b04: gated clock control register 1 (pcmu_gatedclk1) name address register name bit function setting init. r/w remarks C cpuahb_hcke lcdcahb_hcke gpionstp_hcke sramc_hcke efsiobr_hcke misc_hcke C ivramarb_cke tm5_cke tm4_cke tm3_cke tm2_cke tm1_cke tm0_cke egpio_cke i2s_cke dcsio_cke wdt_cke gpio_cke sramsapb_cke spi_cke efsiosapb_cke card_cke adc_cke itc_cke dma_cke rtcsapb_cke d31C30 d29 d28 d27 d26 d25 d24 d23C20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved cpu_ahb bus clk control (halt) lcdc_ahb bus clk control (halt) gpio no stop clock control (halt) sramc clock control (halt) efsio baud rate clk control (halt) misc clock control (halt) reserved ivram arbiter clock control 16-bit timer 5 clock control 16-bit timer 4 clock control 16-bit timer 3 clock control 16-bit timer 2 clock control 16-bit timer 1 clock control 16-bit timer 0 clock control egpio clock control i 2 s clock control dcsio clock control watchdog timer clock control gpio normal clock control sramc sapb i/f clock control spi clock control efsio sapb i/f clock control card i/f clock control adc clock control itc clock control dmac clock control rtc sapb i/f clock control 1 on 0 off C 1 1 1 1 1 1 C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C r/w r/w r/w r/w r/w r/w C r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0 when being read. 00301b04 (w) gated clock control register 1 (pcmu _gatedclk1) protected C 1 on 0 off C d[31:30] reserved d29 cpuahb_hcke: cpu_ahb bus clock control (halt) bit controls clock (mclk) supply to the cpu_ahb bus in halt mode. 1 (r/w): on (default) 0 (r/w): off d28 lcdcahb_hcke: lcdc_ahb bus clock control (halt) bit controls clock (mclk) supply to the lcdc_ahb bus in halt mode. 1 (r/w): on (default) 0 (r/w): off d27 gpionstp_hcke: gpio no stop clock control (halt) bit controls clock (mclk) supply to the gpio input/interrupt circui ts in halt mode. 1 (r/w): on (default) 0 (r/w): off d26 sramc_hcke: sramc clock control (halt) bit controls clock (mclk) supply to the sramc in halt mode. 1 (r/w): on (default) 0 (r/w): off d25 efsiobr_hcke: efsio baud rate clock control (halt) bit controls clock (mclk) supply to the efsio baud rate timer i n halt mode. 1 (r/w): on (default) 0 (r/w): off d24 misc_hcke: misc clock control (halt) bit controls clock (mclk) supply to the misc registers in halt mode. 1 (r/w): on (default) 0 (r/w): off d[23:20] reserved
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-38 epson s1c33e08 technical manual d19 ivramarb_cke: ivram arbiter clock control bit controls clock (mclk) supply to the ivram arbiter. 1 (r/w): on (default) 0 (r/w): off d18 tm5_cke: 16-bit timer 5 clock control bit controls clock (mclk) supply to the 16-bit timer 5. 1 (r/w): on (default) 0 (r/w): off d17 tm4_cke: 16-bit timer 4 clock control bit controls clock (mclk) supply to the 16-bit timer 4. 1 (r/w): on (default) 0 (r/w): off d16 tm3_cke: 16-bit timer 3 clock control bit controls clock (mclk) supply to the 16-bit timer 3. 1 (r/w): on (default) 0 (r/w): off d15 tm2_cke: 16-bit timer 2 clock control bit controls clock (mclk) supply to the 16-bit timer 2. 1 (r/w): on (default) 0 (r/w): off d14 tm1_cke: 16-bit timer 1 clock control bit controls clock (mclk) supply to the 16-bit timer 1. 1 (r/w): on (default) 0 (r/w): off d13 tm0_cke: 16-bit timer 0 clock control bit controls clock (mclk) supply to the 16-bit timer 0. 1 (r/w): on (default) 0 (r/w): off d12 egpio_cke: egpio clock control bit controls clock (mclk) supply to the egpio. 1 (r/w): on (default) 0 (r/w): off d11 i2s_cke: i 2 s clock control bit controls clock (mclk) supply to the i 2 s interface. 1 (r/w): on (default) 0 (r/w): off d10 dcsio_cke: dcsio clock control bit controls clock (mclk) supply to the dcsio. 1 (r/w): on (default) 0 (r/w): off d9 wdt_cke: watchdog timer clock control bit controls clock (mclk) supply to the watchdog timer. 1 (r/w): on (default) 0 (r/w): off
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d8 gpio_cke: gpio normal clock control bit controls clock (mclk) supply to the gpio. 1 (r/w): on (default) 0 (r/w): off d7 sramsapb_cke: sramc sapb interface clock control bit controls clock (mclk) supply to the sramc sapb interface. 1 (r/w): on (default) 0 (r/w): off d6 spi_cke: spi clock control bit controls clock (mclk) supply to the spi. 1 (r/w): on (default) 0 (r/w): off d5 efsiosapb_cke: efsio sapb interface clock control bit controls clock (mclk) supply to the efsio sapb interface. 1 (r/w): on (default) 0 (r/w): off d4 card_cke: card interface clock control bit controls clock (mclk) supply to the card interface. 1 (r/w): on (default) 0 (r/w): off d3 adc_cke: a/d converter clock control bit controls clock (mclk) supply to the a/d converter. 1 (r/w): on (default) 0 (r/w): off d2 itc_cke: itc clock control bit controls clock (mclk) supply to the itc. 1 (r/w): on (default) 0 (r/w): off d1 dma_cke: dmac clock control bit controls clock (mclk) supply to the dma controllers. 1 (r/w): on (default) 0 (r/w): off d0 rtcsapb_cke: rtc sapb interface clock control bit controls clock (mclk) supply to the rtc sapb interface. 1 (r/w): on (default) 0 (r/w): off
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-40 epson s1c33e08 technical manual 0x301b08: system clock control register (pcmu_clkcntl) name address register name bit function setting init. r/w remarks C cmu_clksel4 cmu_clksel3 cmu_clksel2 cmu_clksel1 cmu_clksel0 pllindiv3 pllindiv2 pllindiv1 pllindiv0 lcdcdiv3 lcdcdiv2 lcdcdiv1 lcdcdiv0 C mclkdiv C osc3div2 osc3div1 osc3div0 C oscsel1 oscsel0 sosc3 sosc1 d31C29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C13 d12 d11 d10 d9 d8 d7C4 d3 d2 d1 d0 reserved cmu_clk output clock source selection pll input clock source divider selection lcdc clock divider selection reserved mclk clock divider selection reserved osc3 clock divider selection reserved osc clock selection high-speed oscillation (osc3) on/of f low-speed oscillation (osc1) on/of f 1 1/2 0 1/1 1 on 0 off 1 on 0 off C 0 0 0 0 0 0 1 1 1 0 1 1 1 C 0 C 0 0 0 C 0 0 1 1 C r/w r/w r/w C r/w C r/w C r/w r/w r/w 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301b08 (w) system clock control register (pcmu_clkcntl) protected C C C C cmu_clksel[4:0] other 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 clock source reserved osc3_div*1/32 osc3_div*1/16 osc3_div*1/8 osc3_div*1/4 osc3_div*1/2 osc3_div*1/1 lcdc_clk mclk pll osc1 osc3 pllindiv[3:0] other 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 divider osc3*1/8 osc3*1/10 osc3*1/9 osc3*1/8 osc3*1/7 osc3*1/6 osc3*1/5 osc3*1/4 osc3*1/3 osc3*1/2 osc3*1/1 lcdcdiv[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 divider osc3*1/16 osc3*1/15 osc3*1/14 osc3*1/13 osc3*1/12 osc3*1/11 osc3*1/10 osc3*1/9 osc3*1/8 osc3*1/7 osc3*1/6 osc3*1/5 osc3*1/4 osc3*1/3 osc3*1/2 osc3*1/1 osc3div[2:0] 111 110 101 100 011 010 001 000 divider osc3*1/1 osc3*1/1 osc3*1/32 osc3*1/16 osc3*1/8 osc3*1/4 osc3*1/2 osc3*1/1 oscsel[1:0] 11 10 01 00 clock source pll osc3 osc1 osc3
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d[31:29] reserved d[28:24] cmu_clksel[4:0]: cmu_clk output clock source select bits cmu_clk is the clock for the external bus. it can be selected from the 11 clocks listed in table iii.1.14.2. table iii. 1.14.2 selecting cmu_clk cmu_clksel3 1 1 1 0 0 0 0 0 0 0 0 cmu_clksel2 0 0 0 1 1 1 1 0 0 0 0 cmu_clk osc3_div?1/32 osc3_div?1/16 osc3_div?1/8 osc3_div?1/4 osc3_div?1/2 osc3_div?1/1 lcdc_clk mclk pll osc1 osc3 reser ve d cmu_clksel4 0 0 0 0 0 0 0 0 0 0 0 other cmu_clksel1 1 0 0 1 1 0 0 1 1 0 0 cmu_clksel0 0 1 0 1 0 1 0 1 0 1 0 (default: 0b00000) cmu_clk can be selected at any time. however, switching over the clocks creates hazards. when cmu_clk must be output to external devices, it is also necessary to select a port function. for details on how to control clock output and about the port to be used, see section i. 3.3, switching over the multiplexed pin functions. note : other settings than that listed in table iii.1.14.2 are reserved for testing. do not set undescribed values to cmu_clksel[4:0] as undesired clocks may output. d[23:20] pllindiv[3:0]: pll input clock source divider select bits pllindiv[ 3:0] is used to select the pll input clock from among 10 kinds of osc3 divided clocks. table iii. 1.14.3 selecting the pll input clock pllindiv3 1 1 0 0 0 0 0 0 0 0 pllindiv2 0 0 1 1 1 1 0 0 0 0 pll input c loc k osc3?1/10 osc3?1/9 osc3?1/8 osc3?1/7 osc3?1/6 osc3?1/5 osc3?1/4 osc3?1/3 osc3?1/2 osc3?1/1 osc3?1/8 pllindiv1 0 0 1 1 0 0 1 1 0 0 pllindiv0 1 0 1 0 1 0 1 0 1 0 other (default: 0b0111) note : the pll input clock can only be selected when the pll is turned off (pllpowr (d0/ 0x301b0c) = 0) and the clock source is other than the pll (oscsel[1:0] (d[3:2]) = 0C2). if the pll input clock is changed while the system is operating with the pll clock, the system may operate erratically.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-42 epson s1c33e08 technical manual d[19:16] lcdcdiv[3:0]: lcdc clock divider select bits lcdcdiv[ 3:0 ] is used to select the lcd interface clock (lcdc_clk) from among 16 kinds of osc3 divided clocks. select a divided clock according to the frame rate. f lcdc frame rate = [hz] ht vt f lcdc : lcdc_clk frequency ht: horizontal total period (including non-display period) [pixels] vt: vertical total period (including non-display period) [pixels] table iii. 1.14.4 selecting the lcdc clock lcdcdiv3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 lcdcdiv2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 lcdc_clk osc3?1/16 osc3?1/15 osc3?1/14 osc3?1/13 osc3?1/12 osc3?1/11 osc3?1/10 osc3?1/9 osc3?1/8 osc3?1/7 osc3?1/6 osc3?1/5 osc3?1/4 osc3?1/3 osc3?1/2 osc3?1/1 lcdcdiv1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 lcdcdiv0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0111) d[15:13] reserved d12 mclkdiv: mclk clock divider select bit selects the main system clock. 1 (r/w): osc?1/2 0 (r/w): osc?1/1 (default) mclk is the main system clock for the s 1c33e08 . it is derived from the system s source clock osc (selected using oscsel[1:0] (d[3:2 ])) by dividing its frequency by 1 or 2. when using the sdram in double frequency mode (mclk max. = 45 mhz, sdram clock max. = 90 mhz), mclkdiv should be set to 1. d11 reserved d[10:8] osc3div[2:0]: osc3 clock divider select bits osc 3 div[2:0 ] is used to select the system clock frequency when osc3 is selected as the system clock source. it is derived from the osc 3 clock by dividing its frequency by a given value. use osc3div[2:0 ] to select this clock divide ratio. table iii. 1.14.5 selecting an osc3 divided clock osc3div2 1 1 1 1 0 0 0 0 osc3div1 1 1 0 0 1 1 0 0 cmu_clk osc3?1/1 osc3?1/1 osc3?1/32 osc3?1/16 osc3?1/8 osc3?1/4 osc3?1/2 osc3?1/1 osc3div0 1 0 1 0 1 0 1 0 (default: 0b000) a divided clock can be selected at any time. however, up to 32 osc3 clock cycles are required before the clocks are actually changed after altering the register values.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-43 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d[7:4] reserved d[3:2] oscsel[1:0]: osc clock select bits selects the clock source for the system (osc). table iii. 1.14.6 selecting the system clock source oscsel1 1 1 0 0 oscsel0 1 0 1 0 cloc k sour ce pll osc3 osc1 osc3 (default: 0b00) the clock sources changed here are not switched over immediately, but are actually switched over upon returning from sleep mode. therefore, the cpu must be placed in sleep mode after setting up oscsel[1:0]. note : when clock sources are changed, the clock control registers must be set so that the cmu is supplied with a clock from the selected clock source upon returning from sleep mode immediately after the change. otherwise, the chip does not restart after return from sleep mode. d1 sosc3: high-speed oscillation (osc3) on/off bit turns the osc 3 oscillator circuit on or off. 1 (r/w): on (default) 0 (r/w): off d0 sosc1: low-speed oscillation (osc1) on/off bit turns the osc 1 oscillator circuit on or off. 1 (r/w): on (default) 0 (r/w): off note : when sosc3 (d1) or sosc1 (d0) is set from 0 to 1 for initiating oscillation by the oscillator, a finite time is required until the oscillation stabilizes. to prevent erratic operation, do not use the oscillator-derived clock until the oscillation start time stipulated in the electrical characteristics table elapses.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-44 epson s1c33e08 technical manual 0x301b0c: pll control register (pcmu_pll) name address register name bit function setting init. r/w remarks C pllcs1 pllcs0 pllbyp pllcp4 pllcp3 pllcp2 pllcp1 pllcp0 pllvc3 pllvc2 pllvc1 pllvc0 pllrs3 pllrs2 pllrs1 pllrs0 plln3 plln2 plln1 plln0 pllv1 pllv0 C pllpowr d31C24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved pll lpf capacitance setup pll bypass mode setup pll charge pump current setup pll vco kv setup pll lpf resistance setup pll multiplication rate setup pll v-divider setup reserved pll on/off control C 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 C 0 C r/w r/w r/w r/w r/w r/w r/w C r/w 0 when being read. 0 when being read. 00301b0c (w) pll control register (pcmu_pll) protected fixed at "0" (default) C fixed at "00" (default) fixed at "10000" (default) pllvc[3:0] 1000 0111 0110 0101 0100 0011 0010 0001 other f vco [mhz] 360 < f vco 400 320 < f vco 360 280 < f vco 320 240 < f vco 280 200 < f vco 240 160 < f vco 200 120 < f vco 160 100 f vco 120 not allowed pllrs[3:0] 1010 1000 other f refck [mhz] 5 f refck < 20 20 f refck 150 not allowed 1 on 0 off plln[3:0] 1111 1110 : 0001 0000 multiplication rate x16 x15 : x2 x1 pllv[1:0] 11 10 01 00 w 8 4 2 not allowed C note : when d[23:2] in this register must be altered, turn off the pll (pllpowr (d0) = 0) before changing the bits. d[31:24] reserved d[23:22] pllcs[1:0]: pll lpf capacitance setup bits sets the lpf capacitance value (cs value). (default: 0b00) this bit should be left as at initial reset, without altering i ts settings while in use. d21 pllbyp: pll bypass mode setup bit sets pll bypass mode. (default: 0) this bit should be left as at initial reset, without altering i ts settings while in use. d[20:16] pllcp[4:0]: pll charge pump current setup bits sets the charge pump current value (cp value). (default: 0b10000) this bit should be left as at initial reset, without altering i ts settings while in use. d[15:12] pllvc[3:0]: pll vco kv setup bits sets the vco kv circuit constant (vc value) according to the range of f vco frequencies obtained by .
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-45 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table iii. 1.14.7 settings of the vc value pll vc3 1 0 0 0 0 0 0 0 other pll vc2 0 1 1 1 1 0 0 0 f vco [mhz] 360 < f vco 400 320 < f vco 360 280 < f vco 320 240 < f vco 280 200 < f vco 240 160 < f vco 200 120 < f vco 160 100 f vco 120 not allowed pll vc1 0 1 1 0 0 1 1 0 pll vc0 0 1 0 1 0 1 0 1 (default: 0b0001) d[11:8] pllrs[3:0]: pll lpf resistance setup bits sets the lpf resistance value of the pll (rs value) according to the input clock (osc 3 ) frequency. table iii. 1.14.8 settings of the rs value pllrs3 1 1 other pllrs2 0 0 f refck [mhz] 5 f refck < 20 20 f refck 150 not allowed pllrs1 1 0 pllrs0 0 0 (default: 0b1000) d[7:4] plln[3:0]: pll multiplication rate setup bits sets the frequency multiplication rate of the pll. (default: 0b0000 = 1) pll frequency multiplication rate = plln[ 3:0] + 1 ( 1 to 16) note : the frequency multiplication rate must be set so that the pll output clock frequency does not exceed the upper-limit operating clock frequency. for the multiplication rates that can be set and the range of the output clock frequency, see electrical characteristics. d[3:2] pllv[1:0]: pll v-divider setup bits sets the w value so that the f vco frequency obtained by falls within the range of 100 to 400 mhz. table iii. 1.14.9 settings of the w value pll v1 1 1 0 0 pll v0 1 0 1 0 w 8 4 2 not allo we d (default: 0b01) d1 reserved d0 pllpowr: pll on/off control bit turns the pll on or off. 1 (r/w): on 0 (r/w): off (default) up to 200 s is required before the output clock of the pll stabilizes after pllpowr is set to 1. provide this wait time in a program before changing the clock source for the system to the pll. when not using the pll, turn off the pll (power-down mode) to reduce the amount of current consumed on the chip. table iii. 1.14.10 example pll settings pll input c loc k 6 mhz 10 mhz 20 mhz 45 mhz pll output c loc k 90 mhz 60 mhz 80 mhz 40 mhz 80 mhz 40 mhz 90 mhz plln[3:0] x15, 0b1110 x10, 0b1001 x8, 0b0111 x4, 0b0011 x4, 0b0011 x2, 0b0001 x2, 0b0001 pll v[1:0] 0b01 0b01 0b01 0b10 0b01 0b10 0b01 pll vc[3:0] 0b0011 0b0001 0b0010 0b0010 0b0010 0b0010 0b0011 pllrs[3:0] 0b1010 0b1010 0b1010 0b1010 0b1000 0b1000 0b1000
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-46 epson s1c33e08 technical manual 0x301b10: sscg macro control register (pcmu_sscg) name address register name bit function setting init. r/w remarks C ssmcitm3 ssmcitm2 ssmcitm1 ssmcitm0 ssmcidt3 ssmcidt2 ssmcidt1 ssmcidt0 C ssmcon d31C16 d15 d14 d13 d12 d11 d10 d9 d8 d7C1 d0 reserved sscg macro interval timer (itm) setting sscg macro maximum frequency change width setting reserved sscg macro on/off C 1 1 1 1 0 0 0 0 C 0 C r/w r/w C r/w 0 when being read. 0 when being read. 00301b10 (w) sscg macro control register (pcmu_sscg) protected C 0 to 0xf 0 to 0xf C 1 on 0 off note : when the pll is off, the initial values and the written values cannot be read correctly from ssmcidt[3:0] (d[11:8]) and ssmcitm[3:0] (d[15:12]) since the so urce clock is not supplied from the pll (different values are read out). the correct values can be read out when the pll is on. d[31:16] reserved d[15:12] ssmcitm[3:0]: sscg macro interval timer setting bits these bits set the frequency change cycle in ss modulation of the sscg. (see section iii. 1.7, control of the sscg. ) always set these bits to 0b0001 . (default: 0b1111) d[11:8] ssmcidt[3:0]: sscg macro maximum frequency change width setting bits these bits set the maximum frequency change width in ss modulation of the sscg. (see section iii.1.7, control of the sscg. ) table iii. 1.14.11 maximum frequency change width settings ssmcidt2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ssmcidt1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 pll output c loc k frequency f [mhz] f 19.8 19.8 < f 21.2 21.2 < f 22.5 22.5 < f 24.2 24.2 < f 25.9 25.9 < f 28.4 28.4 < f 30.8 30.8 < f 34.2 34.2 < f 37.8 37.8 < f 43.1 43.1 < f 48.9 48.9 < f 58.5 58.5 < f 69.7 69.7 < f 90.0 C C ssmcidt3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 ssmcidt0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0000) note : ssmcidt[3:0] must be set according to the pll output clock frequency as shown in table iii.1.14.11. using the sscg with an improper setting may cause a malfunction of the ic. d[7:1] reserved d0 ssmcon: sscg macro on/off control bit this bit turns the sscg on or off. 1 (r/w): on 0 (r/w): off (default) setting this bit to 1 causes the sscg to start operating. setting this bit to 0 causes the sscg to stop, so that the clock generator bypasses the sscg.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-47 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301b14: clock option register (pcmu_opt) name address register name bit function setting init. r/w remarks C osctm7 osctm6 osctm5 osctm4 osctm3 osctm2 osctm1 osctm0 C osc3off tmhsp C wakeupwt d31C16 d15 d14 d13 d12 d11 d10 d9 d8 d7C4 d3 d2 d1 d0 reserved osc oscillation stabilization-wait timer reserved osc3 disable during sleep wait-timer high-speed mode reserved wakeup-wait function enable 1 wait interrupt 0 no wait 1 high speed 0 normal 1 stop 0 run C 0 0 0 0 0 0 0 0 C 0 0 C 0 C r/w C r/w r/w C r/w 0 when being read. 0 when being read. 0 when being read. 00301b14 (w) C C clock option register (pcmu_opt) protected C 0 to 255 d[31:16] reserved d[15:8] osctm[7:0]: osc oscillation stabilization-wait timer sets an oscillation stabilization wait time during which the cpu is kept waiting before it starts operating upon returning from sleep mode. this wait time can be set in increments of 16 osc clock cycles when tmhsp (d 2 ) = 1 , or 8 , 192 clock cycles when tmhsp (d 2 ) = 0 . (default: 0 b 00 = no wait time) table iii. 1.14.12 oscillation stabilization wait time at wakeup tmhsp 1 0 osctm[7:0] 0x0 0x1 0x2 : 0xff 0x0 0x1 0x2 : 0xff time 0 800 ns 1.6 s : 0.204 ms 0 0.409 ms 0.819 ms : 104.5 ms number of c loc ks 0 16 32 : 4080 0 8192 16384 : 2m (the time shown here is an example when operating with a 20 mhz osc3.) when the osc 3 oscillation is to be turned off during sleep mode, make sure the wait time set by these bits is equal to or greater than the osc 3 oscillation start time stipulated in the electrical characteristics table. note : the osc oscillation start wait timer operates with the operating clock activated after the sleep mode is released. therefore, use the switched clock frequency for calculating the oscillation wait time to be set to osctm[7:0] when executing the slp instruction for switching over the clock sources. d[7:4] reserved d3 osc3off: osc3 disable during sleep selects whether to turn off the osc 3 oscillator circuit during sleep mode. 1 (r/w): stop 0 (r/w): operating (default) continue operating osc 3 when entering sleep mode to switch over the clock sources (osc), or turn it off when entering sleep mode for power-down purposes.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-48 epson s1c33e08 technical manual d2 tmhsp: stabilization-wait timer high-speed mode select bit sets count mode for the oscillation stabilization wait timer (osctm[ 7:0]). 1 (r/w): high-speed mode 0 (r/w): normal mode (default) the oscillation stabilization wait timer counts from 0 to 2 m in units of 8,192 osc clock cycles during normal mode, or from 0 to 4,080 in units of 16 osc clock cycles during high-speed mode. select either mode in which the osc3 oscillation start time can be secured with the osc frequency used. d1 reserved d0 wakeupwt: wakeup-wait function enable bit enables the sleep mode wakeup-wait function used for switching over the clocks. 1 (r/w): wait an interrupt 0 (r/w): no wait (default) when the slp instruction is executed while wakeupwt is set to 0 , the cpu automatically reawakes from sleep mode several 10 clock cycles after instruction execution, and restarts with the source clock selected by oscsel[ 1:0 ] (d[3:2]/0x301b08 ). since even in this case the oscillation stabilization wait time set by osctm[ 7:0 ] (d[15:8 ]) is effective, osctm[7:0 ] should be set to 0x0 when clocks must be switched over in the shortest time possible. when wakeupwt is set to 1 , the cpu can only be reawaken from sleep mode by an interrupt such as initial reset, rtc interrupt, forced break from the debugger, nmi, and other interrupt from an external source.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-49 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301b24: clock control protect register (pcmu_protect) name address register name bit function setting init. r/w remarks C wr iting 10010110 (0x96) remo v es the wr ite protection of the cloc k control registers (0x301b00C0x301b14). wr iting another v alue set the wr ite protection. C clgp7 clgp6 clgp5 clgp4 clgp3 clgp2 clgp1 clgp0 d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved clock control register protect flag C 0 0 0 0 0 0 0 0 C r/w 0 when being read. 00301b24 (w) clock control protect register (pcmu_protect) d[31:8] reserved d[7:0] clgp[7:0]: clock control register protect flag enables/disables write protection of the clock control registers ( 0x301b00C0x301b14). 0x96 (r/w): disable write protection other than 0x96 (r/w): write-protect the register (default: 0x0) before altering any clock control register, write data 0x96 to the register to disable write protection. if this register is set to other than 0x96 , even if an attempt is made to alter any clock control register by executing a write instruction, the content of said register will not be altered even though the instruction may have been executed without a problem. once this register is set to 0x96 , the clock control registers can be rewritten any number of times until being reset to other than 0x96 . when rewriting the clock control registers has finished, this register should be set to other than 0x96 to prevent accidental writing to the clock control registers.
iii peripheral modules 1 (system): clock management unit (cmu) iii-1-50 epson s1c33e08 technical manual iii.1.15 precautions precautions regarding clock control ? the clock control registers ( 0 x 301 b 00 C 0 x 301 b 14 ) are write-protected. before these registers can be rewritten, write protection must be removed by writing data 0 x 96 to the clock control protect register ( 0 x 301 b 24 ). once write protection is removed, the clock control registers can be written to any number of times until the protect register is reset to other than 0 x 96 . note that since unnecessary rewriting of the clock control registers could lead to erratic system operation, the clock control protect register ( 0 x 301 b 24 ) should be set to other than 0 x 96 unless the clock control registers must be rewritten. ? when clock sources are changed, the clock control registers must be set so that the cmu is supplied with a clock from the selected clock source upon returning from sleep mode immediately after the change. otherwise, the chip may not restart after return from sleep mode. furthermore, note that the timer, which generates an oscillation stabilization wait time after the sleep mode is released, operates with the clock after switching over. be sure to use the correct clock frequency for calculating the wait time to be set to osctm[ 7:0] (d[15:8]/0x301b14 ) and tmhsp (d2/0x301b14). ? when sosc3 (d1/0x301b08 ) or sosc1 (d0/0x301b08 ) is set from 0 to 1 for initiating oscillation by the oscillator, a finite time is required until the oscillation stabilizes (e.g., 25 ms for osc3 and 3 seconds for osc1 in the s 1c33e08 ). to prevent erratic operation, do not use the oscillator-derived clock until the oscillation start time stipulated in the electrical characteristics table elapses. ? immediately after the pll is started by setting pllpowr (d0/0x301b0 c) to 1 , an output clock stabilization wait time is required (e.g., 200 s in the s1c33e08 ). when the clock source for the system is switched over to the pll, allow for this wait time after the pll has turned on. ? the frequency multiplication rate of the pll that can be set depends on the upper-limit operating clock frequency ( 90 mhz) and the osc3 oscillation frequency. when setting the frequency multiplication rate, be sure not to exceed the upper-limit operating clock frequency. ? the pll can only be set up when the pll is turned off (pllpowr (d0/0x301b0 c) = 0 ) and the clock source is other than the pll (oscsel[ 1:0 ] (d[3:2 ]/0x301b08 ) = 0C2 ). if settings are changed while the system is operating with the pll clock, the system may operate erraticall y. precautions regarding reset input ? even if the #reset pin is pulled low (= 0 ), the chip may not be reset unless supplied with a clock. to reset the chip for sure, #reset should be held low for at least 3 osc3 clock cycles. however, the input/output port pins will be initialized by reset regardless of whether the chip is supplied with a clock. ? the oscillation start time of the high-speed (osc3 ) oscillator circuit varies with the device used, board patterns, and operating environment. therefore, a sufficient time should be provided before the reset signal is deasserted. precautions regarding nmi input nmi cannot be nested. the cpu keeps nmi input masked out until the reti instruction is executed after an nmi exception occurred.
iii peripheral modules 1 (system): clock management unit (cmu) s1c33e08 technical manual epson iii-1-51 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 precautions regarding sscg control ? when using the sscg, always set ssmcitm[3:0] (d[15:12]/0x301b10) to 0b0001. ? ssmcidt[3:0 ] (d[11:8]/0x301b10 ) must be set according to the pll output clock frequency as shown in table iii.1.7.2.1. using the sscg with an improper setting may cause a malfunction of the ic. ? when the pll is off, the initial values and the written values cannot be read correctly from ssmcidt[3:0] (d[11:8]/0x301b10 ) and ssmcitm[3:0 ] (d[15:12]/0x301b10 ) since the source clock is not supplied from the pll (different values are read out). the correct values can be read out when the pll is on. ? a stabilized clock must be supplied to the sscg module when turning the sscg on and off. the following shows the operation procedure. to turn the sscg on 1 . turn the pll on. 2 . wait more than the pll stabilization time. 3 . turn the sscg on. to turn the sscg off 1 . turn the sscg off. 2 . turn the pll off. ? the ss modulation is effective only for the pll output clock, and is not performed for other source clocks. when the pll output clock is not used for the system clock, tur n the sscg off.
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iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.2 interrupt controller (itc) the s 1c33e08 contains an interrupt controller, making it possible to control all interrupts generated by the internal peripheral circuits. this section explains the functions of this interrupt controller centering around the method for controlling maskable interrupts. for details about the various causes and conditions under which interrupts are generated, refer to the description of each peripheral circuit in this manual. iii.2.1 outline of interrupt functions iii.2.1.1 maskable interrupts the itc can handle 55 kinds of maskable interrupts. table iii.2.1.1.1 shows the trap table in the s1c33e08. table iii. 2.1.1.1 trap table idma ch. C C C C C C C C C C C C C C 1 2 3 4 C C 5 6 C C C C 7 8 C 9 10 C 11 12 C 13 14 C 15 16 C 17 18 C priority 1 C 4 3 C 2 5 6 C high lo w v ector number (he x address) 0(base) 1 2(base+8) 3(base+0c) 4C5 6(base+18) 0x60000 7(base+1c) 8C10 11(base+2c) 12(base+30) 13(base+34) 14(base+38) 15(base+3c) 16(base+40) 17(base+44) 18(base+48) 19(base+4c) 20(base+50) 21(base+54) 22(base+58) 23(base+5c) 24(base+60) 25(base+64) 26(base+68) 27C29 30(base+78) 31(base+7c) 32C33 34(base+88) 35(base+8c) 36C37 38(base+98) 39(base+9c) 40C41 42(base+a8) 43(base+a c) 44C45 46(base+b8) 47(base+bc) 48C49 50(base+c8) 51(base+cc) 52C55 exception/interrupt name (peripheral cir cuit) reset reser ve d ext e xception undefined instr uction e xception reser ve d address misaligned e xception deb ugging e xception nmi reser ve d illegal interr upt e xception softw are e xception 0 softw are e xception 1 softw are e xception 2 softw are e xception 3 po rt input interr upt 0 po rt input interr upt 1 po rt input interr upt 2 po rt input interr upt 3 ke y input interr upt 0 ke y input interr upt 1 high-speed dma ch.0 high-speed dma ch.1 high-speed dma ch.2 high-speed dma ch.3 intelligent dma reser ve d 16-bit timer 0 reser ve d 16-bit timer 1 reser ve d 16-bit timer 2 reser ve d 16-bit timer 3 reser ve d 16-bit timer 4 reser ve d 16-bit timer 5 reser ve d cause of e xception/interrupt lo w input to the reset pin C ext instr uction (illegal use) undefined instr uction C memor y access instr uction brk instr uction, etc. lo w input to the #nmi pin or w atchdog timer ov erflo w C occurrence of illegal interr upt from itc int instr uction int instr uction int instr uction int instr uction edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) rising or f alling edge rising or f alling edge high-speed dma ch.0, end of transf er high-speed dma ch.1, end of transf er high-speed dma ch.2, end of transf er high-speed dma ch.3, end of transf er intelligent dma, end of transf er C timer 0 compare-match b timer 0 compare-match a C timer 1 compare-match b timer 1 compare-match a C timer 2 compare-match b timer 2 compare-match a C timer 3 compare-match b timer 3 compare-match a C timer 4 compare-match b timer 4 compare-match a C timer 5 compare-match b timer 5 compare-match a C
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-2 epson s1c33e08 technical manual idma ch. C 23 24 C C 25 26 C 27 C C 28 29 30 31 C 33 C C 34 35 C 36 37 C 38 39 40 41 42 43 44 45 C 46 C priority high lo w v ector number (he x address) 56(base+e0) 57(base+e4) 58(base+e8) 59 60(base+f0) 61(base+f4) 62(base+f8) 63(base+fc) 64(base+100) 65(base+104) 66C67 68(base+110) 69(base+114) 70(base+118) 71(base+11c) 72(base+120) 73(base+124) 74C75 76(base+130) 77(base+134) 78(base+138) 79C80 81(base+144) 82(base+148) 83 84(base+150) 85(base+154) 86(base+158) 87(base+15c) 88(base+160) 89(base+164) 90(base+168) 91(base+16c) 92C93 94(base+178) 95C107 exception/interrupt name (peripheral cir cuit) ser ial interf ace ch.0 reser ve d ser ial interf ace ch.1 a/d con ve r ter rt c reser ve d po rt input interr upt 4 po rt input interr upt 5 po rt input interr upt 6 po rt input interr upt 7 reser ve d lcdc reser ve d ser ial interf ace ch.2 reser ve d spi reser ve d po rt input interr upt 8 spi po rt input interr upt 9 usb pdreq po rt input interr upt 10 usb po rt input interr upt 11 dcsio po rt input interr upt 12 po rt input interr upt 13 po rt input interr upt 14 po rt input interr upt 15 reser ve d i 2 s interf ace reser ve d cause of e xception/interrupt receiv e error receiv e b uff er full tr ansmit b uff er empty C receiv e error receiv e b uff er full tr ansmit b uff er empty result out of range (upper-limit and lo wer-limit) end of con v ersion 1/64 second, 1 second, 1 minuet, or 1 hour count up C edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) C end of frame C receiv e error receiv e b uff er full tr ansmit b uff er empty C receiv e dma request tr ansmit dma request C edge (r ising or f alling) or le v el (high or lo w) spi interr upt (d[1:0]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) usb dma request (d[3:2]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) usb interr upt (d[5:4]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) dcsio interr upt (d[7:6]/0x3003c4 = 0x10) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) edge (r ising or f alling) or le v el (high or lo w) C i 2 s fifo empty C notes : ? the mp3 decoder bios (mp3 decoder module) uses the hsdma ch.0 , ch.1 and i 2 s and their interrupts for output data requests. therefore, these dma channels and interrupts cannot be used in the user program. ? idma ch.19C22, 32, 47C53 are reserved. contents of table vector number (address) indicates the trap table's vector number. the numerals in parentheses show an offset (in bytes) from the starting address (base) of the trap table. the starting address (base) of the trap table by default is the boot address, 0xc00000 set at an initial reset. this address can be changed using the ttbr register. exception/interrupt name (peripheral circuit) indicates that interrupt levels can be programmed for each peripheral circuit written. cause of exception/interrupt indicates the cause of the interrupt occurring in each interrupt system. idma ch. indicates that a cause of interrupt which has a numeric value in this column can start up the intelligent dma (idma) to transfer data when a cause of interrupt occurs. the numeric value indicates the idma's channel number. causes of interrupt that do not have a numeric value here cannot start up the idma. priority indicates the priority of interrupts in cases when all interrupt systems are set to the same interrupt level. if two or more causes of interrupt occur simultaneously, interrupt requests are accepted in order of highest priority. interrupt priority varies depending on the interrupt levels set in each interrupt system. however, the priorities of causes of interrupt in the same interrupt system are fixed in the order that they are written here.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 multiplexed interrupts the following vector numbers have two causes of interrupts assigned: no. 84: port input interrupt 8 and spi interrupt no. 85: port input interrupt 9 and usb pdreq interrupt no. 86: port input interrupt 10 and usb interrupt no. 87: port input interrupt 11 and dcsio interrupt at initial reset, these vector addresses are set for port interrupts. each port interrupt allows selection of an input port to be used for generating interrupts from four different ports and spi, usb, or dcsio is included in this selection as a port. therefore, when using the spi, usb, or dcsio interrupt, select it instead of an input port using the port input interrupt select register 3 (0x3003c4 ). also this setting changes the interrupt control registers for the port input interrupt to be used for controlling the spi, usb, or dcsio interrupt. for details of the port input interrupt select register 3 (0x3003c4), see section iii.2.7, details of control registers. maskable interrupt generating conditions a maskable interrupt to the cpu occurs when all of the conditi ons described below are met. ? the interrupt enable register for the cause of interrupt that has occurred is set to 1. ? the ie (interrupt enable) bit of the processor status register (psr) in the cpu is set to 1. ? the cause of interrupt that has occurred has a higher priority level than the value that is set in the psr's interrupt level (il). (the interrupt levels can be set using the interrupt priority register in each interrupt system.) ? no other cause of trap having higher priority, such as nmi, has occurred. ? the cause of interrupt does not invoke idma (the idma request bit is set to 0). when a cause of interrupt occurs, the corresponding cause-of-interrupt flag is set to 1 and the flag remains set until it is reset in the software program. therefore, in no cases can the generated cause of interrupt be inadvertently cleared even if the above conditions are not met when the cause of interrupt has occurred. the interrupt will occur when the above conditions are met. however, when the cause of interrupt invokes idma, the cause of interrupt is reset if the following condition is met. ? the idma transfer counter is not 0. ? interrupts are disabled in the idma control information even if the transfer counter is 0. if two or more maskable causes of interrupt occur simultaneously, the cause of interrupt that has the highest priority is allowed to signal an interrupt request to the cpu. the other interrupts with lower priorities are kept pending until the above conditions are met. the psr and interrupt control register will be detailed later. for details about cause of interrupt generating conditions, refer to the description of each peripheral circuit in this manual. illegal interrupt exception (vector no. 11) there is a time lag between latching the interrupt signal and latching the interrupt vector and level signals caused by the interface specifications between the cpu and the itc. 1 . the cpu latches the interrupt signal sent from the itc. 2 . the cpu latches the interrupt vector and level signals sent from the itc. 3 . the cpu executes the interrupt handler. an illegal interrupt exception (vector no. 11 ) occurs when a register related to the interrupt signal (itc's interrupt enable and cause-of-interrupt flag registers) is altered before the cpu latches the interrupt vector and level signals (between steps 1 and 2 ). therefore, it is very rare but an illegal interrupt exception may occur if an interrupt related register is altered when interrupts to the cpu are in enabled status (ie bit in psr = 1). however, the illegal interrupt exception that occurs does not affect the program execution if any processing is not performed in the exception handler. to avoid an illegal interrupt exception occurring, disable interrupts to the cpu (set ie bit in psr = 0 ) before altering an interrupt related register.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-4 epson s1c33e08 technical manual iii.2.1.2 causes of interrupt and intelligent dma several causes of interrupt can be set so that they can invoke idma startup. when one of these causes of interrupt occurs, idma is started up before an interrupt request to the cpu. the interrupt request to the cpu is generated after idma is completed. (the interrupt request can be disabled by a program.) idma is always started up regardless of how the psr is set. for details, refer to section iii. 2.5, idma invocation. iii.2.1.3 nonmaskable interrupt (nmi) the nonmaskable interrupt (nmi) can be generated by controlling the #nmi pin or using the internal watchdog timer. the vector number of nmi is 7 , with the vector address set to the trap table's starting address + 28 bytes. this interrupt is prioritized over other interrupts and is unconditionally accepted by the cpu. however, since this interrupt may operate erratically if it occurs before the stack pointer (sp) is set up, it is masked in hardware until a write to the sp is completed after an initial reset. for controlling the #nmi input, refer to section iii. 1.3, nmi input. iii.2.1.4 interrupt processing by the cpu the cpu keeps sampling interrupt requests every cycle. when the cpu accepts an interrupt request, it enters trap processing after completing execution of the instruction that was being executed. the following lists the contents executed in trap processing. (1 ) the psr and the current program counter (pc) value are saved to the stack. (2 ) the ie bit of the psr is reset to 0 (following maskable interrupts are disabled). (3 ) the il of the psr is set to the priority level of the accepted interrupt (nmi does not have its interrupt level changed). (4 ) the vector of the generated cause of interrupt is loaded into the pc, thus executing the interrupt processing routine. thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in ( 2 ). multiple interrupts can also be handled by setting the ie bit to 1 in the interrupt processing routine. in this case, since the il has been changed in (3), only an interrupt that has a higher priority than that of the currently processed interrupt is accepted. when the interrupt processing routine is terminated by the reti instruction, the psr is restored to its previous status before the interrupt has occurred. the program restarts processing after branching to the instruction next to the one that was being executed when the interrupt occurred. iii.2.1.5 clearing standby mode by interrupts the standby modes (halt and sleep) are cleared by an nmi or a maskable interrupt. all maskable interrupts can be used to clear halt mode. in sleep mode, since the clock supply to the peripheral circuit is disabled, interrupts from the peripheral circuits except rtc and i/o ports cannot be used. interrupts that can be used to clear basic halt mode: nmi and all maskable interrupts interrupts that can be used to clear sleep mode: nmi, i/o port interrupts, and rtc interrupt when the cpu is released from halt mode by an interrupt, it enters a program executable state by trap processing and executes an interrupt handling routine for the interrupt generated. in trap processing of the cpu, the address for the instruction next to halt is saved to the stack as a return address from the interrupt handling routine, so that the reti instruction in the interrupt handling routine branches t o the instruction next to halt. the cpu is released from halt mode when the itc asserts the interrupt signal to be sent to the cpu. in other words, when a cause-of-interrupt flag of the interrupts that have been enabled by the interrupt enable bits in the itc is set to 1 , the cpu can be released from halt mode even if the psr is set to disable interrupts. however, in this case the cpu does not execute the interrupt handling routine. the #nmi signal releases the cpu from halt mode when it goes low level.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 when the cpu is reawaken from sleep mode by an interrupt, it enters a program executable state by trap processing and executes an interrupt handling routine for the interrupt generated. in trap processing of the cpu, the address for the instruction next to slp is saved to the stack as a return address from the interrupt handling routine, so that the reti instruction in the interrupt handling routine bra nches to the instruction next to slp. cause-of-interrupt flags in the interrupt controller (itc) cannot be set in sleep mode as the clock is not supplied to the itc in sleep mode. therefore, when the clock is not supplied to the itc, the interrupt signals from the interrupt sources that have been enabled to generate an interrupt are input to the cmu through the itc and used to wake up the cpu from a standby mode. in this case, the cause-of-interrupt flag is set after the clock has started supplying to the itc. the cpu can wake up from sleep mode by a cause of interrupt as described above even if the psr is set to disable interrupts, note however, that the cpu does not execute the interrupt handling routine. the #nmi signal releases the cpu from sleep mode when it goes l ow level. notes : ? in sleep mode, there is a time lag between input of an interrupt signal for wakeup and the start of the clock supply to the itc, so a delay will occur until the interrupt controller (itc) sets the cause-of-interrupt flag. therefore, no interrupt will occur if the interrupt signal is deasserted before the clock is supplied to the itc, as the cause-of-interrupt flag in the itc is not set. furthermore, additional time is needed for the cpu to accept the interrupt request from the itc, the cpu may execute a few instructions that follow the slp instruction before it starts the interrupt processing. the same problem may occur when the cpu wakes up from sleep mode by nmi. no interrupt will occur if the #nmi signal is deasserted before the clock is supplied, as the nmi flag is not set. ? if the cause of interrupt used to restart from the standby mode has been set to invoke the idma, the idma is started up by that interrupt. if an interrupt to be generated upon completion of idma is disabled at the setting of the idma side, no interrupt request is signaled to the cpu. therefore, the cpu remains idle until the next interrupt request is generated.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-6 epson s1c33e08 technical manual iii.2.2 trap table the c33 pe core allows the base (starting) address of the trap table to be set by the ttbr register. after an initial reset, the ttbr register is set to 0xc00000. bits 9 to 0 in the ttbr register are fixed at 0 . therefore, the trap table starting address always begins with a 1kb boundary address.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.2.3 itc operating clock the itc is clocked by the itc operating clock (itc_clk = mclk) generated by the cmu. for details on how to set mclk and control the clock, see section iii. 1, clock management unit (cmu). controlling supply of the itc operating clock the itc operating clock is supplied to the itc with default settings. when this clock supply is turned off, the itc registers except the interrupt cause flag registers and idma related registers (interrupt priority registers, interrupt enable registers, and hsdma trigger setup registers) are disabled for writing. however, the cause-of-interrupt flags can be set by the corresponding interrupt request signals from the peripheral circuit, thus interrupt requests to the cpu can also be generated if the interrupt has been enabled. the cause-of-interrupt flag can be cleared by software. moreover, hsdma can be invoked normally. idma cannot be invoked. however, an interrupt sets the idma request bit when the idma enable bit has been set to 1 (idma request enabled). (the idma does not activate even if the idma request bit is set.) the clock supply can be controlled by itc_cke (d 2/0x301b04). ? itc_cke : itc clock control bit in the gated clock control register 1 (d2/0x301b04) clock state in standby mode the supply of the itc operating clock stops depending on the t ype of standby mode. halt mode: the clock is supplied the same way as in normal mode. sleep mode: the clock supply stops. therefore, the itc also stops operating in sleep mode.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-8 epson s1c33e08 technical manual iii.2.4 control of maskable interrupts iii.2.4.1 structure of the interrupt controller the interrupt controller is configured as shown in figure iii. 2.4.1.1. cpu interrupt priority judgment (with interrupt level) interrupt vector generator cause-of-interrupt flag interrupt enable idma request idma enable interrupt request interrupt level interrupt vector key input x hsdma x #dmareq x input software trigger 16-bit timer x serial i/f x a/d port input x rtc idma lcdc spi usb dcsio i 2 s cpu itc idma request priority judgment (without interrupt level) idma channel number generator cause-of-interrupt flag interrupt enable idma request idma enable idma request idma channel number idma completion reset a reset b reset c ch. x hsdma request hsdma trigger selection circuit idma hsdma ch. x causes of interrupt ? ? ? figure iii.2.4.1.1 configuration of interrupt controller the following sections explain the functions of the registers used to control interrupts. iii.2.4.2 processor status register (psr) the psr is a special register incorporated in the core cpu and contains control bits to enable or disable an interrupt request to the cpu. interrupt enable (ie) bit: psr[ 4] this bit is used to enable or disable an interrupt request to the cpu. when this bit is set to 1 , the cpu is enabled to accept a maskable interrupt request. when this bit is reset to 0 , no maskable interrupt request is accepted by the cpu. when the cpu accepts an interrupt request (or some other trap occurs), it saves the psr to the stack and resets the ie bit to 0 . consequently, no maskable interrupt request occurring thereafter will be accepted unless the ie bit is set to 1 in software program or the interrupt (trap) processing routine is terminated by the reti instruction. the ie bit is initialized to 0 (interrupts disabled) by an initial reset. interrupt level (il): psr[ 11:8] the il bits disable the interrupts whose priorities are below the set interrupt level. for example, if the interrupt level set in the il is 3 , the interrupts whose priorities are set below 3 in the interrupt priority register (described later) are not accepted by the cpu even if the ie bit is set to 1 . the il and the interrupt priority register together allow you to control the interrupt priorities in each interrupt system. for details about the interrupt levels, refer to section iii.2.4.4, interrupt priority register and interrupt levels. when the cpu accepts a maskable interrupt request, it saves the psr to the stack and sets the il to the accepted interrupt's priority level. therefore, even when the ie bit is set to 1 in the interrupt processing routine, no interrupts whose priority levels are equal or below that of the interrupt currently being processed are accepted unless the il is rewritten. the il is restored to its previous status when the interrupt processing routine is terminated by the reti instruction. the il is rewritten for only maskable interrupts and not for any other traps (except a reset). the il is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset. note : as the c33 pe core function, the il allows interrupt levels to be set in the range of 0 to 15. however, since the interrupt priority register in the itc consists of three bits, interrupt levels in each interrupt system can only be set for up to 8.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.2.4.3 cause-of-interrupt flag and interrupt enable register a cause-of-interrupt flag and an interrupt enable register are provided for each cause of maskable interrupt. cause-of-interrupt flag the cause-of-interrupt flag is set to 1 when the corresponding cause of interrupt occurs. reading the flag enables you to determine what caused an interrupt, making it unnecessary to resort to the cpu's trap processing. the cause-of-interrupt flag is reset by writing data in software. note that the method by which this flag is reset can be selected from the software application using either of the two methods described below. this selection is accomplished using rstonly (d 0/0x30029f). ? rstonly : cause-of-interrupt flag reset method select bit in the flag set/reset method select register (d0/0x30029f) ? reset-only method (default) this method is selected (rstonly (d 0/0x30029f) = 1) when initially reset. with this method, the cause-of-interrupt flag is reset by writing 1 . although multiple cause-of-interrupt flags are located at the same address of the interrupt control register, the cause-of-interrupt flags for which 0 has been written can be neither set nor reset. therefore, this method ensures that only a specific cause-of-interrupt flag is reset. however, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that a cause-of-interrupt flag that has been set to 1 is reset by writing. in this method, no cause-of-interrupt flag can be set in the s oftware application. ? read/write method this method is selected by writing 0 to rstonly (d0/0x30029f). when this method is used, cause-of-interrupt flags can be read and written as for other registers. therefore, the flag is reset by writing 0 and set by writing 1 . in this case, all cause-of-interrupt flags for which 0 has been written are reset. even in a read-modify-write operation, a cause of interrupt can occur between the read and the write, so be careful when using this method. since cause-of-interrupt flags are not initialized by an initial reset, be sure to reset them before enabling interrupts. note : even when a maskable interrupt request is accepted by the cpu and control branches off to the interrupt processing routine, the cause-of-interrupt flag is not reset. consequently, if control is returned from the interrupt processing routine by the reti instruction without resetting the cause- of-interrupt flag in a program, the same cause of interrupt occurs again. rstonly (d0/0x30029f), which is used to select a cause-of-interrupt flag reset method, must be set to 1 (reset-only method) when the mp3 decoder function is used. for details about cause of interrupt generating conditions, refer to the description of each peripheral circuit in this manual. interrupt enable register this register controls the output of an interrupt request to the cpu. only when the interrupt enable bit of this register is set to 1 can an interrupt request to the cpu be enabled by an occurrence of the corresponding cause of interrupt. if the bit is set to 0 , no interrupt request is made to the cpu even when the corresponding cause of interrupt occurs. interrupt enable bits can be read and written as for other registers. therefore, the interrupt enable bit is reset by writing 0 and set by writing 1 . by reading this register, its setup status can be checked at any time. settings of the interrupt enable register do not affect the operation of cause-of-interrupt flags, so when a cause of interrupt occurs the cause-of-interrupt flag is set to 1 even if the corresponding interrupt enable bit is set to 0. when initially reset, the interrupt enable register is set to 0 (interrupts are disabled). in cases when idma is started up by occurrence of a cause of interrupt or when clearing standby mode (halt or sleep mode) too, the corresponding interrupt enable bit must be set to 1.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-10 epson s1c33e08 technical manual the interrupt controller outputs an interrupt request to the cpu when the following conditions are met: ? a cause of interrupt has occurred and the cause-of-interrupt flag is set to 1. ? the bit of the interrupt enable register for the cause of interrupt that has occurred is set to 1 (interrupt enable). ? the bit of the idma request register for the cause of interrupt that has occurred is set to 0 (interrupt request). if two or more causes of interrupt occur simultaneously, the cause of interrupt that has the highest priority is allowed to signal an interrupt request to the cpu. (see the following section.) when these conditions are met, the interrupt controller outputs an interrupt request signal to the cpu along with the setup content (interrupt level) of the interrupt priority register for the generated interrupt system and its vector number. these signals remain asserted until the cause-of-interrupt flag is reset to 0 or the corresponding bit of the interrupt enable register is set to 0 (interrupts are disabled) or until some other cause of interrupt of higher priority occurs. they are not cleared if the cpu simply accepts the interrupt request. iii.2.4.4 interrupt priority register and interrupt levels the interrupt priority register is a 3 -bit register provided for each interrupt system. it allows the interrupt levels of a given interrupt system to be set in the range of 0 to 7 . the default priorities shown in table iii.2.1.1.1 can be modified according to system requirements by this setting. the value set in this register is used by the interrupt controller and the cpu as described below. roles of the interrupt priority register in the interrupt controller if two or more causes of interrupt that have been enabled by the interrupt enable register occur simultaneously, the cause of interrupt in the interrupt system whose interrupt priority register contains the greatest value is allowed by the interrupt controller to signal an interrupt request to the cpu. if a cause of interrupt occurs in two or more interrupt systems having the same value, the interrupt priority is resolved according to the default priorities in table iii. 2.1.1.1 . causes of interrupt in the same interrupt system also have their priorities resolved according to the order in table iii. 2.1.1.1. other causes of interrupt are kept pending until all interrupts of higher priority are accepted by the cpu. when outputting an interrupt request signal to the cpu, the interrupt controller outputs the content of the interrupt priority register to the cpu along with it. if another cause of interrupt of higher priority occurs during outputting an interrupt request signal, the interrupt controller changes the vector number and interrupt level to those of the new cause of interrupt before they are output to the cpu. the first interrupt request is left pending. roles of the interrupt priority register in cpu processing the cpu compares the content of the interrupt priority register received from the interrupt controller with the interrupt level that is set in the il of the psr to determine whether or not to accept the interrupt request. ie bit = 1 & il < interrupt priority register: the interrupt request is accepted ie bit = 1 & il interrupt priority register: the interrupt request is rejected before interrupts can be controlled by an interrupt level, the interrupt disabling level must be written to the il. for example, if the value written to the il is 3 , only the interrupts whose interrupt levels written in the interrupt priority register are 4 or more will be accepted. when an interrupt is accepted, the interrupt level that is set in its interrupt priority register is written to the il. as a result, the interrupt requests below that interrupt level can no longer be accepted. if the interrupt priority register for an interrupt is set to 0 , the interrupt is disabled. however, invoking idma by means of a cause of interrupt works fine. notes : ? as the c33 pe core function, the il allows interrupt levels to be set in the range of 0 to 15 . however, since the interrupt priority register in the itc consists of three bits, interrupt levels in each interrupt system can only be set for up to 8 . ? multiple interrupts can also be handled by rewriting the interrupt level to the il in the interrupt processing routine. however, if the interrupt level of the il is set below the current level and the ie is set to enable interrupts before resetting the cause-of-interrupt flag after an interrupt has occurred, the same interrupt may occur again.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.2.5 idma invocation the causes of interrupt for which idma channel numbers are written in table iii. 2.1.1.1 have the function to invoke the intelligent dma (idma). idma request register the idma request register is used to specify the cause of interrupt that invoke an idma transfer. if an idma request bit is set to 1 , the idma request will be generated when the corresponding cause of interrupt occurs. when the idma request bit is set to 0 , the corresponding cause of interrupt does not invoke idma and a normal interrupt processing will be performed. the idma request register is set to 0 by an initial reset. the method by which this register is set can be selected from the software application using either of the two methods described below. this selection is accomplished using idmaonly (d 1/0x30029f). ? idmaonly : idma request register set method select bit in the flag set/reset method select register (d1/0x30029f) ? set-only method (default) this method is selected (idmaonly (d 1/0x30029f) = 1) when initially reset. with this method, an idma request bit is set by writing 1 . although multiple idma request bits are located in the idma request register, the idma request bits for which 0 has been written can be neither set nor reset. therefore, this method ensures that only a specific idma request bit is set. however, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an idma request bit that has been set to 1 is not reset by writing. ? read/write method this method is selected by writing 0 to idmaonly (d1/0x30029f). when this method is used, idma request bits can be read and written as for other registers. therefore, the idma request bit is reset by writing 0 and set by writing 1 . in this case, all idma request bits for which 0 has been written are reset. even in a read-modify-write operation, an idma request bit can be reset by the hardware between the read and the write, so be careful when using this method. idma enable register to perform idma transfer using a cause of interrupt, the corresponding bit of the idma enable register must be set to 1 . if this bit is set to 0 , the cause of interrupt cannot invoke the idma channel. the idma enable register is set to 0 by an initial reset. the idma enable register allows selection of a set method (set-only method or read/write method) similar to the idma request register. this selection is accomplished using denonly (d 2/0x30029 f). see the above explanation for the set method. ? denonly : idma enable register set method select bit in the flag set/reset method select register (d2/0x30029f) invoking idma before idma can be invoked by the occurrence of a cause of interrupt, the corresponding bits of the idma request and idma enable registers must be set to 1 . then when a cause of interrupt occurs, the interrupt request to the cpu is made pending and the corresponding idma channel is invoked. the dma transfer is performed according to the control information of that idma channel. the interrupt level set by the interrupt priority register of the itc does not affect the idma invocation. the idma request can be accepted even if the interrupt level of the cpu is higher than the set value of the interrupt priority register. however, when generating the interrupt request to the cpu after the idma transfer is completed, the interrupt is controlled using the interrupt level set by the interrupt priority register. an idma invocation request is accepted even when the interrupt enable register and psr of the cpu is set to disable interrupts. it is also necessary that the control information for the idma channel has been set.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-12 epson s1c33e08 technical manual interrupt after idma transfer to generate an interrupt after completion of idma transfer: the interrupt request that has been kept pending can be generated after completion of the dma transfer. in this case, the interrupt must be enabled by the idma control information (dinten = 1 ) in addition to the interrupt controller and the psr register settings. however, if the transfer counter set for the selected idma channel does not reach the terminal count of 0 after the number of transfers set have been performed, the cause-of-interrupt flag is reset and no interrupt request is generated. the transfer counter is decremented by 1 for each transfer performed. if the transfer counter is decremented to 0 when dinten is set to 1 , the cause-of-interrupt flag is not reset and the idma request bit is cleared to 0 . an interrupt request is generated if other interrupt conditions are met. the idma request bit must be set up again in order for idma to be invoked when a cause of interrupt occurs next time as well. to ensure that no unwanted idma request occurs, this setup must be performed after resetting the cause-of-interrupt flag. figure iii. 2.5.1 shows the hardware sequence when dinten is set to 1. 3 2 1 0 idma trigger (cause-of-interrupt flag) transfer counter data transfer reset a signal (reset cause-of-interrupt flag) reset b signal (reset idma request bit) idma request bit interrupt request figure iii.2.5.1 sequence when dinten = 1 to disable an interrupt after completion of idma transfer: if an interrupt has been disabled in the idma control information (dinten = 0 ), the interrupt is not generated since the cause-of-interrupt flag is reset when the transfer counter becomes 0. in this case, the idma request bit remains set to 1 without being cleared. however, the idma enable bit is cleared, so the following idma request by the same cause of interrupt will be disabled. figure iii. 2.5.2 shows the hardware sequence when dinten is set to 0. 3 2 1 0 idma trigger (cause-of-interrupt flag) transfer counter data transfer reset a signal (reset cause-of-interrupt flag) reset b signal (reset idma request bit) reset c signal (reset idma enable bit) idma request bit idma enable bit l "1" figure iii.2.5.2 sequence when dinten = 0 for details on idma, refer to section ii. 2, intelligent dma (idma).
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.2.6 hsdma invocation some causes of interrupt can invoke high-speed dmas (hsdma). hsdma trigger set-up register the dma block contains four channel of hsdma circuit. each chan nel allows selection of a cause of interrupt as the trigger. hsd xs[3:0] (0x300298C0x300299) is used for this selection. ? hsd0s[3:0] : ch.0 trigger set-up bits in the hsdma ch.0C1 trigger set-up register (d[3:0]/0x300298) ? hsd1s[3:0] : ch.1 trigger set-up bits in the hsdma ch.0C1 trigger set-up register (d[7:4]/0x300298) ? hsd2s[3:0] : ch.2 trigger set-up bits in the hsdma ch.2C3 trigger set-up register (d[3:0]/0x300299) ? hsd3s[3:0] : ch.3 trigger set-up bits in the hsdma ch.2C3 trigger set-up register (d[7:4]/0x300299) table iii. 2.6.1 shows the setting value and the corresponding trigger source. table iii. 2.6.1 hsdma trigger source v alue 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 ch.0 trigger sour ce softw are tr igger #dmareq0 input (f alling edge) #dmareq0 input (r ising edge) po rt 0 input po rt 4 input (reser v ed) 16-bit timer 0 compare b 16-bit timer 0 compare a 16-bit timer 4 compare b i 2 s left ser ial i/f ch.0 rx b uff er full ser ial i/f ch.0 tx b uff er empty a/d con v ersion completion po rt 8 input (spi interr upt) po rt 12 input ch.1 trigger sour ce softw are tr igger #dmareq1 input (f alling edge) #dmareq1 input (r ising edge) po rt 1 input po rt 5 input (reser v ed) 16-bit timer 1 compare b 16-bit timer 1 compare a 16-bit timer 5 compare b i 2 s r ight ser ial i/f ch.1 rx b uff er full ser ial i/f ch.1 tx b uff er empty a/d con v ersion completion po rt 9 input (usb pdreq) po rt 13 input ch.2 trigger sour ce softw are tr igger #dmareq2 input (f alling edge) #dmareq2 input (r ising edge) po rt 2 input po rt 6 input (reser v ed) 16-bit timer 2 compare b 16-bit timer 2 compare a (reser v ed) spi transmit dma request ser ial i/f ch.2 rx b uff er full ser ial i/f ch.2 tx b uff er empty a/d con v ersion completion po rt 10 input (usb interr upt) po rt 14 input ch.3 trigger sour ce softw are tr igger #dmareq3 input (f alling edge) #dmareq3 input (r ising edge) po rt 3 input po rt 7 input (reser v ed) 16-bit timer 3 compare b 16-bit timer 3 compare a (reser v ed) spi receiv e dma request (reser v ed) (reser v ed) a/d con v ersion completion po rt 11 input (dcsio interr upt) po rt 15 input invoking hsdma by selecting a cause of interrupt with the hsdma trigger set-up register, the hsdma channel is invoked when the selected cause of interrupt occurs. the interrupt control bits (cause-of-interrupt flag, interrupt enable register, idma request register, interrupt priority register) do not affect this invocation. the interrupt request to the cpu by the cause of interrupt that invokes hsdma is output two clocks (mclk) after the hsdma request, so the dma transfer and interrupt handling are performed concurrently when the cpu runs with the instructions in the cache. however, when the interrupt handler contains an instruction that accesses a peripheral circuit, the execution of the instruction is pending until the dma transfer is completed since the bus is used by the hsdma. before hsdma can be invoked by the occurrence of a cause of interrupt, it is necessary that dma be enabled on the hsdma side by setting the control register for hsdma transfer. for details about hsdma, refer to section ii. 1, high-speed dma (hsdma).
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-14 epson s1c33e08 technical manual iii.2.7 details of control registers table iii. 2.7.1 list of itc registers address 0x00300260 0x00300261 0x00300262 0x00300263 0x00300264 0x00300265 0x00300266 0x00300267 0x00300268 0x00300269 0x0030026a 0x0030026b 0x0030026c 0x0030026d 0x0030026e 0x00300270 0x00300271 0x00300272 0x00300273 0x00300274 0x00300276 0x00300277 0x00300278 0x00300279 0x00300280 0x00300281 0x00300282 0x00300283 0x00300284 0x00300286 0x00300287 0x00300288 0x00300289 0x00300290 0x00300291 0x00300292 0x00300293 function sets interrupt level for port input 0C1 interrupts. sets interrupt level for port input 2C3 interrupts. sets interrupt level for key input interrupts. sets interrupt level for hsdma ch.0C1 interrupts. sets interrupt level for hsdma ch.2C3 interrupts. sets interrupt level for idma interrupts. sets interrupt level for 16-bit timer 0C1 interrupts. sets interrupt level for 16-bit timer 2C3 interrupts. sets interrupt level for 16-bit timer 4C5 interrupts. sets interrupt level for lcdc and serial i/f ch.0 interrupts. sets interrupt level for serial i/f ch.1 and a/d converter interrupts. sets interrupt level for rtc interrupts. sets interrupt level for port input 4C5 interrupts. sets interrupt level for port input 6C7 interrupts. sets interrupt level for serial i/f ch.2 and spi interrupts. enables key input and port input 0C3 interrupts. enables dma interrupts. enables 16-bit timer 0C1 interrupts. enables 16-bit timer 2C3 interrupts. enables 16-bit timer 4C5 interrupts. enables serial i/f ch.0C1 interrupts. enables port input 4C7, rtc and a/d interrupts. enables lcdc interrupts. enables serial i/f ch.2 and spi interrupts. indicates/resets key input and port input 0C3 interrupt status. indicates/resets dma interrupt status. indicates/resets 16-bit timer 0C1 interrupt status. indicates/resets 16-bit timer 2C3 interrupt status. indicates/resets 16-bit timer 4C5 interrupt status. indicates/resets serial i/f ch.0C1 interrupt status. indicates/resets port input 4C7, rtc and a/d converter interrupt status. indicates/resets lcdc interrupt status. indicates/resets serial i/f ch.2 and spi interrupt status. sets idma invocation by port input 0C3, hsdma ch.0C1 and 16-bit timer 0. sets idma invocation by 16-bit timer 1C4. sets idma invocation by 16-bit timer 5 and serial i/f ch.0. sets idma invocation by serial i/f ch.1, a/d converter, and port input 4C7. register name port input 0C1 interrupt priority register (pint_pp01l) port input 2C3 interrupt priority register (pint_pp23l) key input interrupt priority register (pint_pk01l) hsdma ch.0C1 interrupt priority register (pint_phsd01l) hsdma ch.2C3 interrupt priority register (pint_phsd23l) idma interrupt priority register (pint_pdm) 16-bit timer 0C1 interrupt priority register (pint_p16t01) 16-bit timer 2C3 interrupt priority register (pint_p16t23) 16-bit timer 4C5 interrupt priority register (pint_p16t45) lcdc, serial i/f ch.0 interrupt priority register (pint_plcdc_psi00) serial i/f ch.1, a/d interrupt priority register (pint_psi01_pad) rtc interrupt priority register (pint_prtc) port input 4C5 interrupt priority register (pint_pp45l) port input 6C7 interrupt priority register (pint_pp67l) serial i/f ch.2, spi interrupt priority register (pint_psi02_pspi) key input, port input 0C3 interrupt enable register (pint_ek01_ep03) dma interrupt enable register (pint_edma) 16-bit timer 0C1 interrupt enable register (pint_e16t01) 16-bit timer 2C3 interrupt enable register (pint_e16t23) 16-bit timer 4C5 interrupt enable register (pint_e16t45) serial i/f ch.0C1 interrupt enable register (pint_esif01) port input 4C7, rtc, a/d interrupt enable register (pint_ep47_ertc_ead) lcdc interrupt enable register (pint_elcdc) serial i/f ch.2, spi interrupt enable register (pint_esif2_espi ) key input, port input 0C3 interrupt cause flag register (pint_fk01_fp03) dma interrupt cause flag register (pint_fdma) 16-bit timer 0C1 interrupt cause flag register (pint_f16t01) 16-bit timer 2C3 interrupt cause flag register (pint_f16t23) 16-bit timer 4C5 interrupt cause flag register (pint_f16t45) serial i/f ch.0C1 interrupt cause flag register (pint_fsif01) port input 4C7, rtc, a/d interrupt cause flag register (pint_fp47_frtc_fad) lcdc interrupt cause flag register (pint_flcdc) serial i/f ch.2, spi interrupt cause flag register (pint_fsif2_fspi) port input 0C3, hsdma ch.0C1, 16-bit timer 0 idma request register (pidmareq_rp03_rhs_r16t0) 16-bit timer 1C4 idma request register (pidmareq_r16t14) 16-bit timer 5, serial i/f ch.0 idma request register (pidmareq_r16t5_rsif0) serial i/f ch.1, a/d, port input 4C7 idma request register (pidmareq_rsif1_rad_rp47) siz e 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 address 0x00300294 0x00300295 0x00300296 0x00300297 0x00300298 0x00300299 0x0030029a 0x0030029b 0x0030029c 0x0030029f 0x003002a0 0x003002a1 0x003002a2 0x003002a3 0x003002a4 0x003002a6 0x003002a7 0x003002a9 0x003002aa 0x003002ac 0x003002ad 0x003002ae 0x003002af 0x003003c4 function enables idma requests by port input 0C3, hsdma ch.0C1, and 16-bit timer 0. enables idma requests by 16-bit timer 1C4. enables idma requests by 16-bit timer 5 and serial i/f ch.0. enables idma requests by serial i/f ch.1, a/d converter, and port input 4C7. selects hsdma ch.0C1 trigger sources. selects hsdma ch.2C3 trigger sources. invokes hsdma. sets idma invocation by lcdc, serial i/f ch.2, and spi . enables idma requests by lcdc, serial i/f ch.2, and spi . selects flag set/reset method. sets interrupt level for port input 8C9 interrupts. sets interrupt level for port input 10C11 interrupts. sets interrupt level for port input 12C13 interrupts. sets interrupt level for port input 14C15 interrupts. sets interrupt level for i 2 s interrupts. enables port input 8C15 interrupts. enables i 2 s interrupts. indicates/resets port input 8C15 interrupt status. indicates/resets i 2 s interrupt status. sets idma invocation by port input 8C15. sets idma invocation by i 2 s. enables idma requests by port input 8C15. enables idma requests by i 2 s. selects ports used for fpt8Cfpt11 port input interrupts. (gpio register) register name port input 0C3, hsdma ch.0C1, 16-bit timer 0 idma enable register (pidmaen_dep03_dehs_de16t0) 16-bit timer 1C4 idma enable register (pidmaen_de16t14) 16-bit timer 5, serial i/f ch.0 idma enable register (pidmaen_de16t5_desif0) serial i/f ch.1, a/d, port input 4C7 idma enable register (pidmaen_desif1_dead_dep47) hsdma ch.0C1 trigger set-up register (phsdma_htgr1) hsdma dma ch.2C3 trigger set-up register (phsdma_htgr2) hsdma software trigger register (phsdma_hsofttgr) lcdc, serial i/f ch.2, spi idma request register (pidmareq_rlcdc_rsif2_rspi) lcdc, serial i/f ch.2, spi idma enable register (pidmaen_delcdc_desif2_despi) flag set/reset method select register (prst_reset) port input 8C9 interrupt priority register (pint_pp89l) port input 10C11 interrupt priority register (pint_pp1011l) port input 12C13 interrupt priority register (pint_pp1213l) port input 14C15 interrupt priority register (pint_pp1415l) i 2 s interrupt priority register (pint_pi2s) port input 8C15 interrupt enable register (pint_ep815) i 2 s interrupt enable register (pint_ei2s) port input 8C15 interrupt cause flag register (pint_fp815) i 2 s interrupt cause flag register (pint_fi2s) port input 8C15 idma request register (pidmareq_rp815) i 2 s idma request register (pidmareq_ri2s) port input 8C15 idma enable register (pidmaen_dep815) i 2 s idma enable register (pidmaen_dei2s) port input interrupt select register 3 (ppintsel_spt811) siz e 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 the following describes each itc control register. the itc control registers are mapped in the 8 -bit device area from 0x300260 to 0x3002 af, and can be accessed in units of bytes. notes : ? when setting the itc control registers, be sure to write a 0, and not a 1 , for all reserved bits. ? the control registers for port input interrupts 8 to 11 change their functions for the spi, usb, and dcsio interrupts by setting the port input interrupt select register 3 (0x3003c4). ? address 0x300275 is a reserved register. be sure not to write 1 to d[3:0 ] in this address.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-16 epson s1c33e08 technical manual 0x300260: port input 0C1 interrupt priority register (pint_pp01l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp1l2 pp1l1 pp1l0 C pp0l2 pp0l1 pp0l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 1 interrupt level reserved port input 0 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300260 (b) port input 0C1 interrupt priority register (pint_pp01l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pp1l[2:0]: port input 1 interrupt level bits sets the priority level of the port input 1 interrupt. d3 reserved d[2:0] pp0l[2:0]: port input 0 interrupt level bits sets the priority level of the port input 0 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300261: port input 2C3 interrupt priority register (pint_pp23l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp3l2 pp3l1 pp3l0 C pp2l2 pp2l1 pp2l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 3 interrupt level reserved port input 2 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300261 (b) port input 2C3 interrupt priority register (pint_pp23l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pp3l[2:0]: port input 3 interrupt level bits sets the priority level of the port input 3 interrupt. d3 reserved d[2:0] pp2l[2:0]: port input 2 interrupt level bits sets the priority level of the port input 2 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-18 epson s1c33e08 technical manual 0x300262: key input interrupt priority register (pint_pk01l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pk1l2 pk1l1 pk1l0 C pk0l2 pk0l1 pk0l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved key input 1 interrupt level reserved key input 0 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300262 (b) key input interrupt priority register (pint_pk01l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pk1l[2:0]: key input 1 interrupt level bits sets the priority level of the key input 1 interrupt. d3 reserved d[2:0] pk0l[2:0]: key input 0 interrupt level bits sets the priority level of the key input 0 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300263: hsdma ch.0C1 interrupt priority register (pint_phsd01l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C phsd1l2 phsd1l1 phsd1l0 C phsd0l2 phsd0l1 phsd0l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved hsdma ch.1 interrupt level reserved hsdma ch.0 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300263 (b) hsdma ch.0C1 interrupt priority register (pint_phsd01l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] phsd1l[2:0]: hsdma ch.1 interrupt level bits sets the priority level of the hsdma ch. 1 interrupt. d3 reserved d[2:0] phsd0l[2:0]: hsdma ch.0 interrupt level bits sets the priority level of the hsdma ch. 0 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-20 epson s1c33e08 technical manual 0x300264: hsdma ch.2C3 interrupt priority register (pint_phsd23l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C phsd3l2 phsd3l1 phsd3l0 C phsd2l2 phsd2l1 phsd2l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved hsdma ch.3 interrupt level reserved hsdma ch.2 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300264 (b) hsdma ch.2C3 interrupt priority register (pint_phsd23l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] phsd3l[2:0]: hsdma ch.3 interrupt level bits sets the priority level of the hsdma ch. 3 interrupt. d3 reserved d[2:0] phsd2l[2:0]: hsdma ch.2 interrupt level bits sets the priority level of the hsdma ch. 2 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300265: idma interrupt priority register (pint_pdm) name address register name bit function setting init. r/w remarks C 0 to 7 C pdm2 pdm1 pdm0 d7C3 d2 d1 d0 reserved idma interrupt level C x x x C r/w 0 when being read. 00300265 (b) idma interrupt priority register (pint_pdm) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d[7:3] reserved d[2:0] pdm[2:0]: idma interrupt level bits sets the priority level of the idma interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-22 epson s1c33e08 technical manual 0x300266: 16-bit timer 0C1 interrupt priority register (pint_p16t01) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C p16t12 p16t11 p16t10 C p16t02 p16t01 p16t00 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 1 interrupt level reserved 16-bit timer 0 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300266 (b) 16-bit timer 0C1 interrupt priority register (pint_p16t01) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] p16t1[2:0]: 16-bit timer 1 interrupt level bits sets the priority levels of the 16-bit timer 1 interrupt. d3 reserved d[2:0] p16t0[2:0]: 16-bit timer 0 interrupt level bits sets the priority levels of the 16-bit timer 0 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300267: 16-bit timer 2C3 interrupt priority register (pint_p16t23) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C p16t32 p16t31 p16t30 C p16t22 p16t21 p16t20 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 3 interrupt level reserved 16-bit timer 2 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300267 (b) 16-bit timer 2C3 interrupt priority register (pint_p16t23) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] p16t3[2:0]: 16-bit timer 3 interrupt level bits sets the priority levels of the 16-bit timer 3 interrupt. d3 reserved d[2:0] p16t2[2:0]: 16-bit timer 2 interrupt level bits sets the priority levels of the 16-bit timer 2 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-24 epson s1c33e08 technical manual 0x300268: 16-bit timer 4C5 interrupt priority register (pint_p16t45) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C p16t52 p16t51 p16t50 C p16t42 p16t41 p16t40 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 5 interrupt level reserved 16-bit timer 4 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300268 (b) 16-bit timer 4C5 interrupt priority register (pint_p16t45) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] p16t5[2:0]: 16-bit timer 5 interrupt level bits sets the priority levels of the 16-bit timer 5 interrupt. d3 reserved d[2:0] p16t4[2:0]: 16-bit timer 4 interrupt level bits sets the priority levels of the 16-bit timer 4 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300269: lcdc, serial i/f ch.0 interrupt priority register (pint_plcdc_psi00) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C psio02 psio01 psio00 C plcdc2 plcdc1 plcdc0 d7 d6 d5 d4 d3 d2 d1 d0 reserved serial interface ch.0 interrupt level reserved lcdc interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300269 (b) lcdc, serial i/f ch.0 interrupt priority register (pint_plcdc_ psi00) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] psio0[2:0]: serial interface ch.0 interrupt level bits sets the priority levels of the serial interface ch. 0 interrupt. d3 reserved d[2:0] plcdc[2:0]: lcdc interrupt level bits sets the priority levels of the lcdc interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-26 epson s1c33e08 technical manual 0x30026a: serial i/f ch.1, a/d interrupt priority register (pint_psi01_pad) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pad2 pad1 pad0 C psio12 psio11 psio10 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d converter interrupt level reserved serial interface ch.1 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 0030026a (b) serial i/f ch.1, a/d interrupt priority register (pint_psi01_pad) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pad[2:0]: a/d converter interrupt level bits sets the priority levels of the a/d converter interrupt. d3 reserved d[2:0] psio1[2:0]: serial interface ch.1 interrupt level bits sets the priority levels of the serial interface ch. 1 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30026b: rtc interrupt priority register (pint_prtc) name address register name bit function setting init. r/w remarks C 0 to 7 C prtc2 prtc1 prtc0 d7C3 d2 d1 d0 reserved rtc interrupt level C x x x C r/w writing 1 not allowed. 0030026b (b) rtc interrupt priority register (pint_prtc) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d[7:3] reserved d[2:0] prtc[2:0]: rtc interrupt level bits sets the priority level of the rtc interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-28 epson s1c33e08 technical manual 0x30026c: port input 4C5 interrupt priority register (pint_pp45l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp5l2 pp5l1 pp5l0 C pp4l2 pp4l1 pp4l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 5 interrupt level reserved port input 4 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 0030026c (b) port input 4C5 interrupt priority register (pint_pp45l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pp5l[2:0]: port input 5 interrupt level bits sets the priority level of the port input 5 interrupt. d3 reserved d[2:0] pp4l[2:0]: port input 4 interrupt level bits sets the priority level of the port input 4 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30026d: port input 6C7 interrupt priority register (pint_pp67l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp7l2 pp7l1 pp7l0 C pp6l2 pp6l1 pp6l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 7 interrupt level reserved port input 6 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 0030026d (b) port input 6C7 interrupt priority register (pint_pp67l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pp7l[2:0]: port input 7 interrupt level bits sets the priority level of the port input 7 interrupt. d3 reserved d[2:0] pp6l[2:0]: port input 6 interrupt level bits sets the priority level of the port input 6 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-30 epson s1c33e08 technical manual 0x30026e: serial i/f ch.2, spi interrupt priority register (pint_psi02_pspi) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pspi2 pspi1 pspi0 C psio22 psio21 psio20 d7 d6 d5 d4 d3 d2 d1 d0 reserved spi interrupt level reserved serial interface ch.2 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 0030026e (b) serial i/f ch.2, spi interrupt priority register (pint_psi02_pspi) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pspi[2:0]: spi interrupt level bits sets the priority levels of the spi interrupt. d3 reserved d[2:0] psio2[2:0]: serial interface ch.2 interrupt level bits sets the priority levels of the serial interface ch. 2 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300270: key input, port input 0C3 interrupt enable register (pint_ek01_ep03) name address register name bit function setting init. r/w remarks C ek1 ek0 ep3 ep2 ep1 ep0 d7C6 d5 d4 d3 d2 d1 d0 reserved key input 1 key input 0 port input 3 port input 2 port input 1 port input 0 C C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300270 (b) 1 enabled 0 disabled key input, port input 0C3 interrupt enable register (pint_ek01_ep03) each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d[7:6] reserved d5 ek1: key input 1 interrupt enable bit enables or disables the key input 1 interrupt. d4 ek0: key input 0 interrupt enable bit enables or disables the key input 0 interrupt. d3 ep3: port input 3 interrupt enable bit enables or disables the port input 3 interrupt. d2 ep2: port input 2 interrupt enable bit enables or disables the port input 2 interrupt. d1 ep1: port input 1 interrupt enable bit enables or disables the port input 1 interrupt. d0 ep0: port input 0 interrupt enable bit enables or disables the port input 0 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-32 epson s1c33e08 technical manual 0x300271: dma interrupt enable register (pint_edma) name address register name bit function setting init. r/w remarks C eidma ehdm3 ehdm2 ehdm1 ehdm0 d7C5 d4 d3 d2 d1 d0 reserved idma hsdma ch.3 hsdma ch.2 hsdma ch.1 hsdma ch.0 C C 0 0 0 0 0 C r/w r/w r/w r/w r/w 0 when being read. 00300271 (b) 1 enabled 0 disabled dma interrupt enable register (pint_edma) each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d[7:5] reserved d4 eidma: idma enable interrupt bit enables or disables the idma interrupt. d3 ehdma3: hsdma ch.3 interrupt enable bit enables or disables the hsdma ch. 3 interrupt. d2 ehdma2: hsdma ch.2 interrupt enable bit enables or disables the hsdma ch. 2 interrupt. d1 ehdma1: hsdma ch.1 interrupt enable bit enables or disables the hsdma ch. 1 interrupt. d0 ehdma0: hsdma ch.0 interrupt enable bit enables or disables the hsdma ch. 0 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300272: 16-bit timer 0C1 interrupt enable register (pint_e16t01) name address register name bit function setting init. r/w remarks e16tc1 e16tu1 C e16tc0 e16tu0 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 1 comparison a 16-bit timer 1 comparison b reserved 16-bit timer 0 comparison a 16-bit timer 0 comparison b reserved 0 0 C 0 0 C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300272 (b) 1 enabled 0 disabled 16-bit timer 0C1 interrupt enable register (pint_e16t01) C 1 enabled 0 disabled C each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d7 e16tc1: 16-bit timer 1 comparison a interrupt enable bit enables or disables the 16-bit timer 1 comparison a interrupt. d6 e16tu1: 16-bit timer 1 comparison b interrupt enable bit enables or disables the 16-bit timer 1 comparison b interrupt. d[5:4] reserved d3 e16tc0: 16-bit timer 0 comparison a interrupt enable bit enables or disables the 16-bit timer 0 comparison a interrupt. d2 e16tu0: 16-bit timer 0 comparison b interrupt enable bit enables or disables the 16-bit timer 0 comparison b interrupt. d[1:0] reserved
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-34 epson s1c33e08 technical manual 0x300273: 16-bit timer 2C3 interrupt enable register (pint_e16t23) name address register name bit function setting init. r/w remarks e16tc3 e16tu3 C e16tc2 e16tu2 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 3 comparison a 16-bit timer 3 comparison b reserved 16-bit timer 2 comparison a 16-bit timer 2 comparison b reserved 0 0 C 0 0 C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300273 (b) 1 enabled 0 disabled 16-bit timer 2C3 interrupt enable register (pint_e16t23) C 1 enabled 0 disabled C each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d7 e16tc3: 16-bit timer 3 comparison a interrupt enable bit enables or disables the 16-bit timer 3 comparison a interrupt. d6 e16tu3: 16-bit timer 3 comparison b interrupt enable bit enables or disables the 16-bit timer 3 comparison b interrupt. d[5:4] reserved d3 e16tc2: 16-bit timer 2 comparison a interrupt enable bit enables or disables the 16-bit timer 2 comparison a interrupt. d2 e16tu2: 16-bit timer 2 comparison b interrupt enable bit enables or disables the 16-bit timer 2 comparison b interrupt. d[1:0] reserved
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300274: 16-bit timer 4C5 interrupt enable register (pint_e16t45) name address register name bit function setting init. r/w remarks e16tc5 e16tu5 C e16tc4 e16tu4 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 5 comparison a 16-bit timer 5 comparison b reserved 16-bit timer 4 comparison a 16-bit timer 4 comparison b reserved 0 0 C 0 0 C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300274 (b) 1 enabled 0 disabled 16-bit timer 4C5 interrupt enable register (pint_e16t45) C 1 enabled 0 disabled C each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d7 e16tc5: 16-bit timer 5 comparison a interrupt enable bit enables or disables the 16-bit timer 5 comparison a interrupt. d6 e16tu5: 16-bit timer 5 comparison b interrupt enable bit enables or disables the 16-bit timer 5 comparison b interrupt. d[5:4] reserved d3 e16tc4: 16-bit timer 4 comparison a interrupt enable bit enables or disables the 16-bit timer 4 comparison a interrupt. d2 e16tu4: 16-bit timer 4 comparison b interrupt enable bit enables or disables the 16-bit timer 4 comparison b interrupt. d[1:0] reserved
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-36 epson s1c33e08 technical manual 0x300276: serial i/f ch.0C1 interrupt enable register (pint_esif01) name address register name bit function setting init. r/w remarks C estx1 esrx1 eserr1 estx0 esrx0 eserr0 d7C6 d5 d4 d3 d2 d1 d0 reserved sif ch.1 transmit buffer empty sif ch.1 receive buffer full sif ch.1 receive error sif ch.0 transmit buffer empty sif ch.0 receive buffer full sif ch.0 receive error C C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300276 (b) 1 enabled 0 disabled serial i/f ch.0C1 interrupt enable register (pint_esif01) each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d[7:6] reserved d5 estx1: sif ch.1 transmit buffer empty interrupt enable bit enables or disables the sif ch. 1 transmit buffer empty interrupt. d4 esrx1: sif ch.1 receive buffer full interrupt enable bit enables or disables the sif ch. 1 receive buffer full interrupt. d3 eserr1: sif ch.1 receive error interrupt enable bit enables or disables the sif ch. 1 receive error interrupt. d2 estx0: sif ch.0 transmit buffer empty interrupt enable bit enables or disables the sif ch. 0 transmit buffer empty interrupt. d1 esrx0: sif ch.0 receive buffer full interrupt enable bit enables or disables the sif ch. 0 receive buffer full interrupt. d0 eserr0: sif ch.0 receive error interrupt enable bit enables or disables the sif ch. 0 receive error interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300277: port input 4C7, rtc, a/d interrupt enable register (pint_ep47_ertc_ead) name address register name bit function setting init. r/w remarks C ep7 ep6 ep5 ep4 ertc eade eadc d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 7 port input 6 port input 5 port input 4 rtc a/d conversion completion a/d out-of-range C C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300277 (b) 1 enabled 0 disabled port input 4C7, rtc, a/d interrupt enable register (pint_ep47_ertc _ead) each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d7 reserved d6 ep7: port input 7 interrupt enable bit enables or disables the port input 7 interrupt. d5 ep6: port input 6 interrupt enable bit enables or disables the port input 6 interrupt. d4 ep5: port input 5 interrupt enable bit enables or disables the port input 5 interrupt. d3 ep4: port input 4 interrupt enable bit enables or disables the port input 4 interrupt. d2 ertc: rtc interrupt enable bit enables or disables the rtc interrupt. d1 eade: a/d conversion completion interrupt enable bit enables or disables the a/d conversion completion interrupt. d0 eadc: a/d out-of-range interrupt enable bit enables or disables the a/d upper/lower limit interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-38 epson s1c33e08 technical manual 0x300278: lcdc interrupt enable register (pint_elcdc) name address register name bit function setting init. r/w remarks C elcdc C d7C2 d1 d0 reserved lcdc frame end reserved C 0 C C r/w C 0 when being read. do not write 1. 00300278 (b) lcdc interrupt enable register (pint_elcdc) C C 1 enabled 0 disabled each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d[7:2] reserved d1 elcdc: lcdc interrupt enable bit enables or disables interrupt generation of the lcdc interrupt. d0 reserved (do not write 1 to this bit.)
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300279: serial i/f ch.2, spi interrupt enable register (pint_esif2_espi) name address register name bit function setting init. r/w remarks C espitx espirx C estx2 esrx2 eserr2 d7C6 d5 d4 d3 d2 d1 d0 reserved spi transmit dma spi receive dma reserved sif ch.2 transmit buffer empty sif ch.2 receive buffer full sif ch.2 receive error C C 0 0 C 0 0 0 C r/w r/w C r/w r/w r/w 0 when being read. do not write 1. 00300279 (b) 1 enabled 0 disabled 1 enabled 0 disabled serial i/f ch.2, spi interrupt enable register (pint_esif2_espi) C each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d[7:6] reserved d5 espitx: spi transmit dma interrupt enable bit enables or disables the spi transmit dma interrupt. d4 espirx: spi receive dma interrupt enable bit enables or disables the spi receive dma interrupt. d3 reserved (do not write 1 to this bit.) d2 estx2: sif ch.2 transmit buffer empty interrupt enable bit enables or disables the sif ch. 2 transmit buffer empty interrupt. d1 esrx2: sif ch.2 receive buffer full interrupt enable bit enables or disables the sif ch. 2 receive buffer full interrupt. d0 eserr2: sif ch.2 receive error interrupt enable bit enables or disables the sif ch. 2 receive error interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-40 epson s1c33e08 technical manual 0x300280: key input, port input 0C3 interrupt cause flag register (pint_fk01_fp03) name address register name bit function setting init. r/w remarks C fk1 fk0 fp3 fp2 fp1 fp0 d7C6 d5 d4 d3 d2 d1 d0 reserved key input 1 key input 0 port input 3 port input 2 port input 1 port input 0 C C x x x x x x C r/w r/w r/w r/w r/w r/w 0 when being read. 00300280 (b) 1 occurred 0 not occurred key input, port input 0C3 interrupt cause flag register (pint_fk01_fp03) each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset the cause-of-interrupt flag is set to 1 when a cause of interrupt occurs in each peripheral circuit. if the following conditions are met at this time, an interrupt is generated to the cpu: 1 . the corresponding bit of the interrupt enable register is set to 1. 2. no other interrupt request of higher priority has occurred. 3 . the ie bit of the psr is set to 1 (interrupt enabled). 4 . the corresponding interrupt priority register is set to a level higher than the cpu's interrupt level (il). when using a cause of interrupt to request idma, note that even when the above conditions are met, no interrupt request to the cpu is generated for the cause of interrupt that has occurred. if interrupts are enabled at the setting of idma, an interrupt is generated under the above conditions after the data transfer by idma is completed. the cause-of-interrupt flag is always set to 1 when a cause of interrupt occurs no matter how the interrupt enable and interrupt priority registers are set. in order for the next interrupt to be accepted after interrupt generation, the cause-of-interrupt flag must be reset and the psr must be set up again (by setting the il below the level indicated by the interrupt priority register and setting the ie bit to 1 or executing the reti instruction). the cause-of-interrupt flag can only be reset by a write instruction in the software application. if the psr is again set up to accept interrupts (or the reti instruction is executed) without resetting the cause-of-interrupt flag, the same interrupt may occur again. note also that the value to be written to reset the flag is 1 when using the reset-only method (rstonly (d 0 / 0 x 30029 f) = 1 ) and 0 when using the read/write method (rstonly (d 0 / 0 x 30029 f) = 0 ). be careful not to confuse these two conditions. the cause-of-interrupt flag becomes indeterminate when initially reset, so be sure to reset the flag in the software application. note : even when a maskable interrupt request is accepted by the cpu and control branches off to the interrupt processing routine, the cause-of-interrupt flag is not reset. consequently, if control is returned from the interrupt processing routine by the reti instruction without resetting the cause- of-interrupt flag in a program, the same cause of interrupt occurs again.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d[7:6] reserved d5 fk1: key input 1 cause-of-interrupt flag indicates the key input 1 interrupt cause status. d4 fk0: key input 0 cause-of-interrupt flag indicates the key input 0 interrupt cause status. d3 fp3: port input 3 cause-of-interrupt flag indicates the port input 3 interrupt cause status. d2 fp2: port input 2 cause-of-interrupt flag indicates the port input 2 interrupt cause status. d1 fp1: port input 1 cause-of-interrupt flag indicates the port input 1 interrupt cause status. d0 fp0: port input 0 cause-of-interrupt flag indicates the port input 0 interrupt cause status.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-42 epson s1c33e08 technical manual 0x300281: dma interrupt cause flag register (pint_fdma) name address register name bit function setting init. r/w remarks C fidma fhdm3 fhdm2 fhdm1 fhdm0 d7C5 d4 d3 d2 d1 d0 reserved idma hsdma ch.3 hsdma ch.2 hsdma ch.1 hsdma ch.0 C C x x x x x C r/w r/w r/w r/w r/w 0 when being read. 00300281 (b) dma interrupt cause flag register (pint_fdma) 1 occurred 0 not occurred each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d[7:5] reserved d4 fidma: idma cause-of-interrupt flag indicates the idma interrupt cause status. d3 fhdm3: hsdma ch.3 cause-of-interrupt flag indicates the hsdma ch. 3 interrupt cause status. d2 ehdm2: hsdma ch.2 cause-of-interrupt flag indicates the hsdma ch. 2 interrupt cause status. d1 fhdm1: hsdma ch.1 cause-of-interrupt flag indicates the hsdma ch. 1 interrupt cause status. d0 fhdm0: hsdma ch.0 cause-of-interrupt flag indicates the hsdma ch. 0 interrupt cause status.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-43 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300282: 16-bit timer 0C1 interrupt cause flag register (pint_f16t01) name address register name bit function setting init. r/w remarks f16tc1 f16tu1 C f16tc0 f16tu0 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 1 comparison a 16-bit timer 1 comparison b reserved 16-bit timer 0 comparison a 16-bit timer 0 comparison b reserved x x C x x C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300282 (b) 1 occurred 0 not occurred 16-bit timer 0C1 interrupt cause flag register (pint_f16t01) C 1 occurred 0 not occurred C each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d7 f16tc1: 16-bit timer 1 comparison a cause-of-interrupt flag indicates the 16-bit timer 1 comparison a interrupt cause status. d6 f16tu1: 16-bit timer 1 comparison b cause-of-interrupt flag indicates the 16-bit timer 1 comparison b interrupt cause status. d[5:4] reserved d3 f16tc0: 16-bit timer 0 comparison a cause-of-interrupt flag indicates the 16-bit timer 0 comparison a interrupt cause status. d2 f16tu0: 16-bit timer 0 comparison b cause-of-interrupt flag indicates the 16-bit timer 0 comparison b interrupt cause status. d[1:0] reserved
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-44 epson s1c33e08 technical manual 0x300283: 16-bit timer 2C3 interrupt cause flag register (pint_f16t23) name address register name bit function setting init. r/w remarks f16tc3 f16tu3 C f16tc2 f16tu2 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 3 comparison a 16-bit timer 3 comparison b reserved 16-bit timer 2 comparison a 16-bit timer 2 comparison b reserved x x C x x C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300283 (b) 1 occurred 0 not occurred 16-bit timer 2C3 interrupt cause flag register (pint_f16t23) C 1 occurred 0 not occurred C each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d7 f16tc3: 16-bit timer 3 comparison a cause-of-interrupt flag indicates the 16-bit timer 3 comparison a interrupt cause status. d6 f16tu3: 16-bit timer 3 comparison b cause-of-interrupt flag indicates the 16-bit timer 3 comparison b interrupt cause status. d[5:4] reserved d3 f16tc2: 16-bit timer 2 comparison a cause-of-interrupt flag indicates the 16-bit timer 2 comparison a interrupt cause status. d2 f16tu2: 16-bit timer 2 comparison b cause-of-interrupt flag indicates the 16-bit timer 2 comparison b interrupt cause status. d[1:0] reserved
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-45 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300284: 16-bit timer 4C5 interrupt cause flag register (pint_f16t45) name address register name bit function setting init. r/w remarks f16tc5 f16tu5 C f16tc4 f16tu4 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 5 comparison a 16-bit timer 5 comparison b reserved 16-bit timer 4 comparison a 16-bit timer 4 comparison b reserved x x C x x C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300284 (b) 1 occurred 0 not occurred 16-bit timer 4C5 interrupt cause flag register (pint_f16t45) C 1 occurred 0 not occurred C each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d7 f16tc5: 16-bit timer 5 comparison a cause-of-interrupt flag indicates the 16-bit timer 5 comparison a interrupt cause status. d6 f16tu5: 16-bit timer 5 comparison b cause-of-interrupt flag indicates the 16-bit timer 5 comparison b interrupt cause status. d[5:4] reserved d3 f16tc4: 16-bit timer 4 comparison a cause-of-interrupt flag indicates the 16-bit timer 4 comparison a interrupt cause status. d2 f16tu4: 16-bit timer 4 comparison b cause-of-interrupt flag indicates the 16-bit timer 4 comparison b interrupt cause status. d[1:0] reserved
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-46 epson s1c33e08 technical manual 0x300286: serial i/f ch.0C1 interrupt cause flag register (pint_fsif01) name address register name bit function setting init. r/w remarks C fstx1 fsrx1 fserr1 fstx0 fsrx0 fserr0 d7C6 d5 d4 d3 d2 d1 d0 reserved sif ch.1 transmit buffer empty sif ch.1 receive buffer full sif ch.1 receive error sif ch.0 transmit buffer empty sif ch.0 receive buffer full sif ch.0 receive error C C x x x x x x C r/w r/w r/w r/w r/w r/w 0 when being read. 00300286 (b) 1 occurred 0 not occurred serial i/f ch.0C1 interrupt cause flag register (pint_fsif01) each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d[7:6] reserved d5 fstx1: sif ch.1 transmit buffer empty cause-of-interrupt flag indicates the sif ch. 1 transmit buffer empty interrupt cause status. d4 fsrx1: sif ch.1 receive buffer full cause-of-interrupt flag indicates the sif ch. 1 receive buffer full interrupt cause status. d3 fserr1: sif ch.1 receive error cause-of-interrupt flag indicates the sif ch. 1 receive error interrupt cause status. d2 fstx0: sif ch.0 transmit buffer empty cause-of-interrupt flag indicates the sif ch. 0 transmit buffer empty interrupt cause status. d1 fsrx0: sif ch.0 receive buffer full cause-of-interrupt flag indicates the sif ch. 0 receive buffer full interrupt cause status. d0 fserr0: sif ch.0 receive error cause-of-interrupt flag indicates the sif ch. 0 receive error interrupt cause status.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-47 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300287: port input 4C7, rtc, a/d interrupt cause flag register (pint_fp47_frtc_fad) name address register name bit function setting init. r/w remarks C fp7 fp6 fp5 fp4 frtc fade fadc d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 7 port input 6 port input 5 port input 4 rtc a/d conversion completion a/d out-of-range C C x x x x x x x C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300287 (b) 1 occurred 0 not occurred port input 4C7, rtc, a/d interrupt cause flag register (pint_fp47_frtc _fad) each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d7 reserved d6 fp7: port input 7 cause-of-interrupt flag indicates the port input 7 interrupt cause status. d5 fp6: port input 6 cause-of-interrupt flag indicates the port input 6 interrupt cause status. d4 fp5: port input 5 cause-of-interrupt flag indicates the port input 5 interrupt cause status. d3 fp4: port input 4 cause-of-interrupt flag indicates the port input 4 interrupt cause status. d2 frtc: rtc cause-of-interrupt flag indicates the rtc interrupt cause status. d1 fade: a/d conversion completion cause-of-interrupt flag indicates the a/d conversion completion interrupt cause status. d0 fadc: a/d out-of-range cause-of-interrupt flag indicates the a/d upper/lower limit interrupt cause status.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-48 epson s1c33e08 technical manual 0x300288: lcdc interrupt cause flag register (pint_flcdc) name address register name bit function setting init. r/w remarks C flcdc C d7C2 d1 d0 reserved lcdc frame end reserved C x C C r/w C 0 when being read. 0 when being read. 00300288 (b) lcdc interrupt cause flag register (pint_flcdc) C 1 occurred 0 not occurred C each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d[7:2] reserved d1 flcdc: lcdc cause-of-interrupt flag indicates the lcdc interrupt cause status. d0 reserved
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-49 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300289: serial i/f ch.2, spi interrupt cause flag register (pint_fsif2_fspi) name address register name bit function setting init. r/w remarks C fspitx fspirx C fstx2 fsrx2 fserr2 d7C6 d5 d4 d3 d2 d1 d0 reserved spi transmit dma spi receive dma reserved sif ch.2 transmit buffer empty sif ch.2 receive buffer full sif ch.2 receive error C C x x C x x x C r/w r/w C r/w r/w r/w 0 when being read. 0 when being read. 00300289 (b) 1 occurred 0 not occurred serial i/f ch.2, spi interrupt cause flag register (pint_fsif2_fspi) C 1 occurred 0 not occurred each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d[7:6] reserved d5 fspitx: spi transmit dma cause-of-interrupt flag indicates the spi transmit dma interrupt cause status. d4 fspirx: spi receive dma cause-of-interrupt flag indicates the spi receive dma interrupt cause status. d3 reserved d2 fstx2: sif ch.2 transmit buffer empty cause-of-interrupt flag indicates the sif ch. 2 transmit buffer empty interrupt cause status. d1 fsrx2: sif ch.2 receive buffer full cause-of-interrupt flag indicates the sif ch. 2 receive buffer full interrupt cause status. d0 fserr2: sif ch.2 receive error cause-of-interrupt flag indicates the sif ch. 2 receive error interrupt cause status.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-50 epson s1c33e08 technical manual 0x300290: port input 0C3, hsdma ch.0C1, 16-bit timer 0 idma request register (pidmareq_rp03_rhs_r16t0) name address register name bit function setting init. r/w remarks r16tc0 r16tu0 rhdm1 rhdm0 rp3 rp2 rp1 rp0 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 0 comparison a 16-bit timer 0 comparison b hsdma ch.1 hsdma ch.0 port input 3 port input 2 port input 1 port input 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300290 (b) 1 idma request 0 interrupt request port input 0C3, hsdma ch.0C1, 16-bit timer 0 idma request register (pidmareq_rp03 _rhs_r16t0) each bit in this register specifies whether to invoke idma when a cause of interrupt occurs. when using the set-only method (default) 1 (r/w): idma request 0 (r/w): idma not invoked (default) when using the read/write method 1 (r/w): idma request 0 (r/w): interrupt request if the bit is set to 1 , idma is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. if the bit is set to 0 , normal interrupt processing is performed, without invoking idma. for details on idma, refer to section ii. 2, intelligent dma (idma). if interrupts are enabled on the idma side and the transfer counter reaches the terminal count of 0 after completion of dma transfer, the idma request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled idma invoking is generated. d7 r16tc0: 16-bit timer 0 comparison a idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 0 comparison a interrupt occurs or not. d6 r16tu0: 16-bit timer 0 comparison b idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 0 comparison b interrupt occurs or not. d5 rhdm1: hsdma ch.1 idma request bit specifies whether to invoke idma when a cause of the hsdma ch. 1 interrupt occurs or not. d4 rhdm0: hsdma ch.0 idma request bit specifies whether to invoke idma when a cause of the hsdma ch. 0 interrupt occurs or not. d3 rp3: port input 3 idma request bit specifies whether to invoke idma when a cause of the port input 3 interrupt occurs or not. d2 rp2: port input 2 idma request bit specifies whether to invoke idma when a cause of the port input 2 interrupt occurs or not. d1 rp1: port input 1 idma request bit specifies whether to invoke idma when a cause of the port input 1 interrupt occurs or not. d0 rp0: port input 0 idma request bit specifies whether to invoke idma when a cause of the port input 0 interrupt occurs or not.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-51 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300291: 16-bit timer 1C4 idma request register (pidmareq_r16t14) name address register name bit function setting init. r/w remarks r16tc4 r16tu4 r16tc3 r16tu3 r16tc2 r16tu2 r16tc1 r16tu1 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 4 comparison a 16-bit timer 4 comparison b 16-bit timer 3 comparison a 16-bit timer 3 comparison b 16-bit timer 2 comparison a 16-bit timer 2 comparison b 16-bit timer 1 comparison a 16-bit timer 1 comparison b 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300291 (b) 1 idma request 0 interrupt request 16-bit timer 1C4 idma request register (pidmareq _r16t14) each bit in this register specifies whether to invoke idma when a cause of interrupt occurs. when using the set-only method (default) 1 (r/w): idma request 0 (r/w): idma not invoked (default) when using the read/write method 1 (r/w): idma request 0 (r/w): interrupt request if the bit is set to 1 , idma is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. if the bit is set to 0 , normal interrupt processing is performed, without invoking idma. for details on idma, refer to section ii. 2, intelligent dma (idma). if interrupts are enabled on the idma side and the transfer counter reaches the terminal count of 0 after completion of dma transfer, the idma request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled idma invoking is generated. d7 r16tc4: 16-bit timer 4 comparison a idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 4 comparison a interrupt occurs or not. d6 r16tu4: 16-bit timer 4 comparison b idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 4 comparison b interrupt occurs or not. d5 r16tc3: 16-bit timer 3 comparison a idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 3 comparison a interrupt occurs or not. d4 r16tu3: 16-bit timer 3 comparison b idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 3 comparison b interrupt occurs or not. d3 r16tc2: 16-bit timer 2 comparison a idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 2 comparison a interrupt occurs or not. d2 r16tu2: 16-bit timer 2 comparison b idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 2 comparison b interrupt occurs or not. d1 r16tc1: 16-bit timer 1 comparison a idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 1 comparison a interrupt occurs or not. d0 r16tu1: 16-bit timer 1 comparison b idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 1 comparison b interrupt occurs or not.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-52 epson s1c33e08 technical manual 0x300292: 16-bit timer 5, serial i/f ch.0 idma request register (pidmareq_r16t5_rsif0) name address register name bit function setting init. r/w remarks rstx0 rsrx0 C r16tc5 r16tu5 d7 d6 d5C2 d1 d0 sif ch.0 transmit buffer empty sif ch.0 receive buffer full reserved 16-bit timer 5 comparison a 16-bit timer 5 comparison b 0 0 C 0 0 r/w r/w C r/w r/w 0 when being read. 00300292 (b) 1 idma request 0 interrupt request 1 idma request 0 interrupt request 16-bit timer 5, serial i/f ch.0 idma request register (pidmareq_r16t5 _rsif0) C each bit in this register specifies whether to invoke idma when a cause of interrupt occurs. when using the set-only method (default) 1 (r/w): idma request 0 (r/w): idma not invoked (default) when using the read/write method 1 (r/w): idma request 0 (r/w): interrupt request if the bit is set to 1 , idma is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. if the bit is set to 0 , normal interrupt processing is performed, without invoking idma. for details on idma, refer to section ii. 2, intelligent dma (idma). if interrupts are enabled on the idma side and the transfer counter reaches the terminal count of 0 after completion of dma transfer, the idma request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled idma invoking is generated. d7 rstx0: sif ch.0 transmit buffer empty idma request bit specifies whether to invoke idma when a cause of the sif ch. 0 transmit buffer empty interrupt occurs or not. d6 rsrx0: sif ch.0 receive buffer full idma request bit specifies whether to invoke idma when a cause of the sif ch. 0 receive buffer full interrupt occurs or not. d[5:2] reserved d1 r16tc5: 16-bit timer 5 comparison a idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 5 comparison a interrupt occurs or not. d0 r16tu5: 16-bit timer 5 comparison b idma request bit specifies whether to invoke idma when a cause of the 16 -bit timer 5 comparison b interrupt occurs or not.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-53 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300293: serial i/f ch.1, a/d, port input 4C7 idma request register (pidmareq_rsif1_rad_rp47) name address register name bit function setting init. r/w remarks rp7 rp6 rp5 rp4 C rade rstx1 rsrx1 d7 d6 d5 d4 d3 d2 d1 d0 port input 7 port input 6 port input 5 port input 4 reserved a/d conversion completion sif ch.1 transmit buffer empty sif ch.1 receive buffer full 0 0 0 0 C 0 0 0 r/w r/w r/w r/w C r/w r/w r/w 0 when being read. 00300293 (b) 1 idma request 0 interrupt request 1 idma request 0 interrupt request C serial i/f ch.1, a/d, port input 4C7 idma request register (pidmareq_rsif1 _rad_rp47) each bit in this register specifies whether to invoke idma when a cause of interrupt occurs. when using the set-only method (default) 1 (r/w): idma request 0 (r/w): idma not invoked (default) when using the read/write method 1 (r/w): idma request 0 (r/w): interrupt request if the bit is set to 1 , idma is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. if the bit is set to 0 , normal interrupt processing is performed, without invoking idma. for details on idma, refer to section ii. 2, intelligent dma (idma). if interrupts are enabled on the idma side and the transfer counter reaches the terminal count of 0 after completion of dma transfer, the idma request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled idma invoking is generated. d7 rp7: port input 7 idma request bit specifies whether to invoke idma when a cause of the port input 7 interrupt occurs or not. d6 rp6: port input 6 idma request bit specifies whether to invoke idma when a cause of the port input 6 interrupt occurs or not. d5 rp5: port input 5 idma request bit specifies whether to invoke idma when a cause of the port input 5 interrupt occurs or not. d4 rp4: port input 4 idma request bit specifies whether to invoke idma when a cause of the port input 4 interrupt occurs or not. d3 reserved d2 rade: a/d conversion completion idma request bit specifies whether to invoke idma when a cause of the a/d conversion completion interrupt occurs or not. d1 rstx1: sif ch.1 transmit buffer empty idma request bit specifies whether to invoke idma when a cause of the sif ch. 1 transmit buffer empty interrupt occurs or not. d0 rsrx1: sif ch.1 receive buffer full idma request bit specifies whether to invoke idma when a cause of the sif ch. 1 receive buffer full interrupt occurs or not.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-54 epson s1c33e08 technical manual 0x300294: port input 0C3, hsdma ch.0C1, 16-bit timer 0 idma enable register (pidmaen_dep03_dehs_de16t0) name address register name bit function setting init. r/w remarks de16tc0 de16tu0 dehdm1 dehdm0 dep3 dep2 dep1 dep0 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 0 comparison a 16-bit timer 0 comparison b hsdma ch.1 hsdma ch.0 port input 3 port input 2 port input 1 port input 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300294 (b) 1 idma enabled 0 idma disabled port input 0C3, hsdma ch.0C1, 16-bit timer 0 idma enable register (pidmaen_dep03 _dehs_de16t0) each bit in this register enables or disables the idma request by a cause of interrupt. when using the set-only method (default) 1 (r/w): idma-request enabled 0 (r): idma-request disabled (default) 0 (w): has no effect when using the read/write method 1 (r/w): idma-request enabled 0 (r/w): idma-request disabled if a bit of this register is set to 1 , the idma request by the cause of interrupt is enabled. if the register bit is set to 0, the idma request is disabled. d7 de16tc0: 16-bit timer 0 comparison a idma enable bit enables or disables the idma request by a cause of the 16-bit timer 0 comparison a interrupt. d6 de16tu0: 16-bit timer 0 comparison b idma enable bit enables or disables the idma request by a cause of the 16-bit timer 0 comparison b interrupt. d5 dehdm1: hsdma ch.1 idma enable bit enables or disables the idma request by a cause of the hsdm a ch. 1 interrupt. d4 dehdm0: hsdma ch.0 idma enable bit enables or disables the idma request by a cause of the hsdm a ch. 0 interrupt. d3 dep3: port input 3 idma enable bit enables or disables the idma request by a cause of the port i nput 3 interrupt. d2 dep2: port input 2 idma enable bit enables or disables the idma request by a cause of the port i nput 2 interrupt. d1 dep1: port input 1 idma enable bit enables or disables the idma request by a cause of the port i nput 1 interrupt. d0 dep0: port input 0 idma enable bit enables or disables the idma request by a cause of the port i nput 0 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-55 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300295: 16-bit timer 1C4 idma enable register (pidmaen_de16t14) name address register name bit function setting init. r/w remarks de16tc4 de16tu4 de16tc3 de16tu3 de16tc2 de16tu2 de16tc1 de16tu1 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 4 comparison a 16-bit timer 4 comparison b 16-bit timer 3 comparison a 16-bit timer 3 comparison b 16-bit timer 2 comparison a 16-bit timer 2 comparison b 16-bit timer 1 comparison a 16-bit timer 1 comparison b 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300295 (b) 1 idma enabled 0 idma disabled 16-bit timer 1C4 idma enable register (pidmaen _de16t14) each bit in this register enables or disables the idma request by a cause of interrupt. when using the set-only method (default) 1 (r/w): idma-request enabled 0 (r): idma-request disabled (default) 0 (w): has no effect when using the read/write method 1 (r/w): idma-request enabled 0 (r/w): idma-request disabled if a bit of this register is set to 1 , the idma request by the cause of interrupt is enabled. if the register bit is set to 0, the idma request is disabled. d7 de16tc4: 16-bit timer 4 comparison a idma enable bit enables or disables the idma request by a cause of the 16-bit timer 4 comparison a interrupt. d6 de16tu4: 16-bit timer 4 comparison b idma enable bit enables or disables the idma request by a cause of the 16-bit timer 4 comparison b interrupt. d5 de16tc3: 16-bit timer 3 comparison a idma enable bit enables or disables the idma request by a cause of the 16-bit timer 3 comparison a interrupt. d4 de16tu3: 16-bit timer 3 comparison b idma enable bit enables or disables the idma request by a cause of the 16-bit timer 3 comparison b interrupt. d3 de16tc2: 16-bit timer 2 comparison a idma enable bit enables or disables the idma request by a cause of the 16-bit timer 2 comparison a interrupt. d2 de16tu2: 16-bit timer 2 comparison b idma enable bit enables or disables the idma request by a cause of the 16-bit timer 2 comparison b interrupt. d1 de16tc1: 16-bit timer 1 comparison a idma enable bit enables or disables the idma request by a cause of the 16-bit timer 1 comparison a interrupt. d0 de16tu1: 16-bit timer 1 comparison b idma enable bit enables or disables the idma request by a cause of the 16-bit timer 1 comparison b interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-56 epson s1c33e08 technical manual 0x300296: 16-bit timer 5, serial i/f ch.0 idma enable register (pidmaen_de16t5_desif0) name address register name bit function setting init. r/w remarks destx0 desrx0 C de16tc5 de16tu5 d7 d6 d5C2 d1 d0 sif ch.0 transmit buffer empty sif ch.0 receive buffer full reserved 16-bit timer 5 comparison a 16-bit timer 5 comparison b 0 0 C 0 0 r/w r/w C r/w r/w 0 when being read. 00300296 (b) 1 idma enabled 0 idma disabled 1 idma enabled 0 idma disabled 16-bit timer 5, serial i/f ch.0 idma enable register (pidmaen_de16t5 _desif0) C each bit in this register enables or disables the idma request by a cause of interrupt. when using the set-only method (default) 1 (r/w): idma-request enabled 0 (r): idma-request disabled (default) 0 (w): has no effect when using the read/write method 1 (r/w): idma-request enabled 0 (r/w): idma-request disabled if a bit of this register is set to 1 , the idma request by the cause of interrupt is enabled. if the register bit is set to 0, the idma request is disabled. d7 destx0: sif ch.0 transmit buffer empty idma enable bit enables or disables the idma request by a cause of the sif ch. 0 transmit buffer empty interrupt. d6 desrx0: sif ch.0 receive buffer full idma enable bit enables or disables the idma request by a cause of the sif ch. 0 receive buffer full interrupt. d[5:2] reserved d1 de16tc5: 16-bit timer 5 comparison a idma enable bit enables or disables the idma request by a cause of the 16-bit timer 5 comparison a interrupt. d0 de16tu5: 16-bit timer 5 comparison b idma enable bit enables or disables the idma request by a cause of the 16-bit timer 5 comparison b interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-57 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300297: serial i/f ch.1, a/d, port input 4C7 idma enable register (pidmaen_desif1_dead_dep47) name address register name bit function setting init. r/w remarks dep7 dep6 dep5 dep4 C deade destx1 desrx1 d7 d6 d5 d4 d3 d2 d1 d0 port input 7 port input 6 port input 5 port input 4 reserved a/d conversion completion sif ch.1 transmit buffer empty sif ch.1 receive buffer full 0 0 0 0 C 0 0 0 r/w r/w r/w r/w C r/w r/w r/w 0 when being read. 00300297 (b) 1 idma enabled 0 idma disabled 1 idma enabled 0 idma disabled C serial i/f ch.1, a/d, port input 4C7 idma enable register (pidmaen_desif1 _dead_dep47) each bit in this register enables or disables the idma request by a cause of interrupt. when using the set-only method (default) 1 (r/w): idma-request enabled 0 (r): idma-request disabled (default) 0 (w): has no effect when using the read/write method 1 (r/w): idma-request enabled 0 (r/w): idma-request disabled if a bit of this register is set to 1 , the idma request by the cause of interrupt is enabled. if the register bit is set to 0, the idma request is disabled. d7 dep7: port input 7 idma enable bit enables or disables the idma request by a cause of the port i nput 7 interrupt. d6 dep6: port input 6 idma enable bit enables or disables the idma request by a cause of the port i nput 6 interrupt. d5 dep5: port input 5 idma enable bit enables or disables the idma request by a cause of the port i nput 5 interrupt. d4 dep4: port input 4 idma enable bit enables or disables the idma request by a cause of the port i nput 4 interrupt. d3 reserved d2 deade: a/d conversion completion idma enable bit enables or disables the idma request by a cause of the a/d conversion completion interrupt. d1 destx1: sif ch.1 transmit buffer empty idma enable bit enables or disables the idma request by a cause of the sif ch. 1 transmit buffer empty interrupt. d0 desrx1: sif ch.1 receive buffer full idma enable bit enables or disables the idma request by a cause of the sif ch. 1 receive buffer full interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-58 epson s1c33e08 technical manual 0x300298: hsdma ch.0C1 trigger set-up register (phsdma_htgr1) 0x300299: hsdma ch.2C3 trigger set-up register (phsdma_htgr2) name address register name bit function setting init. r/w remarks hsd1s3 hsd1s2 hsd1s1 hsd1s0 hsd0s3 hsd0s2 hsd0s1 hsd0s0 d7 d6 d5 d4 d3 d2 d1 d0 hsdma ch.1 trigger set-up hsdma ch.0 trigger set-up 0 0 0 0 0 0 0 0 r/w r/w 00300298 (b) 0 1 2 3 4 5 6 7 8 9 a b c d e software trigger #dmareq1 input (falling edge) #dmareq1 input (rising edge) port 1 input port 5 input (reserved) 16-bit timer 1 compare b 16-bit timer 1 compare a 16-bit timer 5 compare b i 2 s right si/f ch.1 rx buffer full si/f ch.1 tx buffer empty a/d conversion completion port 9 input (usb pdreq) port 13 input 0 1 2 3 4 5 6 7 8 9 a b c d e software trigger #dmareq0 input (falling edge) #dmareq0 input (rising edge) port 0 input port 4 input (reserved) 16-bit timer 0 compare b 16-bit timer 0 compare a 16-bit timer 4 compare b i 2 s left si/f ch.0 rx buffer full si/f ch.0 tx buffer empty a/d conversion completion port 8 input (spi interrupt) port 12 input hsdma ch.0C1 trigger set-up register (phsdma_htgr1) hsd3s3 hsd3s2 hsd3s1 hsd3s0 hsd2s3 hsd2s2 hsd2s1 hsd2s0 d7 d6 d5 d4 d3 d2 d1 d0 hsdma ch.3 trigger set-up hsdma ch.2 trigger set-up 0 0 0 0 0 0 0 0 r/w r/w 00300299 (b) 0 1 2 3 4 5 6 7 8 9 a b c d e software trigger #dmareq3 input (falling edge) #dmareq3 input (rising edge) port 3 input port 7 input (reserved) 16-bit timer 3 compare b 16-bit timer 3 compare a (reserved) spi rx (reserved) (reserved) a/d conversion completion port 11 input (dcsio interrupt) port 15 input 0 1 2 3 4 5 6 7 8 9 a b c d e software trigger #dmareq2 input (falling edge) #dmareq2 input (rising edge) port 2 input port 6 input (reserved) 16-bit timer 2 compare b 16-bit timer 2 compare a (reserved) spi tx si/f ch.2 rx buffer full si/f ch.2 tx buffer empty a/d conversion completion port 10 input (usb interrupt) port 14 input hsdma ch.2C3 trigger set-up register (phsdma_htgr2)
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-59 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 these registers are used to select a trigger source for invoking each hsdma channel. table iii. 2.7.2 hsdma trigger source v alue 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 ch.0 trigger sour ce softw are tr igger #dmareq0 input (f alling edge) #dmareq0 input (r ising edge) po rt 0 input po rt 4 input (reser v ed) 16-bit timer 0 compare b 16-bit timer 0 compare a 16-bit timer 4 compare b i 2 s left ser ial i/f ch.0 rx b uff er full ser ial i/f ch.0 tx b uff er empty a/d con v ersion completion po rt 8 input (spi interr upt) po rt 12 input ch.1 trigger sour ce softw are tr igger #dmareq1 input (f alling edge) #dmareq1 input (r ising edge) po rt 1 input po rt 5 input (reser v ed) 16-bit timer 1 compare b 16-bit timer 1 compare a 16-bit timer 5 compare b i 2 s r ight ser ial i/f ch.1 rx b uff er full ser ial i/f ch.1 tx b uff er empty a/d con v ersion completion po rt 9 input (usb pdreq) po rt 13 input ch.2 trigger sour ce softw are tr igger #dmareq2 input (f alling edge) #dmareq2 input (r ising edge) po rt 2 input po rt 6 input (reser v ed) 16-bit timer 2 compare b 16-bit timer 2 compare a (reser v ed) spi transmit dma request ser ial i/f ch.2 rx b uff er full ser ial i/f ch.2 tx b uff er empty a/d con v ersion completion po rt 10 input (usb interr upt) po rt 14 input ch.3 trigger sour ce softw are tr igger #dmareq3 input (f alling edge) #dmareq3 input (r ising edge) po rt 3 input po rt 7 input (reser v ed) 16-bit timer 3 compare b 16-bit timer 3 compare a (reser v ed) spi receiv e dma request (reser v ed) (reser v ed) a/d con v ersion completion po rt 11 input (dcsio interr upt) po rt 15 input (default: 0000) by selecting a cause of interrupt with the hsdma trigger set-up bit, the hsdma channel is invoked when the selected cause of interrupt occurs. the interrupt control bits (cause-of-interrupt flag, interrupt enable register, idma request register, interrupt priority register) do not affect this invocation. the interrupt request to the cpu by the cause of interrupt that invokes hsdma is output two clocks (mclk) after the hsdma request, so the dma transfer and interrupt handling are performed concurrently when the cpu runs with the instructions in the cache. however, when the interrupt handler contains an instruction that accesses a peripheral circuit, the execution of the instruction is pending until the dma transfer is completed since the bus is used by the hsdma. before hsdma can be invoked by the occurrence of a cause of interrupt, it is necessary that dma be enabled on the hsdma side by setting the control register for hsdma transfer. for details about hsdma, refer to section ii. 1, high-speed dma (hsdma).
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-60 epson s1c33e08 technical manual 0x30029a: hsdma software trigger register (phsdma_hsofttgr) name address register name bit function setting init. r/w remarks C hst3 hst2 hst1 hst0 d7C4 d3 d2 d1 d0 reserved hsdma ch.3 software trigger hsdma ch.2 software trigger hsdma ch.1 software trigger hsdma ch.0 software trigger C 0 0 0 0 C w w w w 0 when being read. 0030029a (b) C 1 trigger 0 invalid hsdma software trigger register (phsdma _hsofttgr) each control bit in this register is used to start a hsdma transfer. 1 (w): trigger 0 (w): has no effect 0 (r): always 0 when read (default) writing 1 to hst x generates a trigger pulse that starts a dma transfer. hst x is effective only when software trigger is selected as the trigger source of the hsdma channel using a hsdma trigger set-up register ( 0x300298 or 0x300299). d[7:4] reserved d3 hst3: hsdma ch.3 software trigger starts a dma transfer using the hsdma ch. 3. d2 hst2: hsdma ch.2 software trigger starts a dma transfer using the hsdma ch. 2. d1 hst1: hsdma ch.1 software trigger starts a dma transfer using the hsdma ch. 1. d0 hst0: hsdma ch.0 software trigger starts a dma transfer using the hsdma ch. 0.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-61 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30029b: lcdc, serial i/f ch.2, spi idma request register (pidmareq_rlcdc_rsif2_rspi) name address register name bit function setting init. r/w remarks C rspitx rspirx rstx2 rsrx2 rlcdc C d7C6 d5 d4 d3 d2 d1 d0 reserved spi transmit dma spi receive dma sif ch.2 transmit buffer empty sif ch.2 receive buffer full lcdc frame end reserved C C 0 0 0 0 0 C C r/w r/w r/w r/w r/w C 0 when being read. 0 when being read. 0030029b (b) 1 idma request 0 interrupt request lcdc, serial i/f ch.2, spi idma request register (pidmareq_rlcdc _rsif2_rspi ) C each bit in this register specifies whether to invoke idma when a cause of interrupt occurs. when using the set-only method (default) 1 (r/w): idma request 0 (r/w): idma not invoked (default) when using the read/write method 1 (r/w): idma request 0 (r/w): interrupt request if the bit is set to 1 , idma is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. if the bit is set to 0 , normal interrupt processing is performed, without invoking idma. for details on idma, refer to section ii. 2, intelligent dma (idma). if interrupts are enabled on the idma side and the transfer counter reaches the terminal count of 0 after completion of dma transfer, the idma request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled idma invoking is generated. d[7:6] reserved d5 rspitx: spi transmit idma request bit specifies whether to invoke idma when a cause of the spi transmit dma interrupt occurs or not. d4 rspirx: spi receive idma request bit specifies whether to invoke idma when a cause of the spi receive dma interrupt occurs or not. d3 rstx2: sif ch.2 transmit buffer empty idma request bit specifies whether to invoke idma when a cause of the sif ch. 2 transmit buffer empty interrupt occurs or not. d2 rsrx2: sif ch.2 receive buffer full idma request bit specifies whether to invoke idma when a cause of the sif ch. 2 receive buffer full interrupt occurs or not. d1 rlcdc: lcdc idma request bit specifies whether to invoke idma when a cause of the lcdc interrupt occurs or not. d0 reserved
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-62 epson s1c33e08 technical manual 0x30029c: lcdc, serial i/f ch.2, spi idma enable register (pidmaen_delcdc_desif2_despi) name address register name bit function setting init. r/w remarks C despitx despirx destx2 desrx2 delcdc C d7C6 d5 d4 d3 d2 d1 d0 reserved spi transmit dma spi receive dma sif ch.2 transmit buffer empty sif ch.2 receive buffer full lcdc frame end reserved C C 0 0 0 0 0 C C r/w r/w r/w r/w r/w C 0 when being read. 0 when being read. 0030029c (b) 1 idma enabled 0 idma disabled lcdc, serial i/f ch.2, spi idma enable register (pidmaen_delcdc _desif2_despi) C each bit in this register enables or disables the idma request by a cause of interrupt. when using the set-only method (default) 1 (r/w): idma-request enabled 0 (r): idma-request disabled (default) 0 (w): has no effect when using the read/write method 1 (r/w): idma-request enabled 0 (r/w): idma-request disabled if a bit of this register is set to 1 , the idma request by the cause of interrupt is enabled. if the register bit is set to 0, the idma request is disabled. d[7:6] reserved d5 despitx: spi transmit idma enable bit enables or disables the idma request by a cause of the spi tra nsmit dma interrupt. d4 despirx: spi receive idma enable bit enables or disables the idma request by a cause of the spi rece ive dma interrupt. d3 destx2: sif ch.2 transmit buffer empty idma enable bit enables or disables the idma request by a cause of the sif ch. 2 transmit buffer empty interrupt. d2 desrx2: sif ch.2 receive buffer full idma enable bit enables or disables the idma request by a cause of the sif ch. 2 receive buffer full interrupt. d1 delcdc: lcdc idma enable bit enables or disables the idma request by a cause of the lcdc int errupt. d0 reserved
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-63 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30029f: flag set/reset method select register (prst_reset) name address register name bit function setting init. r/w remarks C denonly idmaonly rstonly d7C3 d2 d1 d0 reserved idma enable register set method selection idma request register set method selection cause-of-interrupt flag reset method selection C C 1 1 1 C r/w r/w r/w 0 when being read. 0030029f (b) flag set/reset method select register (prst_reset) 1 set only 0 rd/wr 1 set only 0 rd/wr 1 reset only 0 rd/wr d[7:3] reserved d2 denonly: idma enable register set method select bit selects the method for setting the idma enable registers. 1 (r/w): set-only method (default) 0 (r/w): read/write method with the set-only method, idma enable bits are set by writing 1. the idma enable bits for which 0 has been written can neither be set nor reset. therefore, this method ensures that only a specific idma enable bit is set. however, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an idma enable bit that has been set to 1 is not reset by writing. the read/write method is selected by writing 0 to this bit. when this method is selected, idma enable bits can be read and written as for other registers. therefore, the idma enable bit is reset by writing 0 and set by writing 1 . in this case all idma enable bits for which 0 has been written are reset. even in a read-modify-write operation, an idma enable bit can be reset by the hardware between the read and the write, so be careful when using this method. d1 idmaonly: idma request register set method select bit selects the method for setting the idma request registers. 1 (r/w): set-only method (default) 0 (r/w): read/write method with the set-only method, idma request bits are set by writing 1. the idma request bits for which 0 has been written can neither be set nor reset. therefore, this method ensures that only a specific idma request bit is set. however, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an idma request bit that has been set to 1 is not reset by writing. the read/write method is selected by writing 0 to this bit. when this method is selected, idma request bits can be read and written as for other registers. therefore, the idma request bit is reset by writing 0 and set by writing 1 . in this case all idma request bits for which 0 has been written are reset. even in a read-modify-write operation, an idma request bit can be reset by the hardware between the read and the write, so be careful when using this method. d0 rstonly: cause-of-interrupt flag reset method select bit selects the method for resetting the cause-of-interrupt flags. 1 (r/w): reset-only method (default) 0 (r/w): read/write method with the reset-only method, the cause-of-interrupt flag is reset by writing 1. the cause-of-interrupt flags for which 0 has been written can neither be set nor reset. therefore, this method ensures that only a specific cause-of-interrupt flag is reset. however, when using read- modify-write instructions (e.g., bset, bclr, or bnot), note that a cause-of-interrupt flag that has been set to 1 is reset by writing. this method cannot be used to set any cause-of-interrupt flag in the software application. the read/write method is selected by writing 0 to this bit. when this method is selected, cause-of- interrupt flags can be read and written as for other registers. therefore, the flag is reset by writing 0 and set by writing 1 . in this case all cause-of-interrupt flags for which 0 has been written are reset. even in a read-modify-write operation, a cause of interrupt can occur between read and write instructions, so be careful when using this method.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-64 epson s1c33e08 technical manual 0x3002a0: port input 8C9 interrupt priority register (pint_pp89l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp9l2 pp9l1 pp9l0 C pp8l2 pp8l1 pp8l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 9/usb pdreq interrupt level reserved port input 8/spi interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 003002a0 (b) port input 8C9 interrupt priority register (pint_pp89l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pp9l[2:0]: port input 9/usb pdreq interrupt level bits sets the priority level of the port input 9 interrupt. note : these bits function as the usb pdreq interrupt control bits when spt9[1:0] (d[3:2]/0x3003c4) = 10. d3 reserved d[2:0] pp8l[2:0]: port input 8/spi interrupt level bits sets the priority level of the port input 8 interrupt. note : these bits function as the spi interrupt control bits when spt8[1:0] (d[1:0]/0x3003c4) = 10.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-65 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3002a1: port input 10C11 interrupt priority register (pint_pp1011l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp11l2 pp11l1 pp11l0 C pp10l2 pp10l1 pp10l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 11/dcsio interrupt level reserved port input 10/usb interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 003002a1 (b) port input 10C11 interrupt priority register (pint_pp1011l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pp11l[2:0]: port input 11/dcsio interrupt level bits sets the priority level of the port input 11 interrupt. note : these bits function as the dcsio interrupt control bits when sptb[1:0] (d[7:6]/0x3003c4) = 10. d3 reserved d[2:0] pp10l[2:0]: port input 10/usb interrupt level bits sets the priority level of the port input 10 interrupt. note : these bits function as the usb interrupt control bits when spta[1:0] (d[5:4]/0x3003c4) = 10.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-66 epson s1c33e08 technical manual 0x3002a2: port input 12C13 interrupt priority register (pint_pp1213l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp13l2 pp13l1 pp13l0 C pp12l2 pp12l1 pp12l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 13 interrupt level reserved port input 12 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 003002a2 (b) port input 12C13 interrupt priority register (pint_pp1213l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pp13l[2:0]: port input 13 interrupt level bits sets the priority level of the port input 13 interrupt. d3 reserved d[2:0] pp12l[2:0]: port input 12 interrupt level bits sets the priority level of the port input 12 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-67 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3002a3: port input 14C15 interrupt priority register (pint_pp1415l) name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp15l2 pp15l1 pp15l0 C pp14l2 pp14l1 pp14l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 15 interrupt level reserved port input 14 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 003002a3 (b) port input 14C15 interrupt priority register (pint_pp1415l) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d7 reserved d[6:4] pp15l[2:0]: port input 15 interrupt level bits sets the priority level of the port input 15 interrupt. d3 reserved d[2:0] pp14l[2:0]: port input 14 interrupt level bits sets the priority level of the port input 14 interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-68 epson s1c33e08 technical manual 0x3002a4: i 2 s interrupt priority register (pint_pi2s) name address register name bit function setting init. r/w remarks C 0 to 7 C pi2s2 pi2s1 pi2s0 d7C3 d2 d1 d0 reserved i 2 s interrupt level C x x x C r/w 0 when being read. 003002a4 (b) i 2 s interrupt priority register (pint_pi2s) this register is used to set an interrupt priority level. (default: indeterminate) the priority level can be set in the range of 0 to 7. if the level is set below the il value of the psr, no interrupt is generated. d[7:3] reserved d[2:0] pi2s[2:0]: i 2 s interrupt level bits sets the priority levels of the i 2 s interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-69 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3002a6: port input 8C15 interrupt enable register (pint_ep815) name address register name bit function setting init. r/w remarks ep15 ep14 ep13 ep12 ep11 ep10 ep9 ep8 d7 d6 d5 d4 d3 d2 d1 d0 port input 15 port input 14 port input 13 port input 12 port input 11/dcsio port input 10/usb port input 9/usb pdreq port input 8/spi 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 003002a6 (b) 1 enabled 0 disabled port input 8C15 interrupt enable register (pint_ep815) each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d7 ep15: port input 15 enable bit enables or disables the port input 15 interrupt. d6 ep14: port input 14 enable bit enables or disables the port input 14 interrupt. d5 ep13: port input 13 enable bit enables or disables the port input 13 interrupt. d4 ep12: port input 12 enable bit enables or disables the port input 12 interrupt. d3 ep11: port input 11/dcsio enable bit enables or disables the port input 11 interrupt. note : this bit functions as the dcsio interrupt control bit when sptb[1:0] (d[7:6]/0x3003c4) = 10. d2 ep10: port input 10/usb enable bit enables or disables the port input 10 interrupt. note : this bit functions as the usb interrupt control bit when spta[1:0] (d[5:4]/0x3003c4) = 10. d1 ep9: port input 9/usb pdreq enable bit enables or disables the port input 9 interrupt. note : this bit functions as the usb pdreq interrupt control bit when spt9[1:0] (d[3:2]/0x3003c4) = 10. d0 ep8: port input 8/spi enable bit enables or disables the port input 8 interrupt. note : this bit functions as the spi interrupt control bit when spt8[1:0] (d[1:0]/0x3003c4) = 10.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-70 epson s1c33e08 technical manual 0x3002a7: i 2 s interrupt enable register (pint_ei2s) name address register name bit function setting init. r/w remarks C ei2s C d7C3 d2 d1C0 reserved i 2 s reserved C 0 C C r/w C 0 when being read. 0 when being read. 003002a7 (b) i 2 s interrupt enable register (pint_ei2s) C 1 enabled 0 disabled C each bit in this register enables or disables an interrupt to the cpu. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. for the causes of interrupt used to request idma invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. d[7:3] reserved d2 ei2s: i 2 s enable bit enables or disables the i 2 s interrupt. d[1:0] reserved
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-71 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3002a9: port input 8C15 interrupt cause flag register (pint_fp815) name address register name bit function setting init. r/w remarks fp15 fp14 fp13 fp12 fp11 fp10 fp9 fp8 d7 d6 d5 d4 d3 d2 d1 d0 port input 15 port input 14 port input 13 port input 12 port input 11/dcsio port input 10/usb port input 9/usb pdreq port input 8/spi x x x x x x x x r/w r/w r/w r/w r/w r/w r/w r/w 003002a9 (b) 1 occurred 0 not occurred port input 8C15 interrupt cause flag register (pint_fp815) each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d7 fp15: port input 15 cause-of-interrupt flag indicates the port input 15 interrupt cause status. d6 fp14: port input 14 cause-of-interrupt flag indicates the port input 14 interrupt cause status. d5 fp13: port input 13 cause-of-interrupt flag indicates the port input 13 interrupt cause status. d4 fp12: port input 12 cause-of-interrupt flag indicates the port input 12 interrupt cause status. d3 fp11: port input 11/dcsio cause-of-interrupt flag indicates the port input 11 interrupt cause status. note : this bit functions as the dcsio interrupt control bit when sptb[1:0] (d[7:6]/0x3003c4) = 10. d2 fp10: port input 10/usb cause-of-interrupt flag indicates the port input 10 interrupt cause status. note : this bit functions as the usb interrupt control bit when spta[1:0] (d[5:4]/0x3003c4) = 10. d1 fp9: port input 9/usb pdreq cause-of-interrupt flag indicates the port input 9 interrupt cause status. note : this bit functions as the usb pdreq interrupt control bit when spt9[1:0] (d[3:2]/0x3003c4) = 10. d0 fp8: port input 8/spi cause-of-interrupt flag indicates the port input 8 interrupt cause status. note : this bit functions as the spi interrupt control bit when spt8[1:0] (d[1:0]/0x3003c4) = 10.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-72 epson s1c33e08 technical manual 0x3002aa: i 2 s interrupt cause flag register (pint_fi2s) name address register name bit function setting init. r/w remarks C fi2s C d7C3 d2 d1C0 reserved i 2 s reserved C x C C r/w C 0 when being read. 0 when being read. 003002aa (b) 1 occurred 0 not occurred i 2 s interrupt cause flag register (pint_fi2s) C C each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. the flag that has been set can be reset by writing. (default: indeterminate) 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred when written using the reset-only method (default) 1 (w): flag is reset 0 (w): has no effect when written using the read/write method 1 (w): flag is set 0 (w): flag is reset see key input, port input 0C3 interrupt cause flag register (0x300280) for more information. d[7:3] reserved d2 fi2s: i 2 s cause-of-interrupt flag indicates the i 2 s interrupt cause status. d[1:0] reserved
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-73 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3002ac: port input 8C15 idma request register (pidmareq_rp815) name address register name bit function setting init. r/w remarks rp15 rp14 rp13 rp12 rp11 rp10 rp9 rp8 d7 d6 d5 d4 d3 d2 d1 d0 port input 15 port input 14 port input 13 port input 12 port input 11/dcsio port input 10/usb port input 9/usb pdreq port input 8/spi 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 003002ac (b) 1 idma request 0 interrupt request port input 8C15 idma request register (pidmareq _rp815) each bit in this register specifies whether to invoke idma when a cause of interrupt occurs. when using the set-only method (default) 1 (r/w): idma request 0 (r/w): idma not invoked (default) when using the read/write method 1 (r/w): idma request 0 (r/w): interrupt request if the bit is set to 1 , idma is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. if the bit is set to 0 , normal interrupt processing is performed, without invoking idma. for details on idma, refer to section ii. 2, intelligent dma (idma). if interrupts are enabled on the idma side and the transfer counter reaches the terminal count of 0 after completion of dma transfer, the idma request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled idma invoking is generated. d7 rp15: port input 15 idma request bit specifies whether to invoke idma when a cause of the port input 15 interrupt occurs or not. d6 rp14: port input 14 idma request bit specifies whether to invoke idma when a cause of the port input 14 interrupt occurs or not. d5 rp13: port input 13 idma request bit specifies whether to invoke idma when a cause of the port input 13 interrupt occurs or not. d4 rp12: port input 12 idma request bit specifies whether to invoke idma when a cause of the port input 12 interrupt occurs or not. d3 rp11: port input 11/dcsio idma request bit specifies whether to invoke idma when a cause of the port input 11 interrupt occurs or not. note : this bit functions as the dcsio interrupt control bit when sptb[1:0] (d[7:6]/0x3003c4) = 10. d2 rp10: port input 10/usb idma request bit specifies whether to invoke idma when a cause of the port input 10 interrupt occurs or not. note : this bit functions as the usb interrupt control bit when spta[1:0] (d[5:4]/0x3003c4) = 10. d1 rp9: port input 9/usb pdreq idma request bit specifies whether to invoke idma when a cause of the port input 9 interrupt occurs or not. note : this bit functions as the usb pdreq interrupt control bit when spt9[1:0] (d[3:2]/0x3003c4) = 10. d0 rp8: port input 8/spi idma request bit specifies whether to invoke idma when a cause of the port input 8 interrupt occurs or not. note : this bit functions as the spi interrupt control bit when spt8[1:0] (d[1:0]/0x3003c4) = 10.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-74 epson s1c33e08 technical manual 0x3002ad: i 2 s idma request register (pidmareq_ri2s) name address register name bit function setting init. r/w remarks C ri2s d7C1 d0 reserved i 2 s C 0 C r/w C 0 when being read. 003002ad (b) 1 idma request 0 interrupt request i 2 s idma request register (pidmareq_ri2s) each bit in this register specifies whether to invoke idma when a cause of interrupt occurs. when using the set-only method (default) 1 (r/w): idma request 0 (r/w): idma not invoked (default) when using the read/write method 1 (r/w): idma request 0 (r/w): interrupt request if the bit is set to 1 , idma is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. if the bit is set to 0 , normal interrupt processing is performed, without invoking idma. for details on idma, refer to section ii. 2, intelligent dma (idma). if interrupts are enabled on the idma side and the transfer counter reaches the terminal count of 0 after completion of dma transfer, the idma request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled idma invoking is generated. d[7:1] reserved d0 ri2s: i 2 s idma request bit specifies whether to invoke idma when a cause of the i 2 s interrupt occurs or not.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-75 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3002ae: port input 8C15 idma enable register (pidmaen_dep815) name address register name bit function setting init. r/w remarks dep15 dep14 dep13 dep12 dep11 dep10 dep9 dep8 d7 d6 d5 d4 d3 d2 d1 d0 port input 15 port input 14 port input 13 port input 12 port input 11/dcsio port input 10/usb port input 9/usb pdreq port input 8/spi 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 003002ae (b) 1 idma enabled 0 idma disabled port input 8C15 idma enable register (pidmaen_dep815) each bit in this register enables or disables the idma request by a cause of interrupt. when using the set-only method (default) 1 (r/w): idma-request enabled 0 (r): idma-request disabled (default) 0 (w): has no effect when using the read/write method 1 (r/w): idma-request enabled 0 (r/w): idma-request disabled if a bit of this register is set to 1 , the idma request by the cause of interrupt is enabled. if the register bit is set to 0, the idma request is disabled. d7 dep15: port input 15 idma enable bit enables or disables the idma request by a cause of the port i nput 15 interrupt. d6 dep14: port input 14 idma enable bit enables or disables the idma request by a cause of the port i nput 14 interrupt. d5 dep13: port input 13 idma enable bit enables or disables the idma request by a cause of the port i nput 13 interrupt. d4 dep12: port input 12 idma enable bit enables or disables the idma request by a cause of the port i nput 12 interrupt. d3 dep11: port input 11/dcsio idma enable bit enables or disables the idma request by a cause of the port i nput 11 interrupt. note : this bit functions as the dcsio interrupt control bit when sptb[1:0] (d[7:6]/0x3003c4) = 10. d2 dep10: port input 10/usb idma enable bit enables or disables the idma request by a cause of the port i nput 10 interrupt. note : this bit functions as the usb interrupt control bit when spta[1:0] (d[5:4]/0x3003c4) = 10. d1 dep9: port input 9/usb pdreq idma enable bit enables or disables the idma request by a cause of the port i nput 9 interrupt. note : this bit functions as the usb pdreq interrupt control bit when spt9[1:0] (d[3:2]/0x3003c4) = 10. d0 dep8: port input 8/spi idma enable bit enables or disables the idma request by a cause of the port i nput 8 interrupt. note : this bit functions as the spi interrupt control bit when spt8[1:0] (d[1:0]/0x3003c4) = 10.
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-76 epson s1c33e08 technical manual 0x3002af: i 2 s idma enable register (pidmaen_dei2s) name address register name bit function setting init. r/w remarks C dei2s d7C1 d0 reserved i 2 s C 0 C r/w C 0 when being read. 003002af (b) 1 idma enabled 0 idma disabled i 2 s idma enable register (pidmaen_dei2s) each bit in this register enables or disables the idma request by a cause of interrupt. when using the set-only method (default) 1 (r/w): idma-request enabled 0 (r): idma-request disabled (default) 0 (w): has no effect when using the read/write method 1 (r/w): idma-request enabled 0 (r/w): idma-request disabled if a bit of this register is set to 1 , the idma request by the cause of interrupt is enabled. if the register bit is set to 0, the idma request is disabled. d[7:1] reserved d0 dei2s: i 2 s idma enable bit enables or disables the idma request by a cause of the i 2 s interrupt.
iii peripheral modules 1 (system): interrupt controller (itc) s1c33e08 technical manual epson iii-2-77 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3003c4: port input interrupt select register 3 (ppintsel_spt811) name address register name bit function setting init. r/w remarks sptb1 sptb0 spta1 spta0 spt91 spt90 spt81 spt80 d7 d6 d5 d4 d3 d2 d1 d0 fpt11 interrupt input port selection fpt10 interrupt input port selection fpt9 interrupt input port selectio n fpt8 interrupt input port selectio n 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c4 (b) port input interrupt select register 3 (ppintsel _spt811) sptb[1:0] port p93 int_dcsio p83 p73 spta[1:0] port p92 int_usb p82 p72 spt9[1:0] port p91 usb_pdreq p81 p71 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 spt8[1:0] port p90 int_spi p80 p70 spt x [1:0]: fpt x interrupt input port select bits selects an input pin or interrupt source used to generate the fpt x port input interrupt. table iii. 2.7.3 selecting port for port input interrupts interrupt system fpt11 fpt10 fpt9 fpt8 11 p93 p92 p91 p90 10 int_dcsio int_usb usb_pdreq int_spi 01 p83 p82 p81 p80 00 p73 p72 p71 p70 spt settings (default: 0b00)
iii peripheral modules 1 (system): interrupt controller (itc) iii-2-78 epson s1c33e08 technical manual iii.2.8 precautions ? in sleep mode, there is a time lag between input of an interrupt signal for wakeup and the start of the clock supply to the itc, so a delay will occur until the itc sets the cause-of-interrupt flag. therefore, no interrupt will occur if the interrupt signal is deasserted before the clock is supplied to the itc, as the cause-of-interrupt flag in the itc is not set. furthermore, additional time is needed for the cpu to accept the interrupt request from the itc, the cpu may execute a few instructions that follow the slp instruction before it starts the interrupt processing. the same problem may occur when the cpu wakes up from sleep mode by nmi. no interrupt will occur if the #nmi signal is deasserted before the clock is supplied, as the nmi flag is not set. ? if the cause of interrupt used to restart from the standby mode has been set to invoke the idma, the idma is started up by that interrupt. if an interrupt to be generated upon completion of idma is disabled at the setting of the idma side, no interrupt request is signaled to the cpu. therefore, the cpu remains idle until the next interrupt request is generated. ? as the c33 pe core function, the il allows interrupt levels to be set in the range of 0 to 15 . however, since the interrupt priority register in the itc consists of three bits, interrupt levels in each interrupt system can only be set for up to 8. ? when the reset-only method is used to reset the cause-of-interrupt flag (by writing 1 ), if a read-modify-write instruction (e.g., bset, bclr, or bnot) is executed, the other cause-of-interrupt flags at the same address that have been set to 1 are reset by a write. this requires caution. in cases when the read/write method is used to reset the cause-of-interrupt flag (by writing 0 ), all cause-of-interrupt flags for which 0 has been written are reset. when a read-modify-write operation is performed, a cause of interrupt may occur between reads and writes, so be careful when using this method. the same applies to the set-only method and read/write method for the idma request and idma enable registers. ? after an initial reset, the cause-of-interrupt flags and interrupt priority registers all become indeterminate. to prevent unwanted interrupts or idma requests from being generated inadvertently, be sure to reset these flags and registers in the software application. ? to prevent another interrupt from being generated for the same cause again after generation of an interrupt, be sure to reset the cause-of-interrupt flag before enabling interrupts and setting the psr again or executing the reti instruction. ? there is a time lag between latching the interrupt signal and latching the interrupt vector and level signals caused by the interface specifications between the cpu and the itc. 1 . the cpu latches the interrupt signal sent from the itc. 2 . the cpu latches the interrupt vector and level signals sent from the itc. 3 . the cpu executes the interrupt handler. an illegal interrupt exception (vector no. 11 ) occurs when a register related to the interrupt signal (itc s interrupt enable and cause-of-interrupt flag registers) is altered before the cpu latches the interrupt vector and level signals (between steps 1 and 2). therefore, it is very rare but an illegal interrupt exception may occur if an interrupt related register is altered when interrupts to the cpu are in enabled status (ie bit in psr = 1). however, the illegal interrupt exception that occurs does not affect the program execution if any processing is not performed in the exception handler. to avoid an illegal interrupt exception occurring, disable interrupts to the cpu (set ie bit in psr = 0 ) before altering an interrupt related register.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.3 real-time clock (rtc) iii.3.1 overview of the rtc the s 1c33e08 incorporates a real-time clock (rtc) with a perpetual calendar, and an osc1 oscillator circuit to generate the operating clock for the rtc. the rtc and osc 1 oscillator circuit operate in sleep mode. moreover, the rtc can periodically generate interrupt requests to the cpu. the main features of the rtc are outlined below. ? contains time counters (seconds, minutes, and hours) and calendar counters (days, days of the week, months, and year). ? bcd data can be read from and written to both counters. ? capable of controlling the starting and stopping of time clocks. ? 24-hour or 12-hour mode can be selected. ? a 30 -second correction function can be implemented in software. ? periodic interrupts are possible. ? interrupt period can be selected from 1/64 second, 1 second, 1 minute, or 1 hour, with selectable level/edge interrupts. ? independent power supply, so that the rtc can continue operating even when system power is turned off. (standby mode) ? a built-in osc1 oscillator circuit (crystal oscillator or external clock input) that generates a 32.768 -khz (typ.) operating clock. figure iii.3.1.1 shows a block diagram of the rtc. 1 hz 24h/12h 1/64 second 1 second 1 minute 1 hour cmu interrupt request to itc (sleep release request to cmu) rtc osc1 oscillator (32khz) interrupt control 1-second counter divider controller 10-second counter rtc_clki rtc_clko 1-minute counter 10-minute counter 1-hour counter 10-hour counter am/pm 1-day counter 10-day counter 1-month counter 10-month counter 1-year counter 10-year counter days of week counter data bus figure iii.3.1.1 rtc block diagram
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-2 epson s1c33e08 technical manual iii.3.2 rtc counters the rtc contains the following 13 counters, whose count values can be read out as bcd data from the respective registers. each counter can also be set to any desired date and time by writing data to the respective register. 1-second counter this 4 -bit bcd counter counts in units of seconds. it counts from 0 to 9 synchronously with a 1 -second signal derived from the 32.768 -khz osc1 clock by dividing the clock into smaller frequencies. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -second counter. the count data is read out and written using rtcsl[ 3:0] (d[3:0]/0x301910). ? rtcsl[3:0] : rtc 1-second counter bits in the rtc second register (d[3:0]/0x301910) 10-second counter this 3 -bit bcd counter counts tens of seconds. it counts from 0 to 5 with 1 carried over from the 1-second counter. this counter is reset to 0 after 5 and outputs a carry over of 1 to the 1 -minute counter. the count data is read out and written using rtcsh[ 2:0] (d[6:4]/0x301910). ? rtcsh[2:0] : rtc 10-second counter bits in the rtc second register (d[6:4]/0x301910) 1 -minute counter this 4 -bit bcd counter counts in units of minutes. it counts from 0 to 9 with 1 carried over from the 10-second counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -minute counter. the count data is read out and written using rtcmil[ 3:0] (d[3:0]/0x301914). ? rtcmil[3:0] : rtc 1-minute counter bits in the rtc minute register (d[3:0]/0x301914) 10 -minute counter this 3 -bit bcd counter counts tens of minutes. it counts from 0 to 5 with 1 carried over from the 1-minute counter. this counter is reset to 0 after 5 and outputs a carry over of 1 to the 1 -hour counter. the count data is read out and written using rtcmih[ 2:0] (d[6:4]/0x301914). ? rtcmih[2:0] : rtc 10-minute counter bits in the rtc minute register (d[6:4]/0x301914) 1-hour counter this 4 -bit bcd counter counts in units of hours. it counts from 0 to 9 with 1 carried over from the 10-minute counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -hour counter. depending whether 12 -hour or 24 -hour mode is selected, the counter is reset at 12 o clock or 24 o clock. the count data is read out and written using rtchl[ 3:0] (d[3:0]/0x301918). ? rtchl[3:0] : rtc 1-hour counter bits in the rtc hour register (d[3:0]/0x301918) 10-hour counter this 2 -bit bcd counter counts tens of hours. with a carry over of 1 from the 1 -hour counter, this counter counts from 0 to 1 (when 12 -hour mode is selected) or from 0 to 2 (when 24 -hour mode is selected). the counter is reset at 12 o clock or 24 o clock, and outputs a carry over of 1 to the 1 -day counter. the count data is read out and written using rtchh[ 1:0] (d[5:4]/0x301918). ? rtchh[1:0] : rtc 10-hour counter bits in the rtc hour register (d[5:4]/0x301918) when 12 -hour mode is selected, rtcap (d6/0x301918 ) that indicates a.m. or p.m. is enabled, with a.m. and p.m. represented by 0 and 1 , respectively. for 24 -hour mode, rtcap (d6/0x301918 ) is fixed to 0. ? rtcap : am/pm indicator bit in the rtc hour register (d6/0x301918)
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 1 -day counter this 4 -bit bcd counter counts in units of days. it counts from 0 to 9 with 1 carried over from the hour counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -day counter. the number of days in each month and leap years are taken into account, so that the counter is reset to 1 when months change. the count data is read out and written using rtcdl[ 3:0] (d[3:0]/0x30191c). ? rtcdl[3:0] : rtc 1-day counter bits in the rtc day register (d[3:0]/0x30191c) 10 -day counter this 2 -bit bcd counter counts tens of days. it counts from 0 to 2 or 3 with 1 carried over from the 1 -day counter. the number of days in each month and leap years are taken into account, so that when months change the counter is reset to 0 along with the 1 -day counter, and outputs a carry over of 1 to the 1 -month counter. the count data is read out and written using rtcdh[ 1:0] (d[5:4]/0x30191c). ? rtcdh[1:0] : rtc 10-day counter bits in the rtc day register (d[5:4]/0x30191c) 1-month counter this 4 -bit bcd counter counts in units of months. it counts from 0 to 9 with 1 carried over from the day counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -month counter. the counter is reset to 1 when years change. the count data is read out and written using rtcmol[3:0] (d[3:0]/0x301920). ? rtcmol[3:0] : rtc 1-month counter bits in the rtc month register (d[3:0]/0x301920) 10-month counter this counter counts in units of 10 months, and is set to 1 with 1 carried over from the 1 -month counter. when years change, this counter is reset to 0 along with the 1 -month counter, and outputs a carry over of 1 to the 1 -year counter. the count data is read out and written using rtcmoh (d4/0x301920). ? rtcmoh : rtc 10-month counter bit in the rtc month register (d4/0x301920) 1 -year counter this 4 -bit bcd counter counts in units of years. it counts from 0 to 9 with 1 carried over from the month counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -year counter. the count data is read out and written using rtcyl[ 3:0] (d[3:0]/0x301924). ? rtcyl[3:0] : rtc 1-year counter bits in the rtc year register (d[3:0]/0x301924) 10 -year counter this 4 -bit bcd counter counts tens of years. it counts from 0 to 9 with 1 carried over from the 1 -year counter. the count data is read out and written using rtcyh[ 3:0] (d[7:4]/0x301924). ? rtcyh[3:0] : rtc 10-year counter bits in the rtc year register (d[7:4]/0x301924) days of week counter this is a septenary counter (that counts from 0 to 6 ) representing the days of the week. it counts with the same timing as the 1 -day counter. the count data is read out and written using rtcwk[2:0] (d[2:0]/0x301928). ? rtcwk[2:0] : rtc days of week counter bits in the rtc days of week register (d[2:0]/0x301928) the correspondence between the counter values and days of the week can be set in a program as desired. table iii.3.2.1 lists the basic correspondence. table iii. 3.2.1 correspondence between counter values and days of the week r tcwk2 1 1 1 0 0 0 0 r tcwk1 1 0 0 1 1 0 0 da ys of the week saturda y fr ida y thursda y w ednesda y t uesda y monda y sunda y r tcwk0 0 1 0 1 0 1 0
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-4 epson s1c33e08 technical manual initial counter values when initially reset, the counter values are not initialized. after power-on, the counter values are indeterminate. be sure to initialize the counters by following the procedure described in section iii. 3.3.2, initial sequence of the rtc. about detection of leap years the algorithm used in the rtc to detect leap years is for anno domini (a.d.) only, and can automatically identify leap years up to the year 2399. years ( 0 to 99 ) without a remainder when divided by 4 are considered leap years. when the 1 -year and 10-year counters both are 0, a common year is assumed.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.3.3 control of the rtc iii.3.3.1 controlling the operating clock counter clock the rtc is clocked by the 32.768 -khz (typ.) osc1 clock. osc1 oscillation can be turned on or off using sosc1 (d0/0x301b08) of the cmu. ? sosc1 : low-speed oscillation (osc1) on/off control bit in the system clock control register (d0/0x301b08) to use the rtc, sosc 1 (d0/0x301b08 ) must be set to 1 (default) to turn the osc1 oscillator circuit on and keep it running. note : if the osc1 oscillator circuit is turned on while idle, a finite time (of about 3 seconds) is required for its oscillation to stabilize. do not let the rtc start counting until this time elapses. the osc 1 clock does not stop regardless of chip standby mode (halt or sleep). for details of clock control, see section iii. 1, clock management unit (cmu). for the configuration of the osc1 oscillator circuit, see section iii.3.5, osc1 oscillator circuit. register clock the rtc_clk clock (= mclk) is used to operate the rtc control registers. to setup the registers, this clock is required. after the registers are set up, the clock supply can be stopped to reduce current consumption by setting rtcsapb_cke (d 0/0x301b04) to 0. ? rtcsapb_cke : rtc sapb bus interface clock control bit in the gated clock control register 1 (d0/0x301b04)
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-6 epson s1c33e08 technical manual iii.3.3.2 initial sequence of the rtc immediately after power-on, the contents of rtc registers are indeterminate. after powering on, follow the procedure below to let the rtc start ticking the time. later sections detail the contents of each control. 1 . power-on 2 . system initialization processing and waiting for osc1 stabilization although the osc 1 oscillator circuit starts oscillating immediately after power is switched on, a finite time of up to 3 seconds is required before the output clock stabilizes. 3 . disabling rtc interrupts to prevent the occurrence of unwanted rtc interrupts, the following register settings are required: write 0x0 to the rtc interrupt mode register (0x301904 ) to disable rtc interrupts. write 0x1 to the rtc interrupt status register (0x301900 ) to clear the rtc interrupt status. for details, see section iii. 3.4, rtc interrupts. 4 . starting the count write 0x2 (for 12 -hour mode) or 0x12 (for 24 -hour mode) to the rtc control register (0x301908 ) to start counting by the rtc. this operation initializes the contents of 12 -hour/ 24 -hour mode, etc. that affect count data when settings are changed, and is not the standard operation to start counting. for details, see section iii. 3.3.3, selecting 12/24 -hour mode and setting the counters, and section iii.3.3.4, starting, stopping, and resetting counters. 5 . confirming accessibility status of the rtc use the rtc access control register ( 0x30190 c) to retain the counters intact and read out the busy flag to confirm that the rtc can now be accessed. for details, see section iii. 3.3.5, counter hold and busy flag. 6 . stopping and resetting the count write 0x1 to the rtc control register (0x301908 ) to stop the count, then reset the divide-by stage of the count clock. for details, see section iii. 3.3.4, starting, stopping, and resetting counters. 7 . setting the date and time use the respective count registers to initialize all counters to the current date and time. for details, see section iii. 3.3.3, selecting 12/24-hour mode and setting the counters. 8 . restarting count release the counters from the hold state (set in step 5) and repeat step 4 to restart counting by the rtc. for details, see section iii. 3.3.5, counter hold and busy flag, and section iii.3.3.4, starting, stopping, and resetting counters.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.3.3.3 selecting 12/24 -hour mode and setting the counters selecting 12-hour/24-hour mode whether to use the time clock in 12-hour or 24 -hour mode can be selected using rtc24h (d4/0x301908). rtc 24h = 1: 24-hour mode rtc 24h = 0: 12-hour mode the count range of hour counters changes with this selection. ? rtc24h : 24h/12h mode select bit in the rtc control register (d4/0x301908) basically, this setting should be changed while the counters are idle. rtc 24 h (d4/0x301908 ) is allocated to the same address as the control bits that start the counters. therefore, 12 -hour mode or 24 -hour mode can be selected at the same time the counters are started. note : rewriting rtc24h (d4/0x301908) may corrupt count data for the hours, days, months, years or days of the week. therefore, once rtc24h (d4/0x301908) settings are changed, be sure to set data back in these counters again. checking a.m./p.m. with 12-hour mode selected when 12 -hour mode is selected, rtcap (d6/0x301918 ) that indicates a.m. or p.m. is enabled. rtcap = 0 : a.m. rtcap = 1 : p.m. for 24 -hour mode, rtcap (d6/0x301918 ) is fixed to 0. ? rtcap : am/pm indicator bit in the rtc hour register (d6/0x301918) when setting the time of day, write either of the values above to this bit to specify a.m. or p.m. setting the counters idle counters can be accessed for read or write at any time. however, settings like those shown below should be avoided, since such settings may cause timekeeping errors. ? settings exceeding the effective range do not set count data exceeding 60 seconds, 60 minutes, 12 or 24 hours, 31 days, 12 months, or 99 years. ? settings nonexistent in the calendar do not set such nonexistent dates as april 31 or february 29, 2006 . even if such settings are made, the counters operate normally, so that when 1 is carried over from the hour counter to the 1 -day counter, the day counter counts up to the first day of the next month. (for april 31 , the day counter counts up to may 1 ; for february 29, 2006, the day counter counts up to march 1, 2006.) if any counter must be rewritten while operating, there is a procedure that must be followed to ensure that the counter is rewritten correctly. for details, see section iii. 3.3.6, reading from and writing to counters in operation. iii.3.3.4 starting, stopping, and resetting counters starting and stopping counters the rtc starts counting when rtcstp (d 1/0x301908) is set to 0, and stops counting when this bit is set to 1. ? rtcstp : counter run/stop control bit in the rtc control register (d1/0x301908) the rtc is stopped by writing 1 to rtcstp (d 1/ 0x 301908 ) at the 32 -khz input clock divide-by stage of 8 , 192 hz or those stages that follow. the rtc does not stop at up to the input clock divide-by- 2 stage (16,384 hz). if the rtc stops counting when 1 is carried over to the next-digit counter, the count value may be corrupted. therefore, see the next section to ensure that 1 is not carried over when counters are made to stop. this is unnecessary, however, when the contents of all counters are newly set again. resetting the counters rtcrst (d 0/0x301908) is the bit used to reset the 32 khz to 2 hz counters. ? rtcrst : software reset bit in the rtc control register (d0/0x301908) setting rtcrst (d 0/0x301908 ) to 1 resets the counters above (cleared to 0 ), and writing 0 to this bit negates the reset.
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-8 epson s1c33e08 technical manual iii.3.3.5 counter hold and busy flag if 1 is carried over when reading the counters, the correct counter value may not be read out. moreover, if a write or stop operation is attempted, the counter value may be corrupted. therefore, whether counters are in a carry (busy) state should be checked before reading or writing data from or to the count registers. for this purpose, control bits rtcbsy (d 1/0x30190 c) and rtchld (d0/0x30190 c) are provided. ? rtcbsy : counter busy flag in the rtc access control register (d1/0x30190c) ? rtchld : counter hold control bit in the rtc access control register (d0/0x30190c) rtcbsy (d 1/0x30190 c) is a read-only flag indicating that 1 is being carried over. rtcbsy (d1/0x30190 c) is set to 1 when 1 is being carried over; otherwise, it is 0 . rtcbsy (d1/0x30190 c) should be confirmed as being 0 before accessing the counters to ensure that the correct value will be read or set. note, however, that rtcbsy (d 1/0x30190 c) is fixed to 1 while counting is in progress. to reflect the current state in the count value, rtchld (d 0/0x30190c) should be set to 1. rtcbsy = 0 (rtc accessible) if the value of rtcbsy (d 1 / 0 x 30190 c) is 0 when this bit is read out after writing 1 to rtchld (d 0 / 0 x 30190 c), it means that 1 is not being carried over. in this case, the counter hold function is actuated, with a carry over of 1 to the 1 -second counter disabled in hardware. counters that count less than seconds continue operating. data can be read from or written to the count registers in this state. after reading or writing data, reset rtchld (d 0/0x30190c) to 0. when 1 must be carried over while data is being read or written with counters in the hold state, 1 second is automatically added at the time, with rtchld (d 0/0x30190 c) reset to 0 to correct the count value. this correction is effective for only 1 second, and the time to carry over 1 on subsequent occasions is ignored. in this case, timekeeping data gets out of order. therefore, be sure to reset rtchld (d 0/0x30190 c) to 0 as soon as possible after completing the necessary read or write operation. rtcbsy = 1 (rtc is busy) if the value of rtcbsy (d 1/0x30190 c) is 1 when this bit is read after writing 1 to rtchld (d0/0x30190c), it means that 1 is being carried over. the period needed for the counters to carry over 1 is 4 ms per second. in this case, reset rtchld (d 0/0x30190 c) to 0 as soon as possible and [a] recheck rtcbsy (d1/0x30190c) by following the same procedure or [b] wait 4 ms before checking rtcbsy (d1/0x30190c). if rtcbsy (d 1/0x30190 c) is found to be 1 , be sure to immediately reset rtchld (d0/0x30190 c) to 0 . if rtchld (d 0/0x30190c) is left at 1, the time of day may become incorrect. rtchld 1 rtcbsy read register read/write rtchld 0 rtcbsy = 0? rtchld 0 no a b yes rtchld 1 rtcbsy read register read/write rtchld 0 rtcbsy = 0? rtchld 0 no yes 4 ms wait figure iii.3.3.5.1 procedure for checking whether the rtc is busy there is also a method of reading out data without using rtchld (d 0/0x30190 c) and rtcbsy (d1/0x30190c). (see the next section.)
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.3.3.6 reading from and writing to counters in operation as described in the previous section, the counters must be accessed for read/write when 1 is not being carried over. follow the procedure shown in the flowchart in figure iii. 3.3.5.1 to read from or write to the counters. the counters can be read without using rtchld (d 0/0x30190 c) and rtcbsy (d1/0x30190 c), as shown in figure iii.3.3.6.1. first data read (data1) second data read (data2) data1 = data2? no yes figure iii.3.3.6.1 procedure for reading counters not in the hold state iii.3.3.7 30-second correction the description 30 -second correction means adding 1 to the minutes when seconds of the time clock are in the range of 30 to 59 seconds, and doing nothing when in the range of 0 to 29 seconds. this function may be used to round up seconds to minutes when resetting seconds in an application. this function can be executed by writing 1 to rtcadj (d2/0x301908). ? rtcadj : 30-second adjustment bit in the rtc control register (d2/0x301908) writing 1 to rtcadj (d2/0x301908 ) causes the rtc to operate as follows: ? when the 10 -second counter is 3 or more, the rtc generates a carry over of 1 to start counting by the 1-minute counter. ? when the 10-second counter is 2 or less, the rtc does not generate a carry over of 1. after rtcadj (d 2/0x301908 ) is set to 1 , it remains set for the 4 -ms period required for this processing, then automatically returns to 0. accessing the counters while rtcadj (d 2/0x301908 ) = 1 is prohibited. writing 0 to rtcadj (d2/0x301908 ) is also prohibited, because it would cause the rtc to operate erratically. rtcadj 1 rtcadj read rtcadj = 0? no a b yes rtcadj 1 rtcadj read rtcadj = 0? no yes wait 4 ms or more figure iii.3.3.7.1 procedure for executing 30-second correction
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-10 epson s1c33e08 technical manual iii.3.4 rtc interrupts the rtc has a function to generate interrupts at given intervals. since the rtc is active even in standby mode, interrupts may be used to turn off sleep mode. this section describes the internal interrupt control function of the rtc. to generate interrupts to the cpu, the itc must also be set up. for details on how to control the itc, see section iii. 2, interrupt controller (itc). for details on how to turn off sleep mode using an interrupt, see section iii. 1, clock management unit (cmu). setting the interrupt cycle the interrupt cycle (in which the rtc outputs interrupt requests at specific intervals) can be selected from four choices listed in table iii. 3.4.1 by using rtct[1:0] (d[3:2]/0x301904). ? rtct[1:0] : rtc interrupt cycle setup bits in the rtc interrupt mode register (d[3:2]/0x301904) table iii. 3.4.1 interrupt cycle settings r tct1 1 1 0 0 r tct0 1 0 1 0 interrupt cy cl e 1 hour 1 minute 1 second 1/64 second rtct[ 1:0 ] (d[3:2]/0x301904 ) should be set while rtc interrupts are disabled. (see the procedure for enabling and disabling interrupts described below.) setting interrupt conditions the interrupt requests sent to the itc can be selected as edge-triggered or level-sensed interrupts by setting a register bit. rtcimd (d 1/0x301904 ) is the bit provided for this purpose. ? rtcimd : rtc interrupt mode select bit in the rtc interrupt mode register (d1/0x301904) setting rtcimd (d 1/0x301904 ) to 1 selects a level-sensed interrupt; setting it to 0 selects an edge-triggered interrupt. when an edge-triggered interrupt has been selected, the rtc outputs an interrupt pulse to the itc using the bus clock supplied from the cmu. if a cause of interrupt occurs when the bus clock has not been supplied such as in sleep mode, the rtc switches the interrupt mode to level-sensed and sets the interrupt signal to the active level from occurrence of the interrupt cause until the bus clock supply is started. enabling and disabling interrupts the rtc interrupt requests output to the itc are enabled by setting rtcien (d 0/0x301904 ) to 1 and disabled by setting it to 0. ? rtcien : rtc interrupt enable bit in the rtc interrupt mode register (d0/0x301904) interrupt status when the rtc is up and running, rtcirq (d 0/0x301900 ) is set at the cyclic interrupt intervals set up by rtct[ 1:0 ]. when rtc interrupts are enabled by rtcien (d0/0x301904 ), interrupt requests are sent to the itc. ? rtcirq : interrupt status bit in the rtc interrupt status register (d0/0x301900) writing 1 to this status bit clears the bit. because this bit is not cleared in hardware, be sure to clear it in software after an interrupt is generated. if this bit remains set while interrupts are re-enabled or control is returned from the interrupt handler routine by the reti instruc tion, the same interrupt may be generated again. precautions all rtc interrupt control bits described above are indeterminate when power is turned on. moreover, these bits are not initialized to specific values by an initial reset. after power-on, be sure to set rtcien (d 0/0x301904 ) to 0 (interrupt disabled) to prevent the occurrence of unwanted rtc interrupts. also be sure to write 1 to rtcirq (d0/0x301900) to reset it.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.3.5 osc1 oscillator circuit the s 1c33e08 contains an oscillator circuit (osc1 ) used to generate a 32.768 khz (typ.) clock as the clock source for timekeeping operation of the rtc. the osc 1 clock can also be used as a power-saving operating clock for the core system or peripheral circuits. for details, see section iii.1, clock management unit (cmu). iii.3.5.1 input/output pins of the osc1 oscillator circuit table iii. 3.5.1.1 lists the input/output pins of the osc1 oscillator circuit. table iii. 3.5.1.1 input/output pins of the low-speed (osc1) oscillator circuit pin name r tc_clki r tc_clk o i/o i o function osc1 input pin: cr ystal oscillator or e xter nal cloc k input osc1 output pin: cr ystal oscillator output (left open when e xter nal cloc k is input) iii.3.5.2 structure of the osc1 oscillator circuit the osc 1 oscillator circuit accommodates a crystal oscillator and external clock input. as for the rtc, v dd is used to supply power to this circuit. figure iii.3.5.2.1 shows the structure of the osc1 oscillator circuit. low level oscillation circuit control signal oscillation circuit control signal osc1 rtc_clko rtc_clki external clock n.c. v ss v dd osc1 (1) crystal oscillation circuit v ss rtc_clko rtc_clki oscillation circuit control signal (3) when not used (2) external clock input v ss rtc_clko rtc_clki c d1 c g1 x'tal1 r f r d figure iii.3.5.2.1 osc1 oscillator circuit for use as a crystal oscillator circuit, connect a crystal resonator x tal1 (32.768 khz, typ.), feedback resistor (r f ), two capacitors (c g1 , c d1 ), and, if necessary, a drain resistor (r d ) to the rtc_clki and rtc_clko pins and v ss , as shown in figure iii. 3.5.2.1 (1). to use an external clock, leave the rtc_clko pin open and input a v dd level clock (whose duty cycle is 50 %) to the rtc_clki pin. do not input v ddh or other i/o level clocks. the oscillator frequency/input clock frequency is 32.768 khz (typ.). make sure the crystal resonator or external clock used in the rtc has this clock frequency. with any other clock frequencies, the rtc cannot be used for timekeeping purposes. for details of oscillation characteristics and the input characteristics of external clock, see electrical characteristics. when not using the osc 1 oscillator circuit, connect the rtc_clki pin to v ss and leave the rtc_clko pin open.
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-12 epson s1c33e08 technical manual iii.3.5.3 oscillation control internal control bit sosc1 (d0/0x301b08 ) of the cmu register is used to control osc1 oscillation. ? sosc1 : low-speed oscillation (osc1) on/off control bit in the system clock control register (d0/0x301b08) setting this control bit to 0 causes the osc1 oscillator circuit to stop; setting it to 1 causes the osc1 oscillator circuit to start oscillating, thereby outputting a clock signal waveform. when initially reset, this bit is set to 1 , so that the osc1 oscillator circuit continues oscillating. notes : ? the system clock control register (0x301b08 ) is write-protected. the write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be removed by writing 0 x 96 to the clock control protect register ( 0 x 301 b 24 ). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register ( 0x301b24 ) is other than 0x96 unless rewriting the said registers. ? when the oscillator is made to start oscillating by setting sosc1 (d0/0x301b08 ) from 0 to 1 , a finite time (of up to 3 seconds) is required until oscillation stabilizes. to prevent system malfunction, do not use the oscillator-derived clock until this oscillation stabilization time elapses.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.3.6 details of control registers table iii. 3.6.1 rtc register list address 0x00301900 0x00301904 0x00301908 0x0030190c 0x00301910 0x00301914 0x00301918 0x0030191c 0x00301920 0x00301924 0x00301928 function rtc interrupt status sets rtc interrupt conditions and enables rtc interrupts. controls rtc operation. controls rtc busy status and counter hold. seconds counter data minutes counter data hours counter data days counter data months counter data years counter data days of the week counter data register name rtc interrupt status register (prtcintstat) rtc interrupt mode register (prtcintmode) rtc control register (prtc_cntl0) rtc access control register (prtc_cntl1) rtc second register (prtcsec) rtc minute register (prtcmin) rtc hour register (prtchour) rtc day register (prtcday) rtc month register (prtcmonth) rtc year register (prtcyear) rtc days of week register (prtcdayweek) siz e 32 32 32 32 32 32 32 32 32 32 32 each rtc control register is described below. the rtc control registers are mapped as 32 -bit devices to area 6 at addresses 0x301900 to 0x301928 , and can be accessed in units of words, half-words, or bytes. notes : ? the contents of all rtc control registers are indeterminate when power is turned on, and are not initialized to specific values by initial reset. these registers should be initialized in software. ? if 1 is being carried over when the counters are accessed for read, the correct counter value may not be read out. moreover, attempting to write to a counter or other control register may corrupt the counter value. therefore, do not write to counters while 1 is being carried over. for the correct method of operation, see section iii. 3.3.5, counter hold and busy flag, and section iii.3.3.6, reading from and writing to counters in operation. ? to access the rtc control registers, the number of wait cycles must be set up in the misc register. for setting details, see section iii. 4, misc registers. ? for details of rtc-related registers in the cmu and itc mentioned here, see the following sections: - section iii. 1, clock management unit (cmu) - section iii. 2, interrupt controller (itc)
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-14 epson s1c33e08 technical manual 0x301900: rtc interrupt status register (prtcintstat) name address register name bit function setting init. r/w remarks C rtcirq d31C 1 d0 reserved interrupt status C x C r/w 0 when being read. reset by writing 1. 00301900 (w) rtc interrupt status register (prtcintstat) C 1 occurred 0 not occurred d[31:1] reserved d0 rtcirq: interrupt status bit this bit indicates whether a cause of rtc interrupt occurred as follows: 1 (r): cause of interrupt occurred 0 (r): no cause of interrupt occurred 1 (w): resets this bit to 0 0 (w): has no effect this bit is set at cyclic interrupt intervals set up by rtct[ 1:0 ] (d[3:2 ]/0x301904 ). when rtc interrupts have been enabled by rtcien (d 0/0x301904 ) at this time, an interrupt request is sent to the itc. this bit is always set, even when rtc interrupts are disabled. note : writing 1 to this status bit clears it. because this bit is not cleared in hardware, be sure to clear it in software after an interrupt is generated. if this bit remains set while interrupts are re-enabled or control is returned from the interrupt handler routine by the reti instruction, the same interrupt may be generated again. moreover, the value of this bit is indeterminate after power-on, and is not initialized to 0 by initial reset. to prevent the occurrence of unwanted rtc interrupts, be sure to reset this bit in software after power-on and initial reset.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301904: rtc interrupt mode register (prtcintmode) name address register name bit function setting init. r/w remarks C rtct1 rtct0 rtcimd rtcien d31C4 d3 d2 d1 d0 reserved rtc interrupt cycle setup rtc interrupt mode select rtc interrupt enable C x x x x C r/w r/w r/w 0 when being read. 00301904 (w) rtc interrupt mode register (prtcintmode) C 1 level sense 0 edge trigger 1 enabled 0 disabled 11 10 01 00 rtct[1:0] cycle 1 hour 1 minute 1 second 1/64 second d[31:4] reserved d[3:2] rtct[1:0]: rtc interrupt cycle setup bits these bits select the rtc interrupt cycle. table iii. 3.6.2 interrupt cycle settings r tct1 1 1 0 0 r tct0 1 0 1 0 interrupt cy cl e 1 hour 1 minute 1 second 1/64 second (default: indeterminate) rtcirq (d 0/0x301900 ) is set by a count-up pulse of the interrupt cycle counter selected. when rtc interrupts are enabled by rtcien (d 0), an interrupt request is sent to the itc. rtct[ 1:0 ] should be set while rtc interrupts are disabled. (these bits may also be set simultaneously when rtc interrupts are enabled.) d1 rtcimd: rtc interrupt mode select bit this bit specifies whether rtc interrupts are to be generated by an edge or level of the interrupt request signal. 1 (r/w): level sensed 0 (r/w): edge triggered when an edge-triggered interrupt is selected and used to turn off sleep mode via the cmu, note that no interrupts will be generated because the itc is inactive. when an rtc interrupt handler routine must be executed after exiting sleep mode, select a level-sensed interrupt. d0 rtcien: rtc interrupt-enable bit this bit enables or disables rtc interrupt request output to the itc. 1 (r/w): enable interrupts 0 (r/w): disable interrupts to generate an rtc interrupt or use an rtc interrupt request signal to turn off sleep mode, set this bit to 1 . when this bit is 0 , no interrupts are generated even when rtcirq (d0/0x301900 ) is set and sleep mode cannot be turned off. note : the value of rtcien is indeterminate after power-on, and not initialized to 0 by initial reset. to prevent the occurrence of unwanted rtc interrupts, be sure to clear this bit in software after power-on and initial reset.
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-16 epson s1c33e08 technical manual 0x301908: rtc control register (prtc_cntl0) name address register name bit function setting init. r/w remarks C rtc24h C rtcadj rtcstp rtcrst d31C5 d4 d3 d2 d1 d0 reserved 24h/12h mode select reserved 30-second adjustment counter run/stop control software reset C x C x x x C r/w C r/w r/w r/w 0 when being read. 00301908 (w) rtc control register (prtc_cntl0) C C 1 24h 0 12h 1 stop 0 run 1 adjust 0 C 1 reset 0 C d[31:5] reserved d4 rtc24h: 24h/12h mode select bit this bit selects whether to use the hour counter in 24-hour or 12-hour mode. 1 (r/w): 24-hour mode 0 (r/w): 12-hour mode the count range of hour counters changes with this selection. basically, this setting should be changed while the counters are idle. since this register is assigned a control bit (d 1 ) to start the counters, 12 -hour or 24 -hour mode may be selected when starting the counters. note : rewriting rtc24h may corrupt the count data for hours, days, months, years, or days of the week. therefore, after changing the rtc24h setting, be sure to set data back in these counters again. d3 reserved d2 rtcadj: 30-second adjustment bit this bit executes 30-second correction. 1 (w): execute 30-second correction 0 (w): has no effect 1 (r): 30 -second correction being executed 0 (r): 30 -second correction completed (not being executed) the description 30 -second correction means adding 1 to the minutes when seconds of the time clock are in the 30-to-59 second range, and doing nothing in the 0-to-29 second range. this function may be used to round up seconds to minutes when resetting seconds in an application. writing 1 to this bit causes the rtc to operate as follows: ? when the 10 -second counter is 3 or more, the rtc generates a carry over of 1 to start counting by the 1 -minute counter. ? when the 10-second counter is 2 or less, the rtc does not generate a carry over of 1. after being set to 1 , this bit remains set for the 4 -ms period needed for the processing above, then is automatically reset to 0. note : accessing the counters while rtcadj = 1 is prohibited. writing 0 to this bit during such time is also prohibited, because it would cause the rtc to operate erratically.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d1 rtcstp: counter run/stop control bit this bit starts or stops the counters. it also indicates counte r operating status. 1 (r/w): stops counters/counters idle 0 (r/w): starts counters/counters operating setting this bit to 0 starts the counters; setting it to 1 stops the counters. the value read from this bit is 0 when the counters are operating, and 1 when the counters are idle. writing 1 to this bit stops the counters at the 32 -khz input clock divide-by stage of 8,192 hz or stages that follow. the counters do not stop at up to the input clock divide-by- 2 stage (16,384 hz). if the counters stop while 1 is being carried over, the count value may be corrupted. therefore, see section iii. 3.3.5 to ensure that 1 is not being carried over when the counters are stopped. this is unnecessary when, for example, the contents of all counters are newly set again. d0 rtcrst: software reset bit this bit resets the counters currently at divide-by stages. 1 (r/w): reset counters 0 (r/w): negate reset setting this bit to 1 resets the 32 khz to 2 hz counters (cleared to 0 ). writing 0 to this bit negates the reset.
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-18 epson s1c33e08 technical manual 0x30190c: rtc access control register (prtc_cntl1) name address register name bit function setting init. r/w remarks C rtcbsy rtchld d31C 2 d1 d0 reserved counter busy flag counter hold control C x x C r r/w 0 when being read. 0030190c (w) rtc access control register (prtc_cntl1) C 1 busy 0 r/w possibl e 1 hold 0 running d[31:2] reserved d1 rtcbsy: counter busy flag this flag indicates whether 1 is being carried over to the next-digit counter. 1 (r): busy (while 1 is being carried over) 0 (r): accessible for read/write 1/0 (w): has no effect if 1 is being carried over while the counters are being read, correct counter values may not be read. moreover, attempting a write or stop operation may corrupt the counter values. therefore, this bit should be checked to confirm that the counters are not in a carry (busy) state before reading or writing data from or to the count registers. however, because this bit is fixed to 1 while the counters are operating, rtchld (d0 ) should be set to 1 so that the count value reflects the current state. when a value of 0 is read from this bit after writing 1 to rtchld (d0 ), it means that 1 is not now being carried over. in this case, the counter hold function is also actuated, with a carry over of 1 to the 1 -second counter disabled in hardware. counters for less than seconds continue operating. in this state, data can be read from or written to the count registers. after reading or writing data, reset rtchld (d 0 ) to 0. if 1 is being carried over when data is being read from or written to counters in the hold state, 1 second is automatically added at that time, with rtchld (d 0 ) reset to 0 for correcting the count value. this correction is only effective for 1 second, thus ignoring the time needed to carry over 1 on subsequent occasions. in this case, the timekeeping data gets out of order. therefore, be sure to reset rtchld (d 0 ) to 0 as soon as possible after completing the required read or write operation. when a value of 1 is read from this bit after writing 1 to rtchld (d0 ), it means that 1 is now being carried over. a period of 4 ms per second is required for a carry over of 1 to the counters. in this case, reset rtchld (d 0 ) to 0 as soon as possible and check this bit again by following the same procedure, or wait 4 ms before checking this bit. if this bit is set to 1 , always reset rtchld (d0 ) to 0 immediately. leaving rtchld (d 0) set to 1 may result in an incorrect time of day. d0 rtchld: counter hold control bit this bit allows the busy state of counters to be checked and the counters held intact. 1 (r/w): checks for busy state/holds counters 0 (r/w): normal operation for the operation of this bit, see the description of rtcbsy (d 1 ) above.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301910: rtc second register (prtcsec) name address register name bit function setting init. r/w remarks C rtcsh2 rtcsh1 rtcsh0 rtcsl3 rtcsl2 rtcsl1 rtcsl0 d31C7 d6 d5 d4 d3 d2 d1 d0 reserved rtc 10-second counter rtc 1-second counter C x x x x x x x C r/w r/w 0 when being read. 00301910 (w) rtc second register (prtcsec) 0 to 5 C 0 to 9 note : data should not be read from or written to the counters while 1 is being carried over. (see section iii.3.3.5, counter hold and busy flag, and section iii.3.3.6, reading from and writing to counters in operation.) d[31:7] reserved d[6:4] rtcsh[2:0]: rtc 10-second counter bits these bits comprise a 3-bit bcd counter used to count tens of seconds. the counter counts from 0 to 5 with a carry over of 1 from the 1 -second counter. this counter is reset to 0 after 5 and outputs a carry over of 1 to the 1 -minute counter. d[3:0] rtcsl[3:0]: rtc 1-second counter bits these bits comprise a 4-bit bcd counter used to count units of seconds. the counter counts from 0 to 9 synchronously with a 1 -second signal derived from the 32.768 -khz osc1 clock. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -second counter.
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-20 epson s1c33e08 technical manual 0x301914: rtc minute register (prtcmin) name address register name bit function setting init. r/w remarks C rtcmih2 rtcmih1 rtcmih0 rtcmil3 rtcmil2 rtcmil1 rtcmil0 d31C7 d6 d5 d4 d3 d2 d1 d0 reserved rtc 10-minute counter rtc 1-minute counter C x x x x x x x C r/w r/w 0 when being read. 00301914 (w) rtc minute register (prtcmin) 0 to 5 C 0 to 9 note : data should not be read from or written to the counters while 1 is being carried over. (see section iii.3.3.5, counter hold and busy flag, and section iii.3.3.6, reading from and writing to counters in operation.) d[31:7] reserved d[6:4] rtcmih[2:0]: rtc 10-minute counter bits these bits comprise a 3-bit bcd counter used to count tens of minutes. the counter counts from 0 to 5 with a carry over of 1 from the 1 -minute counter. this counter is reset to 0 after 5 and outputs a carry over of 1 to the 1 -hour counter. d[3:0] rtcmil[3:0]: rtc 1-minute counter bits these bits comprise a 4-bit bcd counter used to count units of minutes. the counter counts from 0 to 9 with a carry over of 1 from the 10 -second counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -minute counter.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301918: rtc hour register (prtchour) name address register name bit function setting init. r/w remarks C rtcap rtchh1 rtchh0 rtchl3 rtchl2 rtchl1 rtchl0 d31C7 d6 d5 d4 d3 d2 d1 d0 reserved am/pm indicator rtc 10-hour counter rtc 1-hour counter C x x x x x x x C r/w r/w r/w 0 when being read. 00301918 (w) rtc hour register (prtchour) 0 to 2 or 0 to 1 C 1 pm 0 am 0 to 9 notes : ? data should not be read from or written to the counters while 1 is being carried over. (see section iii. 3.3.5, counter hold and busy flag, and section iii. 3.3.6, reading from and writing to counters in operation. ) ? rewriting rtc24 h (d4/0x301908 ) may corrupt the count data in this register. therefore, after changing the rtc 24h (d4/0x301908 ) setting, be sure to set up this register again. d[31:7] reserved d6 rtcap: am/pm indicator bit when 12 -hour mode is selected, this bit indicates a.m. or p.m. 1 (r/w): p.m. 0 (r/w): a.m. this bit is only effective when rtc 24h (d4/0x301908) is set to 0 (12-hour mode). when 24 -hour mode is selected, this bit is fixed to 0. in this case, do not write 1 to rtcap. note : the rtcap bit keeps the current set value even if rtc24h (d4/0x301908) is changed from 12-hour mode to 24-hour mode, and will be fixed at 0 after the hour counter is updated (or reset in software). d[5:4] rtchh[1:0]: rtc 10-hour counter bits these bits comprise a 2-bit bcd counter used to count tens of hours. with a carry over of 1 from the 1 -hour counter, the counter counts from 0 to 1 when 12 -hour mode is selected, or from 0 to 2 when 24 -hour mode is selected. the counter is reset at 12 0clock or 24 0clock, and outputs a carry over of 1 to the 1 -day counter. d[3:0] rtchl[3:0]: rtc 1-hour counter bits these bits comprise a 4-bit bcd counter used to count units of hours. the counter counts from 0 to 9 with a carry over of 1 from the 10 -minute counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -hour counter. depending on whether 12 -hour mode or 24-hour mode is selected, the counter is reset at 12 0clock or 24 0clock.
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-22 epson s1c33e08 technical manual 0x30191c: rtc day register (prtcday) name address register name bit function setting init. r/w remarks C rtcdh1 rtcdh0 rtcdl3 rtcdl2 rtcdl1 rtcdl0 d31C6 d5 d4 d3 d2 d1 d0 reserved rtc 10-day counter rtc 1-day counter C x x x x x x C r/w r/w 0 when being read. 0030191c (w) rtc day register (prtcday) 0 to 3 C 0 to 9 notes : ? data should not be read from or written to the counters while 1 is being carried over. (see section iii. 3.3.5, counter hold and busy flag, and section iii. 3.3.6, reading from and writing to counters in operation. ) ? rewriting rtc24 h (d4/0x301908 ) may corrupt the count data in this register. therefore, after changing the rtc 24h (d4/0x301908 ) setting, be sure to set up this register again. d[31:6] reserved d[5:4] rtcdh[1:0]: rtc 10-day counter bits these bits comprise a 2 -bit bcd counter used to count tens of days. the counter counts from 0 to 2 or 3 with a carry over of 1 from the 1 -day counter. the number of days in each month and leap years are taken into account, so that when months change the counter is reset to 0 along with the 1 -day counter, and a carry over of 1 is output to the 1 -month counter. d[3:0] rtcdl[3:0]: rtc 1-day counter bits these bits comprise a 4-bit bcd counter used to count units of days. the counter counts from 0 to 9 with a carry over of 1 from the hour counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -day counter. the number of days in each month and leap years are taken into account, so that the counter is reset to 1 when months change.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301920: rtc month register (prtcmonth) name address register name bit function setting init. r/w remarks C rtcmoh rtcmol3 rtcmol2 rtcmol1 rtcmol0 d31C5 d4 d3 d2 d1 d0 reserved rtc 10-month counter rtc 1-month counter C x x x x x C r/w r/w 0 when being read. 00301920 (w) rtc month register (prtcmonth) 0 or 1 C 0 to 9 notes : ? data should not be read from or written to the counters while 1 is being carried over. (see section iii. 3.3.5, counter hold and busy flag, and section iii. 3.3.6, reading from and writing to counters in operation. ) ? rewriting rtc24 h (d4/0x301908 ) may corrupt the count data in this register. therefore, after changing the rtc 24h (d4/0x301908 ) setting, be sure to set up this register again. d[31:5] reserved d4 rtcmoh: rtc 10-month counter bit this is a tens of months count bit. this bit is set to 1 with a carry over of 1 from the 1 -month counter. when years change, this bit is reset to 0 along with the 1 -month counter, and a carry over of 1 is output to the 1 -year counter. d[3:0] rtcmol[3:0]: rtc 1-month counter bits these bits comprise a 4-bit bcd counter used to count units of months. the counter counts from 0 to 9 with a carry over of 1 from the day counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -month counter. the counter is reset to 1 when years change.
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-24 epson s1c33e08 technical manual 0x301924: rtc year register (prtcyear) name address register name bit function setting init. r/w remarks C rtcyh3 rtcyh2 rtcyh1 rtcyh0 rtcyl3 rtcyl2 rtcyl1 rtcyl0 d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved rtc 10-year counter rtc 1-year counter C x x x x x x x x C r/w r/w 0 when being read. 00301924 (w) rtc year register (prtcyear) 0 to 9 C 0 to 9 notes : ? data should not be read from or written to the counters while 1 is being carried over. (see section iii. 3.3.5, counter hold and busy flag, and section iii. 3.3.6, reading from and writing to counters in operation. ) ? rewriting rtc24 h (d4/0x301908 ) may corrupt the count data in this register. therefore, after changing the rtc 24h (d4/0x301908 ) setting, be sure to set up this register again. d[31:8] reserved d[7:4] rtcyh[3:0]: rtc 10-year counter bits these bits comprise a 4 -bit bcd counter used to count tens of years. the counter counts from 0 to 9 with a carry over of 1 from the 1 -year counter. d[3:0] rtcyl[3:0]: rtc 1-year counter bits these bits comprise a 4-bit bcd counter used to count units of years. the counter counts from 0 to 9 with a carry over of 1 from the month counter. this counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 -year counter.
iii peripheral modules 1 (system): real-time clock (rtc) s1c33e08 technical manual epson iii-3-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301928: rtc days of week register (prtcdayweek) name address register name bit function setting init. r/w remarks C rtcwk2 rtcwk1 rtcwk0 d31C 3 d2 d1 d0 reserved rtc days of week counter C x x x C r/w 0 when being read. 00301928 (w) rtc days of week register (prtcdayweek) C 111 110 101 100 011 010 001 000 rtcwk[2:0] days of week C saturday friday thursday wednesday tuesday monday sunday notes : ? data should not be read from or written to the counters while 1 is being carried over. (see section iii. 3.3.5, counter hold and busy flag, and section iii. 3.3.6, reading from and writing to counters in operation. ) ? rewriting rtc24 h (d4/0x301908 ) may corrupt the count data in this register. therefore, after changing the rtc 24h (d4/0x301908 ) setting, be sure to set up this register again. d[31:3] reserved d[2:0] rtcwk[2:0]: rtc days of week counter bits this is a septenary counter (that counts from 0 to 6 ) representing days of the week. this counter counts at the same timing as the 1 -day counter. the correspondence between the counter values and days of the week can be set in a program as desired. table iii. 3.6.3 lists the basic correspondence. table iii. 3.6.3 correspondence between counter values and days of the week r tcwk2 1 1 1 0 0 0 0 r tcwk1 1 0 0 1 1 0 0 da ys of the week saturda y fr ida y thursda y w ednesda y t uesda y monda y sunda y r tcwk0 0 1 0 1 0 1 0 (default: indeterminate)
iii peripheral modules 1 (system): real-time clock (rtc) iii-3-26 epson s1c33e08 technical manual iii.3.7 precautions ? the contents of all rtc control registers are indeterminate when power is turned on and are not initialized to specific values by initial reset. be sure to initialize these registers in software. ? while 1 is being carried over to the next-digit counter, the correct counter value may not be read out. moreover, attempting to write to the counters or other control registers may corrupt the counter value. therefore, do not write to the counters while 1 is being carried over. for the correct method of operation, see section iii.3.3.5, counter hold and busy flag, and section iii.3.3.6, reading from and writing to counters in operation. ? note that rewriting rtc24 h (d4/0x301908 ) to switch between 12 -hour mode and 24 -hour mode may corrupt the count data for hours, days, months, years, or days of the week. therefore, after changing the rtc 24 h (d4/ 0x301908 ) setting, be sure to set data in these counters back again. ? avoid the settings below that may cause timekeeping errors. - settings exceeding the effective range do not set count data exceeding 60 seconds, 60 minutes, 12 or 24 hours, 31 days, 12 months, or 99 years. - settings nonexistent in the calendar do not set nonexistent dates such as april 31 or february 29, 2006 . even if such settings are made, the counters operate normally, so that when 1 is carried over from the hour counter to the 1 -day counter, the day counter counts up to the first day of the next month. (for april 31 , the day counter counts up to may 1 ; for february 29, 2006, the day counter counts up to march 1, 2006.) ? the contents of all rtc interrupt control bits are indeterminate when power is turned on, and are not initialized to specific values by initial reset. after power-on, be sure to set rtcien (d 0/0x301904 ) to 0 (interrupt disabled) for preventing the occurrence of unwanted rtc interrupts. also be sure to write 1 to rtcirq (d0/0x301900) to reset it. ? immediately after the osc1 oscillator circuit is activated (as at power-on), a finite time (of about 3 seconds) is required for osc1 oscillation to stabilize. do not let the rtc start counting until this time elapses.
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.4 misc registers note : the misc registers at addresses 0x300010C0x30001a are write-protected. before the misc reg - isters can be rewritten, write protection of these registers must be removed by writing data 0x96 to the misc protect register (0x300020). note that since unnecessary rewrites to addresses 0x300010C0x30001a could lead to erratic system operation, the misc protect register (0x300020) should be set to other than 0x96 unless said misc registers must be rewritten. iii.4.1 rtc and usb wait control registers iii.4.1.1 setting wait cycles for accessing the rtc the rtc wait control register ( 0x300010 ) contains the control bits rtcwt[2:0 ] (d[2:0 ]) used to set the number of wait cycles to be inserted when accessing the rtc registers. ? rtcwt[2:0] : rtc register access wait control bits in the rtc wait control register (d[2:0]/0x300010) table iii. 4.1.1.1 number of wait cycles during rtc access r tcwt2 1 1 1 1 0 0 0 0 r tcwt1 1 1 0 0 1 1 0 0 r tcwt0 1 0 1 0 1 0 1 0 number of wait cyc les (in units of mclk cyc les) 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle 0 cycles (default: 0b111 = 7 cycles) the number of wait cycles should be set according to the mclk clock frequency. the s1c33e08 is able to operate with rtcwt[2:0] 1. iii.4.1.2 settings for the usb the usb wait control register ( 0x300012 ) contains the control bits usbwt[2:0 ] (d[2:0 ]) used to set the number of wait cycles to be inserted when accessing the usb registers. ? usbwt[2:0] : usb register access wait control bits in the usb wait control register (d[2:0]/0x300012) table iii. 4.1.2.1 number of wait cycles during usb access usbwt2 1 1 1 1 0 0 0 0 usbwt1 1 1 0 0 1 1 0 0 usbwt0 1 0 1 0 1 0 1 0 number of wait cyc les (in units of mclk cyc les) 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle 0 cycles mclk clock frequency 60 mhz or less 56 mhz or less 45 mhz or less 36 mhz or less 24 mhz or less 16 mhz or less 8 mhz or less 8 mhz or less (default: 0b111 = 7 cycles) the number of wait cycles should be set according to the mclk clock frequency. also the usb wait control register ( 0x300012) contains the usbsnz bit (d5) that controls snooze mode for the usb function controller. setting usbsnz (d 5/0x300012) to 1 enables snooze mode. ? usbsnz : usb snooze control bit in the usb wait control register (d5/0x300012) refer to section ix.1, usb function controller, for details on control of the usb function controller.
iii peripheral modules 1 (system): misc registers iii-4-2 epson s1c33e08 technical manual iii.4.2 debug port mux register the p 15Cp17 and p34Cp36 pins are shared with the pc trace debugging function and other peripheral functions. these pins are configured as the debug pins dst 0 (p15 ), dst1 (p16 ), dpco (p17 ), dsio (p34 ), dclk (p35), and dst 2 (p36 ) at initial reset. when using these pins as gpio or other peripheral function pins, trcmux (d0/ 0x300014) must be set to 0. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) when trcmux (d 0/0x300014 ) is set to 0 , the port function select bits for p15Cp17 and p34Cp36 are enabled to select the pin function. set trcmux (d 0/0x300014) to 1 to use these pins for debugging.
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.4.3 boot register the boot register ( 0x300018 ) is used to confirm the boot device and configure #ce10 boot conditions. boot[ 3:0] (d[7:4]/0x300018 ) indicates the boot device that has been specified by the boot1 and boot0 pins. ? boot[3:0] : boot mode indicator bits in the boot register (d[7:4]/0x300018) table iii. 4.3.1 boot[3:0] bits boo t3 1 0 0 0 boo t2 0 1 0 0 boo t1 0 0 1 0 boo t0 0 0 0 1 boot mode spi boot nor flash/e xter nal r om boot reser ve d nand flash boot the boot register ( 0x300018 ) contains two more control bits, boot_ena (d1 ) and ce10 _size (d0 ) that are used for the booting process by the internal boot firmware. ? boot_ena : #ce10 area boot enable bit in the boot register (d1/0x300018) ? ce10_size : #ce10 area size select bit in the boot register (d0/0x300018) note : when programming a flash memory on the target board, boot_ena (d1/0x300018) must be set to 0. be sure to avoid changing the boot mode when writing the boot register (0x300018).
iii peripheral modules 1 (system): misc registers iii-4-4 epson s1c33e08 technical manual iii.4.4 pin control registers iii.4.4.1 pull-up control the s1c33e08 input/output pins have a pull-up resistor that can be connected/disconnected to/from the pin by soft - ware control, except some special pins. each pin has a pull-up control bit to select whether the pull-up resistor is used or not. table iii. 4.4.1.1 lists the correspondence between the register/control bits and pins. table iii. 4.4.1.1 correspondence between pull-up control bits and pins pin p07Cp00 p17Cp15 p14Cp10 p27Cp20 p36Cp34 p33Cp30 p47Cp40 p57Cp50 p67Cp60 p74Cp70 p85Cp80 p97Cp90 p a4Cp a0 pb3Cpb0 contr ol bit pup0[7:0] (d[7:0]) pup1[7:5] (d[7:5]) pup1[4:0] (d[4:0]) pup2[7:0] (d[7:0]) pup3[6:4] (d[6:4]) pup3[3:0] (d[3:0]) pup4[7:0] (d[7:0]) pup5[7:0] (d[7:0]) pup6[7:0] (d[7:0]) pup7[4:0] (d[4:0]) pup8[5:0] (d[5:0]) pup9[7:0] (d[7:0]) pup a[4:0] (d[4:0]) pupb[3:0] (d[3:0]) contr ol register p0 pull-up control register (0x300c42) p1 pull-up control register (0x300c43) p2 pull-up control register (0x300c44) p3 pull-up control register (0x300c45) p4 pull-up control register (0x300c46) p5 pull-up control register (0x300c47) p6 pull-up control register (0x300c48) p7 pull-up control register (0x300c49) p8 pull-up control register (0x300c4a) p9 pull-up control register (0x300c4b) pa pull-up control register (0x300c4c) pb pull-up control register (0x300c4d) init. no pull-up pull-up no pull-up pull-up pull-up no pull-up pull-up pull-up no pull-up no pull-up no pull-up no pull-up pull-up pull-up when the pull-up control bit is set to 1 , the corresponding pin will be pulled up in input mode. when not using pull-up resistors, set the corresponding pull-up control bits to 0. notes : ? the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on-chip peripheral circuit or general-purpose i/o port. ? when the port is in output mode, the port pin is not pulled up regardless of how the pull-up control bit is set. iii.4.4.2 driving bus signals low the s 1c33e08 can drive the bus signal output pins forcibly low using a control register. this function is useful when turning off the power of the external device connected to the bus. table iii. 4.4.2.1 lists the correspondence between the register/control bits and bus signals. table iii. 4.4.2.1 correspondence between low-drive control bits and bus signals bus signal d[15:0] #ce[11:4] a[24:0] #rd , #wrl, #wrh, #bsl contr ol bit ldr vdb (d3) ldr vce (d2) ldr v ad (d1) ldr vr w (d0) contr ol register bus signal lo w dr iv e control register (0x300c41) when the control bit is set to 1 , the corresponding bus signal goes low. when the control bit is set to 0 , the signal control goes back to the sramc/sdramc. notes : ? the low-drive control bit is disabled when the pin is used as the general-purpose i/o port (p xx ). ? if the above signals are forcibly driven low when the cpu is running by the instructions fetched from an external memory, the cpu will not be able to run after that point. to drive the signals low, the cpu must be running with the program stored in the internal ram.
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.4.5 misc register operating clock the misc registers are clocked by the misc_clk clock (= mclk) generated by the cmu. for details on how to control the clock, see section iii. 1, clock management unit (cmu). controlling the supply of the misc register operating clock misc_clk is always supplied to the misc registers and cannot be stopped in normal operation mode. however, the clock supply can be stopped in halt mode. by setting misc_hcke (d 24/0x301b04 ) to 0 , misc_clk stops when the cpu enters halt mode and it resumes when the cpu exits halt mode. ? misc_hcke : misc clock control (halt) bit in the gated clock control register 1 (d24/0x301b04) clock state in standby mode the supply of the misc register operating clock stops depending on the type of standby mode. halt mode: the operating clock is supplied the same way as in normal mode. it can be stopped by setting misc_hcke (d24/0x301b04) to 0. sleep mode: the clock supply stops. therefore, the misc registers also stop operating in sleep mode.
iii peripheral modules 1 (system): misc registers iii-4-6 epson s1c33e08 technical manual iii.4.6 details of control registers table iii. 4.6.1 list of misc registers address 0x00300010 0x00300012 0x00300014 0x00300016 0x00300018 0x0030001a 0x00300020 0x00300c41 0x00300c42 0x00300c43 0x00300c44 0x00300c45 0x00300c46 0x00300c47 0x00300c48 0x00300c49 0x00300c4a 0x00300c4b 0x00300c4c 0x00300c4d function sets the rtc register access wait cycle. sets the usb register access wait cycle. configures the p15Cp17 and p34Cp36 pins for debugging. test register indicates/sets boot conditions. test register enables/disables write protection of misc registers. drives the bus signals low. controls the p0 port pull-up resistors. controls the p1 port pull-up resistors. controls the p2 port pull-up resistors. controls the p3 port pull-up resistors. controls the p4 port pull-up resistors. controls the p5 port pull-up resistors. controls the p6 port pull-up resistors. controls the p7 port pull-up resistors. controls the p8 port pull-up resistors. controls the p9 port pull-up resistors. controls the pa port pull-up resistors. controls the pb port pull-up resistors. register name rtc wait control register (pmisc_rtcwt) usb wait control register (pmisc_usbwt) debug port mux register (pmisc_pmux) performance analyzer control register (pmisc_pac) boot register (pmisc_boot) corom switch register (pmisc_corom) misc protect register (pmisc_prot) bus signal low drive control register (pmisc_buslow ) p0 pull-up control register (pmisc_pup0) p1 pull-up control register (pmisc_pup1) p2 pull-up control register (pmisc_pup2) p3 pull-up control register (pmisc_pup3) p4 pull-up control register (pmisc_pup4) p5 pull-up control register (pmisc_pup5) p6 pull-up control register (pmisc_pup6) p7 pull-up control register (pmisc_pup7) p8 pull-up control register (pmisc_pup8) p9 pull-up control register (pmisc_pup9) pa pull-up control register (pmisc_pupa) pb pull-up control register (pmisc_pupb) siz e 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 the following describes the misc registers. the misc registers are mapped as 8 -bit devices to area 6 at addresses 0x300010 to 0x300020 and 0x300c41 to 0x300c4d, and can be accessed in units of bytes. note : the misc registers at addresses 0x300010C0x30001a are write-protected. before the misc reg - isters can be rewritten, write protection of these registers must be removed by writing data 0x96 to the misc protect register (0x300020). note that since unnecessary rewrites to addresses 0x300010C0x30001a could lead to erratic system operation, the misc protect register (0x300020) should be set to other than 0x96 unless said misc registers must be rewritten. the registers located from 0x300c41 to 0x300c4d are not protected.
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300010: rtc wait control register (pmisc_rtcwt) name address register name bit function setting init. r/w remarks C rtcwt2 rtcwt1 rtcwt0 d7C3 d2 d1 d0 reserved rtc register access wait control C 1 1 1 C r/w 0 when being read. 00300010 (b) rtc wait control register (pmisc_rtcwt) protected 0 to 7 (cycles) C d[7:3] reserved d[2:0] rtcwt[2:0]: rtc register access wait control bits these bits set the number of wait cycles to be inserted when accessing the rtc control register. table iii. 4.6.2 number of wait cycles during rtc access r tcwt2 1 1 1 1 0 0 0 0 r tcwt1 1 1 0 0 1 1 0 0 r tcwt0 1 0 1 0 1 0 1 0 number of wait cyc les (in units of mclk cyc les) 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle 0 cycles (default: 0b111 = 7 cycles) the number of wait cycles should be set according to the mclk clock frequency. the s 1c33e08 is able to operate with rtcwt[2:0] 1.
iii peripheral modules 1 (system): misc registers iii-4-8 epson s1c33e08 technical manual 0x300012: usb wait control register (pmisc_usbwt) name address register name bit function setting init. r/w remarks C usbsnz C usbwt2 usbwt1 usbwt0 d7C6 d5 d4C3 d2 d1 d0 reserved usb snooze control reserved usb register access wait control C 0 C 1 1 1 C r/w C r/w 0 when being read. 0 when being read. 00300012 (b) usb wait control register (pmisc_usbwt) protected 0 to 7 (cycles) C C 1 enabled 0 disabled d[7:6] reserved d5 usbsnz: usb snooze control bit this bit enables/disables the usb snooze control. 1 (r/w): enable 0 (r/w): disable (default) when this bit is set to 1 , the usb controller performs a transition sequence and then it enters snooze mode. when this bit is set to 0 , the usb controller resumes operating. for details of the snooze se - quence, see section ix.1.4.4, snooze. d[4:3] reserved d[2:0] usbwt[2:0]: usb register access wait control bits these bits set the number of wait cycles to be inserted when accessing the usb control register. table iii. 4.6.3 number of wait cycles during usb access usbwt2 1 1 1 1 0 0 0 0 usbwt1 1 1 0 0 1 1 0 0 usbwt0 1 0 1 0 1 0 1 0 number of wait cyc les (in units of mclk cyc les) 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle 0 cycles mclk clock frequency 60 mhz or less 56 mhz or less 45 mhz or less 36 mhz or less 24 mhz or less 16 mhz or less 8 mhz or less 8 mhz or less (default: 0b111 = 7 cycles) the number of wait cycles should be set according to the mclk clock frequency.
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300014: debug port mux register (pmisc_pmux) name address register name bit function setting init. r/w remarks C trcmux d7C1 d0 reserved p15C17, p34C36 debug function selection C 1 C r/w 0 when being read. 00300014 (b) debug port mux register (pmisc_pmux) protected C 1 debug 0 gpio, etc. d[7:1] reserved d0 trcmux: p15C17, p34C36 debug function select bit this bit configures the p 15Cp17 and p34Cp36 pins for debugging. 1 (r/w): debug pin (default) 0 (r/w): gpio or peripheral function pin the p 15Cp17 and p34Cp36 pins are shared with the pc trace debugging function and other peripheral functions. these pins are configured as the debug pins dst 0 (p15 ), dst1 (p16 ), dpco (p17 ), dsio (p34 ), dclk (p35 ), and dst2 (p36 ) at initial reset. when using these pins as gpio or other peripheral function pins, trcmux must be set to 0. when trcmux is set to 0 , the port function select bits for p15Cp17 and p34Cp36 are enabled to select the pin function. set trcmux to 1 to use these pins for debugging.
iii peripheral modules 1 (system): misc registers iii-4-10 epson s1c33e08 technical manual 0x300016: performance analyzer control register (pmisc_pac) name address register name bit function setting init. r/w remarks C parun paclr d7C2 d1 d0 reserved test bit test bit C C C C C C do not access in the user program. 00300016 (b) performance analyzer control register (pmisc_pac) protected C C C d[7:2] reserved d1 parun: test bit d0 paclr: test bit note : this register is used for factory tests. do not access from the user program.
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300018: boot register (pmisc_boot) name address register name bit function setting init. r/w remarks boot3 boot2 boot1 boot0 C boot_ena ce10_size d7 d6 d5 d4 d3C2 d1 d0 boot mode indicator reserved #ce10 area boot enable #ce10 area size x x x x C 1 1 r/w C r/w r/w depend on the boot1 and boot0 pin status at initial reset 0 when being read. 00300018 (b) boot register (pmisc_boot) protected C 1 1 internal 16 bits 0 0 external 8 bits boot[3:0] boot mode spi nor flash/rom reserved nand flash 1000 0100 0010 0001 d[7:4] boot[3:0]: boot mode indicator bits these bits indicate the boot device that has been specified by the boot 1 and boot0 pins. table iii. 4.6.4 boot[3:0] bits boo t3 1 0 0 0 boo t2 0 1 0 0 boo t1 0 0 1 0 boo t0 0 0 0 1 boot mode spi boot nor flash/e xter nal r om boot reser ve d nand flash boot these bit are set in the system boot program. do not alter thes e bit values from the user routine. d[3:2] reserved d1 boot_ena: #ce10 area boot enable bit this bit enables fetching the reset vector from the #ce 10 external area (0xc00000). 1 (r/w): internal boot (default) 0 (r/w): external boot this bit is set in the system boot program. when programming a flash memory on the target board, boot_ena must be set to 0. d0 ce10_size: #ce10 area size select bit this bit sets the #ce 10 area size in the booting process. 1 (r/w): 16 bits (default) 0 (r/w): 8 bits this bit is set in the system boot program. do not alter this bit value from the user routine.
iii peripheral modules 1 (system): misc registers iii-4-12 epson s1c33e08 technical manual 0x30001a: corom switch register (pmisc_corom) name address register name bit function setting init. r/w remarks C corom_sw d7C1 d0 reserved test bit C C C C do not access in the user program. 0030001a (b) corom switch register (pmisc_corom) protected C C d[7:1] reserved d0 corom_sw: test bit note : this register is used for factory tests. do not access from the user program.
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300020: misc protect register (pmisc_prot) name address register name bit function setting init. r/w remarks wr iting 10010110 (0x96) remo v es the wr ite protection of the misc registers (0x300010C0x30001a). wr iting another v alue set the wr ite protection. prot7 prot6 prot5 prot4 prot3 prot2 prot1 prot0 d7 d6 d5 d4 d3 d2 d1 d0 misc register protect flag 0 0 0 0 0 0 0 0 r/w 00300020 (b) misc protect register (pmisc_prot) d[7:0] prot[7:0]: misc register protect flag enables/disables write protection of the misc registers ( 0x300010C0x30001a). 0x96 (r/w): disable write protection other than 0x96 (r/w): write-protect the register (default: 0x0) before altering any misc register from 0x300010 to 0x30001 a, write data 0x96 to this register to dis - able write protection. if this register is set to other than 0x96 , even if an attempt is made to alter any misc register by executing a write instruction, the content of said register will not be altered even though the instruction may have been executed without a problem. once this register is set to 0x96 , the misc registers can be rewritten any number of times until being reset to other than 0x96 . when rewrit - ing the misc registers has finished, this register should be set to other than 0x96 to prevent accidental writing to the misc registers.
iii peripheral modules 1 (system): misc registers iii-4-14 epson s1c33e08 technical manual 0x300c41: bus signal low drive control register (pmisc_buslow) name address register name bit function setting init. r/w remarks C ldrvdb ldrvce ldrvad ldrvrw d7C4 d3 d2 d1 d0 reserved d15Cd0 low drive #ce11C#ce4 low drive a24Ca0 low drive #rd,#wrl,#wrh,#bsl low driv e C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300c41 (b) bus signal low drive control register (pmisc_buslow) 1 low drive 0 normal output C d[7:4] reserved d3 ldrvdb: d15Cd0 low drive control bit drives the data bus signals forcibly low. 1 (r/w): low drive 0 (r/w): normal output (default) when ldrvdb is set to 1 , the d15Cd0 signals are forcibly driven low. when it is set to 0 , the signals are controlled by the sramc/sdramc normally. d2 ldrvce: #ce11C#ce4 low drive control bit drives the chip enable signals forcibly low. 1 (r/w): low drive 0 (r/w): normal output (default) when ldrvce is set to 1 , the #ce11C#ce4 signals are forcibly driven low. when it is set to 0 , the signals are controlled by the sramc/sdramc normally. d1 ldrvad: a24Ca0 low drive control bit drives the address bus signals forcibly low. 1 (r/w): low drive 0 (r/w): normal output (default) when ldrvad is set to 1 , the a24Ca0 signals are forcibly driven low. when it is set to 0 , the signals are controlled by the sramc/sdramc normally. d0 ldrvrw: #rd, #wrl, #wrh, #bsl low drive control bit drives the bus control signals forcibly low. 1 (r/w): low drive 0 (r/w): normal output (default) when ldrvrw is set to 1 , the #rd, #wrl, #wrh, and #bsl signals are forcibly driven low. when it is set to 0 , the signals are controlled by the sramc normally. notes : ? when the pins are used as the general-purpose i/o port (p xx ), the low-drive control is not ef - fective. ? if the bus signals are forcibly driven low when the cpu is running by the instructions fetched from an external memory, the cpu will not be able to run after that point. to drive the signals low, the cpu must be running with the program stored in the internal ram.
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300c42: p0 pull-up control register (pmisc_pup0) name address register name bit function setting init. r/w remarks pup07 pup06 pup05 pup04 pup03 pup02 pup01 pup00 d7 d6 d5 d4 d3 d2 d1 d0 p07 pull-up p06 pull-up p05 pull-up p04 pull-up p03 pull-up p02 pull-up p01 pull-up p00 pull-up 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c42 (b) 1 pulled up 0 no pull-up p0 pull-up control register (pmisc_pup0) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d7 pup07: p07 pull-up control bit controls the pull-up resistor at the p 07 port. (default: 0, no pull-up) d6 pup06: p06 pull-up control bit controls the pull-up resistor at the p 06 port. (default: 0, no pull-up) d5 pup05: p05 pull-up control bit controls the pull-up resistor at the p 05 port. (default: 0, no pull-up) d4 pup04: p04 pull-up control bit controls the pull-up resistor at the p 04 port. (default: 0, no pull-up) d3 pup03: p03 pull-up control bit controls the pull-up resistor at the p 03 port. (default: 0, no pull-up) d2 pup02: p02 pull-up control bit controls the pull-up resistor at the p 02 port. (default: 0, no pull-up) d1 pup01: p01 pull-up control bit controls the pull-up resistor at the p 01 port. (default: 0, no pull-up) d0 pup00: p00 pull-up control bit controls the pull-up resistor at the p 00 port. (default: 0, no pull-up)
iii peripheral modules 1 (system): misc registers iii-4-16 epson s1c33e08 technical manual 0x300c43: p1 pull-up control register (pmisc_pup1) name address register name bit function setting init. r/w remarks pup17 pup16 pup15 pup14 pup13 pup12 pup11 pup10 d7 d6 d5 d4 d3 d2 d1 d0 p17 pull-up p16 pull-up p15 pull-up p14 pull-up p13 pull-up p12 pull-up p11 pull-up p10 pull-up 1 1 1 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c43 (b) 1 pulled up 0 no pull-up p1 pull-up control register (pmisc_pup1) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d7 pup17: p17 pull-up control bit controls the pull-up resistor at the p 17 port. (default: 1, pulled up) d6 pup16: p16 pull-up control bit controls the pull-up resistor at the p 16 port. (default: 1, pulled up) d5 pup15: p15 pull-up control bit controls the pull-up resistor at the p 15 port. (default: 1, pulled up) d4 pup14: p14 pull-up control bit controls the pull-up resistor at the p 14 port. (default: 0, no pull-up) d3 pup13: p13 pull-up control bit controls the pull-up resistor at the p 13 port. (default: 0, no pull-up) d2 pup12: p12 pull-up control bit controls the pull-up resistor at the p 12 port. (default: 0, no pull-up) d1 pup11: p11 pull-up control bit controls the pull-up resistor at the p 11 port. (default: 0, no pull-up) d0 pup10: p10 pull-up control bit controls the pull-up resistor at the p 10 port. (default: 0, no pull-up)
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300c44: p2 pull-up control register (pmisc_pup2) name address register name bit function setting init. r/w remarks pup27 pup26 pup25 pup24 pup23 pup22 pup21 pup20 d7 d6 d5 d4 d3 d2 d1 d0 p27 pull-up p26 pull-up p25 pull-up p24 pull-up p23 pull-up p22 pull-up p21 pull-up p20 pull-up 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 00300c44 (b) 1 pulled up 0 no pull-up p2 pull-up control register (pmisc_pup2) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d7 pup27: p27 pull-up control bit controls the pull-up resistor at the p 27 port. (default: 1, pulled up) d6 pup26: p26 pull-up control bit controls the pull-up resistor at the p 26 port. (default: 1, pulled up) d5 pup25: p25 pull-up control bit controls the pull-up resistor at the p 25 port. (default: 1, pulled up) d4 pup24: p24 pull-up control bit controls the pull-up resistor at the p 24 port. (default: 1, pulled up) d3 pup23: p23 pull-up control bit controls the pull-up resistor at the p 23 port. (default: 1, pulled up) d2 pup22: p22 pull-up control bit controls the pull-up resistor at the p 22 port. (default: 1, pulled up) d1 pup21: p21 pull-up control bit controls the pull-up resistor at the p 21 port. (default: 1, pulled up) d0 pup20: p20 pull-up control bit controls the pull-up resistor at the p 20 port. (default: 1, pulled up)
iii peripheral modules 1 (system): misc registers iii-4-18 epson s1c33e08 technical manual 0x300c45: p3 pull-up control register (pmisc_pup3) name address register name bit function setting init. r/w remarks C pup36 pup35 pup34 pup33 pup32 pup31 pup30 d7 d6 d5 d4 d3 d2 d1 d0 reserved p36 pull-up p35 pull-up p34 pull-up p33 pull-up p32 pull-up p31 pull-up p30 pull-up C 1 1 1 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 1 when being read. C 00300c45 (b) 1 pulled up 0 no pull-up p3 pull-up control register (pmisc_pup3) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d7 reserved d6 pup36: p36 pull-up control bit controls the pull-up resistor at the p 36 port. (default: 1, pulled up) d5 pup35: p35 pull-up control bit controls the pull-up resistor at the p 35 port. (default: 1, pulled up) d4 pup34: p34 pull-up control bit controls the pull-up resistor at the p 34 port. (default: 1, pulled up) d3 pup33: p33 pull-up control bit controls the pull-up resistor at the p 33 port. (default: 0, no pull-up) d2 pup32: p32 pull-up control bit controls the pull-up resistor at the p 32 port. (default: 0, no pull-up) d1 pup31: p31 pull-up control bit controls the pull-up resistor at the p 31 port. (default: 0, no pull-up) d0 pup30: p30 pull-up control bit controls the pull-up resistor at the p 30 port. (default: 0, no pull-up)
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300c46: p4 pull-up control register (pmisc_pup4) name address register name bit function setting init. r/w remarks pup47 pup46 pup45 pup44 pup43 pup42 pup41 pup40 d7 d6 d5 d4 d3 d2 d1 d0 p47 pull-up p46 pull-up p45 pull-up p44 pull-up p43 pull-up p42 pull-up p41 pull-up p40 pull-up 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 00300c46 (b) 1 pulled up 0 no pull-up p4 pull-up control register (pmisc_pup4) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d7 pup47: p47 pull-up control bit controls the pull-up resistor at the p 47 port. (default: 1, pulled up) d6 pup46: p46 pull-up control bit controls the pull-up resistor at the p 46 port. (default: 1, pulled up) d5 pup45: p45 pull-up control bit controls the pull-up resistor at the p 45 port. (default: 1, pulled up) d4 pup44: p44 pull-up control bit controls the pull-up resistor at the p 44 port. (default: 1, pulled up) d3 pup43: p43 pull-up control bit controls the pull-up resistor at the p 43 port. (default: 1, pulled up) d2 pup42: p42 pull-up control bit controls the pull-up resistor at the p 42 port. (default: 1, pulled up) d1 pup41: p41 pull-up control bit controls the pull-up resistor at the p 41 port. (default: 1, pulled up) d0 pup40: p40 pull-up control bit controls the pull-up resistor at the p 40 port. (default: 1, pulled up)
iii peripheral modules 1 (system): misc registers iii-4-20 epson s1c33e08 technical manual 0x300c47: p5 pull-up control register (pmisc_pup5) name address register name bit function setting init. r/w remarks pup57 pup56 pup55 pup54 pup53 pup52 pup51 pup50 d7 d6 d5 d4 d3 d2 d1 d0 p57 pull-up p56 pull-up p55 pull-up p54 pull-up p53 pull-up p52 pull-up p51 pull-up p50 pull-up 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 00300c47 (b) 1 pulled up 0 no pull-up p5 pull-up control register (pmisc_pup5) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d7 pup57: p57 pull-up control bit controls the pull-up resistor at the p 57 port. (default: 1, pulled up) d6 pup56: p56 pull-up control bit controls the pull-up resistor at the p 56 port. (default: 1, pulled up) d5 pup55: p55 pull-up control bit controls the pull-up resistor at the p 55 port. (default: 1, pulled up) d4 pup54: p54 pull-up control bit controls the pull-up resistor at the p 54 port. (default: 1, pulled up) d3 pup53: p53 pull-up control bit controls the pull-up resistor at the p 53 port. (default: 1, pulled up) d2 pup52: p52 pull-up control bit controls the pull-up resistor at the p 52 port. (default: 1, pulled up) d1 pup51: p51 pull-up control bit controls the pull-up resistor at the p 51 port. (default: 1, pulled up) d0 pup50: p50 pull-up control bit controls the pull-up resistor at the p 50 port. (default: 1, pulled up)
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300c48: p6 pull-up control register (pmisc_pup6) name address register name bit function setting init. r/w remarks pup67 pup66 pup65 pup64 pup63 pup62 pup61 pup60 d7 d6 d5 d4 d3 d2 d1 d0 p67 pull-up p66 pull-up p65 pull-up p64 pull-up p63 pull-up p62 pull-up p61 pull-up p60 pull-up 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c48 (b) 1 pulled up 0 no pull-up p6 pull-up control register (pmisc_pup6) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d7 pup67: p67 pull-up control bit controls the pull-up resistor at the p 67 port. (default: 0, no pull-up) d6 pup66: p66 pull-up control bit controls the pull-up resistor at the p 66 port. (default: 0, no pull-up) d5 pup65: p65 pull-up control bit controls the pull-up resistor at the p 65 port. (default: 0, no pull-up) d4 pup64: p64 pull-up control bit controls the pull-up resistor at the p 64 port. (default: 0, no pull-up) d3 pup63: p63 pull-up control bit controls the pull-up resistor at the p 63 port. (default: 0, no pull-up) d2 pup62: p62 pull-up control bit controls the pull-up resistor at the p 62 port. (default: 0, no pull-up) d1 pup61: p61 pull-up control bit controls the pull-up resistor at the p 61 port. (default: 0, no pull-up) d0 pup60: p60 pull-up control bit controls the pull-up resistor at the p 60 port. (default: 0, no pull-up)
iii peripheral modules 1 (system): misc registers iii-4-22 epson s1c33e08 technical manual 0x300c49: p7 pull-up control register (pmisc_pup7) name address register name bit function setting init. r/w remarks C pup74 pup73 pup72 pup71 pup70 d7C5 d4 d3 d2 d1 d0 reserved p74 pull-up p73 pull-up p72 pull-up p71 pull-up p70 pull-up C 0 0 0 0 0 C r/w r/w r/w r/w r/w 1 when being read. C 00300c49 (b) 1 pulled up 0 no pull-up p7 pull-up control register (pmisc_pup7) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d[7:5] reserved d4 pup74: p74 pull-up control bit controls the pull-up resistor at the p 74 port. (default: 0, no pull-up) d3 pup73: p73 pull-up control bit controls the pull-up resistor at the p 73 port. (default: 0, no pull-up) d2 pup72: p72 pull-up control bit controls the pull-up resistor at the p 72 port. (default: 0, no pull-up) d1 pup71: p71 pull-up control bit controls the pull-up resistor at the p 71 port. (default: 0, no pull-up) d0 pup70: p70 pull-up control bit controls the pull-up resistor at the p 70 port. (default: 0, no pull-up)
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300c4a: p8 pull-up control register (pmisc_pup8) name address register name bit function setting init. r/w remarks C pup85 pup84 pup83 pup82 pup81 pup80 d7C6 d5 d4 d3 d2 d1 d0 reserved p85 pull-up p84 pull-up p83 pull-up p82 pull-up p81 pull-up p80 pull-up C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 1 when being read. C 00300c4a (b) 1 pulled up 0 no pull-up p8 pull-up control register (pmisc_pup8) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d[7:6] reserved d5 pup85: p85 pull-up control bit controls the pull-up resistor at the p 85 port. (default: 0, no pull-up) d4 pup84: p84 pull-up control bit controls the pull-up resistor at the p 84 port. (default: 0, no pull-up) d3 pup83: p83 pull-up control bit controls the pull-up resistor at the p 83 port. (default: 0, no pull-up) d2 pup82: p82 pull-up control bit controls the pull-up resistor at the p 82 port. (default: 0, no pull-up) d1 pup81: p81 pull-up control bit controls the pull-up resistor at the p 81 port. (default: 0, no pull-up) d0 pup80: p80 pull-up control bit controls the pull-up resistor at the p 80 port. (default: 0, no pull-up)
iii peripheral modules 1 (system): misc registers iii-4-24 epson s1c33e08 technical manual 0x300c4b: p9 pull-up control register (pmisc_pup9) name address register name bit function setting init. r/w remarks pup97 pup96 pup95 pup94 pup93 pup92 pup91 pup90 d7 d6 d5 d4 d3 d2 d1 d0 p97 pull-up p96 pull-up p95 pull-up p94 pull-up p93 pull-up p92 pull-up p91 pull-up p90 pull-up 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c4b (b) 1 pulled up 0 no pull-up p9 pull-up control register (pmisc_pup9) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d7 pup97: p97 pull-up control bit controls the pull-up resistor at the p 97 port. (default: 0, no pull-up) d6 pup96: p96 pull-up control bit controls the pull-up resistor at the p 96 port. (default: 0, no pull-up) d5 pup95: p95 pull-up control bit controls the pull-up resistor at the p 95 port. (default: 0, no pull-up) d4 pup94: p94 pull-up control bit controls the pull-up resistor at the p 94 port. (default: 0, no pull-up) d3 pup93: p93 pull-up control bit controls the pull-up resistor at the p 93 port. (default: 0, no pull-up) d2 pup92: p92 pull-up control bit controls the pull-up resistor at the p 92 port. (default: 0, no pull-up) d1 pup91: p91 pull-up control bit controls the pull-up resistor at the p 91 port. (default: 0, no pull-up) d0 pup90: p90 pull-up control bit controls the pull-up resistor at the p 90 port. (default: 0, no pull-up)
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300c4c: pa pull-up control register (pmisc_pupa) name address register name bit function setting init. r/w remarks C pupa4 pupa3 pupa2 pupa1 pupa0 d7C5 d4 d3 d2 d1 d0 reserved pa4 pull-up pa3 pull-up pa2 pull-up pa1 pull-up pa0 pull-up C 1 1 1 1 1 C r/w r/w r/w r/w r/w 1 when being read. C 00300c4c (b) 1 pulled up 0 no pull-up pa pull-up control register (pmisc_pupa) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d[7:5] reserved d4 pupa4: pa4 pull-up control bit controls the pull-up resistor at the pa 4 port. (default: 1, pulled up) d3 pupa3: pa3 pull-up control bit controls the pull-up resistor at the pa 3 port. (default: 1, pulled up) d2 pupa2: pa2 pull-up control bit controls the pull-up resistor at the pa 2 port. (default: 1, pulled up) d1 pupa1: pa1 pull-up control bit controls the pull-up resistor at the pa 1 port. (default: 1, pulled up) d0 pupa0: pa0 pull-up control bit controls the pull-up resistor at the pa 0 port. (default: 1, pulled up)
iii peripheral modules 1 (system): misc registers iii-4-26 epson s1c33e08 technical manual 0x300c4d: pb pull-up control register (pmisc_pupb) name address register name bit function setting init. r/w remarks C pupb3 pupb2 pupb1 pupb0 d7C4 d3 d2 d1 d0 reserved pb3 pull-up pb2 pull-up pb1 pull-up pb0 pull-up C 1 1 1 1 C r/w r/w r/w r/w 1 when being read. C 00300c4d (b) 1 pulled up 0 no pull-up pb pull-up control register (pmisc_pupb) this register controls the pull-up resistors for the i/o port pins. 1 (r/w): pulled up 0 (r/w): no pull-up when the pull-up control bit is set to 1 , the corresponding pins are pulled up to high during input mode. when it is set to 0 , the pins are not pulled up. when the port is in output mode, the port pin is not pulled up even if the pull-up control bit is set to 1. the pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on- chip peripheral circuit or general-purpose i/o port. d[7:4] reserved d3 pupb3: pb3 pull-up control bit controls the pull-up resistor at the pb 3 port. (default: 1, pulled up) d2 pupb2: pb2 pull-up control bit controls the pull-up resistor at the pb 2 port. (default: 1, pulled up) d1 pupb1: pb1 pull-up control bit controls the pull-up resistor at the pb 1 port. (default: 1, pulled up) d0 pupb0: pb0 pull-up control bit controls the pull-up resistor at the pb 0 port. (default: 1, pulled up)
iii peripheral modules 1 (system): misc registers s1c33e08 technical manual epson iii-4-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iii.4.7 precautions ? the misc registers at addresses 0x300010C0x30001 a are write-protected. before the misc registers can be re - written, write protection of these registers must be removed by writing data 0x96 to the misc protect register (0x300020 ). note that since unnecessary rewrites to addresses 0x300010C0x30001 a could lead to erratic system operation, the misc protect register ( 0x300020 ) should be set to other than 0x96 unless said misc registers must be rewritten. ? the low-drive control bit is disabled when the pin is used as the general-purpose i/o port (p xx). ? if the bus signals are forcibly driven low when the cpu is running by the instructions fetched from an external memory, the cpu will not be able to run after that point. to drive the signals low, the cpu must be running with the program stored in the internal ram.
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i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual iv peripheral m odules 2 (t imers)

iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iv. 1 16 -bit timers (t16) iv. 1.1 configuration of 16 -bit timer the s 1c33e08 contains 6 systems of 16 -bit programmable timers (timers 0 to 5 ). the following lists the main functions of the 16-bit timers. ? programmable count clocks using the prescaler embedded in each 16-bit timer ? event counter function using external clocks ? interrupt generation function with programmable interrupt cycles using the compare data registers ? pwm output using the compare data registers ? supports fine mode and da16 mode suitable for high-quality audio output using pwm note : on the following pages, each timer is identified as timer x ( x = 0 to 5). the functions and control register structures of 16-bit timers 0 to 5 are the same. control bit names are assigned numerals 0 to 5 denoting timer numbers. since explanations are common to all timers, timer numbers are represented by x unless it is necessary to specify a timer number. figure iv. 1.1.1 shows the structure of one channel of the 16 -bit timer. data bus 16-bit up counter (tc x ) 16-bit comparison data register b (cr x b) comparison register b buffer (crb x b) 16-bit comparison data register a (cr x a) comparison register a buffer (crb x a) timer x control register control circuit clock select circuit prescaler cmu comparator comparator incl x clock output tm x comparison a interrupt comparison b interrupt comparison match b comparison match a comparison a comparison b timer x interrupt controller external clock excl x figure iv. 1.1.1 structure of 16 -bit timer in each timer, a 16 -bit up-counter (tc x[15:0 ] (d[15:0]/0x300784 + 8? x )), as well as two 16 -bit comparison data registers (cr x a[ 15 : 0 ] (d[ 15 : 0 ]/ 0 x 300780 + 8 ? x ), cr x b[ 15 : 0 ] (d[ 15 : 0 ]/ 0 x 300782 + 8 ? x )) and their buffers (crb x a, crb x b), are provided. ? tc x [15:0] : 16-bit timer x counter data bits in the 16-bit timer x counter data register (d[15:0]/0x300784 + 8? x ) ? cr x a[15:0] : 16-bit timer x comparison data a bits in the 16-bit timer x comparison data a setup register (d[15:0]/0x300780 + 8? x ) ? cr x b[15:0] : 16-bit timer x comparison data b bits in the 16-bit timer x comparison data b setup register (d[15:0]/0x300782 + 8? x ) the 16 -bit counter can be reset to 0 by software and counts up using the prescaler output clock or an external signal input from the i/o port. the counter value can be read by software.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-2 epson s1c33e08 technical manual the comparison data registers a and b are used to store the data to be compared with the content of the up- counter. this register can be directly read and written. furthermore, comparison data can be set via the comparison register buffer. in this case, the set value is loaded to the comparison data register when the counter is reset by the comparison match b signal or software (by writing 1 to preset x (d1/0x300786 + 8? x )). the software can select whether comparison data is written to the comparison data register or the buffer. ? preset x : 16-bit timer x reset bit in the 16-bit timer x control register (d1/0x300786 + 8? x ) when the counter value matches to the content of each comparison data register, the comparator outputs a signal that controls the interrupt and the output signal. thus the registers allow interrupt generating intervals and the timer's output clock frequency and duty ratio to be programmed.
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iv. 1.2 i/o pins of 16 -bit timers table iv. 1.2.1 shows the input/output pins used for the 16-bit timers. table iv. 1.2.1 i/o pins of 16 -bit timer pin name excl0 excl1 excl2 excl3 excl4 excl5 tm0 tm1 tm2 tm3 tm4 tm5 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o function 16-bit timer 0 ev ent counter input 16-bit timer 1 ev ent counter input 16-bit timer 2 ev ent counter input 16-bit timer 3 ev ent counter input 16-bit timer 4 ev ent counter input 16-bit timer 5 ev ent counter input 16-bit timer 0 output 16-bit timer 1 output 16-bit timer 2 output 16-bit timer 3 output 16-bit timer 4 output 16-bit timer 5 output tm x (output pin of the 16-bit timer) this pin outputs a clock generated by the timer x . excl x (event counter input pin) when using the timer x as an event counter, input count pulses from an external source to this pin. note : the 16-bit timer input/output pins are shared with general-purpose i/o ports or other peripheral circuit inputs/outputs, so that functionality in the initial state is set to other than the 16-bit timer input/output. before the 16-bit timer input/output signals assigned to these pins can be used, the function of these pins must be switched for the 16-bit timer input/output by setting the corresponding port function select registers. for details of pin functions and how to switch over, see section i.3.3, switching over the multiplexed pin functions.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-4 epson s1c33e08 technical manual iv. 1.3 uses of 16 -bit timers the up-counters of the 16 -bit timer cyclically output a comparison-match signal in accordance with the comparison data that are set in the software. this signal is used to generate an interrupt request to the cpu or control the internal peripheral circuits. a clock generated from the signal can also be output to external devices. cpu interrupt request/idma invocation request (timers 0 to 5) each timer's comparison match (matching of counter and comparison data) can be used as a cause of interrupt to generate an interrupt request to the cpu. therefore, an interrupt can be generated at an interval that is set in the software. furthermore, this cause of interrupt can also be used to invoke idma or hsdma. clock output to external devices (timers 0 to 5) a clock generated from the comparison-match signal can be output from the chip to the outside. the clock cycle is determined by comparison data b, and the duty ratio is determined by comparison data a. this output can be used to control external devices. the output pin of each timer is described in the preceding section. a/d converter start trigger (timer 0) the a/d converter allows a trigger to start the a/d conversion to be selected from among four available types. one is the comparison-match b of the 16 -bit timer 0 . this makes it possible to perform the a/d conversion at programmable intervals. to use this function, write 0b01 to the a/d converter control bit ts[1:0 ] (d[4:3]/0x300542 ) to select the 16-bit timer 0 as the trigger. ? ts[1:0] : a/d conversion trigger select bits in the a/d trigger/channel select register (d[4:3]/0x300542)
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iv. 1.4 16 -bit timer operating clock the 16 -bit timers use the tm x _clk clock (= mclk) generated by the cmu as the operating clock. the count clock is generated from the tm x _clk by the prescaler embedded in each timer. controlling the supply of the operating clock the tm x _clk clock is supplied to the 16 -bit timers with default settings. it can be turned off using tm x_cke (d13+ x/0x301b04 ) to reduce the amount of power consumed on the chip if 16-bit timers are not used. ? tm x _cke : 16-bit timer x clock control bit in the gated clock control register 1 (d13+ x /0x301b04) setting tm x _cke (d13+ x/0x301b04 ) to 0 (1 by default) turns off the tm x _clk clock supply to the 16-bit timer x . when the clock supply is turned off, the 16 -bit timer control registers cannot be accessed and the count operation stops. for details on how to set and control the operating clock, refer to section iii. 1, clock management unit (cmu). clock state in standby mode the clock supply to the 16-bit timer stops depending on type of standby mode. halt mode: the operating clock is supplied the same way as in normal mode. sleep mode: the operating clock supply stops. therefore, the 16-bit timer also stops operating in sleep mode.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-6 epson s1c33e08 technical manual iv. 1.5 control and operation of 16 -bit timer the following settings must first be made before the 16-bit timer starts counting: 1. setting pins for input/output (only when necessary) ... see sections iv.1.2 and i.3.3. 2. setting count clock 3 . selecting comparison data register/buffer 4 . setting clock output conditions (signal active level, initial signal level, fine mode) ... see section iv.1.6. 5. setting comparison data 6 . setting interrupt/dma ... see section iv.1.7. standard mode and advanced mode the 16 -bit timer in the s1c33e08 is extended from that of the c33 std models. this 16 -bit timer has two operating modes, standard (std) mode of which functions are compatible with the existing c 33 std models and an advanced (adv) mode allowing use of the extended functions. table iv. 1.5.1 shows differences between standard mode and advanced mode. table iv. 1.5.1 differences between standard mode and advanced mode function wr iting to the count data register setting of the initial timer output le v el (high or lo w) d a16 function (d a16 registers) multiple timer full-sync function ad v anced mode enabled enabled (can be specified using initol x ) can be used supported (can be controlled using pause x ) standar d mode disabled (read only) disabled (depending on the outinv x set value) cannot be used not supported to configure the 16 -bit timer in advanced mode, set t16 adv (d0/0x3007 de) to 1 . the control registers/bits for the extended functions are enabled to write after this setting. at initial reset, t 16 adv (d0/0x3007de) is set to 0 and the 16-bit timer enters standard mode. ? t16adv : standard mode/advanced mode select bit in the 16-bit timer std/adv mode select register (d0/0x3007de) the following descriptions unless otherwise specified are common contents for both modes. the extended functions in advanced mode are explained assuming that t 16 adv (d0/0x3007de) has been set to 1. note : standard or advanced mode currently set is applied to all the 16-bit timers. it cannot be selected for each timer individually. setting the count clock the count clock for each timer can be selected from between an internal clock and an external clock. select the input clock using cksl x (d3/0x300786 + 8? x). ? cksl x : 16-bit timer x input clock select bit in the 16-bit timer x control register (d3/0x300786 + 8? x ) an external clock is selected by writing 1 to cksl x (d3/0x300786 + 8? x ), and the internal clock is selected by writing 0 . at initial reset, cksl x (d3/0x300786 + 8? x) is set for the internal clock. an external clock can be used for the timer for which the pin is set for input. ? internal clock when the internal clock is selected as a timer, the count clock is generated from the tm x _clk (= mclk) by the prescaler embedded in each timer. the prescaler's division ratio can be selected from among eight ratios using p 16 ts x [ 2 : 0 ] (d[ 2 : 0 ]/ 0 x 3007 e 0 + 2 ? x ). the divided clock is output from the prescaler by writing 1 to p16 ton x (d3/0x3007e0 + 2? x). ? p16ts x [2:0] : 16-bit timer x clock division ratio select bits in the 16-bit timer x clock control register (d[2:0]/0x3007e0 + 2? x ) ? p16ton x : 16-bit timer x clock control bit in the 16-bit timer x clock control register (d3/0x3007e0 + 2? x )
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 table iv. 1.5.2 division ratio p16ts x 2 1 1 1 1 0 0 0 0 p16ts x 1 1 1 0 0 1 1 0 0 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 p16ts x 0 1 0 1 0 1 0 1 0 (default: 0b000 = mclk/1) notes : ? when setting a count clock, make sure the 16 -bit timer is turned off. ? p 16 ton x (d 3 / 0 x 3007 e 0 + 2 ? x ) for unused timers should be set to 0 to reduce current consumption. ? external clock when using the timer as an event counter by supplying clock pulses from an external source, make sure the event cycle is at least two cpu operating clock cycles. selecting comparison data register/buffer the comparison data registers a and b are used to store the data to be compared with the content of the up- counter. this register can be directly read and written. furthermore, comparison data can be set via the comparison register buffer. in this case, the set value is loaded to the comparison data register when the counter is reset by the comparison match b signal or software (by writing 1 to preset x (d1/0x300786 + 8? x)). select whether comparison data is written to the comparison data register or the buffer using selcrb x (d5/ 0x300786 + 8? x ). ? selcrb x : 16-bit timer x comparison register buffer enable bit in the 16-bit timer x control register (d5/0x300786 + 8? x ) when 1 is written to selcrb x (d5/0x300786 + 8? x ), the comparison register buffer is selected and when 0 is written, the comparison data register is selected. at initial reset, the comparison data register is selected. setting comparison data the timer contains two data comparators that allows the count data to be compared with given values. cr xa[15:0] (d[15:0]/0x300780 + 8? x) and cr xb[15:0] (d[15:0]/0x300782 + 8? x ) are used to set these values. ? cr x a[15:0] : 16-bit timer x comparison data a bits in the 16-bit timer x comparison data a setup register (d[15:0]/0x300780 + 8? x ) ? cr x b[15:0] : 16-bit timer x comparison data b bits in the 16-bit timer x comparison data b setup register (d[15:0]/0x300782 + 8? x ) when selcrb x (d5/0x300786 + 8? x ) is set to 0 , these registers allow direct reading/writing from/to the comparison data register. when selcrb x is set to 1 , these registers are used to read/write from/to the comparison register buffer. the content of the buffer is loaded to the comparison data register when the counter is reset. at initial reset, the comparison data registers/buffers are not initialized. the timer compares the comparison data register and count data and, when the two values are equal, generates a comparison match signal. this comparison match signal controls the clock output (tm x signal) to external devices, in addition to generating an interrupt. the comparison data b is also used to reset the counter.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-8 epson s1c33e08 technical manual da 16 function (advanced mode) advanced mode supports the da 16 function that divides a 16 -bit data into 10 high-order bits and 6 low-order bits and writes them to the comparison data a registers (or buffers) of a two timer pair simultaneously. this makes it possible to reduce software load for using two 16-bit timers as a 16 -bit d/a converter. three da 16 registers are provided for this function. the following shows the correspondence between these registers and timers: (timer a and timer b) da 16 ch.0 register (0x3007d0 ): timer 1 and timer 2 da 16 ch.1 register (0x3007d2 ): timer 3 and timer 4 da 16 ch.2 register (0x3007d4 ): timer 5 and timer 0 when data is written to this register, 10 high-order bits are loaded into the timer a comparison data a setup register (buffer) as 10 low-order compare data bits and 6 low-order bits are loaded into the timer b comparison data a setup register (buffer) as 6 low-order compare data bits. in standard mode, data cannot be written to the da 16 registers. timer 1 timer 2 cr1a[9:0] 16-bit data write or or comparison data a register comparison data a register buffer da16 ch.0 register da0a[15:6] cr2a[5:0] (cr1a[15:10] = 0) (cr2a[15:6] = 0) da0a[5:0] (selcrb1 = 1) (selcrb1 = 0) (selcrb2 = 1) (selcrb2 = 0) comparator comparison data a register comparison data a register buffer comparator figure iv. 1.5.1 da16 function (ch.0) resetting the counter each timer includes preset x (d1/0x300786 + 8? x ) to reset the counter. ? preset x : 16-bit timer x reset bit in the 16-bit timer x control register (d1/0x300786 + 8? x ) normally, reset the counter before starting count-up by writing 1 to this control bit. after the counter starts counting, it will be reset by comparis on match b. timer run/stop control each timer includes prun x (d0/0x300786 + 8? x ) to control run/stop. ? prun x : 16-bit timer x run/stop control bit in the 16-bit timer x control register (d0/0x300786 + 8? x ) the timer starts counting when 1 is written to prun x (d0/0x300786 + 8? x ). the clock input is disabled and the timer stops counting when 0 is written to prun x . this run/stop control does not affect the counter data. even when the timer has stopped counting, the counter retains its count so that the timer can start counti ng again from that point. if the count of the counter matches the set value of the comparison data register during count-up, the timer generates a comparison match interrupt. when the counter matches comparison data b, an interrupt is generated and the counter is reset. at the same time, the values set in the compare register buffer are loaded to the compare data register if selcrb x (d5/ 0x300786 + 8? x) is set to 1. the counter continues counting up regardless of which interrupt has occurred. in the case of a comparison b interrupt, the counter starts counting beginning with 0. when both prun x (d0/0x300786 + 8? x ) and preset x (d1/0x300786 + 8? x ) are set to 1 at the same time, the timer starts counting after resetting the counter.
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 prun x preset x cr x a cr x b input clock tc x reset comparison a interrupt reset and comparison b interrupt comparison a interrupt reset and comparison b interrupt 0x2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 0x5 figure iv. 1.5.2 basic operation timing of counter to synchronize multiple timers (advanced mode) since the timer run/stop control bits are located in different addresses, two or more timers cannot be started at the same time. to synchronize multiple timers, the control bits pause x (d x/0x3007 dc) that stop each timer are provided in an address. ? pause x : 16-bit timer x count pause bit in the count pause register (d x /0x3007dc) when pause x (d x/0x3007 dc) is set to 1 , timer x is placed in pause state and when set to 0 , timer x starts counting or continues stop state according to the set value of prun x (d0/0x300786 + 8? x). however, it is necessary to set the 16 -bit timer in advanced mode for using pause x (d x/0x3007dc). the following shows a procedure to synchronize multiple timers. 1 . set the prescaler clocks for the timers to be synchronized to t he same condition. 2 . set pause x (d x/0x3007dc) for the timers to 1 to place the timers in pause state. 3 . set prun x (d0/0x300786 + 8? x) for the timers to 1. the timers do not start counting at this time as pause x (d x/0x3007 dc) for the timers have been set to 1. 4 . set all the pause x (d x/0x3007dc) bits for the timers to 0 at the same time. the corresponding timers start counting simultaneously. reading counter data the counter data can be read out from tc x[15:0] (d[15:0]/0x300784 + 8? x ) at any time. ? tc x [15:0] : 16-bit timer x counter data bits in the 16-bit timer x counter data register (d[15:0]/0x300784 + 8? x ) writing counter data (advanced mode) in advanced mode, counter data can be written to tc x[15:0 ] (d[15:0]/0x300784 + 8? x ) at any time. this makes it possible to change the interrupt and/or clock output cycles temporarily. standard mode does not allow writing of counter data.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-10 epson s1c33e08 technical manual iv. 1.6 controlling clock output the timers can generate a tm x signal using the comparison match signals from the counter. figure iv. 1.6.1 shows the 16-bit timer clock output circuit. logic initol x compare a compare b clock ptm x tm x outinv x d q q mux mux figure iv. 1.6.1 16 -bit timer clock output circuit setting the initial output level (advanced mode) the default output level while the clock output is turned off is 0 (low level). this level can be changed to 1 (high level) using initol x (d8/0x300786 + 8? x ). however, this function is available only in advanced mode. ? initol x : 16-bit timer x initial output level select bit in the 16-bit timer x control register (d8/0x300786 + 8? x ) when initol x (d 8 / 0 x 300786 + 8 ? x ) is 0 (default), the initial output level is low. when initol x (d 8 / 0 x 300786 + 8? x) is set to 1 , the initial output level is set to high. the timer output goes to the initial output level when the timer is reset by writing 1 to preset x (d1/0x300786 + 8? x ) as well as when the timer output is turned off. setting the signal active level by default, an active high signal (normal low) is generated. this logic can be inverted using outinv x (d4/ 0x300786 + 8? x ). when 1 is written to outinv x , the timer generates an active low (normal high) signal. ? outinv x : 16-bit timer x clock output inversion bit in the 16-bit timer x control register (d4/0x300786 + 8? x ) note that the initial output level set by initol x (d 8 / 0 x 300786 + 8 ? x ) is inverted when outinv x (d 4 / 0 x 300786 + 8? x) is set to 1. see figure iv. 1.6.2 for the waveforms. setting the output port the tm x signal generated here can be output from the clock output pins (see table iv.1.2.1 ), enabling a programmable clock to be supplied to external devices. after a cold start, the output pins are set for the i/o ports and set in input mode. the pins go into high- impedance status. when the pin function is switched to the timer output, the pin outputs the level according to the set values of initol x (d8/0x300786 + 8? x ) and outinv x (d4/0x300786 + 8? x ). the output pin holds this level until the output level changes due to the counter value after the timer output is enabled. table iv. 1.6.1 initial output level init ol x 1 1 0 0 outinv x 1 0 1 0 initial output le vel lo w high high lo w
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 starting clock output to output the tm x clock, write 1 to the clock output control bit ptm x (d2/0x300786 + 8? x ). clock output is stopped by writing 0 to ptm x and goes to the initial output level according to the set values of initol x (d8/ 0x300786 + 8? x ) and outinv x (d4/0x300786 + 8? x). ? ptm x : 16-bit timer x clock output control bit in the 16-bit timer x control register (d2/0x300786 + 8? x ) figure iv. 1.6.2 shows the waveform of the output signal. input clock preset x ptm x prun x counter value comparison match a signal comparison match b signal tm x output (initol x = 0, outinv x = 0) tm x output (initol x = 0, outinv x = 1) tm x output (initol x = 1, outinv x = 0) tm x output (initol x = 1, outinv x = 1) 1 2 3 4 5 0 0 1 2 3 4 5 0 1 2 3 4 5 0 1 (when cr x a = 3 and cr x b = 5) figure iv. 1.6.2 waveform of 16 -bit timer output when outinv x (d4/0x300786 + 8? x) = 0 (active high): the timer outputs a low level (initial output level when output is started) until the counter becomes equal to the comparison data a set in cr xa[15:0 ] (d[15:0]/0x300780 + 8? x ). when the counter is incremented to the next value from the comparison data a, the output pin goes high and a comparison a interrupt occurs. when the counter becomes equal to the comparison data b set in cr xb[15:0 ] (d[15:0]/0x300782 + 8? x ), the counter is reset and the output pin goes low. at the same time a comparison b interrupt occurs. ? cr x a[15:0] : 16-bit timer x comparison data a bits in the 16-bit timer x comparison data a setup register (d[15:0]/0x300780 + 8? x ) ? cr x b[15:0] : 16-bit timer x comparison data b bits in the 16-bit timer x comparison data b setup register (d[15:0]/0x300782 + 8? x ) when outinv x (d4/0x300786 + 8? x) = 1 (active low): the timer outputs a high level (inverted initial output level when output is started) until the counter becomes equal to the comparison data a set in cr xa[15:0 ] (d[15:0]/0x300780 + 8? x ). when the counter is incremented to the next value from the comparison data a, the output pin goes low and a comparison a interrupt occurs. when the counter becomes equal to the comparison data b set in cr xb[15:0 ] (d[15:0]/0x300782 + 8? x ), the counter is reset and the output pin goes high. at the same time a comparison b interrupt occurs.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-12 epson s1c33e08 technical manual setting clock output fine mode by default (after an initial reset), the clock output signal changes at the rising edge of the input clock when cr xa[15:0] (d[15:0]/0x300780 + 8? x ) becomes equal to tc x[15:0] (d[15:0]/0x300784 + 8? x). ? tc x [15:0] : 16-bit timer x counter data bits in the 16-bit timer x counter data register (d[15:0]/0x300784 + 8? x ) in fine mode, the output signal changes according to cr xa0 (d0/0x300780 + 8? x ) when cr xa[15:1 ] (d[15:1]/ 0x300780 + 8? x ) becomes equal to tc x[14:0] (d[14:0]/0x300784 + 8? x). when cr xa0 is 0, the output signal changes at the rising edge of the input clock. when cr xa0 is 1 , the output signal changes at the falling edge of the input clock a half cycle from the default setting. input clock counter value cr x a cr x b comparison match a signal comparison match b signal tm x output (outinv x = 0) tm x output (outinv x = 1) 0 2 3 4 5 6 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 5 figure iv. 1.6.3 clock output in fine mode as shown in the figure above, in fine mode the output clock duty ratio can be adjusted in the half cycle of the input clock. however, when cr xa[15:0 ] value is 0 , the timer outputs a pulse with a 1 -cycle width as the input clock, the same as the default setting. in fine mode, the maximum value of cr xb[15:0 ] is 2 15 - 1 = 32,767 and the range of cr xa[15:0 ] that can be set is 0 to (2 cr xb[15:0] - 1). the fine mode is set using selfm x (d6/0x300786 + 8? x). ? selfm x : 16-bit timer x fine mode select bit in the 16-bit timer x control register (d6/0x300786 + 8? x ) when 1 is written to selfm x (d6/0x300786 + 8? x ), fine mode is set. at initial reset, the fine mode is disabled. precautions (1 ) if a same value is set to the comparison data a and b registers, a hazard may be generated in the output signal. therefore, do not set the comparison registers as a = b. there is no problem when the interrupt function only is used. (2 ) when using the output clock, set the comparison data registers as a 0 and b 1 . the minimum settings are a = 0 and b = 1 . in this case, the timer output clock cycle is the input clock 1/2. (3 ) when the comparison data registers are set as a > b, no comparison a signal is generated. in this case, the output signal is fixed at the off level.
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iv. 1.7 16 -bit timer interrupts and dma the 16-bit timer has a function for generating an interrupt using the comparison match a and b states. the timing at which an interrupt is generated is shown in figure iv. 1.5.2 in the preceding section. control registers of the interrupt controller table iv. 1.7.1 shows the control registers of the interrupt controller provided for each timer. table iv. 1.7.1 control registers of interrupt controller cause of interrupt timer 0 compar ison a timer 0 compar ison b timer 1 compar ison a timer 1 compar ison b timer 2 compar ison a timer 2 compar ison b timer 3 compar ison a timer 3 compar ison b timer 4 compar ison a timer 4 compar ison b timer 5 compar ison a timer 5 compar ison b cause-of-interrupt fla g f16tc0 (d3/0x300282) f16tu0 (d2/0x300282) f16tc1 (d7/0x300282) f16tu1 (d6/0x300282) f16tc2 (d3/0x300283) f16tu2 (d2/0x300283) f16tc3 (d7/0x300283) f16tu3 (d6/0x300283) f16tc4 (d3/0x300284) f16tu4 (d2/0x300284) f16tc5 (d7/0x300284) f16tu5 (d6/0x300284) interrupt priority register p16t0[2:0] (d[2:0]/0x300266) p16t1[2:0] (d[6:4]/0x300266) p16t2[2:0] (d[2:0]/0x300267) p16t3[2:0] (d[6:4]/0x300267) p16t4[2:0] (d[2:0]/0x300268) p16t5[2:0] (d[6:4]/0x300268) interrupt enable register e16tc0 (d3/0x300272) e16tu0 (d2/0x300272) e16tc1 (d7/0x300272) e16tu1 (d6/0x300272) e16tc2 (d3/0x300273) e16tu2 (d2/0x300273) e16tc3 (d7/0x300273) e16tu3 (d6/0x300273) e16tc4 (d3/0x300274) e16tu4 (d2/0x300274) e16tc5 (d7/0x300274) e16tu5 (d6/0x300274) when a comparison match state occurs in the timer, the corresponding cause-of-interrupt flag is set to 1. if the interrupt enable register bit corresponding to that cause-of-interrupt flag has been set to 1 , an interrupt request is generated. an interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to 0 . the cause-of-interrupt flag is always set to 1 by the timer's comparison match state, regardless of how the interrupt enable register is set (even when set to 0). the interrupt priority register sets an interrupt priority level ( 0 to 7 ) for each timer. priorities within a timer block are such that timers of smaller numbers have a higher priority. priorities between interrupt types are such that the comparison b interrupt has priority over the comparison a interrupt. an interrupt request to the cpu is accepted only when no other interrupt request of a higher priority has been generated. it is only when the psr's ie bit = 1 (interrupts enabled) and the set value of the il is smaller than the timer interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the cpu. for details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to section iii.2, interrupt controller (itc).
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-14 epson s1c33e08 technical manual intelligent dma the cause of interrupt of each timer can also invoke intelligent dma (idma). this allows memory-to-memory dma transfers to be performed cyclically. the following shows the idma channel numbers set for each cause of interrupt of timer: idma ch. idma ch. timer 0 comparison b: 0x07 timer 0 comparison a: 0x08 timer 1 comparison b: 0x09 timer 1 comparison a: 0x0a timer 2 comparison b: 0x0 b timer 2 comparison a: 0x0c timer 3 comparison b: 0x0 d timer 3 comparison a: 0x0e timer 4 comparison b: 0x0 f timer 4 comparison a: 0x10 timer 5 comparison b: 0x11 timer 5 comparison a: 0x12 for idma to be invoked, the idma request and idma enable bits shown in table iv. 1.7.2 must be set to 1 in advance. transfer conditions, etc. must also be set on the idma side in advance. table iv. 1.7.2 control bits for idma transfer cause of interrupt timer 0 compar ison a timer 0 compar ison b timer 1 compar ison a timer 1 compar ison b timer 2 compar ison a timer 2 compar ison b timer 3 compar ison a timer 3 compar ison b timer 4 compar ison a timer 4 compar ison b timer 5 compar ison a timer 5 compar ison b idma request bit r16tc0(d7/0x300290) r16tu0(d6/0x300290) r16tc1(d1/0x300291) r16tu1(d0/0x300291) r16tc2(d3/0x300291) r16tu2(d2/0x300291) r16tc3(d5/0x300291) r16tu3(d4/0x300291) r16tc4(d7/0x300291) r16tu4(d6/0x300291) r16tc5(d1/0x300292) r16tu5(d0/0x300292) idma enable bit de16tc0(d7/0x300294) de16tu0(d6/0x300294) de16tc1(d1/0x300295) de16tu1(d0/0x300295) de16tc2(d3/0x300295) de16tu2(d2/0x300295) de16tc3(d5/0x300295) de16tu3(d4/0x300295) de16tc4(d7/0x300295) de16tu4(d6/0x300295) de16tc5(d1/0x300296) de16tu5(d0/0x300296) if the idma request and enable bits are set to 1 , idma is invoked through generation of a cause of interrupt. no interrupt request is generated at that point. an interrupt request is generated after the dma transfer is completed. the registers can also be set so as not to generate an interrupt, with only a dma transfer performed. for details on idma transfers and interrupt control upon completion of idma transfer, refer to section ii. 2, intelligent dma (idma).
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 high-speed dma the timer 0C5 interrupt causes can also invoke high-speed dma (hsdma). the following shows the hsdma channel number and trigger set-up bit corresponding to the channel 0 to 5 timers: table iv. 1.7.3 hsdma trigger set-up bits cause of interrupt timer 0 compar ison a timer 0 compar ison b timer 1 compar ison a timer 1 compar ison b timer 2 compar ison a timer 2 compar ison b timer 3 compar ison a timer 3 compar ison b timer 4 compar ison b timer 5 compar ison b hsdma channel 0 0 1 1 2 2 3 3 0 1 t rigger set-up bits hsd0s[3:0] (d[3:0]) / hsdma ch.0C1 tr igger set-up register (0x300298) = 0111 hsd0s[3:0] (d[3:0]) / hsdma ch.0C1 tr igger set-up register (0x300298) = 0110 hsd1s[3:0] (d[7:4]) / hsdma ch.0C1 tr igger set-up register (0x300298) = 0111 hsd1s[3:0] (d[7:4]) / hsdma ch.0C1 tr igger set-up register (0x300298) = 0110 hsd2s[3:0] (d[3:0]) / hsdma ch.2C3 tr igger set-up register (0x300299) = 0111 hsd2s[3:0] (d[3:0]) / hsdma ch.2C3 tr igger set-up register (0x300299) = 0110 hsd3s[3:0] (d[7:4]) / hsdma ch.2C3 tr igger set-up register (0x300299) = 0111 hsd3s[3:0] (d[7:4]) / hsdma ch.2C3 tr igger set-up register (0x300299) = 0110 hsd0s[3:0] (d[3:0]) / hsdma ch.0C1 tr igger set-up register (0x300298) = 1000 hsd1s[3:0] (d[7:4]) / hsdma ch.0C1 tr igger set-up register (0x300298) = 1000 for hsdma to be invoked, a 16 -bit timer interrupt cause should be selected using the trigger set-up bits in advance. transfer conditions, etc. must also be set on the hsdma side. if a 16 -bit timer is selected as the hsdma trigger, the hsdma channel is invoked through generation of the cause of interrupt. for details on hsdma transfer, refer to section ii. 1, high-speed dma (hsdma). trap vectors the trap vector addresses for each default cause of interrupt are set as shown below: timer 0 comparison b: 0xc00078 timer 0 comparison a: 0xc0007c timer 1 comparison b: 0xc00088 timer 1 comparison a: 0xc0008c timer 2 comparison b: 0xc00098 timer 2 comparison a: 0xc0009c timer 3 comparison b: 0xc000a8 timer 3 comparison a: 0xc000 ac timer 4 comparison b: 0xc000b8 timer 4 comparison a: 0xc000bc timer 5 comparison b: 0xc000c8 timer 5 comparison a: 0xc000cc the base address of the trap table can be changed using the ttbr register.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-16 epson s1c33e08 technical manual iv. 1.8 details of control registers table iv. 1.8.1 list of 16 -bit timer registers address 0x00300780 0x00300782 0x00300784 0x00300786 0x00300788 0x0030078a 0x0030078c 0x0030078e 0x00300790 0x00300792 0x00300794 0x00300796 0x00300798 0x0030079a 0x0030079c 0x0030079e 0x003007a0 0x003007a2 0x003007a4 0x003007a6 0x003007a8 0x003007aa 0x003007ac 0x003007ae 0x003007d0 0x003007d2 0x003007d4 0x003007dc 0x003007de 0x003007e0 0x003007e2 0x003007e4 0x003007e6 0x003007e8 0x003007ea function sets 16-bit timer 0 comparison data a. sets 16-bit timer 0 comparison data b. 16-bit timer 0 counter data controls 16-bit timer 0. sets 16-bit timer 1 comparison data a. sets 16-bit timer 1 comparison data b. 16-bit timer 1 counter data controls 16-bit timer 1. sets 16-bit timer 2 comparison data a. sets 16-bit timer 2 comparison data b. 16-bit timer 2 counter data controls 16-bit timer 2. sets 16-bit timer 3 comparison data a. sets 16-bit timer 3 comparison data b. 16-bit timer 3 counter data controls 16-bit timer 3. sets 16-bit timer 4 comparison data a. sets 16-bit timer 4 comparison data b. 16-bit timer 4 counter data controls 16-bit timer 4. sets 16-bit timer 5 comparison data a. sets 16-bit timer 5 comparison data b. 16-bit timer 5 counter data controls 16-bit timer 5. sets da16 ch.0 comparison data a. sets da16 ch.1 comparison data a. sets da16 ch.2 comparison data a. stops multiple timers simultaneously. selects standard or advanced mode. controls 16-bit timer 0 clock and selects division ratio. controls 16-bit timer 1 clock and selects division ratio. controls 16-bit timer 2 clock and selects division ratio. controls 16-bit timer 3 clock and selects division ratio. controls 16-bit timer 4 clock and selects division ratio. controls 16-bit timer 5 clock and selects division ratio. register name 16-bit timer 0 comparison data a setup register (pt16_cr0a) 16-bit timer 0 comparison data b setup register (pt16_cr0b) 16-bit timer 0 counter data register (pt16_tc0) 16-bit timer 0 control register (pt16_ctl0) 16-bit timer 1 comparison data a setup register (pt16_cr1a) 16-bit timer 1 comparison data b setup register (pt16_cr1b) 16-bit timer 1 counter data register (pt16_tc1) 16-bit timer 1 control register (pt16_ctl1) 16-bit timer 2 comparison data a setup register (pt16_cr2a) 16-bit timer 2 comparison data b setup register (pt16_cr2b) 16-bit timer 2 counter data register (pt16_tc2) 16-bit timer 2 control register (pt16_ctl2) 16-bit timer 3 comparison data a setup register (pt16_cr3a) 16-bit timer 3 comparison data b setup register (pt16_cr3b) 16-bit timer 3 counter data register (pt16_tc3) 16-bit timer 3 control register (pt16_ctl3) 16-bit timer 4 comparison data a setup register (pt16_cr4a) 16-bit timer 4 comparison data b setup register (pt16_cr4b) 16-bit timer 4 counter data register (pt16_tc4) 16-bit timer 4 control register (pt16_ctl4) 16-bit timer 5 comparison data a setup register (pt16_cr5a) 16-bit timer 5 comparison data b setup register (pt16_cr5b) 16-bit timer 5 counter data register (pt16_tc5) 16-bit timer 5 control register (pt16_ctl5) da16 ch.0 register (pda16_cr0a) da16 ch.1 register (pda16_cr1a) da16 ch.2 register (pda16_cr2a) count pause register (pt16_cnt_pause) 16-bit timer std/adv mode select register (pt16_advmode) 16-bit timer 0 clock control register (pt16_clkctl_0) 16-bit timer 1 clock control register (pt16_clkctl_1) 16-bit timer 2 clock control register (pt16_clkctl_2) 16-bit timer 3 clock control register (pt16_clkctl_3) 16-bit timer 4 clock control register (pt16_clkctl_4) 16-bit timer 5 clock control register (pt16_clkctl_5) siz e 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 the following describes each 16 -bit timer control register. the 16 -bit timer control registers are mapped in the 16 -bit device area from 0x300780 to 0x3007 ea, and can be accessed in units of half-words or bytes. note : when setting the 16-bit timer control registers, be sure to write a 0, and not a 1, for all reserved bits.
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300780C0x3007a8: 16-bit timer x comparison data a setup registers (pt16_cr x a) name address register name bit function setting init. r/w remarks 0 to 65535 cr x a15 cr x a14 cr x a13 cr x a12 cr x a11 cr x a10 cr x a9 cr x a8 cr x a7 cr x a6 cr x a5 cr x a4 cr x a3 cr x a2 cr x a1 cr x a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer x comparison data a cr x a15 = msb cr x a0 = lsb x x x x x x x x x x x x x x x x r/w 00300780 | 003007a8 (hw) 16-bit timer x comparison data a setup register (pt16_cr x a) note : the letter x in bit names, etc., denotes a timer number from 0 to 5. 0x300780 16-bit timer 0 comparison data a setup register (pt16_cr0a) 0x300788 16-bit timer 1 comparison data a setup register (pt16_cr1a) 0x300790 16-bit timer 2 comparison data a setup register (pt16_cr2a) 0x300798 16-bit timer 3 comparison data a setup register (pt16_cr3a) 0x3007a0 16-bit timer 4 comparison data a setup register (pt16_cr4a) 0x3007a8 16-bit timer 5 comparison data a setup register (pt16_cr5a) d[15:0] cr x a[15:0]: 16-bit timer x comparison data a bits sets the comparison data a for each timer. (default: indeterminate) when selcrb x (d5/0x300786 + 8? x ) is set to 0 , comparison data is directly read or writing from/to the comparison data register a. when selcrb x is set to 1 , comparison data is read or written from/to the comparison register buffer a. the content of the buffer is loaded to the comparison data register a when the counter is reset. the data set in this register is compared with each corresponding counter data. when the contents match, a comparison a interrupt is generated and the output signal rises (outinv x (d4/0x300786 + 8? x) = 0 ) or falls (outinv x = 1 ). this does not affect the counter value and count-up operation.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-18 epson s1c33e08 technical manual 0x300782C0x3007aa: 16-bit timer x comparison data b setup registers (pt16_cr x b) name address register name bit function setting init. r/w remarks 0 to 65535 cr x b15 cr x b14 cr x b13 cr x b12 cr x b11 cr x b10 cr x b9 cr x b8 cr x b7 cr x b6 cr x b5 cr x b4 cr x b3 cr x b2 cr x b1 cr x b0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer x comparison data b cr x b15 = msb cr x b0 = lsb x x x x x x x x x x x x x x x x r/w 00300782 | 003007aa (hw) 16-bit timer x comparison data b setup register (pt16_cr x b) note : the letter x in bit names, etc., denotes a timer number from 0 to 5. 0x300782 16-bit timer 0 comparison data b setup register (pt16_cr0b) 0x30078a 16-bit timer 1 comparison data b setup register (pt16_cr1b) 0x300792 16-bit timer 2 comparison data b setup register (pt16_cr2b) 0x30079a 16-bit timer 3 comparison data b setup register (pt16_cr3b) 0x3007a2 16-bit timer 4 comparison data b setup register (pt16_cr4b) 0x3007aa 16-bit timer 5 comparison data b setup register (pt16_cr5b) d[15:0] cr x b[15:0]: 16-bit timer x comparison data b bits sets the comparison data b for each timer. (default: indeterminate) when selcrb x (d5/0x300786 + 8? x ) is set to 0 , comparison data is directly read or writing from/to the comparison data register b. when selcrb x is set to 1 , comparison data is read or written from/to the comparison register buffer b. the content of the buffer is loaded to the comparison data register b when the counter is reset. the data set in this register is compared with each corresponding counter data. when the contents match, a comparison b interrupt is generated and the output signal falls (outinv x (d 4 / 0 x 300786 + 8 ? x ) = 0) or rises (outinv x = 1). furthermore, the counter is reset to 0.
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300784C0x3007ac: 16-bit timer x counter data registers (pt16_tc x ) name address register name bit function setting init. r/w remarks 0 to 65535 tc x 15 tc x 14 tc x 13 tc x 12 tc x 11 tc x 10 tc x 9 tc x 8 tc x 7 tc x 6 tc x 5 tc x 4 tc x 3 tc x 2 tc x 1 tc x 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer x counter data tc x 15 = msb tc x 0 = lsb x x x x x x x x x x x x x x x x r/w data can be written only in advanced mode. 00300784 | 003007ac (hw) 16-bit timer x counter data register (pt16_tc x ) note : the letter x in bit names, etc., denotes a timer number from 0 to 5. 0x300784 16-bit timer 0 counter data register (pt16_tc0) 0x30078c 16-bit timer 1 counter data register (pt16_tc1) 0x300794 16-bit timer 2 counter data register (pt16_tc2) 0x30079c 16-bit timer 3 counter data register (pt16_tc3) 0x3007a4 16-bit timer 4 counter data register (pt16_tc4) 0x3007ac 16-bit timer 5 counter data register (pt16_tc5) d[15:0] tc x [15:0]: 16-bit timer x counter data bits the counter data of each timer can be read from this register. (default: indeterminate) the data can be read out at any time. in advanced mode, counter data can be written at any time. this makes it possible to change the interrupt and/or clock output cycles temporarily. standard mode does not allow writing of counter data.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-20 epson s1c33e08 technical manual 0x300786C0x3007ae: 16-bit timer x control registers (pt16_ctl x ) name address register name bit function setting init. r/w remarks C initol x (tmode x ) selfm x selcrb x outinv x cksl x ptm x preset x prun x d15C9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer x initial output level (reserved for 16-bit timer x test) 16-bit timer x fine mode selection 16-bit timer x comparison buffer 16-bit timer x output inversion 16-bit timer x input clock selectio n 16-bit timer x clock output control 16-bit timer x reset 16-bit timer x run/stop control C 0 0 0 0 0 0 0 0 0 C r/w r r/w r/w r/w r/w r/w w r/w 0 when being read. advanced mode do not write 1. 0 when being read. 00300786 | 003007ae (hw) C 1 enabled 0 disabled 1 fine mode 0 normal 1 invert 0 normal 1 external clock 0 internal clock 1 on 0 off 1 reset 0 invalid 1 run 0 stop 16-bit timer x control register (pt16_ctl x ) 1 test mode 0 normal 1 high 0 low note : the letter x in bit names, etc., denotes a timer number from 0 to 5. 0x300786 16-bit timer 0 control register (pt16_ctl0) 0x30078e 16-bit timer 1 control register (pt16_ctl1) 0x300796 16-bit timer 2 control register (pt16_ctl2) 0x30079e 16-bit timer 3 control register (pt16_ctl3) 0x3007a6 16-bit timer 4 control register (pt16_ctl4) 0x3007ae 16-bit timer 5 control register (pt16_ctl5) d[15:9] reserved d8 initol x : 16-bit timer x initial output level select bit (advanced mode) selects an initial output level for timer output. 1 (r/w): high 0 (r/w): low (default) the timer output pin goes to the initial output level set using this bit when the timer output is turned off by writing 0 to ptm x (d2 ) or when the timer is reset by writing 1 to preset x (d1 ). however, this level is inverted if outinv x (d4) is set to 1. note that writing to this bit is enabled only in advanced mode. d7 (tmode x ): reserved do not set this bit to 1. d6 selfm x : 16-bit timer x fine mode select bit sets fine mode for clock output. 1 (r/w): fine mode 0 (r/w): normal output (default) when selfm x is set to 1 , clock output is set in fine mode which allows adjustment of the output signal duty ratio in units of a half cycle for the input clock. when selfm x is set to 0, normal clock output will be performed. d5 selcrb x : 16-bit timer x comparison buffer enable bit enables or disables writing to the comparison register buffer. 1 (r/w): enabled 0 (r/w): disabled (default) when selcrb x is set to 1 , comparison data is read and written from/to the comparison register buffer. the content of the buffer is loaded to the comparison data register when the counter is reset by the software or the comparison b signal. when selcrb x is set to 0, comparison data is read and written from/to the comparison da ta register.
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d4 outinv x : 16-bit timer x output inversion bit selects a logic of the output signal. 1 (r/w): inverted (active low) 0 (r/w): normal (active high) (default) by writing 1 to outinv x , an active-low signal (off level = high) is generated for the tm x output. when outinv x is set to 0 , an active-high signal (off level = low) is generated. writing 1 to this bit inverts the initial output level set using initol x (d8) as well. d3 cksl x : 16-bit timer x input clock select bit selects the input clock for each timer. 1 (r/w): external clock 0 (r/w): internal clock (default) the internal clock (prescaler output) is selected for the input clock of each timer by writing 0 to cksl x . an external clock (one that is fed from the clock input pin) is selected by writing 1 , and the timer functions as an event counter. in this case, the clock input pin must be set using the corresponding port function select register before an external clock is selected here. d2 ptm x : 16-bit timer x clock output control bit controls the output of the tm x signal (timer output clock). 1 (r/w): on 0 (r/w): off (default) the tm x signal is output from the clock output pin by writing 1 to ptm x . clock output is stopped by writing 0 to ptm x and goes to the off level according to the set values of outinv x (d4 ) and initol x (d8 ). in this case, the clock output pin must be set using the corresponding port function select register before outputting the tm x signal here. d1 preset x : 16-bit timer x reset bit preset the reload data in the counter. 1 (w): reset 0 (w): has no effect 0 (r): always 0 when read (default) the counter of timer x is reset by writing 1 to preset x . d0 prun x : 16-bit timer x run/stop control bit controls the timer's run/stop state. 1 (r/w): run 0 (r/w): stop (default) each timer is made to start counting up by writing 1 to prun x and made to stop counting by writing 0. in the stop state, the counter data is retained until the timer is reset or placed in a run state. by changing states from stop to run, the timer can restart counting beginning at the retained count.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-22 epson s1c33e08 technical manual 0x3007d0C0x3007d4: da16 ch. x registers (pda16_cr x a) name address register name bit function setting init. r/w remarks 0 to 65535 da x a15 da x a14 da x a13 da x a12 da x a11 da x a10 da x a9 da x a8 da x a7 da x a6 da x a5 da x a4 da x a3 da x a2 da x a1 da x a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 da16 ch. x comparison data a da x a15 = msb da x a0 = lsb x x x x x x x x x x x x x x x x r/w advanced mode 003007d0 | 003007d4 (hw) da16 ch. x register (pda16_cr x a) note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x3007d0 da16 ch.0 register (pda16_cr0a) 0x3007d2 da16 ch.1 register (pda16_cr1a) 0x3007d4 da16 ch.2 register (pda16_cr2a) d[15:0] da x a[15:0]: da16 ch. x comparison data a bits (advanced mode) sets the comparison data a for each channel in da 16 mode. (default: indeterminate) the following shows the correspondence between these registers and timers: (timer a and timer b) da 16 ch.0 register: timer 1 and timer 2 da 16 ch.1 register: timer 3 and timer 4 da 16 ch.2 register: timer 5 and timer 0 when data is written to this register, 10 high-order bits (da x a[ 15:6 ]) are loaded into the timer a comparison data a setup register (buffer) as 10 low-order compare data bits and 6 low-order bits (da xa[5:0 ]) are loaded into the timer b comparison data a setup register (buffer) as 6 low-order compare data bits. this makes it possible to reduce software load for using two 16-bit timers as a 16 -bit d/a converter. note that writing to this register is enabled only in advanced mode.
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3007dc: count pause register (pt16_cnt_pause) name address register name bit function setting init. r/w remarks C pause5 pause4 pause3 pause2 pause1 pause0 d15C6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 5 count pause 16-bit timer 4 count pause 16-bit timer 3 count pause 16-bit timer 2 count pause 16-bit timer 1 count pause 16-bit timer 0 count pause C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. advanced mode 003007dc (hw) C count pause register (pt16_cnt_pause) 1 pause 0 count since the timer run/stop control bits are located in different addresses, two or more timers cannot be started at the same time. to synchronize multiple timers, the control bits pause x that stop each timer are provided in this register. 1 (r/w): pause 0 (r/w): count (default) when pause x is set to 1 , timer x is placed in pause state and when set to 0 , timer x starts counting or continues stop state according to the set value of prun x (d0/0x300786 + 8? x). note that writing to this bit is enabled only in advanced mode. the following shows a procedure to synchronize multiple timers. 1 . set the prescaler clocks for the timers to be synchronized to t he same condition. 2 . set pause x for the timers to 1 to place the timers in pause state. 3 . set prun x (d0/0x300786 + 8? x) for the timers to 1. 4 . set all the pause x bits for the timers to 0 at the same time. d[15:6] reserved d5 pause5: 16-bit timer 5 count pause bit (advanced mode) stops the counter in 16-bit timer 5. d4 pause4: 16-bit timer 4 count pause bit (advanced mode) stops the counter in 16-bit timer 4. d3 pause3: 16-bit timer 3 count pause bit (advanced mode) stops the counter in 16-bit timer 3. d2 pause2: 16-bit timer 2 count pause bit (advanced mode) stops the counter in 16-bit timer 2. d1 pause1: 16-bit timer 1 count pause bit (advanced mode) stops the counter in 16-bit timer 1. d0 pause0: 16-bit timer 0 count pause bit (advanced mode) stops the counter in 16-bit timer 0.
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-24 epson s1c33e08 technical manual 0x3007de: 16-bit timer std/adv mode select register (pt16_advmode) name address register name bit function setting init. r/w remarks C t16adv d15C1 d0 reserved standard mode/advanced mode select C 0 C r/w writing 1 not allowed. 003007de (hw) 16-bit timer std/adv mode select register (pt16_advmode) C 1 advanced mode 0 standar d mode d[15:1] reserved d0 t16adv: standard/advanced mode select bit selects standard or advanced mode. 1 (r/w): advanced mode 0 (r/w): standard mode (default) the 16 -bit timer in the s1c33e08 is extended from that of the c33 std models. this 16 -bit timer has two operating modes, standard (std) mode of which functions are compatible with the existing c 33 std models and an advanced (adv) mode allowing use of the extended functions. table iv. 1.8.2 shows differences between standard mode and advanced mode. table iv. 1.8.2 differences between standard mode and advanced mode function wr iting to the count data register setting of the initial timer output le v el (high or lo w) d a16 function (d a16 registers) multiple timer full-sync function ad v anced mode enabled enabled (can be specified using initol x ) can be used supported (can be controlled using pause x ) standar d mode disabled (read only) disabled (depending on the outinv x set value) cannot be used not supported to configure the 16 -bit timer in advanced mode, set this bit to 1 . the control registers/bits for the extended functions are enabled to write after this setting. note : standard or advanced mode currently set is applied to all the 16-bit timers. it cannot be selected for each timer individually.
iv peripheral modules 2 (timers): 16-bit timers (t16) s1c33e08 technical manual epson iv-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3007e0C0x3007ea: 16-bit timer x clock control registers (pt16_clkctl_ x ) name address register name bit function setting init. r/w remarks C C p16ton x p16ts x 2 p16ts x 1 p16ts x 0 d15C4 d3 d2 d1 d0 reserved 16-bit timer x clock control 16-bit timer x clock division ratio selection C 0 0 0 0 C r/w r/w 0 when being read. 003007e0 | 003007ea (hw) 1 on 0 off p16ts x[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 16-bit timer x clock control register (pt16_clkctl_ x ) note : the letter x in bit names, etc., denotes a timer number from 0 to 5. 0x3007e0 16-bit timer 0 clock control register ( pt16_clkctl _0) 0x3007e2 16-bit timer 1 clock control register ( pt16_clkctl _1) 0x3007e4 16-bit timer 2 clock control register ( pt16_clkctl _2) 0x3007e6 16-bit timer 3 clock control register ( pt16_clkctl _3) 0x3007e8 16-bit timer 4 clock control register ( pt16_clkctl _4) 0x3007ea 16-bit timer 5 clock control register ( pt16_clkctl _5) d[15:4] reserved d3 p16ton x : 16-bit timer x clock control bit controls the clock supply to 16-bit timer x . 1 (r/w): on 0 (r/w): off (default) d[2:0] p16ts x [2:0]: 16-bit timer x clock division ratio setup bits selects a division ratio to generate the 16-bit timer x clock. table iv. 1.8.3 selecting division ratio p16ts x 2 1 1 1 1 0 0 0 0 p16ts x 1 1 1 0 0 1 1 0 0 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 p16ts x 0 1 0 1 0 1 0 1 0 (default: 0b000)
iv peripheral modules 2 (timers): 16-bit timers (t16) iv-1-26 epson s1c33e08 technical manual iv. 1.9 precautions ? when setting the count clock or operation mode, make sure the 16 -bit timer is turned off. ? if a same value is set to the comparison data a and b registers, a hazard may be generated in the output signal. therefore, do not set the comparison registers as a = b. there is no problem when the interrupt function only is used. ? when using the output clock, set the comparison data registers as a 0 and b 1 . the minimum settings are a = 0 and b = 1 . in this case, the timer output clock cycle is the input clock 1/2. ? when the comparison data registers are set as a > b in normal mode, no comparison a interrupt is generated. in this case, the output signal is fixed at the off level. in fine mode, no comparison a interrupt is generated when the comparison data registers are set as a > 2 b + 1 . ? after an initial reset, the cause-of-interrupt flag becomes indeterminate. to prevent generation of an unwanted interrupt or idma request, be sure to reset this flag and register in the software. ? to prevent another interrupt from being generated by the same cause of interrupt after an interrupt has occurred, be sure to reset the cause-of-interrupt flag before setting the psr again or executing the reti instruction.
iv peripheral modules 2 (timers): watchdog timer (wdt) s1c33e08 technical manual epson iv-2-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iv. 2 watchdog timer (wdt) iv. 2.1 configuration of the watchdog timer the s 1c33e08 incorporates a watchdog timer to detect the cpu running uncontrollably. the watchdog timer con - sists of a 30 -bit up counter and comparison data register for generating an nmi or internal reset signal at program - mable cycles. by resetting the watchdog timer within such a cycle in software so as not to generate nmi or internal reset signals, it is possible to detect a program running uncontrollably that does not execute that processing routine. the wdt clock (= mclk) or external clock input for 16 -bit timer 0 (excl0 ) can be selected as the count clock for the watchdog timer. moreover, a clock can be generated synchronously with nmi/reset generation cycles (set by the comparison data register) and output from the watchdog timer to external devices. figure iv. 2.1.1 shows a block diagram of the watchdog timer. resen clksel reset watchdog timer reset (wdresen) watchdog timer run/stop control (runstp) watchdog timer data bus nmien clken nmi 30-bit comparison data register (cmpdt) 30-bit up counter (ctrdt) cmu comparator wdt clock wdt_clk #wdt_nmi comparison signal clock output circuit external clock excl0 figure iv. 2.1.1 block diagram of watchdog timer
iv peripheral modules 2 (timers): watchdog timer (wdt) iv-2-2 epson s1c33e08 technical manual iv. 2.2 input/output pins of the watchdog timer table iv. 2.2.1 input/output pins of watchdog timer pin name excl0 wdt_clk #wdt_nmi i/o i o o function exter nal cloc k input pin (e xter nal cloc k input f or 16-bit timer 0) w atchdog timer cloc k output pin w atchdog timer nmi output pin the excl0 pin is used to clock the counter of the watchdog timer with an external clock. the wdt_clk pin is used to output the clock generated in the watchdog timer to external devices. the #wdt_nmi pin is used to output the nmi signal generated i n the watchdog timer to external devices. note : these pins are shared with general-purpose input/output ports or other peripheral circuit input/ output pins, and set for other than the watchdog timer function by default. therefore, before these pins can be used as input/output ports for the watchdog timer clock, the corresponding port func - tion select register must be set to switch over the pin functions. for details about pin functions and how to switch over, see section i.3.3, switching over the mul - tiplexed pin functions.
iv peripheral modules 2 (timers): watchdog timer (wdt) s1c33e08 technical manual epson iv-2-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iv. 2.3 operating clock of the watchdog timer the watchdog timer module is clocked by the wdt clock (= mclk) supplied from the cmu. at initial reset, this clock is selected as the operating clock for the watchdog timer. while the watchdog timer remains idle or is not being used, the clock supplied from the cmu can be turned off to reduce the amount of current consumed on the chip. use wdt_cke (d 9/0x301b04) for this control. ? wdt_cke : watchdog timer clock control bit in the gated clock control register 1 (d9/0x301b04) setting wdt_cke (d 9/0x301b04) to 0 turns off the clock supplied from the cmu to the watchdog timer. for details about clock generation and control, see section iii. 1, clock management unit (cmu). notes : ? even when using an external clock as the count clock for the watchdog timer, the wdt clock is required for watchdog timer operation and access to its control register. ? the gated clock control register 1 (0x301b04 ) is write-protected. to rewrite this register and other cmu control registers at addresses 0x301b00 to 0x301b14 , write protection must be re - moved by writing 0x96 to the clock control protect register (0x301b24 ). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 may cause the system to operate erratically, make sure that data set in the clock control protect register ( 0x301b24 ) is other than 0x96 unless rewriting said registers.
iv peripheral modules 2 (timers): watchdog timer (wdt) iv-2-4 epson s1c33e08 technical manual iv. 2.4 control of the watchdog timer iv. 2.4.1 setting up the watchdog timer selecting the count clock the internal clock (mclk) or external clock (excl 0 ) can be selected as the count clock for the 30 -bit up- counter by using clksel (d6/0x300662). ? clksel : watchdog timer input clock select bit in watchdog timer enable register (d6/0x300662) setting clksel (d 6/0x300662 ) to 0 (default) selects the internal clock (mclk); setting it to 1 selects the external clock (excl 0 ). therefore, before an external clock can be used, the function of the pin set as an i/o port by default must be switched to excl 0 (external clock input for 16 -bit timer 0 ) by using the port function select register. for details about pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. for details about mclk generation and control, see section iii. 1, clock management unit (cmu). setting the nmi/reset generation cycle the watchdog timer has a 30 -bit comparison data register that can be used to set a cycle in which to generate an nmi or reset signal. ? cmpdt[15:0] : 16 low-order comparison data bits in the watchdog timer comparison data setup register 0 (d[15:0]/0x300664) ? cmpdt[29:16] : 14 high-order comparison data bits in the watchdog timer comparison data setup register 1 (d[13:0]/0x300666) the data set in these register bits is compared with the up-counter value. when both match, a specified nmi or reset signal is output. the up-counter is reset to 0 at this time. the nmi/reset generation cycle can be calculated from the equation below. cmpdt + 1 nmi generating cycle = [sec] f wdtin where cmpdt = value set in cmpdt[ 29:0] (d[13:0]/0x300666, d[15:0]/0x300664) f wdtin = mclk or excl0 input clock frequency [hz] for example, the specifiable maximum nmi/reset generation cycle is about 21.47 seconds at 50 -mhz mclk input. note : do not set a value equal to or less than 0x0000001f in the comparison data register. selecting the nmi/reset generation function to output an nmi signal when the watchdog timer is not reset within a specified cycle, set nmien (d 1/ 0x300662) to 1 . to output a reset signal instead, set resen (d0/0x300662) to 1. ? nmien : watchdog timer nmi enable bit in the watchdog timer enable register (d1/0x300662) ? resen : watchdog timer reset enable bit in the watchdog timer enable register (d0/0x300662) setting both bits to 0 (default) generates neither an nmi signal nor a reset signal, although the up-counter re - mains active and can output a clock. setting both bits to 1 outputs both an nmi signal and a reset signal. in this case, however, reset exception han - dling is executed since it has priority over the nmi exception handling. the nmi and reset signals are both output as pulses of 32 mclk clocks in width. note : depending on the counter and comparison register values, an nmi or reset signal may be gener - ated after the nmi or reset function is enabled here (or even when the watchdog timer has not yet been started). always be sure to set comparison data and reset the watchdog timer before writing 1 to nmien (d1/0x300662) or resen (d0/0x300662).
iv peripheral modules 2 (timers): watchdog timer (wdt) s1c33e08 technical manual epson iv-2-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 write protection of watchdog timer registers the watchdog timer enable register ( 0x300662 ) and watchdog timer comparison data registers (0x300664, 0x300666 ) are write-protected to prevent nmi or reset signals from being inadvertently generated by unnec - essary write operations. to rewrite these registers, write protection must be removed by writing 0x96 to the watchdog timer write-protect register ( 0 x 300660 ). once the registers are rewritten, be sure to write other than 0x96 to the watchdog timer write-protect register (0x300660) to reapply write protection. iv. 2.4.2 starting/stopping the watchdog timer writing 1 to runstp (d4/0x300662 ) starts counting by the watchdog timer; writing 0 stops the watchdog timer. ? runstp : watchdog timer run/stop control bit in the watchdog timer enable register (d4/0x300662) since runstp (d 4/0x300662 ) exists in the write-protected watchdog timer enable register (0x300662 ), write protection must be removed by writing 0x96 to the watchdog timer write-protect register (0x300660 ) before the content of runstp can be altered. iv. 2.4.3 resetting the watchdog timer before the nmi/reset generation function of the watchdog timer can be used, a routine to reset the watchdog timer before nmi or reset generation must be prepared in a location for periodic processing. make sure that this routine is processed within the nmi/reset generation cycle described earlier. writing 1 to wdresen (d0/0x30066 c) resets the watchdog timer. the up-counter is reset to 0 at this time, then starts counting nmi/reset generation cycles all over again. ? wdresen : watchdog timer reset bit in the watchdog timer control register (d0/0x30066c) if the watchdog timer is not reset within the set cycle for some reason, the cpu is placed into trap handling by an nmi or reset signal to execute the processing routine. the reset and nmi trap vector addresses are set by default to 0xc00000 and 0xc0001 c, respectively. the trap table base address can be altered by using ttbr. the count value of the up-counter can be read out from the watchdog timer count registers ( 0x300668, 0x30066 a) at any time. ? ctrdt[15:0] : 16 low-order counter data bits in the watchdog timer count register 0 (d[15:0]/0x300668) ? ctrdt[29:16] : 14 high-order counter data bits in the watchdog timer count register 1 (d[13:0]/0x30066a) iv. 2.4.4 operation in standby mode in halt mode in halt mode, the watchdog timer remains active as it is supplied with a clock. therefore, if halt mode re - mains active beyond the nmi/reset generation cycle, an nmi or reset signal deactivates halt mode. to disable the watchdog timer in halt mode, set nmien (d 1/0x300662 ) or resen (d0/0x300662 ) to 0. otherwise, write 0 to runstp (d4/0x300662 ) to stop the watchdog timer before executing the halt instruction. when nmien (d 1/0x300662 ) or resen (d0/0x300662 ) disables nmi or reset generation, the watchdog timer continues counting even in halt mode. to reenable nmi or reset generation after exiting halt mode, be sure to reset the watchdog timer beforehand. when halt mode is entered after stopping the watchdog timer, be sure to reset the watchdog timer before re - starting it. in sleep mode the supply of mclk from the cmu stops in sleep mode. therefore, the watchdog timer also stops operat - ing. to prevent an unnecessary nmi or reset signal from being generated after exiting sleep mode, be sure to reset the watchdog timer before executing the slp instruction. moreover, disable nmi/reset generation by set - ting nmien (d1/0x300662) or resen (d0/0x300662) as required.
iv peripheral modules 2 (timers): watchdog timer (wdt) iv-2-6 epson s1c33e08 technical manual iv. 2.4.5 clock output of the watchdog timer the watchdog timer can output an nmi/reset generation cycle-synchronous clock from the ic to external devices. for this clock output, set clken (d 5/0x300662) to 1 after setting up the wdt_clk pin. ? clken : watchdog timer clock output control bit in the watchdog timer enable register (d5/0x300662) since clken (d 5 / 0 x 300662 ) also exists in the write-protected watchdog timer enable register ( 0 x 300662 ), write protection must be removed by writing 0x96 to the watchdog timer write-protect register (0x300660 ) before the content of clken can be altered. if the watchdog timer is not reset in software, the level of clock output from the ic is reversed synchronously with the nmi generation cycles. (this applies when reset generation is disabled.) when the watchdog timer is reset in software, clock output from the ic goes low at that time and remains low. mclk clock counter data comparison data comparison match signal wdt_clk output clock ffff1d ffff1e ffff1f ffff20 ffff20 0 1 2 ffff1f ffff20 0 1 2 figure iv. 2.4.5.1 clock output of watchdog timer iv. 2.4.6 external nmi output the watchdog timer can output the nmi signal generated to external devices. the watchdog timer uses the #wdt_nmi pin for this output. this pin is configured as a general-purpose i/o pin at initial reset, therefore, the pin function must be set as #wdt_nmi (see section i.3.3). setting nmien (d 1 / 0 x 300662 ) to 1 enables the external nmi signal output as well as the internal nmi signal output. when the watchdog timer counter reaches the comparison data, the #wdt_nmi pin outputs a low pulse with 32 mclk clock cycles. mclk clock counter data comparison data #wdt_nmi output ffff1d ffff1e ffff1f ffff20 ffff20 32 mclk cycles 0 1 2 1e 1f 20 21 22 figure iv. 2.4.6.1 external nmi output
iv peripheral modules 2 (timers): watchdog timer (wdt) s1c33e08 technical manual epson iv-2-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 iv. 2.5 details of control registers table iv. 2.5.1 list of watchdog timer control registers address 0x00300660 0x00300662 0x00300664 0x00300666 0x00300668 0x0030066a 0x0030066c function enables/disables wdt control registers for writing. configures and starts watchdog timer. sets comparison data (16 low-order bits). sets comparison data (14 high-order bits). watchdog timer counter data (16 low-order bits) watchdog timer counter data ( 14 high-order bits) resets watchdog timer. register name watchdog timer write-protect register (pwd_wp) watchdog timer enable register (pwd_en) watchdog timer comparison data setup register 0 (pwd_comp_low) watchdog timer comparison data setup register 1 (pwd_comp_high) watchdog timer count register 0 (pwd_cnt_low) watchdog timer count register 1 (pwd_cnt_high) watchdog timer control register (pwd_cntl) siz e 16 16 16 16 16 16 16 the following describes the watchdog timer control registers. the watchdog timer control registers are mapped to the 16 -bit device area at addresses 0x300660 to 0x30066 c, and can be accessed in units of half-words. notes : ? the watchdog timer control registers allow accessing in half-word size only (except for 0x300662 and 0x30066 c that allow byte access as well as half-word access). do not read/ write the registers in byte size. ? when setting the watchdog timer control registers, be sure to write a 0 , and not a 1 , for all re - served bits.
iv peripheral modules 2 (timers): watchdog timer (wdt) iv-2-8 epson s1c33e08 technical manual 0x300660: watchdog timer write-protect register (pwd_wp) name address register name bit function setting init. r/w remarks wr iting 0x96 remo v es the wr ite protection of the w atchdog timer enab le and compar ison data registers (0x300662C0x300666). wr iting another v alue set the wr ite protection. wdptc15 wdptc14 wdptc13 wdptc12 wdptc11 wdptc10 wdptc9 wdptc8 wdptc7 wdptc6 wdptc5 wdptc4 wdptc3 wdptc2 wdptc1 wdptc0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 watchdog timer register write- protect x x x x x x x x x x x x x x x x w 0 when being read. 00300660 (hw) watchdog timer write- protect register (pwd_wp) d[15:0] wdptc[15:0]: watchdog timer write-protect bits these bits set or clear write protection at addresses 0x300662 to 0x300666. 0x96 (w): clears write protection other than 0x96 (w): applies write protection (default, indeterminate value) 0x0 (r): always 0x0 when read before altering the watchdog timer enable register ( 0x300662 ) or watchdog timer comparison data registers ( 0x300664, 0x300666 ), write 0x96 to this register to remove write protection. setting this register to other than 0x96 will result in the contents of the registers above not being altered even when executing the write instruction without any problem. once write protection is removed by writing 0x96 to this register, said registers can be rewritten any number of times until this register is set to other than 0x96 . when the clock control registers have been rewritten, be sure to write other than 0x96 to this reg - ister to prevent erroneous writing to said registers.
iv peripheral modules 2 (timers): watchdog timer (wdt) s1c33e08 technical manual epson iv-2-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300662: watchdog timer enable register (pwd_en) name address register name bit function setting init. r/w remarks C C C clksel clken runstp C nmien resen d15C7 d6 d5 d4 d3C2 d1 d0 reserved watchdog timer input clock select watchdog timer clock output contro l watchdog timer run/stop control reserved watchdog timer nmi enable watchdog timer reset enable C 0 0 0 C 0 0 C r/w r/w r/w C r/w r/w 0 when being read. 0 when being read. 00300662 (hw) 1 enabled 0 disabled watchdog timer enable register (pwd_en) 1 enabled 0 disabled 1 run 0 stop 1 on 0 off 1 external clock 0 internal cloc k note : this register is write-protected to prevent nmi or reset signals from being inadvertently gener - ated by unnecessary write operations. to rewrite this register, write protection must be removed by writing 0x96 to the watchdog timer write-protect register (0x300660). once the register has been rewritten, be sure to write other than 0x96 to the watchdog timer write-protect register (0x300660) to reapply write protection. d[15:7] reserved d6 clksel: watchdog timer input clock select bit this bit selects the count clock for the watchdog timer. 1 (r/w): external clock (excl0) 0 (r/w): internal clock (mclk) (default) setting this bit to 0 (default) selects the internal clock (mclk); setting it to 1 selects the external clock (excl0 ). before an external clock can be used, the function of the pin set by default as an i/o port must be switched to excl 0 (external clock input for 16 -bit timer 0 ) by using the port function select register. for details about pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. d5 clken: watchdog timer clock output control bit this bit controls the clock output of the watchdog timer. 1 (r/w): on 0 (r/w): off (default) setting this bit to 1 outputs an nmi/reset generation cycle-synchronous clock from the ic. before this clock output can be used, however, the function of the pin set by default as an i/o port must be switched to wdt_clk (watchdog timer clock output) by using the port function select register. for details about pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. d4 runstp: watchdog timer run/stop control bit this bit starts or stops the watchdog timer. 1 (r/w): start 0 (r/w): stop (default) when the nmi or reset generation function is enabled, be sure to set comparison data and reset the watchdog timer before starting the watchdog timer, thus preventing the generation of unnecessary nmi or reset signals. d[3:2] reserved
iv peripheral modules 2 (timers): watchdog timer (wdt) iv-2-10 epson s1c33e08 technical manual d1 nmien: watchdog timer nmi enable bit this bit enables nmi signal output by the watchdog timer. 1 (r/w): enable 0 (r/w): disable (default) setting this bit to 1 outputs an nmi signal (a pulse 32 mclk clocks in width) to the cmu and the #wdt_nmi pin when the count of the up-counter matches the value set in the comparison data regis - ter. setting this bit to 0 outputs no nmi signals. regardless of how this bit is set, the up-counter is reset to 0 when the up-counter and set value of the comparison data register match, then starts counting all over again. d0 resen: watchdog timer reset enable bit this bit enables internal reset signal output by the watchdog timer. 1 (r/w): enable 0 (r/w): disable (default) setting this bit to 1 outputs a reset signal (a pulse 32 mclk clocks in width) to the cmu when the count of the up-counter matches the value set in the comparison data register. setting this bit to 0 out - puts no reset signals.
iv peripheral modules 2 (timers): watchdog timer (wdt) s1c33e08 technical manual epson iv-2-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300664: watchdog timer comparison data setup register 0 (pwd_comp_low) 0x300666: watchdog timer comparison data setup register 1 (pwd_comp_high) name address register name bit function setting init. r/w remarks 0x0 to 0x3fffffff (lo w-order 16 bits) cmpdt15 cmpdt14 cmpdt13 cmpdt12 cmpdt11 cmpdt10 cmpdt9 cmpdt8 cmpdt7 cmpdt6 cmpdt5 cmpdt4 cmpdt3 cmpdt2 cmpdt1 cmpdt0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 watchdog timer comparison data cmpdt0 = lsb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00300664 (hw) watchdog timer comparison data setup register 0 (pwd_comp_low) C 0x0 to 0x3fffffff (high-order 14 bits) C cmpdt29 cmpdt28 cmpdt27 cmpdt26 cmpdt25 cmpdt24 cmpdt23 cmpdt22 cmpdt21 cmpdt20 cmpdt19 cmpdt18 cmpdt17 cmpdt16 d15C14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved watchdog timer comparison data cmpdt29 = msb C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. 00300666 (hw) watchdog timer comparison data setup register 1 (pwd_comp_high) note : these registers are write-protected to prevent nmi or reset signals from being inadvertently generated by unnecessary write operations. to rewrite these registers, write protection must be removed by writing 0x96 to the watchdog timer write-protect register (0x300660). once the reg - isters have been rewritten, be sure to write other than 0x96 to the watchdog timer write-protect register (0x300660) to reapply write protection. use these registers to set the nmi/reset generation cycle. with nmi or reset generation enabled, an nmi or reset signal is output when the up-counter matches the compari - son data set in these registers. when a clock is output from the watchdog timer, these registers also set the output clock cycle. d[15:0]/0x300664 cmpdt[15:0]: watchdog timer comparison data (16 low-order bits) the 16 low-order bits of comparison data are set in these bits. (default: 0x0000) d[13:0]/0x300666 cmpdt[29:16]: watchdog timer comparison data (14 high-order bits) the 14 high-order bits of comparison data are set in these bits. (default: 0x0000) note : do not set a value equal to or less than 0x0000001f as comparison data.
iv peripheral modules 2 (timers): watchdog timer (wdt) iv-2-12 epson s1c33e08 technical manual 0x300668: watchdog timer count register 0 (pwd_cnt_low) 0x30066a: watchdog timer count register 1 (pwd_cnt_high) name address register name bit function setting init. r/w remarks 0x0 to 0x3fffffff (lo w-order 16 bits) ctrdt15 ctrdt14 ctrdt13 ctrdt12 ctrdt11 ctrdt10 ctrdt9 ctrdt8 ctrdt7 ctrdt6 ctrdt5 ctrdt4 ctrdt3 ctrdt2 ctrdt1 ctrdt0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 watchdog timer counter data ctrdt0 = lsb x x x x x x x x x x x x x x x x r 00300668 (hw) watchdog timer count register 0 (pwd_cnt_low) C 0x0 to 0x3fffffff (high-order 14 bits) C ctrdt29 ctrdt28 ctrdt27 ctrdt26 ctrdt25 ctrdt24 ctrdt23 ctrdt22 ctrdt21 ctrdt20 ctrdt19 ctrdt18 ctrdt17 ctrdt16 d15C14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved watchdog timer counter data ctrdt29 = msb C x x x x x x x x x x x x x x C r 0 when being read. 0030066a (hw) watchdog timer count register 1 (pwd_cnt_high) the current count value of the up-counter can be read out from these registers. d[15:0]/0x300668 ctrdt[15:0]: watchdog timer count data (16 low-order bits) the 16 low-order bits of the 30 -bit up-counter are read out from these bits. (default: indeterminate) d[13:0]/0x30066a ctrdt[29:16]: watchdog timer count data (14 high-order bits) the 14 high-order bits of the 30 -bit up-counter are read out from these bits. (default: indeterminate)
iv peripheral modules 2 (timers): watchdog timer (wdt) s1c33e08 technical manual epson iv-2-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30066c: watchdog timer control register (pwd_cntl) name address register name bit function setting init. r/w remarks C C wdresen d15C1 d0 reserved watchdog timer reset C 0 C w 0 when being read. 0030066c (hw) watchdog timer control register (pwd_cntl) 1 reset 0 invalid d[15:1] reserved d0 wdresen: watchdog timer reset bit this bit resets the watchdog timer. 1 (w): reset 0 (w): has no effect 0 (r): always 0 when read (default) with nmi or reset signal output enabled, the watchdog timer must be reset by writing 1 to this bit with - in the set nmi/reset generation cycle. the up-counter is thereby reset to 0 , then starts counting nmi/re - set generation cycles all over again.
iv peripheral modules 2 (timers): watchdog timer (wdt) iv-2-14 epson s1c33e08 technical manual iv. 2.6 precautions ? when nmi or reset signal output by the watchdog timer is enabled, the watchdog timer must be reset within the set nmi/reset generation cycle. ? do not set a value equal to or less than 0x0000001 f in the comparison data register. ? depending on the counter and comparison register values, an nmi or reset signal may be generated after the nmi or reset function is enabled, or immediately after the watchdog timer starts. always be sure to set compari - son data and reset the watchdog timer before writing 1 to nmien (d1/0x300662 ), resen (d0/0x300662 ), or runstp (d 4/0x300662). ? nmien : watchdog timer nmi enable bit in the watchdog timer enable register (d1/0x300662) ? resen : watchdog timer reset enable bit in the watchdog timer enable register (d0/0x300662) ? runstp : watchdog timer run/stop control bit in the watchdog timer enable register (d4/0x300662)
i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual v peripheral m odules 3 ( i nterface )

v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1 general-purpose serial interface (efsio) v. 1.1 configuration of serial interfaces v. 1.1.1 features of serial interfaces the s 1c33e08 contains three channels (ch.0 , ch.1 and ch.2 ) of serial interfaces, the features of which are de - scribed below. ? a clock-synchronized, asynchronous, or iso7816 mode can be selected for the transfer method. clock-synchronized mode (ch. 0, ch.1 and ch.2) data length: 8 bits, fixed (no start, stop, and parity bits) receive error: an overrun error can been detected. asynchronous mode (ch. 0, ch.1 and ch.2) data length: 7 or 8 bits, selectable receive error: overrun, framing, or parity errors can been detected. start bit: 1 bit, fixed stop bit: 1 or 2 bits, selectable parity bit: even, odd, or none, selectable since the transmit and receive units are independent, full-duplex communication is possible. supports irda interface internal clock or external clock is selectable. iso 7816 mode (ch.1) data length: 8 bits, fixed (start, stop, and parity bits are not included) receive error: overrun, framing, or parity errors can been detected. start bit: 1 bit, fixed stop bit: 2 bits (t = 0) or 1 bit (t = 1) parity bit: even, fixed half-duplex communication using one data signal line transmit time guard function for low-speed serial device ? baud-rate setting: any desired baud rate can be set by selecting the baud-rate timer, or using external clock in - put (asynchronous mode only). up to 8 mbps transfer in clock-synchronized mode or up to 1 mbps transfer in asynchronous mode are possible. ? 4 -byte receive buffer (fifo) and 2 -byte transmit buffer (fifo) are built in, allowing for successive receive and transmit operations. ? data transfers using idma or hsdma are possible. ? three types of interrupts (transmit buffer empty, receive buffer full, and receive error) can be generated. figure v. 1.1.1.1 shows the configuration of the serial interface (one channel). efsio #sclk x receive control circuit receive data buffer (4-byte fifo) interrupt control circuit baud-rate timer #srdy x sin x transmit control circuit transmit data buffer (2-byte fifo) sout x clock control circuit cmu sapb bus i/f itc sramc figure v. 1.1.1.1 configuration of serial interface note : ch.0 to ch.2 have the same configuration and the same function (except for iso7816 mode in ch.1). the signal and control bit names are suffixed by a 0, 1, or 2 to indicate the channel number, enabling discrimination between channels 0 to 2. in this manual, however, channel numbers 0 to 2 are replaced with x unless discrimination is necessary, because explanations are common to all three channels.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-2 epson s1c33e08 technical manual v. 1.1.2 i/o pins of serial interface table v. 1.1.2.1 lists the i/o pins used by the serial interface. table v. 1.1.2.1 serial-interface pin configuration pin name sin0 sout0 #sclk0 #srd y0 sin1 sout1 #sclk1 #srd y1 sin2 sout2 #sclk2 #srd y2 i/o i o i/o i/o i o i/o i/o i o i/o i/o function ser ial i/f ch.0 data input ser ial i/f ch.0 data output ser ial i/f ch.0 cloc k input/output ser ial i/f ch.0 ready input/output ser ial i/f ch.1 data input ser ial i/f ch.1 data output ser ial i/f ch.1 cloc k input/output ser ial i/f ch.1 ready input/output ser ial i/f ch.2 data input ser ial i/f ch.2 data output ser ial i/f ch.2 cloc k input/output ser ial i/f ch.2 ready input/output sin x (serial-data input pin) this pin is used to input serial data to the device. sout x (serial-data output pin) this pin is used to output serial data from the device. #sclk x (clock input/output pin) this pin is used to input or output a clock. in clock-synchronized slave mode, it is used as a clock input pin; in clock-synchronized master mode and iso7816 mode (ch.1), it is used as a clock output pin. in asynchronous mode, this pin is used as clock input when an external clock is used. this pin is not used when the internal clock is used, so it can be used as an i/o port. #srdy x (ready-signal input/output pin) this pin is used to input or output the ready signal that is us ed in clock-synchronized mode. in clock-synchronized slave mode, it is used as a ready-signal output pin; in clock-synchronized master mode, it is used as a ready-signal input pin. this pin is not used in asynchronous mode and iso 7816 mode (ch.1), so it can be used as an i/o port. note : the serial interface input/output pins are shared with general-purpose i/o ports or other periph - eral circuit inputs/outputs, so that functionality in the initial state is set to other than the serial interface input/output. before the serial interface input/output signals assigned to these pins can be used, the function of these pins must be switched for the serial interface input/output by setting the corresponding port function select registers. for details of pin functions and how to switch over, see section i.3.3, switching over the multi - plexed pin functions.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1.1.3 setting interface mode and transfer mode the interface type and transfer mode of the serial interface can be set using smd x[1:0 ] (d[1:0]/0x300b x3 ), ir - md x[1:0 ] (d[1:0]/0x300b x4 ), and 7816md1[1:0 ] (d[1:0]/0x300b1 a) individually for each channel as shown in table v. 1.1.3.1 below. ? smd x [1:0] : serial i/f ch. x transfer mode select bits in the serial i/f ch. x control register (d[1:0]/0x300b x 3) ? irmd x [1:0] : serial i/f ch. x interface mode select bits in the serial i/f ch. x irda register (d[1:0]/0x300b x 4) ? 7816md1[1:0] : serial i/f ch.1 iso7816 mode select bits in the serial i/f ch.1 iso87816 mode control register (d[1:0]/0x300b1a) table v. 1.1.3.1 mode settings irmd x [1:0] 00 10 00 smd x[1:0] 11 00 11 00 11 10 11 10 01 00 t ransfer mode iso7816 (t = 1) mode , asynchronous iso7816 (t = 1) mode , cloc k-sync iso7816 (t = 0) mode , asynchronous iso7816 (t = 0) mode , cloc k-sync 8-bit asynchronous mode (ird a i/f) 7-bit asynchronous mode (ird a i/f) 8-bit asynchronous mode (nor mal i/f) 7-bit asynchronous mode (nor mal i/f) cloc k-synchroniz ed sla ve mode cloc k-synchroniz ed master mode reser ve d other interface mode iso7816 mode (ch.1 only) ird a mode nor mal mode 7816md1[1:0] 10 01 00 support ch. ch.1 ch.0 ch.1 ch.2 C at initial reset, 7816md1[1:0 ] (d[1:0]/0x300b1 a) is set to 0b00 , smd x[1:0 ] (d[1:0]/0x300b x3 ) and irmd x[1:0] (d[1:0]/0x300b x4) become indeterminate, so be sure to initialize it in the soft ware. when using the irda interface, set the transfer mode for the asynchronous 7-bit or asynchronous 8-bit mode. the input/output pins are configured differently, depending on the transfer mode. the pin configuration in each mode is shown in table v. 1.1.3.2. table v. 1.1.3.2 pin configuration by transfer mode sin x data input data input data input data input data input sout x data output data output data output data output data output t ransfer mode 8-bit asynchronous mode 7-bit asynchronous mode cloc k-synchroniz ed sla ve mode cloc k-synchroniz ed master mode iso7816 #sclk x cloc k input/p por t cloc k input/p por t cloc k input cloc k output cloc k output #srd y x p por t p por t ready output ready input p por t all four pins are used in the clock-synchronized mode. in the asynchronous mode, since #srdy x is unused, the #srdy x pin can be used as an i/o (p) port. in addition, when an external clock is not used, the #sclk x pin can also be used as an i/o port. the iso7816 mode (ch.1 ) does not use #srdy1, so this pin can be used as an i/o (p) port. the i/o control and data registers for the i/o ports used in the serial interface can be used as general-purpose read/ write registers.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-4 epson s1c33e08 technical manual v. 1.1.4 serial interface operating clock the serial interface use the clocks generated by the cmu as the operating clock. furthermore, each channel uses the data transfer clock generated by the baud-rate timer embedded in the efsio module. controlling the supply of the clock for accessing efsio the sapb bus interface clock (= mclk) is supplied to the serial interface with default settings. it can be turned off using efsiosapb_cke (d 5/0x301b04 ) to reduce the amount of power consumed on the chip if all the serial interface functions are not used. ? efsiosapb_cke : efsio sapb i/f clock control bit in the gated clock control register 1 (d5/0x301b04) setting efsiosapb_cke (d 5/0x301b04 ) to 0 (1 by default) turns off the clock supply to the serial interface. when the clock supply is turned off, the serial interface control registers cannot be accessed. for details on how to set and control clocks, see section iii. 1, clock management unit (cmu). clock for baud-rate timer and interface the data transfer clock is generated by the baud-rate timer embedded in each channel. the baud-rate timer op - erating clock (= mclk) is supplied separately with the sapb bus interface clock shown above. although this clock cannot be turned off while the s 1c33e08 is running, this clock can be automatically turned off in halt mode (see section iii.1.9.2) by setting efsiobr_hcke (d25/0x301b04) to 0 (default: on). ? efsiobr_hcke : efsio baud rate clock control (halt) bit in the gated clock control register 1 (d25/0x301b04) refer to section v. 1.2 for the baud-rate timer. clock state in standby mode the clock supply to the serial interface stops depending on type of standby mode. halt mode: the sapb bus interface clock is supplied the same way as in normal mode (it can be stopped before entering halt mode). the baud-rate timer clock can be automatically stopped in halt mode. sleep mode: the sapb bus interface clock and baud-rate timer clock stop. therefore, the serial interface also stops operating in sleep mode. note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be re - moved by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless re - writing said registers.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1.1.5 standard mode and advanced mode the serial interface in the s 1c33e08 is extended from that of the c33 std models. this serial interface has two operating modes, standard (std) mode of which functions are compatible with the existing c 33 std models and an advanced (adv) mode allowing use of the extended functions. table v. 1.1.5.1 shows differences between stan - dard mode and advanced mode. table v. 1.1.5.1 differences between standard mode and advanced mode function #srd y mask control number of receiv ed data in the b uff er to generate a receiv e-b uff er full interr upt ad v anced mode enabled one to four can be specified. standar d mode disabled one to configure the serial interface in advanced mode, set sioadv (d 0/0x300b4 f) to 1 . the control bits for the ex - tended functions are enabled to write after this setting. at initial reset, sioadv (d 0/0x300b4 f) is set to 0 and the serial interface enters standard mode. ? sioadv : standard mode/advanced mode select bit in the serial i/f std/adv mode select register (d0/0x300b4f) the following descriptions unless otherwise specified are common contents for both modes. the extended func - tions in advanced mode are explained assuming that sioadv (d 0/0x300b4f) has been set to 1. note : standard or advanced mode currently set is applied to all the serial interface channels. it cannot be selected for each channel individually.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-6 epson s1c33e08 technical manual v. 1.2 baud-rate timer (setting baud rate) the clock-synchronized master mode and iso 7816 mode use the internal clock for data transfer. also in the asyn - chronous mode, the internal clock can be selected as the operating clock. each channel has a dedicated baud-rate timer ( 12 -bit programmable timer) built-in to generate this clock. the counter initial value can be set by software, this makes it possible to program a flexible transfer rate/sampling frequency. it is not necessary to configure and run the baud-rate timer, when this serial interface is used in the clock-synchro - nized slave mode or in the asynchronous mode using an external clock. data bus 12-bit reload data register (brtrd x ) 12-bit down counter (brtcd x ) brtrun x clock generator buffer underflow signal clock output sio_clk baud-rate timer operating clock (f brclk ) figure v. 1.2.1 transfer clock generation by the baud-rate timer the baud-rate timer is configured with a 12 -bit presettable down counter brtcd x [11:0 ] (d[3:0 ]/0x300b x9, d[7:0]/0x300b x8 ) and a 12 -bit reload data register brtrd x[11:0 ] (d[3:0]/0x300b x7 , d[7:0]/0x300b x6 ) for set - ting an initial value to the counter. ? brtcd x [11:8] : serial i/f ch. x baud-rate timer counter data [11:8] bits in the serial i/f ch. x baud-rate timer counter data register (msb) (d[3:0]/0x300b x 9) brtcd x [7:0] : serial i/f ch. x baud-rate timer counter data [7:0] bits in the serial i/f ch. x baud-rate timer counter data register (lsb) (d[7:0]/0x300b x 8 ) ? brtrd x [11:8] : serial i/f ch. x baud-rate timer reload data [11:8] bits in the serial i/f ch. x baud-rate timer reload data register (msb) (d[3:0]/0x300b x 7) brtrd x [7:0] : serial i/f ch. x baud-rate timer reload data [7:0] bits in the serial i/f ch. x baud-rate timer reload data register (lsb) (d[7:0]/0x300b x 6 ) the baud-rate timer uses the mclk clock supplied from the cmu as the count clock (brclk). for details on how to set and control the mclk clock, see section iii. 1, clock management unit (cmu). this clock can be automatically turned off in halt mode (see section v. 1.1.4). the following procedure generates the clock by the baud-rate timer. 1 . set an initial value to the reload data register brtrd x[11:0] (d[3:0]/0x300b x7, d[7:0]/0x300b x6). 2 . set brtrun x (d0/0x300b x5) to 1. ? brtrun x : serial i/f ch. x baud-rate timer run/stop control bit in the serial i/f ch. x baud-rate timer control register (d0/0x300b x 5) the baud-rate timer loads the initial value set in the reload data register to the counter when 1 is written to brtrun x (d0/0x300b x5 ), and then starts counting down. when the counter underflows, it outputs an underflow pulse and loads the reload data again to continue counting. the underflow occurs in the cycle determined by the reload data. the clock generator reverses its output signal lev - el using the underflow signal to generate a clock with 50% duty ratio and 1/2 the frequency of the underflow signal. the baud-rate timer should be stopped (set brtrun x to 0 ) when serial communication is not needed to reduce current consumption.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 calculating the reload data the initial value for the reload data register is determined by the expressions shown below. note that the expres - sion depends on the transfer mode. clock-synchronized master mode, iso 7816 mode (clock-synchronized) f brclk brtrd = - 1 2 bps brtrd: reload data register setup value of the baud-rate timer f brclk : baud-rate timer operating clock frequency (= mclk hz) bps: transfer rate (bits/second) asynchronous mode f brclk divmd brtrd = - 1 2 bps brtrd: reload data register setup value of the baud-rate timer f brclk : baud-rate timer operating clock frequency (= mclk hz) bps: transfer rate (bits/second) divmd: internal division ratio of the serial interface ( 1/16 or 1/8 selected by divmd x ) iso 7816 mode f brclk d brtrd = - 1 2 bps f f brclk brtrd = - 1 2 f sio_clk brtrd: reload data register setup value of the baud-rate timer f brclk : baud-rate timer operating clock frequency (= mclk hz) bps: transfer rate (bits/second) d: bit rate adjustment value ( 1, 2, 4, 8, 16, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) f: clock frequency divide value ( 372, 558, 744, 1116, 1488, 1860, 512, 768, 1024, 1536, 2048) f sio_clk : iso 7816 clock frequency (baud-rate timer output and #sclk1 output)
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-8 epson s1c33e08 technical manual v. 1.3 clock-synchronized interface v. 1.3.1 outline of clock-synchronized interface in the clock-synchronized transfer mode, 8 bits of data are synchronized to the common clock on both the transmit and receive sides when the data is transferred. since the transmit unit has 2 -byte buffer and the receive unit has 4 -byte buffer (fifo), successive transmit and receive operations are possible. since the clock line is shared be - tween the transmit and receive units, the communication mode is half-duplex. master and slave modes either the clock-synchronized master mode or the clock-synchronized slave mode can be selected using smd x[1:0] ( d[ 1 : 0 ]/ 0 x 300 b x 3 ) . ? smd x [1:0] : serial i/f ch. x transfer mode select bits in the serial i/f ch. x control register (d[1:0]/0x300b x 3) clock-synchronized master mode (smd x[1:0] = 00) in this mode, clock-synchronized 8 -bit serial transfers, in which the serial interface functions as the master, can be performed using the internal clock to synchronize the operat ion of the internal shift registers. the synchronizing clock is output from the #sclk x pin, enabling an external (slave side) serial input/output device to be controlled. the #srdy x pin is also used to input a signal that indicates whether the external serial input/output device is ready to transmit or receive (when ready in a low level). clock-synchronized slave mode (smd x[1:0] = 01) in this mode, clock-synchronized 8 -bit serial transfers, in which the serial interface functions as a slave, can be performed using the synchronizing clock that is supplied by a n external (master side) serial input/output device. the synchronizing clock is input from the #sclk x pin for use as the synchronizing clock of the serial inter - face. in addition, a #srdy x signal indicating whether the serial interface is ready to transmit or receive (when ready in a low level) is output from the #srdy x pin. figure v. 1 . 3 . 1 . 1 shows an example of how the input/output pins are connected in the clock-synchronized mode. data input data output clock input ready output sin x sout x #sclk x #srdy x sin x sout x #sclk x #srdy x external serial device (1) master mode (2) slave mode s1c33e08 data input data output clock output ready input external serial device s1c33e08 figure v. 1.3.1.1 example of connection in clock-synchronized mode clock-synchronized transfer data format in clock-synchronized transfers, the data format is fixed as shown below. data length: 8 bits start bit: none stop bit: none parity bit: none #sclk x data d0 d1 d2 d3 d4 d5 d6 d7 lsb msb figure v. 1.3.1.2 clock-synchronized transfer data format serial data is transmitted and received starting with the lsb.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1.3.2 setting clock-synchronized interface when performing clock-synchronized transfers via the serial interface, the following settings must be made before data transfer is actually begun: 1. setting input/output pins 2 . setting the interface mode 3. setting the transfer mode 4. setting the clocks 5 . setting the receive fifo level 6. setting interrupts and idma/hsdma the following explains the content of each setting. for details on interrupt/dma settings, refer to section v. 1.7, serial interface interrupts and dma. note : always make sure the serial interface is inactive ( txen x (d 7 /0x300b x3) and rxen x (d 6 / 0x300b x3) = 0) before these settings are made. a change of settings during operation may cause a malfunction. ? txen x : serial i/f ch. x transmit enable bit in the serial i/f ch. x control register (d7/0x300b x 3) ? rxen x : serial i/f ch. x receive enable bit in the serial i/f ch. x control register (d6/0x300b x 3) setting input/output pins all four pins sin x , sout x , #sclk x , and #srdy x are used in the clock-synchronized mode. configure the port function select registers to enable these pin functions according to the channel to be used (two or more channel can be used simultaneously). for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. setting the interface mode write 0b00 to irmd x [1:0 ] (d[1:0 ]/0x300b x4 ) to choose the ordinary interface. since irmd x [1:0 ] (d[1:0 ]/ 0x300b x4) becomes indeterminate at initial reset, it must be initialized. ? irmd x [1:0] : serial i/f ch. x interface mode select bits in the serial i/f ch. x irda register (d[1:0]/0x300b x 4) also 7816md1[1:0] (d[1:0]/0x300b1a) must be set to 0b00 in ch.1. ? 7816md1[1:0] : serial i/f ch.1 iso7816 mode select bits in the serial i/f ch.1 iso7816 mode control register (d[1:0]/0x300b1a) setting the transfer mode use smd x[1:0 ] (d[1:0]/0x300b x3 ) to set the transfer mode of the serial interface as described earlier. when using the serial interface as the master for clock-synchronized transfer, set smd x[1:0 ] to 0b00 ; when using the serial interface as a slave, set smd x[1:0] to 0b01. ? smd x [1:0] : serial i/f ch. x transfer mode select bits in the serial i/f ch. x control register (d[1:0]/0x300b x 3) setting the input clock ? clock-synchronized master mode this mode operates using the internal clock generated by the baud-rate timer. setup the baud-rate timer accord - ing to the transfer rate for each channel. for how to control the baud-rate timer, see section v. 1.2, baud-rate timer (setting baud rate). the serial-interface control register contains ssck x (d2/0x300b x3 ) to select the clock source used for the asynchronous mode. although this bit does not affect the clock in the clock-synchronized mode, its content becomes indeterminate at initial reset. therefore, be sure to initialize this bit by writing 0 (internal clock), even when using the serial interface in the clock-synchronized master mode. ? ssck x : serial i/f ch. x input clock select bit in the serial i/f ch. x control register (d2/0x300b x 3) ? clock-synchronized slave mode this mode operates using the clock that is output by the external master. this clock is input from the #sclk x pin. therefore, there is no need to control the baud-rate timer. initialize ssck x by writing 1 (#sclk x).
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-10 epson s1c33e08 technical manual setting the receive fifo level (advanced mode) this serial interface incorporates a 4 -byte receive fifo allowing up to 4 bytes of data that can be received with - out an error even when the receive data register is not read. this serial interface can generate a receive-buffer full interrupt when the specified number of data are received in the receive fifo. use fifoint x[1:0 ] (d[6:5]/ 0x300b x4 ) to set this number of data. writing 0C3 to fifoint x[1:0 ] (d[6:5]/0x300b x4 ) sets the number of data to 1C4 . the default setting at initial reset is 0 so that a receive-buffer full interrupt will generate when one data is received. ? fifoint x [1:0] : serial i/f ch. x receive buffer full interrupt timing select bits in the serial i/f ch. x irda register (d[6:5]/0x300b x 4) v. 1.3.3 control and operation of clock-synchronized transfer transmit control (1 ) enabling transmit operation use the transmit-enable bit txen x (d7/0x300b x3) for transmit control. when transmit is enabled by writing 1 to this bit, the clock input to the shift register is enabled (ready for in - put), thus allowing for data to be transmitted. the synchronizing clock input/output of the #sclk x pin is also enabled (ready for input/output). transmit is disabled and the transmit data buffer (fifo) is cleared by writing 0 to txen x (d7/0x300b x3). ? txen x : serial i/f ch. x transmit enable bit in the serial i/f ch. x control register (d7/0x300b x 3) after the port function select register is set for the serial input/output, the i/o direction of the #srdy x and #sclk x pins are changed at follows: #srdy x : when slave mode is set, a switch is made to output mode. otherwise, input mode is maintained. #sclk x : when master mode is set, a switch is made to output mode. otherwise, input mode is maintained. note : in clock-synchronized transfers, the clock line is shared between the transmit and receive units, so the communication mode is half-duplex. therefore, txen x ( d7/0x300b x3) and receive-enable bit rxen x ( d6/0x300b x3) cannot be enabled simultaneously. when transmitting data, fix rxen x ( d6/0x300b x3) at 0 and do not change it during a transmit operation. in addition, make sure txen x ( d7/0x300b x3) is not set to 0 during a transmit operation. ? rxen x : serial i/f ch. x receive enable bit in the serial i/f ch. x control register (d6/0x300b x 3) (2 ) transmit procedure the serial interface contains a transmit shift register and a transmit data register, which are provided indepen - dently of those used for a receive operation. transmit data is written to txd x[7:0 ] (d[7:0]/0x300b x0 ). the data written to txd x[7:0 ] (d[7:0]/0x300b x0) enters the transmit data buffer and waits for transmission. ? txd x [7:0] : serial i/f ch. x transmit data bits in the serial i/f ch. x transmit data register (d[7:0]/0x300b x 0) the transmit data buffer is a 2 -byte fifo and up to two data can be written to it successively if empty. older data will be transmitted first and cleared after transmission. the next transmit data can be written to the trans - mit data register, even during data transmission. the transmit data buffer status flag tdbe x (d1/0x300b x2 ) is provided to check whether this buffer is full or not. this flag is set to 1 when the transmit data buffer has a free space for transmit data to be written and reset to 0 when the transmit data buffer becomes full by writing trans - mit data. ? tdbe x : serial i/f ch. x transmit data buffer empty flag in the serial i/f ch. x status register (d1/0x300b x 2)
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 the serial interface starts transmitting when data is written to the transmit data register. the transfer status can be checked using the transmit-completion flag tend x (d5/0x300b x2 ). this flag goes 1 when data is being transmitted and goes 0 when the transmission has completed. ? tend x : serial i/f ch. x transmit-completion flag in the serial i/f ch. x status register (d5/0x300b x 2) when data is transmitted successively in clock-synchronized master mode, tend x (d5/0x300b x2 ) maintains 1 until all data is transmitted (figure v. 1.3.3.1 ). in slave mode, tend x (d5/0x300b x2 ) goes 0 every time 1-byte data is transmitted (figure v. 1.3.3.2). when all the data in the transmit data buffer are transferred, a cause of the transmit-data empty interrupt occurs. since an interrupt can be generated as set by the interrupt controller, the next piece of transmit data can be writ - ten using an interrupt processing routine. in addition, since this cause of interrupt can be used to invoke dma, the data prepared in memory can be transmitted successively to the transmit-data register through dma trans - fers. for details on how to control interrupts and dma requests, refer to section v. 1.7, serial interface interrupts and dma. following explains transmit operation in both the master and slave modes. ? clock-synchronized master mode the timing at which the device starts transmitting in the master mode is as follows: when #srdy x is on a low level while the transmit-data buffer contains data written to it or when data has been written to the transmit-data buffer while #srdy x is on a low level. figure v. 1.3.3.1 shows a transmit timing chart in the clock-synchronized master mode. a b slave device receives the lsb. slave device receives the msb. c d first data is written. (2 bytes) next data is written. (2 bytes) transmit-buffer empty interrupt request transmit-buffer empty interrupt request #sclk x #srdy x sout x tdbe x tend x a b d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d1 d6 d7 b a b a b c d figure v. 1.3.3.1 transmit timing chart in clock-synchronized master mode 1 . if the #srdy x signal from the slave is on a high level, the master waits until it is on a low level (ready to receive). 2 . if #srdy x is on a low level, the synchronizing clock input to the serial interface begins. the synchronizing clock is also output from the #sclk x pin to the slave device. 3 . the content of the data buffer is transferred to the shift register synchronously with the first falling edge of the clock. at the same time, the lsb of the data transferred to the shift register is output from the sout x pin. if the transmit data buffer becomes empty at this point, a transmit-buffer empty interrupt request oc - curs. 4 . the data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the lsb is output from sout x . this operation is repeated until all 8 bits of data are transmitted. the slave device takes in each bit synchronously with the rising edges of the synchronizing clock. 5 . the ne x t data transfer begins if the transmit data buffer contains other data.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-12 epson s1c33e08 technical manual ? clock-synchronized slave mode figure v. 1.3.3.2 shows a transmit timing chart in the clock-synchronized slave mode. a b first data is written. (2 bytes) next data is written. (2 bytes) transmit-buffer empty interrupt request transmit-buffer empty interrupt request #sclk x sout x #srdy x tdbe x tend x d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d1 d6 d7 a b figure v. 1.3.3.2 transmit timing chart in clock-synchronized slave mode 1 . after setting the #srdy x signal to a low level (ready to transmit), the slave waits for clock input from the master. 2 . when the synchronizing clock is input from the #sclk x pin, the content of the data register is transferred to the shift register synchronously with the first falling edge of the clock. at the same time, the lsb of the data transferred to the shift register is output from the sout x pin. if the transmit data buffer becomes empty at this point, a transmit-buffer empty interrupt request occurs. the #srdy x signal is returned to a high level at this point. 3 . the data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the lsb is output from sout x . this operation is repeated until all 8 bits of data are transmitted. 4 . the #srdy x signal is set to a low level when the last bit (8th bit) is output from the sout x pin. the master device takes in each bit synchronously with the rising edges of the synchronizing clock. 5 . the next data transfer begins if the transmit data buffer contains other data. (3 ) terminating transmit operation upon completion of data transmission, write 0 to the transmit-enable bit txen x (d7/0x300b x3 ) to disable transmit operation. this operation clears (initializes) the transmit data buffer (fifo), therefore, make sure that the transmit data buffer does not contain any data waiting for transmission before writing 0 to txen x (d7/ 0x300b x3).
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 receive control (1 ) enabling receive operation use the receive-enable bit rxen x (d6/0x300b x3 ) for receive control. when receive operations are enabled by writing 1 to this bit, clock input to the shift register is enabled (ready for input), thereby starting a data-receive operation. the synchronizing clock input/output on the #sclk x pin also is enabled (ready for input/output). receive operations are disabled and the receive data buffer (fifo) is cleared by writing 0 to rxen x (d6/0x300b x3). ? rxen x : serial i/f ch. x receive enable bit in the serial i/f ch. x control register (d6/0x300b x 3) after the port function select register is set for the serial input/output, the i/o direction of the #srdy x and #sclk x pins are changed at follows: #srdy x : when slave mode is set, a switch is made to output mode. otherwise, input mode is maintained. #sclk x : when master mode is set, a switch is made to output mode. otherwise, input mode is maintained. note : in clock-synchronized transfers, the clock line is shared between the transmit and receive units, so the communication mode is half-duplex. therefore, rxen x (d6/0x300b x3) and transmit-enable bit txen x (d 7/0x300b x3) cannot be enabled simultaneously. when receiving data, fix txen x (d7/0x300b x3) at 0 and do not change it during a receive operation. in addition, make sure rx - en x (d6/0x300b x3) is not set to 0 during a receive operation. ? txen x : serial i/f ch. x transmit enable bit in the serial i/f ch. x control register (d7/0x300b x 3) (2 ) receive procedure this serial interface has a receive shift register, receive data buffer and a receive data register that are provided independently of those used for transmit operations. the received data enters the received data buffer. the receive data buffer is a 4 -byte fifo and can receive data until it becomes full unless the received data is not read out. the received data in the buffer can be read by accessing rxd x[7:0 ] (d[7:0]/0x300b x1 ). the older data is out - put first and cleared by reading. ? rxd x[7:0] : serial i/f ch. x receive data bits in the serial i/f ch. x receive data register (d[7:0]/0x300b x1) the number of data in the receive data buffer can be checked by reading rxd x num[ 1 : 0 ] (d[ 7:6]/0x300b x2 ). when rxd x num[ 1 : 0 ] (d[ 7:6]/0x300b x2 ) is 0 , the buffer contains 0 or 1 data. when rxd x num[ 1 : 0 ] (d[ 7:6]/ 0x300b x2 ) is 1 C 3 , the buffer contains 2 C 4 data. ? rxd x num[1:0] : number of ch. x receive data in fifo in the serial i/f ch. x status register (d[7:6]/0x300b x 2) furthermore, rdbf x (d0/0x300b x2 ) is provided for indicating whether the receive data buffer is empty or not. this flag is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data. ? rdbf x : serial i/f ch. x receive data buffer full flag in the serial i/f ch. x status register (d0/0x300b x 2) when the receive data buffer has received the specified number or more data (one in standard mode or one to four in advanced mode), a cause of the receive-buffer full interrupt occurs. since an interrupt can be generated as set by the interrupt controller, the received data can be read by an interrupt processing routine. in addition, since this cause of interrupt can be used to invoke dma, the received data can be received successively in loca - tions prepared in memory through dma transfers. for details on how to control interrupts/dma, refer to section v. 1.7, serial interface interrupts and dma.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-14 epson s1c33e08 technical manual the following describes a receive operation in the master and slave modes. ? clock-synchronized master mode figure v. 1.3.3.3 shows a receive timing chart in the clock-synchronized master mode. a first data is read. receive-buffer full interrupt request (fifoint x [1:0] = 2) overrun error interrupt request #sclk x sin x receive data buffer rxd x num[1:0] rdbf x #srdy x (srdyctl x = 0) data 1 d0 d1 d6 d7 data 2 d0 d1 d6 d7 data 3 d0 d1 d6 d7 data 4 d0 d1 d6 d7 data 5 d0 d1 d6 d7 data 6 d0 d1 d6 d7 a data 1 1, 2 2, 3, 4, 5 2, 3, 4 1, 2, 3 2, 3 1 3 2 2 1 0 figure v. 1.3.3.3 receive timing chart in clock-synchronized master mode 1 . if the #srdy x signal from the slave is on a high level, the master waits until it turns to a low level (ready to receive). 2 . if #srdy x is on a low level, synchronizing clock input to the serial interface begins. the synchronizing clock is also output from the #sclk x pin to the slave device. 3 . the slave device outputs each bit of data synchronously with the falling edges of the clock. the lsb is out - put first. 4 . this serial interface takes the sin x input into the shift register at the rising edges of the clock. the data in the shift register is sequentially shifted as bits are taken in. this operation is repeated until the msb of data is received. 5 . when the msb is taken in, the data in the shift register is transferred to the receive data buffer, enabling the data to be read out. ? clock-synchronized slave mode figure v. 1.3.3.4 shows a receive timing chart in the clock-synchronized slave mode. a data (1 byte ) is read. receive-buffer full interrupt request (fifoint x [1:0] = 2) overrun error interrupt request #sclk x sin x receive data buffer rxd x num[1:0] rdbf x #srdy x (srdyctl x = 0) data 1 d0 d1 d6 d7 data 2 d0 d1 d6 d7 data 3 d0 d1 d6 d7 data 4 d0 d1 d6 d7 data 5 d0 d1 d6 d7 data 6 d0 d1 d6 d7 data 1 1, 2 2, 3, 4, 5 2, 3, 4 1, 2, 3 2, 3 1 3 2 2 1 0 a a figure v. 1.3.3.4 receive timing chart in clock-synchronized slave mode 1 . after setting the #srdy x signal to a low level (ready to receive), the slave waits for clock input from the master. 2 . the master device outputs each bit of data synchronously with the falling edges of the clock. the lsb is output first. 3 . this serial interface takes the sin x input into the shift register at the rising edges of the clock that is input from #sclk x . the data in the shift register is sequentially shifted as bits are taken in. this operation is re - peated until the msb of data is received. 4 . when the msb is taken in, the data in the shift register is transferred to the receive data buffer, enabling the data to be read out.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 (3 ) overrun error even when the receive data buffer is full ( 4 data have been received), the next (5 th) data can be received into the shift register. if there is no space in the buffer (data has not been read) when the 5 th data has been received, the 5 th data in the shift register cannot be transferred to the buffer. if one more (6 th) data is transferred to this serial interface, the shift register ( 5 th data) is overwritten with the 6 th data and an overrun error is generated. when an overrun error is generated, the overrun error flag oer x (d2/0x300b x2 ) is set to 1 . once the overrun error flag is set to 1, it remains set until it is reset by writing 0 to it in the software. ? oer x : serial i/f ch. x overrun error flag in the serial i/f ch. x status register (d2/0x300b x 2) the overrun error is one of the receive-error interrupt causes in the serial interface. an interrupt can be gener - ated for this error by setting the interrupt controller as necessary, so that the error can be processed by an inter - rupt processing routine. generation of overrun error can be disabled by controlling the #srdy x as shown below. (4 ) controlling the #srdy x signal (advanced mode) when the slave device is in receive mode, the #srdy x signal is output from the slave device to the master de - vice to notify whether the slave device is ready to receive data or not. when this serial interface is in the clock-synchronized slave mode, the #srdy x signal is turned to a low level by writing 1 to rxen x (d6/0x300b x3 ) to enable receive operations, thereby indicating to the master device that the slave is ready to receive. when the lsb of data is received, #srdy x is turned to a high level; when the msb is received, #srdy x is returned to a low level, in preparation for the next receive operation. if an overrun error occurs, #srdy x is turned to a high level (unable to receive) at that point, so receive opera - tions for the following data are suspended. in this case, #srdy x is returned to low by reading out the receive data buffer, and if any receive data follows, the slave restarts receiving data. in the normal mode, the #srdy x signal indicating ready to receive is output even if the receive data buffer is full. if the receive data buffer cannot be read in this case, an overrun error occurs in the next data transfer. to prevent this error, the serial interface provides #srdy x high mask mode. in this mode, if the receive data buffer is full, the #srdy x signal is forcibly fixed at high in order to suspend data transfer from the master device until the data in the buffer is read. to use this function, set srdyctl x (d7/0x300b x4) to 1. ? srdyctl x : serial i/f ch. x #srdy control bit in the serial i/f ch. x irda register (d7/0x300b x 4) this function is effective in the clock-synchronized master mode as well. in this case, the #srdy x signal (low) from the slave device is ignored when the receive data buffer is full and the serial interface stops outputting the #sclk x signal until the buffer data is read. when the receive data buffer is not full, normal receive operation is performed even if this function is enabled.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-16 epson s1c33e08 technical manual a first data is read. the clock output stops while fifo is full. #sclk x sin x receive data buffer rxd x num[1:0] rdbf x #srdy x (srdyctl x = 1) data 1 d0 d1 d6 d7 data 2 d0 d1 d6 d7 data 3 d0 d1 d6 d7 data 4 d0 d1 d6 d7 data 5 d0 d1 d6 a data 1 1, 2 2, 3, 4 1, 2, 3, 4 1 2 3 1, 2, 3 2 0 cloc k-synchroniz ed master mode cloc k-synchroniz ed sla ve mode a first data is read. #srdy x is fixed at high while fifo is full. #sclk x sin x receive data buffer rxd x num[1:0] rdbf x #srdy x (srdyctl x = 1) data 1 d0 d1 d6 d7 data 2 d0 d1 d6 d7 data 3 d0 d1 d6 d7 data 4 d0 d1 d6 d7 data 5 d0 d1 d6 a data 1 1, 2 2, 3, 4 1, 2, 3, 4 1 2 3 1, 2, 3 2 0 figure v. 1.3.3.5 #srdy x high mask mode (5 ) terminating receive operation upon completion of a data receive operation, write 0 to the receive-enable bit rxen x (d6/0x300b x3 ) to dis - able receive operations. this operation clears (initializes) the receive data buffer (fifo), therefore, make sure that there is no data that has not been read in the receive data buffer before setting rxen x (d6/0x300b x3) to 0.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1.4 asynchronous interface v. 1.4.1 outline of asynchronous interface asynchronous transfers are performed by adding a start bit and a stop bit to the start and end points of each serial- converted data. with this method, there is no need to use a clock that is fully synchronized on the transmit and receive sides; instead, transfer operations are timed by the start and stop bits added to the start and end points of each data. in the 8 -bit asynchronous mode (smd x[1:0 ] = 0b11), 8 bits of data can be transferred; in the 7 -bit asynchronous mode (smd x[1:0] = 0b10), 7 bits of data can be transferred. ? smd x [1:0] : serial i/f ch. x transfer mode select bits in the serial i/f ch. x control register (d[1:0]/0x300b x 3) in either mode, it is possible to select the stop-bit length, add a parity bit, and choose between even and odd parity. the start bit is fixed at 1. the operating clock can be selected between an internal clock generated by an 8 -bit timer or an external clock that is input from the #sclk x pin. since the transmit unit has 2 -byte buffer and the receive unit has 4 -byte buffer (fifo), successive transmit and receive operations are possible. furthermore, since the transmit and receive units are independent, full-duplex com - munication in which transmit and receive operations are performed simultaneously is also possible. figure v. 1.4.1.1 shows an example of how input/output pins are connected for transfers in the asynchronous mode. data input data output external clock sin x sout x #sclk x sin x sout x external serial device (1) when external clock is used (2) when internal clock is used s1c33e08 data input data output external serial device s1c33e08 figure v. 1.4.1.1 example of connection in asynchronous mode when the asynchronous mode is selected, it is possible to use t he irda interface function. asynchronous-transfer data format the data format for asynchronous transfer is shown below. data length: 7 or 8 bits (determined by the selected transfer mode) start bit: 1 bit, fixed stop bit: 1 or 2 bits parity bit: even or odd parity, or none sampling clock (for transmitting) s1: start bit, s2 & s3: stop bit, p: parity bit 7-bit asynchronous mode (stop bit: 1 bit, parity: none) s1 d0 d1 d2 d3 d4 d5 d6 s2 (stop bit: 1 bit, parity: used) s1 d0 d1 d2 d3 d4 d5 d6 p s2 (stop bit: 2 bits, parity: none) s1 d0 d1 d2 d3 d4 d5 d6 s2 s3 (stop bit: 2 bits, parity: used) s1 d0 d1 d2 d3 d4 d5 d6 p s2 s3 8-bit asynchronous mode (stop bit: 1 bit, parity: none) s1 d0 d1 d2 d3 d4 d5 d6 d7 s2 (stop bit: 1 bit, parity: used) s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 (stop bit: 2 bits, parity: non) s1 d0 d1 d2 d3 d4 d5 d6 d7 s2 s3 (stop bit: 2 bits, parity: used) s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s3 figure v. 1.4.1.2 data format for asynchronous transfer serial data is transmitted and received, starting with the lsb.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-18 epson s1c33e08 technical manual v. 1.4.2 setting asynchronous interface when performing asynchronous transfer via the serial interface, the following must be done before data transfer can be started: 1. setting input/output pins 2 . setting the interface mode 3. setting the transfer mode 4. setting the input clock 5. setting the data format 6 . setting the receive fifo level 7. setting interrupt/idma/hsdma the following describes how to set each of the above. for details on interrupt/dma settings, refer to section v. 1.7, serial interface interrupts and dma. note : always make sure the serial interface is inactive (txen x (d 7 /0x300b x3) and rxen x (d 6 / 0x300b x3) = 0) before making these settings. a change in settings during operation may result in a malfunction. ? txen x : serial i/f ch. x transmit enable bit in the serial i/f ch. x control register (d7/0x300b x 3) ? rxen x : serial i/f ch. x receive enable bit in the serial i/f ch. x control register (d6/0x300b x 3) setting input/output pins in the asynchronous mode, two pins sin x and sout x are used. when external clock input is used, one more pin, #sclk x , is also used. configure the port function select registers to enable these pin functions according to the channel to be used (two or more channel can be used simultaneously). for details of pin func - tions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. setting the interface mode initialize irmd x[1:0] (d[1:0]/0x300b x4) by writing 0b00 when using the serial interface as a normal interface, or 0b10 when using the serial interface as an irda interface. this setting must be made before a transfer mode is set. ? irmd x [1:0] : serial i/f ch. x interface mode select bits in the serial i/f ch. x irda register (d[1:0]/0x300b x 4) also 7816md1[1:0] (d[1:0]/0x300b1a) must be set to 0b00 in ch.1. ? 7816md1[1:0] : serial i/f ch.1 iso7816 mode select bits in the serial i/f ch.1 iso7816 mode control register (d[1:0]/0x300b1a) setting the transfer mode use smd x[1:0 ] (d[1:0]/0x300b x3 ) to set the transfer mode of the serial interface as described earlier. when using the serial interface in the 8 -bit asynchronous mode, set smd x[1:0 ] (d[1:0]/0x300b x3 ) to 0b11 , when us - ing the serial interface in the 7-bit asynchronous mode, set smd x[1:0] (d[1:0]/0x300b x3) to 0b10. ? smd x [1:0] : serial i/f ch. x transfer mode select bits in the serial i/f ch. x control register (d[1:0]/0x300b x 3) setting the input clock in the asynchronous mode, the operating clock can be selected between the internal clock and an external clock using ssck x (d2/0x300b x3). ? ssck x : serial i/f ch. x input clock select bit in the serial i/f ch. x control register (d2/0x300b x 3) the external clock is selected (input from the #sclk x pin) by writing 1 to ssck x (d2/0x300b x3 ), and an in - ternal clock is selected by writing 0. note : ssck x (d2/0x300b x3) becomes indeterminate at initial reset, so be sure to reset it in the soft - ware.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ? internal clock when the internal clock is selected, the serial interface is clocked by the clock generated using the baud-rate timer. setup the baud-rate timer according to the transfer rate for each channel. for how to control the baud-rate timer, see section v. 1.2, baud-rate timer (setting baud rate). ? external clock when an external clock is selected, the serial interface is clocked by a clock input from the #sclk x pin. there - fore, there is no need to control the baud-rate timer. any desired clock frequency can be set. the clock input from the #sclk x pin is internally divided by 16 or 8 in the serial interface, in order to create a sampling clock (refer to sampling clock ). this division ratio must also be considered when setting the transfer rate. ? sampling clock in the asynchronous mode, sio_clk (the clock output by the baud-rate timer or input from the #sclk x pin) is internally divided in the serial interface, in order to create a sampling clock. a 1 / 16 division ratio is selected by writing 0 to divmd x ( d 4 / 0 x 300 b x 4 ), and a 1 / 8 ratio is selected by writing 1 . ? divmd x : serial i/f ch. x clock division ratio select bit in the serial i/f ch. x irda register (d4/0x300b x 4) note : divmd x (d4/0x300b x4) becomes indeterminate at initial reset, so be sure to reset it in the soft - ware. settings of this bit are valid only in the asynchronous mode (and when using the irda inter - face). for receiving sin x sio_clk sampling clock sampling of start bit start bit d0 1 8 1 8 8 sio_clk 16 sio_clk sampling of d0 bit figure v. 1.4.2.1 sampling clock for asynchronous receive operation (when 1/16 division is selected) each bit data is sampled in the timing shown in figure v. 1.4.2.1 . when the sin x input signal is detected as a low level at the rising edge of sio_clk, sampling for the start bit is performed 8 sio_clk (4 sio_clk when 1/8 division is selected) after that point. if a low level is not detected in the sampling for the start bit, the interface aborts the subsequent samplings and returns to the start bit detection phase (in this case no er - ror occurs). when the sin x input signal is low at the start bit sampling, subsequent bit data is sampled in 16 sio_clk cycles ( 8 sio_clk cycles when 1/8 division is selected). for transmitting sio_clk sampling clock sout x start bit d0 1 8 16 16 sio_clk figure v. 1.4.2.2 sampling clock for asynchronous transmit operation (when 1/16 division is selected) during transmission, each bit data is output from the sout x pin in 16 sio_clk cycles (8 sio_clk cycles when 1/8 division is selected).
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-20 epson s1c33e08 technical manual setting the data format in the asynchronous mode, the data length is 7 or 8 bits as determined by the transfer mode set. the start bit is fixed at 1. the stop and parity bits can be set as shown in the table v. 1.4.2.2 using the control bits listed below. stop bit select ? stpb x : serial i/f ch. x stop-bit length select bit in the serial i/f ch. x control register (d3/0x300b x 3) parity enable ? epr x : serial i/f ch. x parity enable bit in the serial i/f ch. x control register (d5/0x300b x 3) parity mode select ? pmd x : serial i/f ch. x parity mode select bit in the serial i/f ch. x control register (d4/0x300b x 3) table v. 1.4.2.1 stop bit and parity bit settings pmd x 1 0 ? 1 0 ? epr x 1 0 1 0 stpb x 1 0 stop bit 2 bits 2 bits 2 bits 1 bit 1 bit 1 bit p arity bit odd ev en none odd ev en non ? setting pmd x is invalid when epr x = 0. note : these bits become indeterminate at initial reset, so be sure to initialize them in the software. setting the receive fifo level (advanced mode) this serial interface incorporates a 4 -byte receive fifo allowing up to 4 bytes of data that can be received with - out an error even when the receive data register is not read. this serial interface can generate a receive-buffer full interrupt when the specified number of data are received in the receive fifo. use fifoint x[1:0 ] (d[6:5]/ 0x300b x4 ) to set this number of data. writing 0C3 to fifoint x[1:0 ] (d[6:5]/0x300b x4 ) sets the number of data to 1C4 . the default setting at initial reset is 0 so that a receive-buffer full interrupt will generate when one data is received. ? fifoint x [1:0] : serial i/f ch. x receive buffer full interrupt timing select bits in the serial i/f ch. x irda register (d[6:5]/0x300b x 4) v. 1.4.3 control and operation of asynchronous transfer transmit control (1 ) enabling transmit operation use the transmit-enable bit txen x (d7/0x300b x3) for transmit control. when transmit is enabled by writing 1 to this bit, the clock input to the shift register is enabled (ready for in - put), thus allowing data to be transmitted. transmit is disabled and the transmit data buffer (fifo) is cleared by writing 0 to txen x (d7/0x300b x3). ? txen x : serial i/f ch. x transmit enable bit in the serial i/f ch. x control register (d7/0x300b x 3) note : do not set txen x (d7/0x300b x3) to 0 during a transmit operation. (2 ) transmit procedure the serial interface contains a transmit shift register and a transmit data register, which are provided indepen - dently of those used for a receive operation. transmit data is written to txd x[7:0] (d[7:0]/0x300b x0). ? txd x [7:0] : serial i/f ch. x transmit data bits in the serial i/f ch. x transmit data register (d[7:0]/0x300b x 0) in the 7-bit asynchronous mode, bit 7 (msb) in each register is ignored.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 the data written to txd x[7:0] (d[7:0]/0x300b x0 ) enters the transmit data buffer and waits for transmission. the transmit data buffer is a 2 -byte fifo and up to two data can be written to it successively if empty. older data will be transmitted first and cleared after transmission. the next transmit data can be written to the trans - mit data register, even during data transmission. the transmit data buffer status flag tdbe x (d1/0x300b x2 ) is provided to check whether this buffer is full or not. this flag is set to 1 when the transmit data buffer has a free space for transmit data to be written and reset to 0 when the transmit data buffer becomes full by writing trans - mit data. ? tdbe x : serial i/f ch. x transmit data buffer empty flag in the serial i/f ch. x status register (d1/0x300b x 2) the serial interface starts transmitting when data is written to the transmit data register. the transfer status can be checked using the transmit-completion flag tend x (d5/0x300b x2 ). this flag goes 1 when data is being transmitted and goes 0 when the transmission has completed. ? tend x : serial i/f ch. x transmit-completion flag in the serial i/f ch. x status register (d5/0x300b x 2) when all the data in the transmit data buffer are transferred, a cause of the transmit-data empty interrupt occurs. since an interrupt can be generated as set by the interrupt controller, the next piece of transmit data can be writ - ten using an interrupt processing routine. in addition, since this cause of interrupt can be used to invoke dma, the data prepared in memory can be transmitted successively to the transmit-data register through dma trans - fers. for details on how to control interrupts and dma requests, refer to section v. 1.7, serial interface interrupts and dma. figure v. 1.4.3.1 shows a transmit timing chart in the asynchronous mode. example: data length: 8 bits, stop bit: 1 bit, parity bit: included s1 s2 p start bit stop bit parity bit a b first data is written. (2 bytes) next data is written. (2 bytes) transmit-buffer empty interrupt request transmit-buffer empty interrupt request sampling clock sout x tdbe x tend x s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 d7 p s2 s1 d0 d1 d7 p s 2 s1 d0 d1 d7 p s 2 a b figure v. 1.4.3.1 transmit timing chart in asynchronous mode 1 . the contents of the buffer are transferred to the shift register synchronously with the first falling edge of the sampling clock. at the same time, the sout x pin is setting to a low level to send the start bit. 2 . each bit of data in the shift register is transmitted beginning with the lsb at each falling edge of the subse - quent sampling clock. this operation is repeated until all 8 (or 7) bits of data are transmitted. 3 . after sending the msb, the parity bit (if epr x = 1) and the stop bit are transmitted in succession. ? epr x : serial i/f ch. x parity enable bit in the serial i/f ch. x control register (d5/0x300b x 3) 4 . the next data transfer begins if the transmit data buffer contains other data. (3 ) terminating transmit operations when data transmission is completed, write 0 to the transmit-enable bit txen x ( d7/0x300b x3 ) to disable transmit operations. this operation clears (initializes) the transmit data buffer (fifo), therefore, make sure that the transmit data buffer does not contain any data waiting for transmission before writing 0 to txen x (d7/0x300b x3).
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-22 epson s1c33e08 technical manual receive control (1 ) enabling receive operations use the receive-enable bit rxen x (d6/0x300b x3 ) for receive control. when receiving enabled by writing 1 to this bit, clock input to the shift register is enabled (ready for input), meaning that it is ready to receive data. receive operations are disabled and the receive data buffer (fifo) is cleared by writing 0 to rxen x (d6/0x300b x3). ? rxen x : serial i/f ch. x receive enable bit in the serial i/f ch. x control register (d6/0x300b x 3) note : do not set rxen x (d6/0x300b x3) to 0 during a receive operation. (2 ) receive procedure this serial interface has a receive shift register, receive data buffer and a receive data register that are provided independently of those used for transmit operations. the received data enters the received data buffer. the receive data buffer is a 4 -byte fifo and can receive data until it becomes full unless the received data is not read out. the received data in the buffer can be read by accessing rxd x[7:0 ] (d[7:0]/0x300b x1 ). the older data is out - put first and cleared by reading. ? rxd x[7:0] : serial i/f ch. x receive data bits in the serial i/f ch. x receive data register (d[7:0]/0x300b x1) the number of data in the receive data buffer can be checked by reading rxd xnum[1:0 ] (d[7:6]/0x300b x2). when rxd x num[ 1:0 ] (d[7:6 ]/0x300b x2 ) is 0 , the buffer contains 0 or 1 data. when rxd x num[ 1:0] (d[7:6]/0x300b x2) is 1C3 , the buffer contains 2C4 data. ? rxd x num[1:0] : number of ch. x receive data in fifo in the serial i/f ch. x status register (d[7:6]/0x300b x 2) furthermore, rdbf x (d0/0x300b x2 ) is provided for indicating whether the receive data buffer is empty or not. this flag is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data. ? rdbf x : serial i/f ch. x receive data buffer full flag in the serial i/f ch. x status register (d0/0x300b x 2) when the receive data buffer has received the specified number or more data (one in standard mode or one to four in advanced mode), a cause of the receive-buffer full interrupt occurs. since an interrupt can be generated as set by the interrupt controller, the received data can be read by an interrupt processing routine. in addition, since this cause of interrupt can be used to invoke dma, the received data can be received successively in loca - tions prepared in memory through dma transfers. for details on how to control interrupts/dma, refer to section v. 1.7, serial interface interrupts and dma. figure v. 1.4.3.2 shows a receive timing chart in the asynchronous mode.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 example: data length: 8 bits, stop bit: 1 bit, parity bit: included s1 s2 start bit stop bit p a parity bit first data is read. receive-buffer full interrupt request (fifoint x [1:0] = 2) overrun error interrupt request sampling clock sin x receive data buffer rxd x num[1:0] rdbf x data 1 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 data 2 data 3 data 4 data 5 data 6 a data 1 1, 2 2, 3, 4, 5 2, 3, 4 1, 2, 3 2, 3 1 3 2 2 1 0 figure v. 1.4.3.2 receive timing chart in asynchronous mode 1 . the serial interface starts sampling when the start bit is input (sin x = low). 2 . when the start bit is sampled at the first rising edge of the sampling clock, each bit of receive data is taken into the shift register, beginning with the lsb at each rising edge of the subsequent clock. this operation is repeated until the msb of data is received. 3 . when the msb is taken in, the parity bit that follows is also taken in (if epr x = 1). 4 . when the stop bit is sampled, the data in the shift register is transferred to the receive data register, enabling the data to be read out. the parity is checked when data is transferred to the receive data register (if epr x = 1). note : the receive operation is terminated when the first stop bit is sampled even if the stop bit is config - ured with two bits. (3 ) receive errors three types of receive errors can be detected when receiving data in the asynchronous mode. since an interrupt can be generated by setting the interrupt controller, the error can be processed using an inter - rupt processing routine. for details on receive error interrupts, refer to section v. 1.7, serial interface interrupts and dma. ? parity error if epr x (d5/0x300b x3) is set to 1 (parity added), the parity is checked when data is received. this parity check is performed when the data received in the shift register is transferred to the receive data buf - fer in order to check conformity with pmd x (d4/0x300b x3 ) settings (odd or even parity). ? pmd x : serial i/f ch. x parity mode select bit in the serial i/f ch. x control register (d4/0x300b x 3) if any nonconformity is found in this check, a parity error is assumed and the parity error flag per x ( d3/ 0x300b x2) is set to 1. ? per x : serial i/f ch. x parity error flag in the serial i/f ch. x status register (d3/0x300b x 2) even when this error occurs, the received data in error is transferred to the receive data buffer and the receive operation is continued. however, the content of the received data for which a parity error is flagged cannot be guaranteed. per x (d3/0x300b x2) is reset to 0 by writing 0.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-24 epson s1c33e08 technical manual ? framing error if data with a stop bit = 0 is received, the serial interface assumes that the data is out of synchronization and generates a framing error. if two stop bits are used, only the first stop bit is checked. when this error occurs, the framing-error flag fer x (d4/0x300b x2) is set to 1. ? fer x : serial i/f ch. x framing error flag in the serial i/f ch. x status register (d4/0x300b x 2) even when this error occurs, the received data in error is transferred to the receive data buffer and the receive operation is continued. however, the content of the received data for which a framing error is flagged cannot be guaranteed, even if no framing error is found in the following data received. the fer x (d4/0x300b x2) flag is reset to 0 by writing 0. ? overrun error even when the receive data buffer is full ( 4 data have been received), the next (5 th) data can be received into the shift register. if there is no space in the buffer (data has not been read) when the 5 th data has been received, the 5 th data in the shift register cannot be transferred to the buffer. if one more (6 th) data is transferred to this serial interface, the shift register ( 5 th data) is overwritten with the 6 th data and an overrun error is generated. when an overrun error is generated, the overrun error flag oer x ( d 2 / 0 x 300 b x 2 ) is set to 1. ? oer x : serial i/f ch. x overrun error flag in the serial i/f ch. x status register (d2/0x300b x 2) even when this error occurs, the receive operation is continued. oer x (d2/0x300b x2) is reset to 0 by writing 0. (4 ) terminating receive operation when a data receive operation is completed, write 0 to the receive-enable bit rxen x (d6/0x300b x3 ) to disable receive operations. this operation clears (initializes) the receive data buffer (fifo), therefore, make sure that there is no data that has not been read in the receive data buffer before setting rxen x (d6/0x300b x3) to 0.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1.5 irda interface v. 1.5.1 outline of irda interface each channel of the serial interface contains a rzi modulator circuit, allowing an infrared-ray communication cir - cuit to be configured based on irda 1.0 simply by adding a simple external circuit. rzi modulator sout x led txd led a led c rxd cx1 vcc cx2 gnd v p1n v p1n photodiode sin x v dd v ss serial i/f rzi modulator s1c33e08 infrared communication module figure v. 1.5.1.1 configuration example of irda interface this irda interface function can be used only when the selected transfer mode is an asynchronous mode. since the contents of the asynchronous mode are applied directly for the serial-interface functions other than the irda interface unit, refer to section v. 1.4, asynchronous interface, for details on how to set and control the data formats and data transfers. v. 1.5.2 setting irda interface when performing infrared-ray communication, the following settings must be made before communication can be started: 1. setting input/output pins 2 . selecting the interface mode (irda interface function) 3. setting the transfer mode 4. setting the input clock 5. setting the data format 6 . setting the receive fifo level 7. setting the interrupt/idma/hsdma 8. setting the input/output logic the contents for items 1 through 6 have been explained in connection with the asynchronous interface. for details, refer to section v. 1.4, asynchronous interface. for details on item 7 , refer to section v.1.7, serial interface in - terrupts and dma. note : before making these settings, always make sure the serial interface is inactive (txen x (d 7 / 0 x 300 b x 3 ) and rxen x (d 6 / 0 x 300 b x 3 ) are both set to 0), as a change in settings during operation could cause a malfunction. in addition, be sure to set the transfer mode in (3) and the following items after selecting the irda interface function in (2). ? txen x : serial i/f ch. x transmit enable bit in the serial i/f ch. x control register (d7/0x300b x 3) ? rxen x : serial i/f ch. x receive enable bit in the serial i/f ch. x control register (d6/0x300b x 3)
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-26 epson s1c33e08 technical manual selecting the irda interface function to use the irda interface function, select it using irmd x[1:0 ] (d[1:0]/0x300b x4 ) and then set the 8 -bit (or 7-bit) asynchronous mode as the transfer mode. table v. 1.5.2.1 setting of irda interface irmd x 1 1 1 0 0 irmd x 0 1 0 1 0 interface mode do not set. (reser v ed) ird a 1.0 interf ace do not set. (reser v ed) nor mal interf ace ? irmd x [1:0] : serial i/f ch. x interface mode select bits in the serial i/f ch. x irda register (d[1:0]/0x300b x 4) note : irmd x [1:0] (d[1:0]/0x300b x4) becomes indeterminate when initially reset, so be sure to initialize it in the software. setting the input/output logic when using the irda interface, the logic of the input/output signals of the rzi modulator circuit can be changed in accordance with the infrared-ray communication module or the circuit connected externally to the chip. the logic of the internal serial interface is active-low. if the input/output signals are active-high, the logic of these signals must be inverted before they can be used. the input sin x and output sout x logic can be set individually through the use of irrl x (d2/0x300b x4 ) and irtl x (d3/0x300b x4 ), respectively. ? irrl x : serial i/f ch. x irda i/f input logic inversion bit in the serial i/f ch. x irda register (d2/0x300b x 4) ? irtl x : serial i/f ch. x irda i/f output logic inversion bit in the serial i/f ch. x irda register (d3/0x300b x 4) the logic of the input/output signal is inverted by writing 1 to irrl x (d2/0x300b x4 )/irtl x (d3/0x300b x4). logic is not inverted if the bit is set to 0. rzi modulator input (i/f output) rzi modulator output (sout x ) (1) irtl x = 0 when transmitting rzi modulator input (i/f output) rzi modulator output (sout x ) (2) irtl x = 1 rzi modulator input (sin x ) rzi modulator output (i/f input) (1) irrl x = 0 when receiving rzi modulator input (sin x ) rzi modulator output (i/f input) (2) irrl x = 1 figure v. 1.5.2.1 irrl x and irtl x settings note : irrl x (d 2/0x300b x4) and irtl x (d 3/0x300b x4) become indeterminate at initial reset, so be sure to initialize them in the software.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1.5.3 control and operation of irda interface the transmit/receive procedures have been explained in the section on the asynchronous interface, so refer to sec - tion v. 1.4.3, control and operation of asynchronous transfer. the following describes the data modulation and demodulation performed using the rzi modulator circuit: when transmitting during data transmission, the pulse width of the serial interface output signal is set to 3/16 before the signal is output from the sout x pin. sio_clk rzi modulator input (i/f output) rzi modulator output (sout x ) 1 2 3 8 9 1 0 1 1 1 6 3 sio_clk 16 sio_clk figure v. 1.5.3.1 data modulation by rzi circuit when receiving during data reception, the pulse width of the input signal from sin x is set to 16/3 before the signal is trans - ferred to the serial interface. sio_clk rzi modulator input (sin x ) rzi modulator output (i/f input) 1 2 3 4 16 16 sio_clk 3 sio_clk figure v. 1.5.3.2 demodulation by rzi circuit notes : ? when using the irda interface, set the internal division ratio of the serial interface 1 / 16 (divmd x = 1 ), rather than 1/8 (divmd x = 0). ? divmd x : serial i/f ch. x clock division ratio select bit in the serial i/f ch. x irda register (d4/0x300b x 4) ? although figure v.1.5.3.2 shows the input signal as a low pulse of a 3 sio_clk width, the rzi circuit recognizes low pulses by means of the signal edge (rising edge when irrl x = 0 ; falling edge when irrl x = 1 ). note that noise may cause a malfunction.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-28 epson s1c33e08 technical manual v. 1.6 iso7816 interface (ch.1) note : iso7816 mode is available only for ch.1. v. 1.6.1 outline of iso7816 interface s1c33e08 supports a smart card interface in conformity with iso7816-3. the iso7816 interface performs serial communication using two wires for data transfer and clock. the transfer method is an asynchronous system that transfers data with start and stop bits. this interface allows clock synchronized transfer using the same data format. since the data line is shared between the transmitter and receiver, the communication mode is half-duplex. this interface supports t = 0 and t = 1 protocols, and it can be selected using 7816md1[1:0] (d[1:0]/0x300b1a). ? 7816md1[1:0] : serial i/f ch. 1 iso7816 mode select bits in the serial i/f ch. 1 iso7816 mode control register (d[1:0]/0x300b1a) table v. 1.6.1.1 selecting iso7816 mode 7816md11 1 1 0 0 7816md10 1 0 1 0 mode reser ve d iso7816 (t = 1) mode iso7816 (t = 0) mode nor mal interf ace (default: 0b00) figure v. 1.6.1.1 shows a smart card connection example. sout1 #sclk1 i/o clk sin1 p xx rst smart card s1c33e08 figure v. 1.6.1.1 connection example in iso7816 mode iso7816 transfer data format the data format for iso 7816 mode is shown below. data length: 8 bits, fixed start bit: 1 bit, fixed stop bit: 1 bit (t = 1) or 2 bits (t = 0) parity bit: even parity sampling clock (for transmitting) s1: start bit, s2 & s3: stop bit, p: parity bit iso7816 (t = 1) mode (msbsel1 = 0: lsb first) iso7816 (t = 1) mode (msbsel1 = 1: msb first) iso7816 (t = 0) mode (msbsel1 = 0: lsb first) iso7816 (t = 0) mode (msbsel1 = 1: msb first) s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s1 d7 d6 d5 d4 d3 d2 d1 d0 p s2 s1 d7 d6 d5 d4 d3 d2 d1 d0 p s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s3 figure v. 1.6.1.2 iso7816 transfer data format
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1.6.2 setting iso7816 interface when performing transfer in iso7816 mode, the following must be done before data transfer can be started: 1. setting input/output pins 2 . setting the interface mode 3. setting the transfer mode 4. setting the input clock 5 . setting the retransmit count for error recovery and time guard function 6 . setting the receive fifo level 7. setting interrupt/idma/hsdma the following describes how to set each of the above. for details on interrupt/dma settings, refer to section v. 1.7, serial interface interrupts and dma. note : always make sure the serial interface is inactive (txen1 (d 7 /0x300b13) and rxen1 (d 6 / 0x300b13) = 0) before making these settings. a change in settings during operation may result in a malfunction. ? txen1 : serial i/f ch.1 transmit enable bit in the serial i/f ch.1 control register (d7/0x300b13) ? rxen1 : serial i/f ch.1 receive enable bit in the serial i/f ch.1 control register (d6/0x300b13) setting input/output pins in iso 7816 mode, three pins sin1, sout 1 , and #sclk1 are used. configure the port function select registers to enable these pin functions. for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. setting the interface mode set 7816md1[1:0 ] (d[1:0]/0x300b1 a) to 0b10 when t = 1 protocol is used or 0b01 when t = 0 protocol is used. ? 7816md1[1:0] : serial i/f ch.1 iso7816 mode select bits in the serial i/f ch.1 iso7816 mode control register (d[1:0]/0x300b1a) setting the transfer mode use smd 1[1:0 ] (d[1:0]/0x300b13 ) to set the transfer mode of the serial interface as described earlier. when performing asynchronous transfer, set smd 1[1:0 ] to 0b11 , when performing clock synchronized transfer, set smd1[1:0] to 0b00. ? smd1[1:0] : serial i/f ch.1 transfer mode select bits in the serial i/f ch.1 control register (d[1:0]/0x300b13) setting the input clock this mode operates using the internal clock generated by the baud-rate timer. setup the ch. 1 baud-rate timer according to the transfer rate. for how to control the baud-rate timer, see section v. 1.2, baud-rate timer (set - ting baud rate). asynchronous transfer the transfer rate in iso 7816 mode is expressed by the following equation: d bps = f sio_clk f bps: bit rate (bits/second) d: bit rate adjustment value 1, 2, 4, 8, 16, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 f: clock frequency divide value 372 (5 mhz), 558 (6 mhz), 744 (8 mhz), 1116 (12 mhz), 1488 (16 mhz), 1860 (20 mhz), 512 (5 mhz), 768 (7.5 mhz), 1024 (10 mhz), 1536 (15 mhz), 2048 (20 mhz) ( ) indicates the maximum output clock frequency. f sio_clk : iso 7816 clock frequency (baud-rate timer output, which is also output from the #sclk1 pin to clock a card)
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-30 epson s1c33e08 technical manual the sampling clock frequency for asynchronous transfer is expressed by the following equation: d 1 f sampl = f sio_clk f divmd f sampl : sampling clock frequency divmd: divide ratio internally used by the serial interface ( 1/16 or 1/8, selected with divmd1) use fidi 1[13:0 ] (d[5:0]/0x300b1 d, d[7:0]/0x300b1 c) and divmd1 (d4/0x300b14 ) to set up the sampling clock. ? fidi1[13:0] : serial i/f ch.1 iso7816 mode fi/di ratio setup bits in the serial i/f ch.1 iso7816 mode fi/di ratio registers (d[5:0]/0x300b1d, d[7:0]/0x300b1c) ? divmd1 : serial i/f ch.1 clock division ratio select bit in the serial i/f ch.1 irda register (d4/0x300b14) divmd is set to 1/16 when 0 is written to divmd1 (d4/0x300b14) or 1/8 when 1 is written. fidi 1[13:0 ] (d[5:0]/0x300b1 d, d[7:0]/0x300b1 c) should be set to f divmd / d - 1 . tables v.1.6.2.1 and v. 1.6.2.2 list the values that can be set to fidi1[13:0] (d[5:0]/0x300b1d, d[7:0]/0x300b1c). table v. 1.6.2.1 fidi1[13:0 ] set values (divmd = 1/8) f/(d 8) -1 d f 372 558 744 1116 1488 1860 512 768 1024 1536 2048 1 46 69 92 139 185 232 63 95 127 191 255 2 22 34 46 69 92 115 31 47 63 95 127 4 11 16 22 34 46 57 15 23 31 47 63 8 5 8 11 16 22 28 7 11 15 23 31 16 2 3 5 8 11 14 3 5 7 11 15 1/2 92 139 185 278 371 464 127 191 255 383 511 1/4 185 278 371 557 743 929 255 383 511 767 1023 1/8 371 557 743 1115 1487 1859 511 767 1023 1535 2047 1/16 743 1115 1487 2231 2975 3719 1023 1535 2047 3071 4095 1/32 1487 2231 2975 4463 5951 7439 2047 3071 4095 6143 8191 1/64 2975 4463 5951 8927 11903 14879 4095 6143 8191 12287 16383 table v. 1.6.2.2 fidi1[13:0 ] set values (divmd = 1/16) f/(d 16) -1 d f 372 558 744 1116 1488 1860 512 768 1024 1536 2048 1 22 34 46 69 92 115 31 47 63 95 127 2 11 16 22 34 46 57 15 23 31 47 63 4 5 8 11 16 22 28 7 11 15 23 31 8 2 3 5 8 11 14 3 5 7 11 15 16 0 1 2 3 5 6 1 2 3 5 7 1/2 46 69 92 139 185 232 63 95 127 191 255 1/4 92 139 185 278 371 464 127 191 255 383 511 1/8 185 278 371 557 743 929 255 383 511 767 1023 1/16 371 557 743 1115 1487 1859 511 767 1023 1535 2047 1/32 743 1115 1487 2231 2975 3719 1023 1535 2047 3071 4095 1/64 1487 2231 2975 4463 5951 7439 2047 3071 4095 6143 8191 for receiving serial data clk (=sio_clk f / d) sampling clock sampling of start bit start bit d0 1 8 1 8 8 clk 16 clk sampling of d0 bit figure v. 1.6.2.1 sampling clock for asynchronous receive operation (when 1/16 division is selected) each bit data is sampled in the timing shown in figure v. 1.6.2.1.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 when the sin 1 input signal is detected as a low level at the rising edge of clk, sampling for the start bit is performed 8 clk (4 clk when 1/8 division is selected) after that point. if a low level is not detected in the sampling for the start bit, the interface aborts the subsequent samplings and returns to the start bit detection phase (in this case no error occurs). when the sin 1 input signal is low at the start bit sampling, subsequent bit data is sampled in 16 clk cycles (8 clk cycles when 1/8 division is selected). for transmitting clk (=sio_clk f / d) sampling clock serial data start bit d0 1 8 16 16 clk figure v. 1.6.2.2 sampling clock for asynchronous transmit operation (when 1/16 division is selected) during transmission, each bit data is output from the sout 1 pin in 16 clk cycles (8 clk cycles when 1/8 division is selected). clock synchronized transfer the transfer rate in iso 7816 mode clock synchronized transfer can be calculated similar to the asynchronous transfer. note, however, that divmd equals 1 (not 1/16 or 1/8 ) in clock synchronized transfer regardless of how divmd 1 is set. setting the retransmit count for error recovery (t = 0 protocol) the t = 0 protocol allows retransmission of data when an error occurs in data transmission (when the receiver returns nack). retransmission can be repeated if the error occurs successively, and rpnum 1[2:0 ] (d[7:5]/ 0x300b1 a) is used to set the retransmit count. a maximum of seven retransmissions may be specified. when rpnum1[2:0] (d[7:5]/0x300b1a) is set to 0 , this interface does not retransmit data even if a transmit error oc - curs. when a transmit error occurs in t = 1 protocol mode, this interface does not retransmit data regardless of how rpnum1[2:0] (d[7:5]/0x300b1a) is set. ? rpnum1[2:0] : serial i/f ch.1 number of transmit repetition setup bits in the serial i/f ch.1 iso7816 mode control register (d[7:5]/0x300b1a) setting the time guard function the iso 7816 mode supports a time guard function that inserts an idle time between characters during transmis - sion. the idle time to be inserted can be specified in etu (bit cycle) units using ttgr 1 [ 7 : 0 ] (d[ 7 : 0 ]/ 0 x 300 b 1 e). when ttgr 1[7:0 ] (d[7:0]/0x300b1 e) is set to 0 , no idle time is inserted. when a value other than 0 is set, the sout1 output is fixed at high for the specified etu period after a stop bit is output. this high output period is regarded as a long stop bit. ? ttgr1[7:0] : serial i/f ch.1 transmit time guard setup bits in the serial i/f ch.1 transmit time guard register (d[7:0]/0x300b1e) setting the receive fifo level (advanced mode) this serial interface incorporates a 4 -byte receive fifo allowing up to 4 bytes of data that can be received with - out an error even when the receive data register is not read. this serial interface can generate a receive-buffer full interrupt when the specified number of data are received in the receive fifo. use fifoint 1[1:0 ] (d[6:5]/ 0x300b14 ) to set this number of data. writing 0C3 to fifoint1[1:0 ] (d[6:5]/0x300b14 ) sets the number of data to 1C4 . the default setting at initial reset is 0 so that a receive-buffer full interrupt will generate when one data is received. ? fifoint1[1:0] : serial i/f ch.1 receive buffer full interrupt timing select bits in the serial i/f ch.1 irda register (d[6:5]/0x300b14)
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-32 epson s1c33e08 technical manual v. 1.6.3 control and operation of iso7816 mode transmit control (1 ) clock output first, start clock output in the following procedure: 1 . set clkol1 (d3/0x300b1a) to 1 (forced low output is released). 2 . set clkoen1 (d4/0x300b1a) to 1 (clock output begins). ? clkol1 : serial i/f ch.1 clock output forced low bit in the serial i/f ch.1 iso7816 mode control register (d3/0x300b1a) ? clkoen1 : serial i/f ch.1 clock output enable bit in the serial i/f ch.1 iso7816 mode control register (d4/0x300b1a) the clock for asynchronous transfer is output in synchronizati on with the sampling clock. sio_clk (baud-rate timer output) (internal clock) sampling clock clkol1 clkoen1 clock output enable #sclk1 output figure v. 1.6.3.1 clock output control (example in asynchronous mode) (2 ) enabling transmit operation use the transmit-enable bit txen 1 (d7/0x300b13) for transmit control. when transmit is enabled by writing 1 to this bit, the clock input to the shift register is enabled (ready for in - put), thus allowing data to be transmitted. transmit is disabled and the transmit data buffer (fifo) is cleared by writing 0 to txen1 (d7/0x300b13). ? txen1 : serial i/f ch.1 transmit enable bit in the serial i/f ch.1 control register (d7/0x300b13) note : do not set txen1 (d7/0x300b13) to 0 during a transmit operation. (3 ) transmit procedure the serial interface contains a transmit shift register and a transmit data register, which are provided indepen - dently of those used for a receive operation. transmit data is written to txd 1[7:0] (d[7:0]/0x300b10). ? txd1[7:0] : serial i/f ch.1 transmit data bits in the serial i/f ch.1 transmit data register (d[7:0]/0x300b10) the data written to txd 1[7:0] (d[7:0]/0x300b10 ) enters the transmit data buffer and waits for transmission. the transmit data buffer is a 2 -byte fifo and up to two data can be written to it successively if empty. older data will be transmitted first and cleared after transmission. the next transmit data can be written to the trans - mit data register, even during data transmission. the transmit data buffer status flag tdbe 1 (d1/0x300b12 ) is provided to check whether this buffer is full or not. this flag is set to 1 when the transmit data buffer has a free space for transmit data to be written and reset to 0 when the transmit data buffer becomes full by writing trans - mit data. ? tdbe1 : serial i/f ch.1 transmit data buffer empty flag in the serial i/f ch.1 status register (d1/0x300b12)
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 the serial interface starts transmitting when data is written to the transmit data register. the transfer status can be checked using the transmit-completion flag tend 1 (d5/0x300b12 ). this flag goes 1 when data is being transmitted and goes 0 when the transmission has completed. ? tend1 : serial i/f ch.1 transmit-completion flag in the serial i/f ch.1 status register (d5/0x300b12) when all the data in the transmit data buffer are transferred, a cause of the transmit-data empty interrupt occurs. since an interrupt can be generated as set by the interrupt controller, the next piece of transmit data can be written using an interrupt processing routine. in addition, since this cause of interrupt can be used to invoke dma, the data prepared in memory can be transmitted successively to the transmit-data register through dma transfers. for details on how to control interrupts and dma requests, refer to section v. 1.7, serial interface interrupts and dma. figures v. 1.6.3.2 to v.1.6.3.4 show transmit timing charts in iso7816 mode. s1 s2 p start bit stop bit parity bit transmit-buffer empty interrupt request timing time guard s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 synchronous clock ( cloc k-synchroniz ed mode ) sampling clock (asynchronous mode) sout1 figure v. 1.6.3.2 transmit timing chart in iso7816 (t = 1) mode (lsb first, time guard = 2) transmit-buffer empty interrupt request timing s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 s1 s2 p start bit stop bit parity bit synchronous clock ( cloc k-synchroniz ed mode ) sampling clock (asynchronous mode) sout1 figure v. 1.6.3.3 transmit timing chart in iso7816 (t = 0) mode (lsb first, time guard = 0 , no parity error occurred) s1 s2 p er start bit stop bit parity bit error signal from receiver (nack) transmit-buffer empty interrupt request timing retransmit data s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 d2 d3 d4 d5 d6 d7 p s1 d0 s1 d0 d1 er s2 synchronous clock ( cloc k-synchroniz ed mode ) sampling clock (asynchronous mode) sout1 figure v. 1.6.3.4 transmit timing chart in iso7816 (t = 0) mode (lsb first, time guard = 0 , parity error occurred) 1 . the data line (sout1) in idle state is set into high-impedance (pulled up to high). 2 . the contents of the data buffer are transferred to the shift register synchronously with the first falling edge of the clock. at the same time, the sout 1 pin is setting to a low level to send the start bit. 3 . each bit of data in the shift register is transmitted at each falling edge of the subsequent clock. 4 . after sending the 8 th data bit, the parity bit and the stop bit are transmitted in succession. then sout1 is set into high-impedance state (pulled up to high). 5 . the interface idles for a time guard period after sending a stop bit if the time guard period is set. 6 . the next data transfer begins if the transmit data buffer contains other data. 7 . if a parity error occurs in the receiver when data is being transferred in t = 0 mode, the receiver returns a low-level error signal (nack). the interface transmits the same data again when the retransmit count for error recovery has been set. in t = 1 mode, the receiver does not return an error signal even if an error occurs in the receiver.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-34 epson s1c33e08 technical manual (4 ) terminating transmit operations when data transmission is completed, write 0 to the transmit-enable bit txen1 (d7/0x300b13 ) to disable transmit operations. this operation clears (initializes) the transmit data buffer (fifo), therefore, make sure that the transmit data buffer does not contain any data waiting for transmission before writing 0 to txen1 (d7/0x300b13). to disable clock output, first reset clkoen 1 (d4/0x300b1a) to 0 and then clkol1 (d3/0x300b1a) to 0. receive control (1 ) clock output start clock output in the following procedure if it is disabled: 1 . set clkol1 (d3/0x300b1a) to 1 (forced low output is released). 2 . set clkoen1 (d4/0x300b1a) to 1 (clock output begins). ? clkol1 : serial i/f ch.1 clock output forced low bit in the serial i/f ch.1 iso7816 mode control register (d3/0x300b1a) ? clkoen1 : serial i/f ch.1 clock output enable bit in the serial i/f ch.1 iso7816 mode control register (d4/0x300b1a) (2 ) enabling receive operations use the receive-enable bit rxen 1 (d6/0x300b13 ) for receive control. when receiving enabled by writing 1 to this bit, clock input to the shift register is enabled (ready for input), meaning that it is ready to receive data. receive operations are disabled and the receive data buffer (fifo) is cleared by writing 0 to rxen1 (d6/0x300b13). ? rxen1 : serial i/f ch.1 receive enable bit in the serial i/f ch.1 control register (d6/0x300b13) note : do not set rxen1 (d6/0x300b13) to 0 during a receive operation. (3 ) receive procedure this serial interface has a receive shift register, receive data buffer and a receive data register that are provided independently of those used for transmit operations. the received data enters the received data buffer. the receive data buffer is a 4 -byte fifo and can receive data until it becomes full unless the received data is not read out. the received data in the buffer can be read by accessing rxd 1[7:0 ] (d[7:0]/0x300b11 ). the older data is out - put first and cleared by reading. ? rxd1[7:0] : serial i/f ch.1 receive data bits in the serial i/f ch.1 receive data register (d[7:0]/0x300b11) the number of data in the receive data buffer can be checked by reading rxd 1num[1:0 ] (d[7:6]/0x300b12). when rxd 1 num[1:0 ] (d[7:6 ]/0x300b12 ) is 0 , the buffer contains 0 or 1 data. when rxd1 num[1:0] (d[7:6]/0x300b12) is 1C3 , the buffer contains 2C4 data. ? rxd1num[1:0] : number of ch.1 receive data in fifo in the serial i/f ch.1 status register (d[7:6]/0x300b12) furthermore, rdbf 1 (d0/0x300b12 ) is provided for indicating whether the receive data buffer is empty or not. this flag is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data. ? rdbf1 : serial i/f ch.1 receive data buffer full flag in the serial i/f ch.1 status register (d0/0x300b12) when the receive data buffer has received the specified number or more data (one in standard mode or one to four in advanced mode), a cause of the receive-buffer full interrupt occurs. since an interrupt can be generated as set by the interrupt controller, the received data can be read by an interrupt processing routine. in addition, since this cause of interrupt can be used to invoke dma, the received data can be received successively in loca - tions prepared in memory through dma transfers. for details on how to control interrupts/dma, refer to section v. 1.7, serial interface interrupts and dma.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 figures v. 1.6.3.5 to v.1.6.3.7 show receive timing charts in iso7816 mode. s1 s2 start bit stop bit p a parity bit first data is read. receive-buffer full interrupt request (fifoint1[1:0] = 2) overrun error interrupt request synchronous clock ( cloc k-synchroniz ed mode ) sampling clock (asynchronous mode) sin1 receive data buffer rxd1num[1:0] rdbf1 data 1 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 data 2 data 3 data 4 data 5 data 6 a data 1 1, 2 2, 3, 4, 5 2, 3, 4 1, 2, 3 2, 3 1 3 2 2 1 0 figure v. 1.6.3.5 receive timing chart in iso7816 (t = 1) mode (lsb first) s1 s2 p start bit stop bit parity bit receive-buffer full/overrun error interrupt request timing s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 synchronous clock ( cloc k-synchroniz ed mode ) sampling clock (asynchronous mode) sin1 figure v. 1.6.3.6 receive timing chart in iso7816 (t = 0 ) mode (lsb first, no parity error occurred) s1 s2 p er start bit stop bit parity bit error signal to transmitter (nack) receive-buffer full/ overrun error interrupt request timing synchronous clock ( cloc k-synchroniz ed mode ) sampling clock (asynchronous mode) sin1 s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 d2 d3 d4 d5 d6 d7 p s1 d0 s1 d0 d1 er s2 figure v. 1.6.3.7 receive timing chart in iso7816 (t = 0 ) mode (lsb first, parity error occurred) 1 . the serial interface in asynchronous mode starts sampling when the start bit is input (sin1 = low). the serial interface in clock synchronized mode starts sampling at the first rising edge of the synchronous clock. 2 . when the start bit is sampled at the first rising edge of the sampling clock, each bit of receive data is taken into the shift register at each rising edge of the subsequent clock. this operation is repeated until the 8th data is received. 3 . when the 8 th data bit is taken in, the parity bit that follows is also taken in. 4 . when the stop bit is sampled, the data in the shift register is transferred to the receive data register, enabling the data to be read out. the parity is checked when data is transferred to the receive data register. 5 . if a parity error occurs in t = 0 mode, the interface returns a low-level error signal (nack) to the transmit - ter. in t = 1 mode, the interface does not return an error signal even if a parity error occurs.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-36 epson s1c33e08 technical manual (4 ) receive errors three types of receive errors can be detected when receiving data in iso 7816 mode. since an interrupt can be generated by setting the interrupt controller, the error can be processed using an inter - rupt processing routine. for details on receive error interrupts, refer to section v. 1.7, serial interface interrupts and dma. ? parity error in iso 7816 mode, the parity is checked when data is received. this parity check is performed when the data received in the shift register is transferred to the receive data buf - fer. in t = 1 mode, if any nonconformity between the received data and parity bit is found in this check, a parity er - ror is assumed and the parity error flag per1 (d3/0x300b12) is set to 1. ? per1 : serial i/f ch.1 parity error flag in the serial i/f ch.1 status register (d3/0x300b12) even when this error occurs, the received data in error is transferred to the receive data buffer and the receive operation is continued in t= 1 mode. however, the content of the received data for which a parity error is flagged cannot be guaranteed. in t = 0 mode, the received data in error is not loaded to the receive data buffer and a parity error cannot be de - tected. the parity error flag per 1 (d3/0x300b12) will not be set to 1. per 1 (d3/0x300b12) is reset to 0 by writing 0. as described above, if a parity error occurs in t = 0 mode, the interface returns a low-level error signal (nack) to the transmitter (see figure v. 1.6.3.7). in t = 1 mode, the interface does not return an error signal even if a parity error occurs. ? framing error (asynchronous mode) if data with a stop bit = 0 is received, the serial interface assumes that the data is out of synchronization and generates a framing error. if two stop bits are used, only the first stop bit is checked. when this error occurs, the framing-error flag fer 1 (d4/0x300b12) is set to 1. ? fer1 : serial i/f ch.1 framing error flag in the serial i/f ch.1 status register (d4/0x300b12) even when this error occurs, the received data in error is transferred to the receive data buffer and the receive operation is continued. however, the content of the received data for which a framing error is flagged cannot be guaranteed, even if no framing error is found in the following data received. fer 1 (d4/0x300b12) is reset to 0 by writing 0. ? overrun error even when the receive data buffer is full ( 4 data have been received), the next (5 th) data can be received into the shift register. if there is no space in the buffer (data has not been read) when the 5 th data has been received, the 5 th data in the shift register cannot be transferred to the buffer. if one more (6 th) data is transferred to this serial interface, the shift register ( 5 th data) is overwritten with the 6 th data and an overrun error is generated. when an overrun error is generated, the overrun error flag oer 1 (d 2 / 0 x 300 b 12 ) is set to 1. ? oer1 : serial i/f ch.1 overrun error flag in the serial i/f ch.1 status register (d2/0x300b12) even when this error occurs, the receive operation is continued. oer 1 (d2/0x300b12) is reset to 0 by writing 0. (5 ) terminating receive operation when a data receive operation is completed, write 0 to the receive-enable bit rxen 1 (d 6/ 0 x 300 b 13 ) to disable receive operations. this operation clears (initializes) the receive data buffer (fifo), therefore, make sure that there is no data that has not been read in the receive data buffer before setting rxen 1 (d6/0x300b13) to 0. to disable clock output, first reset clkoen 1 (d4/0x300b1a) to 0 and then clkol1 (d3/0x300b1a) to 0.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 1.7 serial interface interrupts and dma the serial interface can generate the following three types of interrupts in each channel: ? transmit-buffer empty interrupt ? receive-buffer full interrupt ? receive-error interrupt transmit-buffer empty interrupt this cause of interrupt occurs when the transmit data set in t he transmit data register is transferred to the shift reg - ister, in which case the cause-of-interrupt flag fstx x is set to 1 . at this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the cpu is generated. occurrence of this cause of interrupt indicates that the next transmit data can be written to the transmit data register. this cause of interrupt can also be used to invoke idma, enabling transmit data to be written to the register by means of a dma transfer. receive-buffer full interrupt this cause of interrupt occurs when the number of data specified with fifoint x[1:0 ] (d[6:5]/0x300b x4 ) (one data in standard mode) has been received in the receive data buffer, in which case the cause-of-interrupt flag fsrx x is set to 1 . at this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the cpu is generated. occurrence of this cause of interrupt indicates that the received data can be read out. this cause of interrupt can also be used to invoke idma, enabling the received data to be written into specified memory locations by means of a dma transfer. ? fifoint x [1:0] : serial i/f ch. x receive buffer full interrupt timing select bits in the serial i/f ch. x irda register (d[6:5]/0x300b x 4) receive-error interrupt this cause of interrupt occurs when a parity, framing, or overrun error is detected during data reception, or when a transmit error is detected during data transmission in iso 7816 t = 0 mode, in which case the cause-of- interrupt flag fserr x is set to 1 . at this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the cpu is generated. since all four types of errors generate the same cause of interrupt, check the error flags per x (parity error), oer x (overrun error), fer x (framing error), and ter1 (transmit error flag) to identify the type of error that has occurred. in the clock-synchronized mode, parity and frami ng errors do not occur. ? per x : serial i/f ch. x parity error flag in the serial i/f ch. x status register (d3/0x300b x 2) ? oer x : serial i/f ch. x overrun error flag in the serial i/f ch. x status register (d2/0x300b x 2) ? fer x : serial i/f ch. x framing error flag in the serial i/f ch. x status register (d4/0x300b x 2) ? ter1 : serial i/f ch.1 iso7816 transmit error flag in the serial i/f ch.1 iso7816 mode status register (d0/0x300b1b) note : if a receive error (parity or framing error) occurs, the receive-error interrupt and receive-buffer full interrupt causes occur simultaneously. however, since the receive-error interrupt has priority over the receive-buffer full interrupt, the receive-error interrupt is processed first. it is therefore neces - sary for the receive-buffer full interrupt cause flag be cleared through the use of the receive-error interrupt processing routine.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-38 epson s1c33e08 technical manual control registers of the interrupt controller table v. 1.7.1 shows the interrupt controller's control registers provided for each interrupt source (channel). table v. 1.7.1 control register of interrupt controller cause of interrupt receiv e-error receiv e-b uff er full tr ansmit-b uff er empty receiv e-error interr upt receiv e-b uff er full tr ansmit-b uff er empty receiv e-error receiv e-b uff er full tr ansmit-b uff er empty channel ch.0 ch.1 ch.2 cause-of-interrupt fla g fserr0(d0/0x300286) fsrx0(d1/0x300286) fstx0(d2/0x300286) fserr1(d3/0x300286) fsrx1(d4/0x300286) fstx1(d5/0x300286) fserr2(d0/0x300289) fsrx2(d1/0x300289) fstx2(d2/0x300289) interrupt priority register psio0[2:0](d[6:4]/0x300269) psio1[2:0](d[2:0]/0x30026a) psio2[2:0](d[2:0]/0x30026e) interrupt enable register eserr0(d0/0x300276) esrx0(d1/0x300276) estx0(d2/0x300276) eserr1(d3/0x300276) esrx1(d4/0x300276) estx1(d5/0x300276) eserr2(d0/0x300279) esrx2(d1/0x300279) estx2(d2/0x300279) when a cause of interrupt described above occurs, the corresponding cause-of-interrupt flag is set to 1 . if the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit for that cause of interrupt set to 0 . the cause-of-interrupt flag is set to 1 whenever interrupt conditions are met, regardless of the setting of the interrupt enable register (even if it is set to 0). the interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7 . an interrupt request to the cpu is accepted only when no other interrupt request of a higher priority has been generated. in addition, only when the psr's ie bit = 1 (interrupts enabled) and the set value of the il is smaller than the input interrupt level set by the interrupt priority register, will the input interrupt request actually be ac - cepted by the cpu. for details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to section iii.2, interrupt controller (itc). intelligent dma the receive-buffer full interrupt and transmit-buffer empty interrupt causes can be used to invoke intelligent dma (idma). this enables successive transmit/receive operations between memory and the transmit/receive- buffer to be performed by means of a dma transfer. the following shows the idma channel numbers set for each cause of interrupt: idma ch. ch. 0 receive-buffer full interrupt: 0x17 ch. 0 transmit-buffer empty interrupt: 0x18 ch. 1 receive-buffer full interrupt: 0x19 ch. 1 transmit-buffer empty interrupt: 0x1a ch. 2 receive-buffer full interrupt: 0x22 ch. 2 transmit-buffer empty interrupt: 0x23 the idma request and enable bits shown in table v. 1.7.2 must be set to 1 for idma to be invoked. transfer conditions, etc. on the idma side must also be set in advance. table v. 1.7.2 control bits for idma transfer cause of interrupt receiv e-b uff er full tr ansmit-b uff er empty receiv e-b uff er full tr ansmit-b uff er empty receiv e-b uff er full tr ansmit-b uff er empty channel ch.0 ch.1 ch.2 idma request bit rsrx0(d6/0x300292) rstx0(d7/0x300292) rsrx1(d0/0x300293) rstx1(d1/0x300293) rsrx2(d2/0x30029b) rstx2(d3/0x30029b) idma enable bit desrx0(d6/0x300296) destx0(d7/0x300296) desrx1(d0/0x300297) destx1(d1/0x300297) desrx2(d2/0x30029c) destx2(d3/0x30029c) if a cause of interrupt occurs when the idma request and enable bits are set to 1 , idma is invoked. no inter - rupt request is generated at that point. an interrupt request is generated upon completion of the dma transfer. the bits can also be set so as not to generate an interrupt, with only a dma transfer performed. for details on dma transfer and how to control interrupts upon completion of dma transfer, refer to section ii.2, intelligent dma (idma).
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 high-speed dma the receive-buffer full interrupt and transmit-buffer empty interrupt causes can also invoke high-speed dma (hsdma). the following shows the hsdma channel number and trigger set-up bit corresponding to each channel: table v. 1.7.3 hsdma trigger set-up bits sif channel 0 1 2 hsdma channel 0 1 2 t rigger set-up bits hsd0s[3:0] (d[3:0]) / hsdma ch.0C1 tr igger set-up register (0x300298) hsd1s[3:0] (d[7:4]) / hsdma ch.0C1 tr igger set-up register (0x300298) hsd2s[3:0] (d[3:0]) / hsdma ch.2C3 tr igger set-up register (0x300299) for hsdma to be invoked by a cause of receive-buffer full interrupt, the trigger set-up bits should be set to 1010. for hsdma to be invoked by a cause of transmit-buffer empty interrupt, the trigger set-up bits should be set to 1011. transfer conditions, etc. must also be set on the hsdma side. the hsdma channel is invoked through generation of the cause of interrupt. for details on hsdma transfer, refer to section ii. 1, high-speed dma (hsdma). trap vectors the trap-vector address of each default cause of interrupt is set as follows: ch. 0 receive-error interrupt: 0xc000e0 ch. 0 receive-buffer full interrupt: 0xc000e4 ch. 0 transmit-buffer empty interrupt: 0xc000e8 ch. 1 receive-error interrupt: 0xc000f0 ch. 1 receive-buffer full interrupt: 0xc000f4 ch. 1 transmit-buffer empty interrupt: 0xc000f8 ch. 2 receive-error interrupt: 0xc00130 ch. 2 receive-buffer full interrupt: 0xc00134 ch. 2 transmit-buffer empty interrupt: 0xc00138 the base address of the trap table can be changed using the ttbr register.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-40 epson s1c33e08 technical manual v. 1.8 details of control registers table v. 1.8.1 list of serial interface registers address 0x00300b00 0x00300b01 0x00300b02 0x00300b03 0x00300b04 0x00300b05 0x00300b06 0x00300b07 0x00300b08 0x00300b09 0x00300b10 0x00300b11 0x00300b12 0x00300b13 0x00300b14 0x00300b15 0x00300b16 0x00300b17 0x00300b18 0x00300b19 0x00300b1a 0x00300b1b 0x00300b1c 0x00300b1d 0x00300b1e 0x00300b1f 0x00300b20 0x00300b21 0x00300b22 0x00300b23 0x00300b24 0x00300b25 0x00300b26 0x00300b27 0x00300b28 0x00300b29 0x00300b4f function ch.0 transmit data ch.0 receive data ch.0 transfer/error status sets ch.0 transfer mode and controls transfer. sets ch.0 asynchronous/irda mode. controls ch.0 baud-rate timer. ch.0 baud-rate timer reload data low-order 8 bits ch.0 baud-rate timer reload data high-order 4 bits ch.0 baud-rate timer count data low-order 8 bits ch.0 baud-rate timer count data high-order 4 bits ch.1 transmit data ch.1 receive data ch.1 transfer/error status sets ch.1 transfer mode and controls transfer. sets ch.1 asynchronous/irda mode. controls ch.1 baud-rate timer. ch.1 baud-rate timer reload data low-order 8 bits ch.1 baud-rate timer reload data high-order 4 bits ch.1 baud-rate timer count data low-order 8 bits ch.1 baud-rate timer count data high-order 4 bits sets ch.1 iso7816 mode and controls clock output. ch.1 iso7816 error status ch.1 iso7816 fi/di ratio low-order 8 bits ch.1 iso7816 fi/di ratio high-order 6 bits sets ch.1 transmit time guard function. sets number of output clocks for ch.1 iso7816 mode. ch.2 transmit data ch.2 receive data ch.2 transfer/error status sets ch.2 transfer mode and controls transfer. sets ch.2 asynchronous/irda mode. controls ch.2 baud-rate timer. ch.2 baud-rate timer reload data low-order 8 bits ch.2 baud-rate timer reload data high-order 4 bits ch.2 baud-rate timer count data low-order 8 bits ch.2 baud-rate timer count data high-order 4 bits selects standard or advanced mode. register name serial i/f ch.0 transmit data register (pefsif0_txd) serial i/f ch.0 receive data register (pefsif0_rxd) serial i/f ch.0 status register (pefsif0_status) serial i/f ch.0 control register (pefsif0_ctl) serial i/f ch.0 irda register (pefsif0_irda) serial i/f ch.0 baud-rate timer control register (pefsif0_brtrun) serial i/f ch.0 baud-rate timer reload data register (lsb) (pefsif0_brtrdl) serial i/f ch.0 baud-rate timer reload data register (msb) (pefsif0_brtrdm) serial i/f ch.0 baud-rate timer count data register (lsb) (pefsif0_brtcdl) serial i/f ch.0 baud-rate timer count data register (msb) (pefsif0_brtcdm) serial i/f ch.1 transmit data register (pefsif1_txd) serial i/f ch.1 receive data register (pefsif1_rxd) serial i/f ch.1 status register (pefsif1_status) serial i/f ch.1 control register (pefsif1_ctl) serial i/f ch.1 irda register (pefsif1_irda) serial i/f ch.1 baud-rate timer control register (pefsif1_brtrun) serial i/f ch.1 baud-rate timer reload data register (lsb) (pefsif1_brtrdl) serial i/f ch.1 baud-rate timer reload data register (msb) (pefsif1_brtrdm) serial i/f ch.1 baud-rate timer count data register (lsb) (pefsif1_brtcdl) serial i/f ch.1 baud-rate timer count data register (msb) (pefsif1_brtcdm) serial i/f ch.1 iso7816 mode control register (pefsif1_7816ctl) serial i/f ch.1 iso7816 mode status register (pefsif1_7816sta) serial i/f ch.1 iso7816 mode fi/di ratio register (lsb) (pefsif1_fidil) serial i/f ch.1 iso7816 mode fi/di ratio register (msb) (pefsif1_fidim) serial i/f ch.1 transmit time guard register (pefsif1_ttgr) serial i/f ch.1 iso7816 mode output clock setup register (pefsif1_clknum) serial i/f ch.2 transmit data register (pefsif2_txd) serial i/f ch.2 receive data register (pefsif2_rxd) serial i/f ch.2 status register (pefsif2_status) serial i/f ch.2 control register (pefsif2_ctl) serial i/f ch.2 irda register (pefsif2_irda) serial i/f ch.2 baud-rate timer control register (pefsif2_brtrun) serial i/f ch.2 baud-rate timer reload data register (lsb) (pefsif2_brtrdl) serial i/f ch.2 baud-rate timer reload data register (msb) (pefsif2_brtrdm) serial i/f ch.2 baud-rate timer count data register (lsb) (pefsif2_brtcdl) serial i/f ch.2 baud-rate timer count data register (msb) (pefsif2_brtcdm) serial i/f std/adv mode select register (pefsif_adv) siz e 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 the following describes each serial interface control register. the serial interface control registers are mapped in the 8 -bit device area from 0x300b00 to 0x300b4 f, and can be accessed in units of bytes. note : when setting the serial interface control registers, be sure to write a 0, and not a 1, for all reserved bits.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b00C0x300b20: serial i/f ch. x transmit data registers (pefsif x _txd) name address register name bit function setting init. r/w remarks 0x0 to 0xff(0x7f) txd x 7 txd x 6 txd x 5 txd x 4 txd x 3 txd x 2 txd x 1 txd x 0 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch. x transmit data txd x 7( x 6) = msb txd x 0 = lsb x x x x x x x x r/w 7-bit asynchronous mode does not use txd x 7. 00300b00 | 00300b20 (b) serial i/f ch. x transmit data register (pefsif x _txd) note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x300b00 serial i/f ch.0 transmit data register (pefsif0_txd) 0x300b10 serial i/f ch.1 transmit data register (pefsif1_txd) 0x300b20 serial i/f ch.2 transmit data register (pefsif2_txd) d[7:0] txd x [7:0]: serial i/f ch. x transmit data bits sets transmit data. (default: indeterminate) when data is written to this register (transmit data buffer) after 1 is written to txen x , a transmit opera - tion is begun. the data written to txd x[7:0 ] enters the transmit data buffer and waits for transmission. the transmit data buffer is a 2 -byte fifo and up to two data can be written to it successively if empty. older data will be transmitted first and cleared after transmission. when all the data in the transmit data buffer are transferred, a cause of transmit-data empty interrupt occurs. in 7 -bit asynchronous mode, txd x7 (msb) is ignored. the serial-converted data is output from the sout x pin beginning with the lsb, in which the bits set to 1 are output as high-level signals and those set to 0 output as low-level signals. this register can be read as well as written.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-42 epson s1c33e08 technical manual 0x300b01C0x300b21: serial i/f ch. x receive data registers (pefsif x _rxd) name address register name bit function setting init. r/w remarks 0x0 to 0xff(0x7f) rxd x 7 rxd x 6 rxd x 5 rxd x 4 rxd x 3 rxd x 2 rxd x 1 rxd x 0 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch. x receive data rxd x 7( x 6) = msb rxd x 0 = lsb x x x x x x x x r 7-bit asynchronous mode does not use rxd x7 (fixed at 0). 00300b01 | 00300b21 (b) serial i/f ch. x receive data register (pefsif x _rxd) note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x300b01 serial i/f ch.0 receive data register (pefsif0_rxd) 0x300b11 serial i/f ch.1 receive data register (pefsif1_rxd) 0x300b21 serial i/f ch.2 receive data register (pefsif2_rxd) d[7:0] rxd x [7:0]: serial i/f ch. x receive data bits the data in the receive data buffer can be read from this register beginning with the oldest data first. the received data enters the receive data buffer. the receive data buffer is a 4 -byte fifo and can re - ceive data until it becomes full unless received data is not read out. when the buffer is full and also the shift register contains received data, an overrun error will occur if the received data is not read until the next data receiving begins. the receive buffer status flag rdbf x is provided to indicate that it is necessary to read the receive data buffer. this flag is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data. when the receive data buffer has received the number of data specified with fifoint x[1:0 ] (one data in standard mode), a cause of receive buffer full interrupt occurs. in 7-bit asynchronous mode, 0 is stored in rxd x7. the serial data input from the sin x pin is converted into parallel data beginning with the lsb, with the high-level signals changed to 1 s and the low-level signals changed to 0 s. the resulting data is stored in this buffer. this register is a read-only register, so no data can be written to it. (default: indeterminate)
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-43 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b02C0x300b22: serial i/f ch. x status registers (pefsif x _status) name address register name bit function setting init. r/w remarks rxd x num1 rxd x num0 tend x fer x per x oer x tdbe x rdbf x d7 d6 d5 d4 d3 d2 d1 d0 number of ch. x receive data in fifo ch. x transmit-completion flag ch. x framing error flag ch. x parity error flag ch. x overrun error flag ch. x transmit data buffer empty ch. x receive data buffer full 0 0 0 0 0 0 1 0 r r r/w r/w r/w r r reset by writing 0. 00300b02 | 00300b22 (b) 1 error 0 normal 1 transmittin g 0 end 1 error 0 normal 1 error 0 normal 1 empty 0 not empty 1 full 0 not full serial i/f ch. x status register (pefsi f x_status) 1 1 0 0 1 0 1 0 rxd xnum[1:0] number of data 4 3 2 1 or 0 note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x300b02 serial i/f ch.0 status register (pefsif0 _status) 0x300b12 serial i/f ch.1 status register (pefsif1 _status) 0x300b22 serial i/f ch.2 status register (pefsif2 _status) d[7:6] rxd x num[1:0]: number of ch. x receive data in fifo indicates the number of data in the receive data buffer (fifo) that have not been read. table v. 1.8.2 number of receive data rxd x num1 1 1 0 0 rxd x num0 1 0 1 0 number of data 4 3 2 1 or 0 (default: 0b00) when rxd xnum[1:0 ] is 0 , it indicates that the receive data buffer contains 0 or 1 received data. when rxd xnum[1:0] is 1 to 3 , it indicates that the receive data buffer contains 2 to 4 received data. d5 tend x : serial i/f ch. x transmit-completion flag indicates the transmission status. 1 (r): during transmitting 0 (r): end of transmission (default) tend x goes 1 when data is being transmitted and goes 0 when the transmission has completed. when data is transmitted successively in clock-synchronized master mode or asynchronous mode, tend x maintains 1 until all data is transmitted (see figure v.1.3.3.1 and figure v.1.4.3.1 ). in clock- synchronized slave mode, tend x goes 0 every time 1 -byte data is transmitted (see figure v.1.3.3.2). d4 fer x : serial i/f ch. x framing error flag indicates whether a framing error occurred. 1 (r): an error occurred 0 (r): no error occurred (default ) 1 (w): has no effect 0 (w): reset to 0 fer x is an error flag indicating whether a framing error occurred. when an error has occurred, it is set to 1 . a framing error occurs when data with a stop bit = 0 is received in iso7816 or asynchronous mode. fer x is reset by writing 0 or when rxen x and txen x both are set to 0.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-44 epson s1c33e08 technical manual d3 per x : serial i/f ch. x parity error flag indicates whether a parity error occurred. 1 (r): an error occurred 0 (r): no error occurred (default) 1 (w): has no effect 0 (w): reset to 0 per x is an error flag indicating whether a parity error occurred. when an error has occurred, it is set to 1 . parity checks are valid only in iso 7816 mode or asynchronous mode with epr x set to 1 (parity added). this check is performed when the received data is transferred from the shift register to the receive data buffer. per x is reset by writing 0 or when rxen x and txen x both are set to 0. d2 oer x : serial i/f ch. x overrun error flag indicates whether an overrun error occurred. 1 (r): an error occurred 0 (r): no error occurred (default) 1 (w): has no effect 0 (w): reset to 0 oer x is an error flag indicating whether an overrun error occurred. when an error has occurred, it is set to 1 . an overrun error will occur if a new data is transferred to this serial interface when the receive data buffer is full and also the shift register contains received data. when this error occurs, the shift register is overwritten with the new received data and the receive data in the buffer is maintained as is. oer x is reset by writing 0 or when rxen x and txen x both are set to 0. d1 tdbe x : serial i/f ch. x transmit data buffer empty flag indicates the status of the transmit data buffer. 1 (r): not full (default) 0 (r): buffer full tdbe x is set to 1 when the transmit data buffer has a free space for transmit data to be written and reset to 0 when the transmit data buffer becomes full by writing transmit data. up to two transmit data can be written to the transmit data buffer. d0 rdbf x : serial i/f ch. x receive data buffer full flag indicates the status of the receive data buffer. 1 (r): not empty 0 (r): buffer empty (default) rdbf x is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-45 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b03C0x300b23: serial i/f ch. x control registers (pefsif x _ctl) name address register name bit function setting init. r/w remarks txen x rxen x epr x pmd x stpb x ssck x smd x 1 smd x 0 d7 d6 d5 d4 d3 d2 d1 d0 ch. x transmit enable ch. x receive enable ch. x parity enable ch. x parity mode select ch. x stop bit select ch. x input clock select ch. x transfer mode select 11 10 01 00 smd x[1:0] transfer mode 8-bit asynchronous 7-bit asynchronous clock sync. slave clock sync. maste r 0 0 x x x x x x r/w r/w r/w r/w r/w r/w r/w valid only in asynchronous mode. 00300b03 | 00300b23 (b) 1 enabled 0 disabled 1 enabled 0 disabled 1 with parity 0 no parity 1 odd 0 even 1 2 bits 0 1 bit 1 #sclk x 0 internal clock serial i/f ch. x control register (pefsif x _ctl) note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x300b03 serial i/f ch.0 control register (pefsif0_ctl) 0x300b13 serial i/f ch.1 control register (pefsif1_ctl) 0x300b23 serial i/f ch.2 control register (pefsif2_ctl) d7 txen x : serial i/f ch. x transmit enable bit enables each channel for transmit operations. 1 (r/w): transmit enabled 0 (r/w): transmit disabled (default) when txen x for a channel is set to 1 , the channel is enabled for transmit operations. when txen x is set to 0, the channel is disabled for transmit operations. always make sure txen x = 0 before setting the transfer mode and other conditions. writing 0 to txen x clears the transmit data buffer (fifo) as well as disabling transmit operations. d6 rxen x : serial i/f ch. x receive enable bit enables each channel for receive operations. 1 (r/w): receive enabled 0 (r/w): receive disabled (default) when rxen x for a channel is set to 1 , the channel is enabled for receive operations. when rxen x is set to 0 , the channel is disabled for receive operations. always make sure rxen x = 0 before setting the transfer mode and other conditions. writing 0 to rxen x clears the receive data buffer (fifo) as well as disabling receive operations. d5 epr x : serial i/f ch. x parity enable bit selects a parity function for asynchronous transfer. (default: indeterminate) 1 (r/w): parity added 0 (r/w): no parity added epr x is used to select whether receive data is to be checked for parity, and whether a parity bit is to be added to transmit data. when epr x is set to 1 , the receive data is checked for parity. a parity bit is au - tomatically added to the transmit data. when epr x is set to 0 , parity is not checked and no parity bit is added. epr x is only effective in asynchronous mode. settings of epr x have no effect in clock-synchronized mode. in iso7816 mode, the parity function is always enabled no matter how epr x is set.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-46 epson s1c33e08 technical manual d4 pmd x : serial i/f ch. x parity mode select bit selects an odd or even parity for asynchronous transfer. (default: indeterminate) 1 (r/w): odd parity 0 (r/w): even parity odd parity is selected by writing 1 to pmd x , and even parity is selected by writing 0 . parity check and the addition of a parity bit are only effective in asynchronous transfers in which epr x is set to 1 . if epr x = 0, settings of pmd x do not have any effect. iso7816 mode supports even parity only. d3 stpb x : serial i/f ch. x stop-bit length select bit selects a stop-bit length for asynchronous transfer. (default: indeterminate) 1 (r/w): 2 bits 0 (r/w): 1 bit stpb x is only valid in asynchronous mode. two stop bits are selected by writing 1 to stpb x , and one stop bit is selected by writing 0 . the start bit is fixed at 1 bit. settings of stpb x are ignored in clock-synchronized mode. in iso 7816 mode, the stop-bit length is fixed at 2 bits for t = 0 protocol or 1 bit for t = 1 protocol. d2 ssck x : serial i/f ch. x input clock select bit selects the clock source for asynchronous transfer. (default: indeterminate) 1 (r/w): #sclk x (external clock) 0 (r/w): internal clock during operation in asynchronous mode, this bit is used to select the clock source between an internal clock (output from the baud-rate timer) and an external clock (input from the #sclk x pin). an external clock is selected by writing 1 to this bit, and an internal clock is selected by writing 0. d[1:0] smd x [1:0]: serial i/f ch. x transfer mode select bits sets the transfer mode of the serial interface as shown in table v. 1.8.3 below. table v. 1.8.3 setting of transfer mode smd x 1 1 1 0 0 smd x 0 1 0 1 0 t ransfer mode 8-bit asynchronous mode 7-bit asynchronous mode cloc k-synchroniz ed sla ve mode cloc k-synchroniz ed master mode (default: indeterminate) smd x[1:0] can be read as well as written. when using the irda interface, always be sure to set asynchronous mode for the transfer mode.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-47 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b04C0x300b24: serial i/f ch. x irda registers (pefsif x _irda) name address register name bit function setting init. r/w remarks srdyctl x fifoint x 1 fifoint x 0 divmd x irtl x irrl x irmd x 1 irmd x 0 d7 d6 d5 d4 d3 d2 d1 d0 ch. x #srdy control ch. x receive buffer full interrupt timing ch. x async. clock division ratio ch. x irda i/f output logic inversion ch. x irda i/f input logic inversion ch. x interface mode select 0 0 0 x x x x x r/w r/w r/w r/w r/w r/w writing is disabled when sioadv (d0/0x300b4f) = "0". valid only in asynchronous mode. 00300b04 | 00300b24 (b) 1 1/8 0 1/16 1 high mask 0 normal 1 inverted 0 direct 1 inverted 0 direct serial i/f ch. x irda register (pefsif x _irda) irmd x[1:0] i/f mode reserved irda 1.0 reserved general i/f 11 10 01 00 11 10 01 00 fifoint x[1:0] receive level 4 3 2 1 note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x300b04 serial i/f ch.0 irda register (pefsif0 _irda) 0x300b14 serial i/f ch.1 irda register (pefsif1 _irda) 0x300b24 serial i/f ch.2 irda register (pefsif2 _irda) d7 srdyctl x : serial i/f ch. x #srdy control bit selects a control method for the #srdy x signal. 1 (r/w): high mask mode 0 (r/w): normal output (default) when srdyctl x is set to 0 , the #srdy x signal is controlled normally and indicates ready to receive even if the receive data buffer is full. when srdyctl x is set to 1 , high-mask mode is selected. the following shows the #srdy x controls in clock-synchronized slave mode and master mode: clock-synchronizes slave mode when the receive data buffer is full, the #srdy x signal is forcibly fixed at high in order to suspend data transfer from the master device until the data in the buffer is read. clock-synchronized master mode when the receive data buffer is full, the #srdy x signal (low) from the slave device is ignored and the serial interface stops outputting the #sclk x signal until the buffer data is read. the high mask mode can avoid overrun errors. when the receive data buffer is not full, normal receive operations are performed even if this function is enabled. in asynchronous mode and iso 7816 mode, this bit is ignored as they do not use the #srdy x signal. note : this bit can be rewritten only when sioadv (d0/0x300b4f) is set to 1 (advanced mode). d[6:5] fifoint x [1:0]: serial i/f ch. x receive buffer full interrupt timing select bits sets the number of data in the receive data buffer to generate a receive-buffer full interrupt. table v. 1.8.4 number of receive data buffer fifoint x 1 1 1 0 0 fifoint x 0 1 0 1 0 receive le vel 4 3 2 1 (default: 0b00) writing 0C3 to fifoint x[1:0 ] sets the number of data to 1C4 . when the number of data in the receive data buffer reaches the number specified here, the receive-buffer full interrupt cause flag fsrx x are set to 1. note : this bit can be rewritten only when sioadv (d0/0x300b4f) is set to 1 (advanced mode).
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-48 epson s1c33e08 technical manual d4 divmd x : serial i/f ch. x clock division ratio select bit selects the division ratio of the sampling clock. (default: indeterminate) 1 (r/w): 1/8 0 (r/w): 1/16 select the division ratio necessary to generate the sampling clock for asynchronous or iso 7816 transfer. when divmd x is set to 1 , the sampling clock is generated from the input clock of the serial interface (output from the baud-rate timer or input from #sclk x ) by dividing it by 8 . when divmd x is set to 0, the input clock is divided by 16. d3 irtl x : serial i/f ch. x irda i/f output logic inversion bit inverts the logic of the irda output signal. (default: indeterminate) 1 (r/w): inverted 0 (r/w): not inverted when using the irda interface, set the logic of the sout x output signal to suit the infrared-ray com - munication circuit that is connected external to the chip. if irtl x is set to 1 , a high pulse is output when the output data = 0 (held low-level when the output data = 1 ). if irtl x is set to 0 , a low pulse is output when the output data = 0 (held high-level when the output data = 1). d2 irrl x : serial i/f ch. x irda i/f input logic inversion bit inverts the logic of the irda input signal. (default: indeterminate) 1 (r/w): inverted 0 (r/w): not inverted when using the irda interface, set the logic of the signal that is input from an external infrared-ray communication circuit to the chip to suit the serial interface. if irrl x is set to 1 , a high pulse is input as a logic 0. if irrl x is set to 0 , a low pulse is input as a logic 0. d[1:0] irmd x [1:0]: serial i/f ch. x interface mode select bits selects the irda interface function. table v. 1.8.5 irda interface setting irmd x 1 1 1 0 0 irmd x 0 1 0 1 0 interface mode do not set. (reser v ed) ird a 1.0 interf ace do not set. (reser v ed) nor mal interf ace (default: indeterminate) when using the irda interface function, write 0 b 10 to irmd x [ 1 : 0 ] while setting to asynchronous mode for the transfer mode. if the irda interface function is not to be used, write 0b00 to irmd x[1:0]. note : this selection must always be performed before the transfer mode and other conditions are set.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-49 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b05C0x300b25: serial i/f ch. x baud-rate timer control registers (pefsif x _brtrun) name address register name bit function setting init. r/w remarks C C brtrun x d7C1 d0 reserved baud-rate timer run/stop control C 0 C r/w 0 when being read. 00300b05 | 00300b25 (b) 1 run 0 stop serial i/f ch. x baud-rate timer control register (pefsi f x_brtrun) note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x300b05 serial i/f ch.0 baud-rate timer control register (pefsif0 _brtrun) 0x300b15 serial i/f ch.1 baud-rate timer control register (pefsif1 _brtrun) 0x300b25 serial i/f ch.2 baud-rate timer control register (pefsif2 _brtrun) d[7:1] reserved d0 brtrun x : baud-rate timer run/stop control bit controls the baud-rate timer s run/stop states. 1 (r/w): run 0 (r/w): stop (default) the baud-rate timer loads the reload data brtrd x [11:0 ] (0x300b x6C0x300b x7 ) to its counter and starts counting down when 1 is written to brtrun x . the baud-rate timer stops counting when 0 is written to brtrun x .
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-50 epson s1c33e08 technical manual 0x300b06C0x300b26: serial i/f ch. x baud-rate timer reload data regis - ters (lsb) (pefsif x _brtrdl) 0x300b07C0x300b27: serial i/f ch. x baud-rate timer reload data regis - ters (msb) (pefsif x _brtrdm) name address register name bit function setting init. r/w remarks 0x0 to 0xff (brtrd x [11:0] = 0x0 to 0xfff) brtrd x 7 brtrd x 6 brtrd x 5 brtrd x 4 brtrd x 3 brtrd x 2 brtrd x 1 brtrd x 0 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch. x baud-rate timer reload data [7:0] 0 0 0 0 0 0 0 0 r/w 00300b06 | 00300b26 (b) serial i/f ch. x baud-rate timer reload data register (lsb) (pefsif x _brtrdl) C 0x0 to 0xf (brtrd x [11:0] = 0x0 to 0xfff) C brtrd x 11 brtrd x 10 brtrd x 9 brtrd x 8 d7C4 d3 d2 d1 d0 reserved serial i/f ch. x baud-rate timer reload data [11:8] C 0 0 0 0 C r/w 0 when being read. 00300b07 | 00300b27 (b) serial i/f ch. x baud-rate timer reload data register (msb) (pefsif x_brtrdm) note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x300b06 serial i/f ch.0 baud-rate timer reload data register (lsb) (pefsif0 _brtrdl) 0x300b07 serial i/f ch.0 baud-rate timer reload data register (msb) (pefsif0 _brtrdm) 0x300b16 serial i/f ch.1 baud-rate timer reload data register (lsb) (pefsif1 _brtrdl) 0x300b17 serial i/f ch.1 baud-rate timer reload data register (msb) (pefsif1 _brtrdm) 0x300b26 serial i/f ch.2 baud-rate timer reload data register (lsb) (pefsif2 _brtrdl) 0x300b27 serial i/f ch.2 baud-rate timer reload data register (msb) (pefsif2 _brtrdm) d[7:0]/0x300b x 6 brtrd x [7:0]: baud-rate timer reload data [7:0] d[3:0]/0x300b x 7 brtrd x [11:8]: baud-rate timer reload data [11:8] set the initial counter value of the baud-rate timer. (default: 0x000) the reload data set in this register is loaded into the counter, and the counter starts counting down be - ginning with this value, which is used as the initial count. there are two cases in which the reload data is loaded into the counter: when the baud-rate timer starts by writing 1 to brtrun x (d0/0x300b x5 ), or when data is automatically reloaded upon counter under - flow.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-51 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b08C0x300b28: serial i/f ch. x baud-rate timer count data registers (lsb) (pefsif x _brtcdl) 0x300b09C0x300b29: serial i/f ch. x baud-rate timer count data registers (msb) (pefsif x _brtcdm) name address register name bit function setting init. r/w remarks 0x0 to 0xff (brtcd x [11:0] = 0x0 to 0xfff) brtcd x 7 brtcd x 6 brtcd x 5 brtcd x 4 brtcd x 3 brtcd x 2 brtcd x 1 brtcd x 0 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch. x baud-rate timer count data [7:0] 0 0 0 0 0 0 0 0 r 00300b08 | 00300b28 (b) serial i/f ch. x baud-rate timer count data register (lsb) (pefsif x _brtcdl) C 0x0 to 0xf (brtcd x [11:0] = 0x0 to 0xfff) C brtcd x 11 brtcd x 10 brtcd x 9 brtcd x 8 d7C4 d3 d2 d1 d0 reserved serial i/f ch. x baud-rate timer count data [11:8] C 0 0 0 0 C r 0 when being read. 00300b09 | 00300b29 (b) serial i/f ch. x baud-rate timer count data register (msb) (pefsi f x _brtcdm) note : the letter x in bit names, etc., denotes a channel number from 0 to 2. 0x300b08 serial i/f ch.0 baud-rate timer count data register (lsb) (pefsif0 _brtcdl) 0x300b09 serial i/f ch.0 baud-rate timer count data register (msb) (pefsif0 _brtcdm) 0x300b18 serial i/f ch.1 baud-rate timer count data register (lsb) (pefsif1 _brtcdl) 0x300b19 serial i/f ch.1 baud-rate timer count data register (msb) (pefsif1 _brtcdm) 0x300b28 serial i/f ch.2 baud-rate timer count data register (lsb) (pefsif2 _brtcdl) 0x300b29 serial i/f ch.2 baud-rate timer count data register (msb) (pefsif2 _brtcdm) d[7:0]/0x300b x 8 brtcd x [7:0]: baud-rate timer count data [7:0] d[3:0]/0x300b x 9 brtcd x [11:8]: baud-rate timer count data [11:8] the baud-rate timer data can be read out from this register. (default: 0x000) this register function as a buffer that retain the counter data when read out, enabling the data to be read out at any time.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-52 epson s1c33e08 technical manual 0x300b1a: serial i/f ch.1 iso7816 mode control register (pefsif1_7816ctl) name address register name bit function setting init. r/w remarks rpnum12 rpnum11 rpnum10 clkoen1 clkol1 msbsel1 7816md11 7816md10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 number of transmit repetition ch.1 clock output enable ch.1 clock output forced low ch.1 msb first selection serial i/f ch.1 iso7816 mode selection 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w 00300b1a (b) serial i/f ch.1 iso7816 mode control register (pefsif1_7816ctl) 7816md1[1:0] mode reserved iso7816, t = 1 iso7816, t = 0 normal i/f 0x0 to 0x7 11 10 01 00 1 normal 0 forced low 1 enabled 0 disabled 1 msb first 0 lsb first d[7:5] rpnum1[2:0]: serial i/f ch.1 number of transmit repetition setup bits sets the retransmit count when a transmit error occurs. (default: 0) the t = 0 protocol allows retransmission of data when an error occurs in data transmission (when the receiver returns nack). retransmission can be repeated if the error occurs successively, and rp - num1[2:0 ] is used to set the retransmit count. a maximum of seven retransmissions may be specified. when rpnum1[2:0] is set to 0 , this interface does not retransmit data even if a transmit error occurs. when a transmit error occurs in t = 1 protocol mode, this interface does not retransmit data regardless of how rpnum 1[2:0] is set. d4 clkoen1: serial i/f ch.1 clock output enable bit enables clock output in iso 7816 mode. 1 (w): enable 0 (w): disable 1 (r): clock is being output. 0 (r): clock is stopped (default) by setting clkone 1 to 1 after clkol1 (d3 ) is set to 1 , the clock is output from the #sclk1 pin. when reading, clkoen 1 indicates whether the clock is being output or stopped. to disables the clock output, wait until clkoen 1 is actually cleared to 0 after writing 0 to clkoen1 , and then set clkol 1 (d3) to 0. clkoen 1 and clkol1 (d3 ) must be set to 0 to output the specified number of clocks using clknen1 (d7/0x300b1f) and clkn1[6:0] (d[6:0]/0x300b1f). d3 clkol1: serial i/f ch.1 clock output forced low bit sets the clock output signal forcibly to low in iso 7816 mode. 1 (r/w): normal output 0 (r/w): forced low (default) when clkol 1 is set to 0 , the #sclk1 pin output is fixed at a low level. to output the clock normally, set clkol 1 to 1 then clkoen1 (d4 ) to 1 . to disable the clock output, wait until clkoen1 (d4 ) is actually cleared to 0 after writing 0 to clkoen1 (d4 ), and then set clkol1 to 0. clkol 1 and clkoen1 (d4 ) must be set to 0 to output the specified number of clocks using clknen1 (d7/0x300b1f) and clkn1[6:0] (d[6:0]/0x300b1f).
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-53 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d2 msbsel1: serial i/f ch.1 msb first select bit selects the data shift direction, msb first or lsb first, in iso 7816 mode. 1 (r/w): msb first 0 (r/w): lsb first (default) when msbsel 1 is 0 , data is serially output from the d0 bit first. to output data beginning with the d7 bit, set msbsel1 to 1. d[1:0] 7816md1[1:0]: serial i/f ch.1 iso7816 mode select bits sets the serial interface in iso 7816 mode. table v. 1.8.6 selecting iso7816 mode 7816md11 1 1 0 0 7816md10 1 0 1 0 mode reser ve d iso7816 (t = 1) mode iso7816 (t = 0) mode nor mal interf ace (default: 0b00)
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-54 epson s1c33e08 technical manual 0x300b1b: serial i/f ch.1 iso7816 mode status register (pefsif1_7816sta) name address register name bit function setting init. r/w remarks C ter1 d7C1 d0 reserved ch.1 iso7816 transmit error flag C 0 C r/w 0 when being read. reset by writing 0. 00300b1b (b) serial i/f ch.1 iso7816 mode status register (pefsif1_7816sta ) C 1 error 0 normal d[7:1] reserved d0 ter1: serial i/f ch.1 iso7816 transmit error flag indicates that a transmit error occurs in iso 7816 (t = 0) mode. 1 (r): an error occurred 0 (r): no error occurred (default) 1 (w): has no effect 0 (w): reset to 0 ter 1 is set to 1 if the receiver returns an error signal (nack) when data has been transmitted in iso 7816 (t = 0 ) mode. when rpnum1[2:0 ] (d[7:5 ]/0x300b1 a) has been set to 0 (retransmission disabled), a transmit error occurs when nack is returned once. if a retransmit count (not 0 ) is set to rpnum1[2:0 ] (d[7:5]/0x300b1 a), the serial interface retransmit data when nack is returned. this retransmission is repeated up to the set retransmit count if the receiver cannot receive that data correct - ly. the nack signals returned in this period do not cause a transmit error. if nack has returned after the last retransmission, ter 1 is set to 1. ter 1 is reset by writing 0 or when rxen1 and txen1 both are set to 0.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-55 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b1c: serial i/f ch.1 iso7816 mode fi/di ratio register (lsb) (pefsif1_fidil) 0x300b1d: serial i/f ch.1 iso7816 mode fi/di ratio register (msb) (pefsif1_fidim) name address register name bit function setting init. r/w remarks 0x0 to 0xff (fidi1[13:0] = 0x0 to 0x3fff) fidi17 fidi16 fidi15 fidi14 fidi13 fidi12 fidi11 fidi10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 iso7816 mode fi/di ratio [7:0] 0 0 0 0 0 0 0 0 r/w valid only in iso7816 mode. 00300b1c (b) serial i/f ch.1 iso7816 mode fi/di ratio register (lsb) (pefsif1_fidil) C 0x0 to 0x3f (fidi1[13:0] = 0x0 to 0x3fff) C fidi113 fidi112 fidi111 fidi110 fidi19 fidi18 d7C6 d5 d4 d3 d2 d1 d0 reserved serial i/f ch.1 iso7816 mode fi/di ratio [13:8] C 0 0 0 0 0 0 C r/w 0 when being read. valid only in iso7816 mode. 00300b1d (b) serial i/f ch.1 iso7816 mode fi/di ratio register (msb) (pefsif1_fidim) d[7:0]/0x300b1c fidi1[7:0]: iso7816 mode fi/di ratio [7:0] d[5:0]/0x300b1d fidi1[13:8]: iso7816 mode fi/di ratio [13:8] sets the fi/di ratio for generating the iso 7816 clock. (default: 0x0000) the bit rate in iso 7816 mode is determined by the equation shown below. d bps = f sio_clk f bps: bit rate (bits/second) d: bit rate adjustment value 1, 2, 4, 8, 16, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 f: clock frequency divide value 372 (5 mhz), 558 (6 mhz), 744 (8 mhz), 1116 (12 mhz), 1488 (16 mhz), 1860 (20 mhz), 512 (5 mhz), 768 (7.5 mhz), 1024 (10 mhz), 1536 (15 mhz), 2048 (20 mhz) ( ) indicates the maximum output clock frequency. f sio_clk : iso 7816 clock frequency (baud-rate timer output and #sclk1 output) the sampling clock frequency for asynchronous transfer is determined by the following equation: d 1 f sampl = f sio_clk f divmd f sampl : sampling clock frequency divmd: divide ratio internally used by the serial interface ( 1/16 or 1/8, selected with divmd1) fidi 1[13:0 ] should be set to f divmd / d - 1 . tables v.1.8.7 and v.1.8.8 list the values that can be set to fidi1[13:0].
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-56 epson s1c33e08 technical manual table v. 1.8.7 fidi1[13:0 ] set values (divmd = 1/8) f/(d 8) -1 d f 372 558 744 1116 1488 1860 512 768 1024 1536 2048 1 46 69 92 139 185 232 63 95 127 191 255 2 22 34 46 69 92 115 31 47 63 95 127 4 11 16 22 34 46 57 15 23 31 47 63 8 5 8 11 16 22 28 7 11 15 23 31 16 2 3 5 8 11 14 3 5 7 11 15 1/2 92 139 185 278 371 464 127 191 255 383 511 1/4 185 278 371 557 743 929 255 383 511 767 1023 1/8 371 557 743 1115 1487 1859 511 767 1023 1535 2047 1/16 743 1115 1487 2231 2975 3719 1023 1535 2047 3071 4095 1/32 1487 2231 2975 4463 5951 7439 2047 3071 4095 6143 8191 1/64 2975 4463 5951 8927 11903 14879 4095 6143 8191 12287 16383 table v. 1.8.8 fidi1[13:0 ] set values (divmd = 1/16) f/(d 16) -1 d f 372 558 744 1116 1488 1860 512 768 1024 1536 2048 1 22 34 46 69 92 115 31 47 63 95 127 2 11 16 22 34 46 57 15 23 31 47 63 4 5 8 11 16 22 28 7 11 15 23 31 8 2 3 5 8 11 14 3 5 7 11 15 16 0 1 2 3 5 6 1 2 3 5 7 1/2 46 69 92 139 185 232 63 95 127 191 255 1/4 92 139 185 278 371 464 127 191 255 383 511 1/8 185 278 371 557 743 929 255 383 511 767 1023 1/16 371 557 743 1115 1487 1859 511 767 1023 1535 2047 1/32 743 1115 1487 2231 2975 3719 1023 1535 2047 3071 4095 1/64 1487 2231 2975 4463 5951 7439 2047 3071 4095 6143 8191
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-57 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b1e: serial i/f ch.1 transmit time guard register (pefsif1_ttgr) name address register name bit function setting init. r/w remarks 0x0 to 0xff ttgr17 ttgr16 ttgr15 ttgr14 ttgr13 ttgr12 ttgr11 ttgr10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 transmit time guard 0 0 0 0 0 0 0 0 r/w 00300b1e (b) serial i/f ch.1 transmit time guard register (pefsif1_ttgr) d[7:0] ttgr1[7:0]: serial i/f ch.1 transmit time guard setup bits sets the time guard function for data transmission. (default: 0x00) the iso 7816 mode supports a time guard function that inserts an idle time between characters during transmission. the idle time to be inserted can be specified in etu (bit cycle) units using ttgr 1[7:0]. when ttgr 1[7:0 ] is set to 0 , no idle time is inserted. when a value other than 0 is set, the sout1 output is fixed at high for the specified etu period after a stop bit is output. this high output period is regarded as a long stop bit.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-58 epson s1c33e08 technical manual 0x300b1f: serial i/f ch.1 iso7816 mode output clock setup register (pefsif1_clknum) name address register name bit function setting init. r/w remarks 0x0 to 0x7f clknen1 clkn16 clkn15 clkn14 clkn13 clkn12 clkn11 clkn10 d7 d6 d5 d4 d3 d2 d1 d0 ch.1 clkn enable serial i/f ch.1 number of output clocks 0 0 0 0 0 0 0 0 r/w r/w 00300b1f (b) serial i/f ch.1 iso7816 mode output clock setup register (pefsif1_clknum) 1 enabled 0 disabled d7 clknen1: serial i/f ch.1 transmit enable bit controls iso 7816 clock output according to the number of clocks specified using clkn1[6:0]. 1 (w): enable 0 (w): disable 1 (r): clock is being output. 0 (r): clock is stopped (default) by writing 1 to clknen1 , the clocks of which the number is specified with clkn1[6:0 ] (d[6:0 ]) is output from the #sclk 1 pin. the clock output starts in synchronization with the sampling clock, there - fore, it is not synchronized with writing to clknen1 . when reading, clknen1 indicates whether the clock is being output or stopped. clkoen 1 (d4/0x300b1 a) and clkol1 (d3/0x300b1 a) must be set to 0 to output the specified number of clocks using clknen1 and clkn1[6:0] (d[6:0]). use clkoen 1 (d4/0x300b1 a) and clkol1 (d3/0x300b1 a) to control normal clock output in iso7816 mode. d[6:0] clkn1[6:0]: serial i/f ch.1 number of output clocks setup bits sets the number of clocks output in iso 7816 mode. (default: 0x00) if the set value is an even number, the number of clocks is set to clkn 1[6:0] / 2. if the set value is an odd number, the number of clocks is set to (clkn 1[6:0] - 1) / 2. clkoen 1 (d4/0x300b1 a) and clkol1 (d3/0x300b1 a) must be set to 0 to output the specified number of clocks using clknen1 (d7) and clkn1[6:0]. sio_clk (baud-rate timer output) clkol1 clkoen1 clknen1 clock counter (clkn1[6:0] = 8) #sclk1 output 1 0 2 3 4 5 6 7 8 0 (0) (0) figure v. 1.8.1 clock output with number of clocks specified
v peripheral modules 3 (interface): general-purpose serial interface (efsio) s1c33e08 technical manual epson v-1-59 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300b4f: serial i/f std/adv mode select register (pefsif_adv) name address register name bit function setting init. r/w remarks C sioadv d7C1 d0 reserved standard mode/advanced mode select C 0 C r/w writing 1 not allowed. 00300b4f (b) serial i/f std/adv mode select register (pefsif_adv) C 1 advanced mode 0 standar d mode d[7:1] reserved d0 sioadv: standard/advanced mode select bit selects standard or advanced mode. 1 (r/w): advanced mode 0 (r/w): standard mode (default) the serial interface in the s 1c33e08 is extended from that of the c33 std models. the s1c33e08 se - rial interface has two operating modes, standard (std) mode of which functions are compatible with the existing c 33 std models and an advanced (adv) mode allowing use of the extended functions. table v. 1.8.9 shows differences between standard mode and advanced mode. table v. 1.8.9 differences between standard mode and advanced mode function #srd y mask control number of receiv ed data in the b uff er to generate a receiv e-b uff er full interr upt ad v anced mode enabled one to four can be specified. standar d mode disabled one to configure the serial interface in advanced mode, set sioadv to 1 . the control bits (srdyctl x and fifoint x[1:0 ]) for the extended functions are enabled to write after this setting. note : standard or advanced mode currently set is applied to all the serial interface channels. it can - not be selected for each channel individually.
v peripheral modules 3 (interface): general-purpose serial interface (efsio) v-1-60 epson s1c33e08 technical manual v. 1.9 precautions ? before setting various serial-interface parameters, make sure the transmit and receive operations are disabled (txen x = rxen x = 0). ? txen x : serial i/f ch. x transmit enable bit in the serial i/f ch. x control register (d7/0x300b x 3) ? rxen x : serial i/f ch. x receive enable bit in the serial i/f ch. x control register (d6/0x300b x 3) ? when the serial interface is transmitting or receiving data, do not set txen x or rxen x to 0 , and do not execute the slp instruction. ? in clock-synchronized transfers, the mode of communication is half-duplex, in which the clock line is shared be - tween the transmit and receive units. therefore, rxen x and txen x cannot be enabled simultaneously. ? after an initial reset, the cause-of-interrupt flags become indeterminate. to prevent generation of an unwanted interrupt or idma request, reset these flags in the program. ? if a receive error occurs, the receive-error interrupt and receive-buffer full interrupt causes occur simultaneously. however, since the receive-error interrupt has priority over the receive-buffer full interrupt, the receive-error in - terrupt is processed first. therefore, it is necessary to reset the receive-buffer full interrupt cause flag through the use of the receive-error interrupt processing routine. ? to prevent the regeneration of interrupts due to the same cause of interrupt following the occurrence of an inter - rupt, always be sure to reset the cause-of-interrupt flag before setting the psr again or executing the reti instruc - tion. ? follow the procedure described below to initialize the serial interface. set irmd x [1:0] set smd x [1:0] other settings enable transmitting/receiving 00(normal i/f) or 10(irda i/f) transfer mode setting data format and clock selection internal division ratio, irda i/o logic and other settings enable transmitting, receiving or both figure v. 1.9.1 serial interface initialize procedure ? when transmitting data in clock-synchronized master mode, transmit data is written to the transmit data register after the initial setting is performed following the flow above. however, the clock generated by the baud-rate timer must be supplied to the serial interface (at least one underflow has had to have occurred in the baud-rate timer) before this writing. otherwise, 0xff will be transmitted prior to the written data. ? the maximum transfer rate of the serial interface is limited to 8 mbps in clock-synchronized mode or 1 mbps in asynchronous mode. do not set a transfer rate (baud rate) that exceeds the limit. ? if the receive circuit is stopped during reception, set both transmission and reception to the disabled status. ? when performing data transfer in the clock-synchronized mode, the division ratio of the reload data for the baud- rate timer should be set so that the baud-rate is 1/4 of the system clock frequency or lower. ? when the transmit-enable bit txen x is set to 0 to disable transmit operations, the transmit data buffer (fifo) is cleared (initialized). similarly, when the receive-enable bit rxen x is set to 0 to disable receive operations, the receive data buffer (fifo) is cleared (initialized). therefore, make sure that the buffer does not contain any data waiting for transmission or reading before writing 0 to these bits. ? during irda receive operations, the rzi circuit recognizes low pulses by means of the signal edge (rising edge when irrl x = 0 ; falling edge when irrl x = 1). note that noise may cause a malfunction. ? irrl x : serial i/f ch. x irda i/f input logic inversion bit in the serial i/f ch. x irda register (d2/0x300b x 4)
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 2 serial peripheral interface (spi) v. 2.1 outline of spi module the s 1c33e08 contains a synchronous serial interface module (hereafter spi module) compatible with motorola spi ? . the following shows its features: ? supports both master and slave modes. ? supports 1 to 32 -bit data transfer. ? programmable bit-rate configuration ? data transfer timing (clock phase and polarity variations) is selectable from among 4 types. ? 1 to 65536 clocks of delay can be inserted between transfers. ? generates transmit data register empty, receive data register full, and receive data overflow interrupts. ? generates dma requests from transmit data register empty and receive data register full. ? spi-eeprom boot is possible (see appendix for details on booting). figure v. 2.1.1 shows the structure of the spi module. internal data bus mclk sdi sdo to itc spi_clk serial bus interface (shift register) internal bus interface/ control registers interrupt control clock/ reset control figure v. 2.1.1 structure of spi module
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-2 epson s1c33e08 technical manual v. 2.2 i/o pins of spi module table v. 2.2.1 lists the i/o pins used by the spi module. table v. 2.2.1 spi pin configuration pin name sdi sdo spi_clk i/o i o i/o function data input data output cloc k output (master mode) or cloc k input (sla ve mode) sdi pin this pin is used to input serial data. sdo pin this pin is used to output serial data. spi_clk pin in master mode, this pin is used to output the spi clock to slave devices. in slave mode, this pin is used to input the spi clock from the master device. note : the spi input/output pins are shared with general-purpose i/o ports or other peripheral circuit in - puts/outputs, so that functionality in the initial state is set to other than the spi input/output. before the spi input/output signals assigned to these pins can be used, the function of these pins must be switched for the spi input/output by setting the corresponding port function select registers. for details of pin functions and how to switch over, see section i.3.3, switching over the multi - plexed pin functions.
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 2.3 spi operating clock the spi module use the spi_clk clock (= mclk) generated by the cmu as the operating clock. the transfer clock is generated in the spi module by dividing spi_clk. controlling the supply of the operating clock spi_clk is supplied to the spi module with default settings. it can be turned off using spi_cke (d 6 / 0 x 301 b 04 ) to reduce the amount of power consumed on the chip if the spi module is not used. ? spi_cke : spi clock control bit in the gated clock control register 1 (d6/0x301b04) setting spi_cke (d 6/0x301b04 ) to 0 (1 by default) turns off the clock supply to the spi module. when the clock supply is turned off, the spi module control registers cannot be accessed. for details on how to set and control the clock, refer to section iii. 1, clock management unit (cmu). note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be re - moved by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless re - writing said registers. clock state in standby mode the clock supply to the spi module stops depending on type of s tandby mode. halt mode: the operating clock is supplied the same way as in normal mode. sleep mode: the operating clock supply stops. therefore, the spi module also stops operating in sleep mode.
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-4 epson s1c33e08 technical manual v. 2.4 setting spi module when performing data transfers via the spi bus, the following settings must be made before data transfer is actually begun: 1. setting input/output pins 2 . selecting master or slave mode 3. setting the data bit width 4. setting the bit rate 5. setting the spi_clk polarity and phase 6 . setting the inter-character wait cycle 7 . setting the receive data mask 8. setting interrupts and idma/hsdma the following explains the content of each setting. for details on interrupt/dma settings, refer to section v. 2 . 6 , spi interrupts and dma. note : always make sure the spi module is inactive ( ena (d 0/0x301708) = 0) before these settings are made. a change of settings during operation may cause a malfunction. ? ena : spi enable bit in the spi control register 1 (d0/0x301708) setting input/output pins the sdi, sdo, and spi_clk pins are used for spi. configure the port function select registers to enable these pin functions. for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. selecting master or slave mode use mode (d 1/0x301708 ) to select whether the spi module is set to master mode or slave mode. setting mode (d 1/0x301708 ) to 1 selects master mode, and setting to 0 (default) selects slave mode. in master mode, the spi performs data transfer using the clock generated in the module. in slave mode, the spi performs data transfer using a clock input from the master device. ? mode : spi mode select bit in the spi control register 1 (d1/0x301708) setting the data bit width use bpt[ 4:0 ] (d[14:10]/0x301708 ) to set the data bit width of the transfer data (characters). data bit width is set as the bpt[4:0] (d[14:10]/0x301708 ) set value + 1 (for example, 16 bits when bpt[4:0] = 15). ? bpt[4:0] : number of data bits per transfer setup bits in the spi control register 1 (d[14:10]/0x301708) setting the bit rate when the spi module is set in master mode, the synchronous clock is generated inside the module. the syn - chronous clock drives the shift register and is output from the spi_clk pin to slave devices. specify the clock frequency using mcbr[ 2:0] (d[6:4]/0x301708) to determine the bit rate. ? mcbr[2:0] : master clock bit rate setup bits in the spi control register 1 (d[6:4]/0x301708) table v. 2.4.1 setting the clock frequency mcbr2 1 1 1 1 0 0 0 0 mcbr1 1 1 0 0 1 1 0 0 mcbr0 1 0 1 0 1 0 1 0 clock frequency (hz) mclk/512 mclk/256 mclk/128 mclk/64 mclk/32 mclk/16 mclk/8 mclk/4 slave mode does not need to set a bit rate as the spi module operates with the clock input from the master de - vice.
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 setting the spi_clk polarity and phase use cpol (d 8/0x301708 ) to select the spi_clk clock polarity. the spi_clk is configured as active low when cpol (d8/0x301708) is set to 1 or active high when cpol (d8/0x301708) is set to 0 (default). ? cpol : spi_clk polarity select bit in the spi control register 1 (d8/0x301708) the spi_clk clock phase is selected with cpha (d 9 / 0 x 301708 ). ? cpha : spi_clk phase select bit in the spi control register 1 (d9/0x301708) setting these control bits determines the transfer timing as i n the figure shown below. spi_clk (cpol = 1, cpha = 1) spi_clk (cpol = 1, cpha = 0) spi_clk (cpol = 0, cpha = 1) spi_clk (cpol = 0, cpha = 0) sdi/sdo fetching receive data into shift register 1 to 32 bits msb lsb figure v. 2.4.1 clock and data transfer timing setting the inter-character wait cycle 1 to 65536 spi_clk clocks of delay time can be inserted between data transfers (in each transfer for specified number of data bits) using the spi wait register ( 0x301710 ). the value set in the register (0 to 65535 ) + 1 is used as the number of wait cycles. setting the receive data mask (1 ) rxme (d1/0x30171c) = 0 (default) the spi receive data register ( 0x301700 ) will receive the data bits specified with bpt[4:0 ] (d[14:10]/ 0x301708) + 1 . the ineffective upper bits are masked with 0. (2 ) rxme (d1/0x30171c) = 1 this setting enables user specified bit mask. the spi receive buffer will receive the data bits specified with bpt[4:0 ] (d[14:10]/0x301708 ) + 1 . the ineffective upper bits are masked with 0 . then only the effective data bits specified with rxmask[ 4:0 ] (d[14:10]/0x30171 c) + 1 in the receive data buffer are loaded to the spi receive data register ( 0x301700 ). the ineffective upper bits are masked with 0. ? rxme : receive data mask enable bit in the spi receive data mask register (d1/0x30171c) ? rxmask[4:0] : receive data mask setup bits in the spi receive data mask register (d[14:10]/0x30171c) figure v. 2.4.2 shows the relationship between the mask control bit settings and the receive data loaded to the spi receive data register ( 0x301700). d0 dn 0 0 d 0 shift register spi receiv e data register rxme = 0 (def ault) v alid data v alid data bpt[4:0] + 1 (bits) 0 0 dm dm d0 shift register spi receiv e b uff er spi receiv e data register rxme = 1 dn mask ed d31 rxmask[4:0] + 1 (bits) d0 dn 0 0 d 0 bpt[4:0] + 1 (bits) dn mask ed d31 mask ed figure v. 2.4.2 receive data mask
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-6 epson s1c33e08 technical manual v. 2.5 control of data transfer data transmission the following shows the data-transmit procedure: 1 . set up the spi conditions as described in the previous section. 2 . set up the interrupt and dma conditions using the itc registers and the spi interrupt control register (ex - plained later). when using the spi interrupt, the cause of spi interrupt flag in the itc must be cleared be - fore enabling the interrupt. 3 . write 1 to the ena (d0/0x301708) to turn the spi circuit on. in master mode, the spi circuit starts frequency division of the source clock. ? ena : spi enable bit in the spi control register 1 (d0/0x301708) 4 . in slave mode, write 1 to ss (d10/0x30170 c) to set this slave spi into selected status. this enables clock input from the spi_clk pin. ? ss : slave select control bit in the spi control register 2 (d10/0x30170c) in master mode, ss (d 10/0x30170c) must be set to 0. 5 . write the transmit data to the spi transmit data register (0x301704). the spi circuit loads the data written to the register into the shift register. in master mode, the spi circuit starts outputting the clock from the spi_clk pin. in slave mode, the spi circuit waits for clock input from the spi_clk pin. the data bits in the shift register are shifted one by one at the rising or falling edge con - figured with cpha (d 9/0x301708 ) and cpol (d8/0x301708 ) (see figure v.2.4.1 ), and are output from the sdo pin. the msb of data is transmitted first. ? cpha : spi_clk phase select bit in the spi control register 1 (d9/0x301708) ? cpol : spi_clk polarity select bit in the spi control register 1 (d8/0x301708) the spi circuit provides tdef (d 4/0x301714 ) to indicate the spi transmit data register (0x301704 ) sta - tus. this flag is reset to 0 (not empty) when data is written to the transmit data register and is set to 1 (empty) when the written data is loaded into the shift register. an interrupt can be generated simultaneous with this flag set to 1 . check to see if the tdef (d4/0x301714 ) is set to 1 by polling or using this interrupt before the next transmit data can be written to the spi transmit data register ( 0x301704). ? tdef : transmit data empty flag in the spi status register (d4/0x301714) furthermore, by setting txde (d 3/0x301708 ) to 1 , a transmit dma request is output to the itc. this dma request can be used to set transmit data without using the interrupt above. ? txde : transmit dma enable bit in the spi control register 1 (d3/0x301708) the spi circuit continues data output from the sdo pin and clock input/output from/to the spi_clk pin until data transmission for the number of bits specified with the bpt[4:0] (d[14:10]/0x301708) is finished. if the next transmit data exists in the spi transmit data register ( 0x301704 ) when a data transfer has fin - ished in master mode, the spi circuit repeats the same transmit operation as above. however, the spi circuit delays starting the next transmission for the number of spi_clk cycles specified with the spi wait regis - ter ( 0x301710 ). the data written to the transmit data register is not loaded into the shift register until after the expiration of the delay time. when a continuous data transmission is being performed in slave mode, the spi wait register ( 0x301710) does not affect the transmission (no delay is inserted) as the clock is controlled by the master device. the next transmit data must be written to the spi transmit data register ( 0x301704 ) before the master starts sending the next data transfer clocks. in master mode, the transmitter status sets/resets bsyf (d 6/0x301714 ). bsyf (d6/0x301714 ) is set to 1 when transmission is in progress or in the wait cycles specified with the spi wait register ( 0x301710 ), and reset to 0 upon completion of a transmit operation. use this flag to check if a transmission has completed. this flag is ineffective in slave mode (always 0 is read). ? bsyf : transfer busy flag in the spi status register (d6/0x301714)
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 6 . after all transmissions have completed, write 0 to ena (d0/0x301708 ) to turn the spi circuit off. in slave mode, write 0 to ss (d10/0x30170 c) to set this spi slave to deselected status before writing 0 to ena (d 0/0x301708). mclk ena div_clk (master mode) spitxd[31:0] shift register spi_clk pin (cpha = 1) spi_clk pin (cpha = 0) data output pin bsyf tdef interr upt a msb b msb a msb- 1 a 0 wr ite wr ite tr ansmit data empty w ait cycles (master mode) (spiw +1) tc(div_clk) data a data b figure v. 2.5.1 data transmit timing chart (cpol = 0) data receiving the following shows the data-receive procedure: 1 . set up the spi conditions as described in the previous section. 2 . set up the interrupt and dma conditions using the itc registers and the spi interrupt control register (ex - plained later). when using the spi interrupt, the cause of spi interrupt flag in the itc must be cleared be - fore enabling the interrupt. 3 . write 1 to the ena (d0/0x301708) to turn the spi circuit on. in master mode, the spi circuit starts frequency division of the source clock. 4 . in slave mode, write 1 to ss (d10/0x30170 c) to set this slave spi into selected state. this enables clock input from the spi_clk pin. in master mode, ss (d 10/0x30170c) must be set to 0. 5 . in master mode, write dummy data to the spi transmit data register ( 0 x 301704 ). writing to the spi trans - mit data register ( 0x301704 ) is used as the trigger for data receiving as well as start of data transmission. also actual data to be transmitted can be written as the spi circuit performs data transmission and reception simultaneously. the spi circuit starts output of the generated clock from the spi_clk pin. in slave mode, the spi circuit waits for clock input from the spi_clk pin. when performing data transmis - sion and reception simultaneously, the transmit data should be written to the spi transmit data register (0x301704) before a clock is input. the data bits are fetched in the shift register one by one at the rising or falling edge configured with cpha (d9/0x301708) and cpol (d8/0x301708 ) (see figure v.2.4.1 ). the msb of data is received first. when the specified number of bit data is received in the shift register, the received data is loaded into the spi receive data register ( 0x301700 ). the bit mask processing is performed in this loading stage. at the same time, rdff (d 2/0x301714 ) is set to 1 (data full) to indicate that the receive data can be read from the spi receive data register ( 0x301700 ) and a data receive interrupt can be generated. ? rdff : receive data full flag in the spi status register (d2/0x301714)
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-8 epson s1c33e08 technical manual 6 . check to see if the rdff (d2/0x301714 ) is set to 1 by polling or using the interrupt and read data from the spi receive data register ( 0x301700 ). when data is read from the spi receive data register (0x301700), rdff (d2/0x301714) is cleared to 0. furthermore, by setting rxde (d 2/0x301708 ) to 1 , a receive dma request is output to the itc. this dma request can be used to store the received data to other memory without using the interrupt above. ? rxde : receive dma enable bit in the spi control register 1 (d2/0x301708) to receive data successively in master mode, write dummy data or transmit data to the spi transmit data register ( 0x301704 ) every time a data frame is received. the spi circuit continues the receive operation when any data has been written to the spi transmit data register ( 0x301704 ). however, the spi circuit delays starting the next receiving for the number of spi_clk cycles specified with the spi wait register (0x301710 ). the clock output is suspended until after the expiration of the delay time. when receiving data in slave mode without any data transmission, it is not necessary to write data to the spi transmit data register ( 0x301704 ). the receive process activates by the clock input from the master device. when performing data transmission simultaneously, write transmit data to the spi transmit data register ( 0x301704) according to the data transmit procedure. 7 . repeat steps 5 and 6 until all data are received. in the same manner as transmission, bsyf (d 6/0x301714 ) is set to 1 when data is being received in master mode. 8 . after all data has been received, write 0 to ena (d0/0x301708 ) to turn the spi circuit off. in slave mode, write 0 to ss (d10/0x30170 c) to set this spi slave to deselected status before writing 0 to ena (d 0/0x301708). mclk ena div_clk (master mode) spitxd[31:0] (master mode) spi_clk pin (cpha = 1) spi_clk pin (cpha = 0) data input pin shift register spirxd[31:0] bsyf rdff interr upt data a a msb b msb a msb- 1 a 0 b 0 wr ite wr ite w ait cycles (master mode) (spiw + 1) tc(div_clk) data receiv e interr upt data receiv e interr upt dumm y dumm y b msb- 1 figure v. 2.5.2 data receive timing chart (cpol = 0) receive data overflow the spi receive data register ( 0x301700 ) is overwritten if a data reception has finished when the previously received data has not been read from the register. therefore, when data is being received continuously, receive data must be read before the following data reception finishes. if the spi receive data register ( 0x301700 ) is overwritten when rdff (d2/0x301714 ) = 1 (the received data has not been read yet), rdof (d 3/0x301714 ) is set to 1 . a receive data overflow interrupt can be generated si - multaneous with this flag set to 1 . use this interrupt for error recovery. ? rdof : receive data overflow flag in the spi status register (d3/0x301714) rdof (d3/0x301714) is reset to 0 by reading data from the spi receive data register (0x301700).
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 data transmit/receive trigger and precautions the spi circuit performs data transmission and reception simult aneously. when data transmission is started, a data receive operation is also performed. therefore, if received data that has not been read exists in the spi receive data register ( 0x301700 ), it will be overwritten. furthermore, un - desired data receive interrupts occur if the interrupts for receiving are enabled. these interrupts should be dis - abled before starting data transmission. before performing data reception after data is transmitted, read the spi receive data register ( 0x301700 ) to clear rdff (d2/0x301714 ) and rdof (d3/0x301714 ), since the flags have been set due to the receive operation performed simultaneously with the previous data transmission. when receiving data, the data transmit interrupt should be disabled in the same way as the data transmission.
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-10 epson s1c33e08 technical manual v. 2.6 spi interrupts and dma the spi module can generate the following three types of interrupts: ? transmit dma interrupt (transmit data empty) ? receive dma interrupt (receive data full) ? spi interrupt (transmit data empty, receive data full, receive data overflow) transmit dma interrupt a cause of interrupt occurs when the transmit data set in the spi transmit data register ( 0x301704 ) is trans - ferred to the shift register. when txde (d 3/0x301708 ) has been set to 1 , the interrupt request signal is output to the itc and it sets the cause-of-interrupt flag fspitx (d5/0x300289) in the itc to 1. ? txde : transmit dma enable bit in the spi control register 1 (d3/0x301708) at this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the cpu is generated. occurrence of this cause of interrupt indicates that the next transmit data can be written to the trans - mit data register. this cause of interrupt can also be used to invoke dma, enabling transmit data to be written to the register by means of a dma transfer. receive dma interrupt a cause of interrupt occurs when the data received in the shift register is loaded into the spi receive data reg - ister ( 0x301700 ). when rxde (d2/0x301708 ) has been set to 1 , the interrupt request signal is output to the itc and it sets the cause-of-interrupt flag fspirx (d4/0x300289) in the itc to 1. ? rxde : receive dma enable bit in the spi control register 1 (d2/0x301708) at this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the cpu is generated. occurrence of this cause of interrupt indicates that the received data can be read out. this cause of interrupt can also be used to invoke dma, enabling the received data to be written into specified memory loca - tions by means of a dma transfer. spi interrupt in addition to the two interrupt request signals shown above, the spi module outputs one more interrupt re - quest signal. this interrupt request circuit is configured as figure v. 2.6.1 and it allows selection of one or more causes of interrupt. interr upt request (int_spi) irqe (d0/0x301718) teie (d4/0x301718) tr ansmit data empty (tdef) r oie (d3/0x301718) receiv e data ov erflo w (rdof) rfie (d2/0x301718) receiv e data full (rdff) mirq (d1/0x301718) figure v. 2.6.1 spi interrupt request circuit to output the spi interrupt requests, enable interrupts of the causes described below and set irqe (d 0 / 0 x 301718 ) to 1 . when irqe (d0/0x301718) is set to 0, no spi interrupt request is output. ? irqe : interrupt request enable bit in the spi interrupt control register (d0/0x301718)
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 transmit data empty a cause of interrupt occurs when the transmit data set in the spi transmit data register ( 0x301704 ) is trans - ferred to the shift register, in which case tdef (d 4/0x301714 ) is set to 1 . set teie (d4/0x301718 ) to 1 to out - put an interrupt request by this cause of interrupt. ? tdef : transmit data empty flag in the spi status register (d4/0x301714) ? teie : transmit data empty interrupt enable bit in the spi interrupt control register (d4/0x301718) this interrupt request occurs by the same cause of interrupt as the transmit dma interrupt. receive data full a cause of interrupt occurs when the data received in the shift register is loaded into the spi receive data reg - ister ( 0x301700 ), in which case rdff (d2/0x301714 ) is set to 1 . set rfie (d2/0x301718 ) to 1 to output an interrupt request by this cause of interrupt. ? rdff : receive data full flag in the spi status register (d2/0x301714) ? rfie : receive data full interrupt enable bit in the spi interrupt control register (d2/0x301718) this interrupt request occurs by the same cause of interrupt as the receive dma interrupt. receive data overflow a cause of interrupt occurs when receive data is loaded into the spi receive data register ( 0x301700 ) before the previous data in the register is read out, in which case rdof (d 3/0x301714 ) is set to 1 . set roie (d3/ 0x301718) to 1 to output an interrupt request by this cause of interrupt. ? rdof : receive data overflow flag in the spi status register (d3/0x301714) ? roie : receive data overflow interrupt enable bit in the spi interrupt control register (d3/0x301718) manual interrupt request an spi interrupt request can be output manually by setting mirq (d 1/0x301718 ) to 1 . after an interrupt oc - curs by this operation, write 0 to mirq (d1/0x301718 ) to negate the spi interrupt request signal. ? mirq : manual irq set/clear bit in the spi interrupt control register (d1/0x301718) the spi interrupt request is sent to the itc as the port 8 input interrupt (fpt8 ) signal and it sets the cause-of- interrupt flag fp 8 (d0/0x3002a9 ) in the itc to 1 . however, int_spi must be selected for the port 8 input in - terrupt. control registers of the interrupt controller table v. 2.6.1 shows the interrupt controller's control registers provided for each interrupt source. table v. 2.6.1 control register of interrupt controller interrupt tr ansmit dma interr upt receiv e dma interr upt spi interr upt cause-of-interrupt fla g fspitx(d5/0x300289) fspirx(d4/0x300289) fp8(d0/0x3002a9) interrupt priority register pspi[2:0](d[6:4]/0x30026e) pp8l[2:0](d[2:0]/0x3002a0) interrupt enable register espitx(d5/0x300279) espirx(d4/0x300279) ep8(d0/0x3002a6) when a cause of interrupt described above occurs, the corresponding cause-of-interrupt flag is set to 1 . if the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit for that cause of interrupt set to 0 . the cause-of-interrupt flag is set to 1 whenever interrupt conditions are met, regardless of the setting of the interrupt enable register (even if it is set to 0). the interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7 . an interrupt request to the cpu is accepted only when no other interrupt request of a higher priority has been generated. in addition, only when the psr's ie bit = 1 (interrupts enabled) and the set value of the il is smaller than the input interrupt level set by the interrupt priority register, will the input interrupt request actually be ac - cepted by the cpu. for details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to section iii.2, interrupt controller (itc).
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-12 epson s1c33e08 technical manual note : the spi interrupt request signal is input to the port 8 input interrupt (fpt8) system. the port 8 in - put interrupt circuit is configured by selecting a port (signal) to be used for generating an interrupt from p90, int_spi, p80, and p70. when using the spi interrupt, set spt8[1:0] (d[1:0]/0x3003c4) to 10 to select int_spi. this setting enables the int_spi signal to be sent to the itc as the port 8 input interrupt signal. furthermore, sppt8 (d0/0x3003c6), which selects the polarity of the fpt8 input signal, should be set to 1 (high level or rising edge). ? spt8[1:0] : fpt8 interrupt input port select bits in the port input interrupt select register 3 (d[1:0]/0x3003c4) ? sppt8 : fpt8 input polarity select bit in the port input interrupt polarity select register 2 (d0/0x3003c6) intelligent dma the transmit dma, receive dma and spi interrupt requests can be used to invoke intelligent dma (idma). this enables successive transmit/receive operations between memory and the transmit/receive-register to be performed by means of a dma transfer. the following shows the idma channel numbers set for each cause of interrupt: idma ch. receive dma interrupt: 0x24 transmit dma interrupt: 0x25 spi interrupt (fpt 8 interrupt): 0x26 the idma request and enable bits shown in table v. 2.6.2 must be set to 1 for idma to be invoked. transfer conditions, etc. on the idma side must also be set in advance. table v. 2.6.2 control bits for idma transfer interrupt tr ansmit dma interr upt receiv e dma interr upt spi interr upt idma request bit rspitx(d5/0x30029b) rspirx(d4/0x30029b) rp8(d0/0x3002a c) idma enable bit despitx(d5/0x30029c) despirx(d4/0x30029c) dep8(d0/0x3002ae) if a cause of interrupt occurs when the idma request and enable bits are set to 1 , idma is invoked. no inter - rupt request is generated at that point. an interrupt request is generated upon completion of the dma transfer. the bits can also be set so as not to generate an interrupt, with only a dma transfer performed. for details on dma transfer and how to control interrupts upon completion of dma transfer, refer to section ii.2, intelligent dma (idma). high-speed dma each interrupt can also invoke high-speed dma (hsdma). the following shows the hsdma channel number and trigger set-up bit corresponding to each interrupt: table v. 2.6.3 hsdma trigger set-up bits interrupt tr ansmit dma interr upt receiv e dma interr upt spi interr upt hsdma ch. 2 3 0 t rigger set-up bits hsd2s[3:0] (d[3:0]) / hsdma ch.2C3 tr igger set-up register (0x300299) hsd3s[3:0] (d[7:4]) / hsdma ch.2C3 tr igger set-up register (0x300299) hsd0s[3:0] (d[3:0]) / hsdma ch.0C1 tr igger set-up register (0x300298) for hsdma to be invoked by a transmit dma interrupt request, the trigger set-up bits for hsdma ch. 2 should be set to 1001. for hsdma to be invoked by a receive dma interrupt request, the trigger set-up bits for hsdma ch. 3 should be set to 1001. for hsdma to be invoked by an spi interrupt (fpt8 interrupt) request, the trigger set-up bits for hsdma ch. 0 should be set to 1101. transfer conditions, etc. must also be set on the hsdma side. the hsdma channel is invoked through generation of the cause of interrupt. for details on hsdma transfer, refer to section ii. 1, high-speed dma (hsdma). trap vectors the default trap-vector address of each cause of interrupt is set as follows: receive dma interrupt: 0xc00144 transmit dma interrupt: 0xc00148 spi interrupt (fpt 8 interrupt): 0xc00150 the base address of the trap table can be changed using the ttbr register.
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 2.7 details of control registers table v. 2.7.1 list of spi registers address 0x00301700 0x00301704 0x00301708 0x0030170c 0x00301710 0x00301714 0x00301718 0x0030171c function receive data transmit data sets spi transfer conditions controls slave mode sets inter-character wait cycle spi transfer/error status controls spi interrupts sets receive data bit mask register name spi receive data register (pspi_rxd) spi transmit data register (pspi_txd) spi control register 1 (pspi_ctl1) spi control register 2 (pspi_ctl2) spi wait register (pspi_wait) spi status register (pspi_stat) spi interrupt control register (pspi_int) spi receive data mask register (pspi_rxmk) siz e 32 32 32 32 32 32 32 32 the following describes each spi control register. the spi control registers are mapped in the 32 -bit device area from 0x301700 to 0x30171 c, and can be accessed in units of words. notes : ? the spi control registers allow accessing in word size only. do not read/write the registers in half-word or byte size. ? when setting the spi control registers, be sure to write a 0, and not a 1 , for all reserved bits.
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-14 epson s1c33e08 technical manual 0x301700: spi receive data register (pspi_rxd) name address register name bit function setting init. r/w remarks 0x0 to 0xffffffff spirxd31 | spirxd0 d31 | d0 spi receive data spirxd31 = msb spirxd0 = lsb 0x0 r 00301700 (w) spi receive data register (pspi_rxd) d[31:0] spirxd[31:0]: spi receive data bits stores received data. (default: 0x0) when a receive operation is completed and the data received in the shift register is loaded to this regis - ter, rdff (d 2/0x301714 ) is set to 1 (data full). at the same time, a cause of receive data full interrupt occurs. thereafter, the data can be read out at any time before a receive operation for the next data is completed. if the next data receive operation is completed before this register is read out, the data in it is overwrit - ten with the newly received data and rdof (d 3/0x301714 ) is set to 1 (data overflow). at the same time, a cause of receive data overflow interrupt occurs. the serial data input from the sdi pin is converted into parallel data beginning with the msb, with the high-level signals changed to 1 s and the low-level signals changed to 0 s. the resulting data is stored in this register. furthermore, the upper bits of the received data specified with the spi receive data mask register (0x30171 c) can be masked (set to 0 ) when it is loaded from the shift register. this register is a read-only register, so no data can be written to it.
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301704: spi transmit data register (pspi_txd) name address register name bit function setting init. r/w remarks 0x0 to 0xffffffff spitxd31 | spitxd0 d31 | d0 spi transmit data spitxd31 = msb spitxd0 = lsb 0x0 r/w 00301704 (w) spi transmit data register (pspi_txd) d[31:0] spitxd[31:0]: spi transmit data bits sets transmit data. (default: 0x0) in master mode, data transmission begins by writing data to this register. in slave mode, the register contents are transferred to the shift register to start data transmission when a clock is input from the master device. tdef (d 4/0x301714 ) is set to 1 (empty) when the data is transferred to the shift register. a cause of data transmit interrupt is simultaneously generated. the next transmit data can be written to the register at any time thereafter, even when the spi is sending data. the serial-converted data is output from the sdo pin beginning with the msb, in which the bits set to 1 are output as high-level signals and those set to 0 output as low-level signals. when the number of data bits per transfer is set to less than 32 using bpt[4:0 ] (d[14:10]/0x301708), only the specified number of low-order bits in this register is transmitted.
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-16 epson s1c33e08 technical manual 0x301708: spi control register 1 (pspi_ctl1) name address register name bit function setting init. r/w remarks C bpt4 bpt3 bpt2 bpt1 bpt0 cpha cpol mwen mcbr2 mcbr1 mcbr0 txde rxde mode ena d31C15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved number of data bits per transfer spi_clk phase selection spi_clk polarity selection reserved master clock bit rate (in master mode only) transmit dma enable receive dma enable spi mode selection spi enable C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w r/w r/w C r/w r/w r/w r/w r/w 0 when being read. 00301708 (w) spi control register 1 (pspi_ctl1) C number of data bits per transfer = bpt + 1 fix at 0. master clock divided value = 4 2 mcbr 1 phase 1 0 0 phase 0 1 enabled disabled 0 1 master slave 0 1 enabled disabled 0 1 enabled disabled 1 active low 0 active high d[31:15] reserved d[14:10] bpt[4:0]: number of data bits per transfer setup bits sets the number of transfer data bits. (default: 0x0) the set value in this register + 1 (1 to 32 ) is the number of bits to be transmitted/received per data trans - fer. d9 cpha: spi_clk phase select bit selects the phase of the spi clock. (default: 0) this bit controls the data transfer timing in conjunction wit h the cpol (d 8 ) bit (see figure v.2.7.1). d8 cpol: spi_clk polarity select bit selects the polarity of the spi clock. 1 (r/w): active low 0 (r/w): active high (default) this bit controls the data transfer timing in conjunction wit h the cpha (d 9 ) bit (see figure v.2.7.1). spi_clk (cpol = 1, cpha = 1) spi_clk (cpol = 1, cpha = 0) spi_clk (cpol = 0, cpha = 1) spi_clk (cpol = 0, cpha = 0) sdi/sdo fetching receive data into shift register 1 to 32 bits msb lsb figure v. 2.7.1 clock and data transfer timing d7 reserved ( do not write 1 to this bit . )
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d[6:4] mcbr[2:0]: master clock bit rate setup bits sets the source clock division ratio for generating the spi clock. the bit rate is determined with this set - ting. table v. 2.7.2 setting bit rate mcbr2 1 1 1 1 0 0 0 0 mcbr1 1 1 0 0 1 1 0 0 mcbr0 1 0 1 0 1 0 1 0 clock frequency (hz) mclk/512 mclk/256 mclk/128 mclk/64 mclk/32 mclk/16 mclk/8 mclk/4 (default: 0x000) slave mode does not need to set a bit rate as the spi module operates with the clock input from the master device. d3 txde: transmit dma enable bit enables/disables transmit dma interrupts. 1 (r/w): enable 0 (r/w): disable (default) when txde is set to 1 , transmit dma interrupt requests to the itc are enabled. a transmit dma interrupt request occurs when the data written to the spi transmit data register ( 0x301704 ) is trans - ferred to the shift register (transmit operation started). at this time, the cause-of-interrupt flag fspitx (d5/0x300289 ) in the itc is set to 1 if txde has been set to 1 (enabled). this interrupt request can invoke hsdma. when txde is set to 0, transmit dma interrupts are not generated. d2 rxde: receive dma enable bit enables/disables receive dma interrupts. 1 (r/w): enable 0 (r/w): disable (default) when rxde is set to 1 , receive dma interrupt requests to the itc are enabled. a receive dma in - terrupt request occurs when the data received in the shift register is loaded to the spi receive data register ( 0x301700 ) (receive operation completed). at this time, the cause-of-interrupt flag fspirx (d4/0x300289 ) in the itc is set to 1 if rxde has been set to 1 (enabled). this interrupt request can invoke hsdma. when rxde is set to 0 , receive dma interrupts are not generated. d1 mode: spi mode select bit sets the spi module in master or slave mode. 1 (r/w): master mode 0 (r/w): slave mode (default) setting mode to 1 selects master mode, and setting to 0 selects slave mode. in master mode, the spi performs data transfer using the clock generated in the module. in slave mode, the spi performs data transfer using a clock input from the master device. d0 ena: spi enable bit enables/disables operation of the spi module. 1 (r/w): enabled (on) 0 (r/w): disabled (off) (default) when ena is set to 1, the spi module starts operating and data transfer is enabled. when ena is set to 0 , the spi module goes off. make sure that this bit is 0 before setting up data transfer conditions using the spi registers.
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-18 epson s1c33e08 technical manual 0x30170c: spi control register 2 (pspi_ctl2) name address register name bit function setting init. r/w remarks C ssa ss ssp ssc C rdyp rdys rdye d31C12 d11 d10 d9 d8 d7C3 d2 d1 d0 reserved reserved slave select control reserved reserved reserved reserved reserved reserved C 0 0 0 0 C 0 0 0 C C r/w C C C C C C 0 when being read. master mode slave mode 0 when being read. 0030170c (w) spi control register 2 (pspi_ctl2) C fix at 0. fix at 0. fix at 0. fix at 0. fix at 0. fix at 0. fix at 0. C 1 0 spi select spi deselect d[31:11] reserved (do not write 1 to this bit.) d10 ss: slave select control bit sets the spi module in selected state in slave mode. 1 (r/w): selected 0 (r/w): not selected (default) write 1 to ss before performing data transmission/reception in slave mode. in slave mode, setting both ena and ss to 1 enables clock input from the master device and data transmission/reception is enabled. in master mode, ss must be fixed at 0. d[9:0] reserved (do not write 1 to this bit.)
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301710: spi wait register (pspi_wait) name address register name bit function setting init. r/w remarks number of wait cycles = spiw[31:0] + 1 (1 to 65536) spiw31 | spiw0 d31 | d0 wait cycle control spiw31 = msb spiw0 = lsb 0x0 r/w 00301710 (w) spi wait register (pspi_wait) d[31:0] spiw[31:0]: wait cycle control bits sets the number of wait cycles to be inserted between data transfers (characters). the set value in this register + 1 is the number of wait cycles. 1 to 65536 spi_clk clock cycles can be specified.
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-20 epson s1c33e08 technical manual 0x301714: spi status register (pspi_stat) name address register name bit function setting init. r/w remarks C C C C bsyf mfef tdef rdof rdff C d31C7 d6 d5 d4 d3 d2 d1C0 reserved transfer busy flag reserved transmit data empty flag receive data overflow flag receive data full flag reserved C 0 C 1 0 0 C C r C r r r C 0 when being read. master mode 0 when being read. 0 when being read. 00301714 (w) 1 busy 0 idle 1 occurred 0 not occurred 1 empty 0 not empty 1 full 0 not full spi status register (pspi_stat) d[31:7] reserved d6 bsyf: transfer busy flag indicates the spi transmit/receive operation status in master mode. 1 (r): busy 0 (r): idle (default) bsyf is set to 1 when the spi starts data transmission/reception in master mode and stays 1 while data transmission/reception is in progress including the wait cycles inserted. bsyf is cleared to 0 upon completion of transmit/receive operation. bsyf is ineffective in slave mode (always 0). d5 reserved d4 tdef: transfer data empty flag indicates the spi transmit data register ( 0x301704) status. 1 (r): empty (default) 0 (r): not empty tdef is cleared to 0 when transmit data is written to the spi transmit data register (0x301704 ) and is set to 1 when the written data is transferred to the shift register (transmit operation started). transmit data can be written to the spi transmit data register ( 0x301704) when this bit = 1. d3 rdof: receive data overflow flag indicates receive data overflow status. 1 (r): overflow occurred 0 (r): overflow not occurred (default) rdof is set to 1 to indicate that the spi receive data register (0x301700 ) is overwritten when a data reception has completed before the previously received data in the register is read out. this bit is reset to 0 when the data is read out. d2 rdff: receive data full flag indicates the spi receive data register ( 0x301700) status. 1 (r): data full 0 (r): not full (default) rdff is set to 1 when the data received in the shift register is loaded to the spi receive data register (0x301700 ) (receive operation completed), indicating that the received data can be read out. this bit is reset to 0 when the data is read out. d[1:0] reserved
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301718: spi interrupt control register (pspi_int) name address register name bit function setting init. r/w remarks C fix at 0. C mfie teie roie rfie mirq irqe d31C6 d5 d4 d3 d2 d1 d0 reserved reserved transmit data empty int. enable receive overflow interrupt enable receive data full interrupt enable manual irq set/clear interrupt request enable C 0 0 0 0 0 0 C C r/w r/w r/w r/w r/w 0 when being read. 00301718 (w) 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 set 0 clear 1 enabled 0 disabled spi interrupt control register (pspi_int) d[31:5] reserved (do not write 1 to this bit.) d4 teie: transmit data empty interrupt enable bit enables/disables spi interrupt caused by transmit data empty. 1 (r/w): enable 0 (r/w): disable (default) when teie is set to 1 , spi (transmit data empty) interrupt requests to the itc are enabled. a transmit data empty interrupt request occurs when the data written to the spi transmit data register ( 0 x 301704 ) is transferred to the shift register (transmit operation started). at this time, the cause-of-interrupt flag fp8 (d0/0x3002a9) in the itc is set to 1 if both teie and irqe (d0 ) have been set to 1 (enabled). when teie is set to 0, spi interrupts caused by transmit data empty are not generated. d3 roie: receive data overflow interrupt enable bit enables/disables spi interrupt caused by receive data overflow. 1 (r/w): enable 0 (r/w): disable (default) when roie is set to 1 , spi (receive data overflow) interrupt requests to the itc are enabled. a receive data overflow interrupt request occurs when a data reception has completed before the previously re - ceived data in the spi receive data register ( 0x301700 ) is read out. at this time, the cause-of-interrupt flag fp 8 (d 0 / 0 x 3002 a 9 ) in the itc is set to 1 if both roie and irqe (d 0 ) have been set to 1 (enabled). when roie is set to 0 , spi interrupts caused by receive data overflow are not generated. d2 rfie: receive data full interrupt enable bit enables/disables spi interrupt caused by receive data full. 1 (r/w): enable 0 (r/w): disable (default) when rfie is set to 1 , spi (receive data full) interrupt requests to the itc are enabled. a receive data full interrupt request occurs when the data received in the shift register is loaded to the spi receive data register ( 0x301700 ) (receive operation completed). at this time, the cause-of-interrupt flag fp8 (d0/0x3002a9) in the itc is set to 1 if both rfie and irqe (d0 ) have been set to 1 (enabled). when rfie is set to 0 , spi interrupts caused by receive data full are not generated. d1 mirq: manual irq set/clear bit generates an spi interrupt request to the itc by manual control . 1 (r/w): set irq 0 (r/w): clear irq (default) if mirq is set to 1 when irqe (d0 ) is set to 1 , the spi interrupt request signal to be delivered to the itc becomes active. as a result, the cause-of-interrupt flag fp 8 (d0/0x3002a9) in the itc is set to 1. when mirq is set to 0 , the spi interrupt request signal becomes inactive (interrupt request is cleared). however, the cause-of-interrupt flag fp 8 (d0/0x3002a9) cannot be cleared to 0 by writing 0 to this bit.
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-22 epson s1c33e08 technical manual d0 irqe: interrupt request enable bit enables/disables spi interrupt requests to the itc. 1 (r/w): enable 0 (r/w): disable (default) when irqe is set to 1 , spi interrupt requests to the itc are enabled. an interrupt request is generated and the cause-of-interrupt flag fp 8 (d0/0x3002a9 ) is set to 1 when an enabled cause of spi interrupt occurs or mirq (d1) is set to 1 manually. when irqe is set to 0 , an spi interrupt request to the itc is not generated even if the spi interrupt for each cause is enabled. also manual interrupt requests using mirq (d 1) are disabled.
v peripheral modules 3 (interface): serial peripheral interface (spi) s1c33e08 technical manual epson v-2-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30171c: spi receive data mask register (pspi_rxmk) name address register name bit function setting init. r/w remarks C 0x0 to 0x1f C C C rxmask4 rxmask3 rxmask2 rxmask1 rxmask0 C rxme C d31C15 d14 d13 d12 d11 d10 d9C2 d1 d0 reserved bit mask for reading received data reserved receive data mask enable reserved C 0 0 0 0 0 C 0 C C r/w C r/w C 0 when being read. 0 when being read. do not write 1. 0030171c (w) 1 enabled 0 disabled spi receive data mask register (pspi_rxmk) d[31:15] reserved d[14:10] rxmask[4:0]: receive data mask setup bits specifies the number of bits for data mask when reading only the required lower bits of the receive data. (default: 0x0) set the msb of the effective bits (e.g., 31 = not masked, 15 = d[31:16 ] is masked). to enable the bit mask using rxmask[ 4:0 ], set rxme (d1 ) to 1 . when the specified bit mask is enabled, the received data is read out with the masked bits set to 0 from the spi receive data register (0x301700). d[9:2] reserved d1 rxme: receive data mask enable bit enables the rxmask[ 4:0] (d[14:10]) setting. 1 (r/w): enable 0 (r/w): disable (default) by setting rxme to 1 , the upper bits of the received data are masked (set to 0 ) according to the rx - mask[ 4:0 ] setting when it is loaded from the receive data buffer to the spi receive data register (0x301700). by setting rxme to 0 , the upper bits of the received data that exceed the data bit length specified with bpt[4:0 ] (d[14:10]/0x301708 ) are masked (set to 0 ) when it is loaded from the shift register to the spi receive data register ( 0x301700). figure v. 2.7.2 shows the relationship between the mask control bit settings and the receive data loaded to the spi receive data register ( 0x301700). d0 reserved do not set this bit to 1. d0 dn 0 0 d 0 shift register spi receiv e data register rxme = 0 (def ault) v alid data v alid data bpt[4:0] + 1 (bits) 0 0 dm dm d0 shift register spi receiv e b uff er spi receiv e data register rxme = 1 dn mask ed d31 rxmask[4:0] + 1 (bits) d0 dn 0 0 d 0 bpt[4:0] + 1 (bits) dn mask ed d31 mask ed figure v. 2.7.2 receive data mask
v peripheral modules 3 (interface): serial peripheral interface (spi) v-2-24 epson s1c33e08 technical manual v. 2.8 precautions ? be sure to use 32 -bit access instructions for reading/writing from/to the spi control registers (0x301700 to 0x30171 c). the spi control registers do not allow reading/writing using 16-bit and 8-bit access instructions. ? do not access the spi control register 1 (0x301708 ), spi control register 2 (0x30170 c), and spi wait register (0x301710) while the bsyf (d6/0x301714) is set to 1 (during data transfer). ? bsyf : transfer busy flag in the spi status register (d6/0x301714) ? to prevent malfunctions, write 0x0 to the spi interrupt control register (0x301718 ) to disable all the spi inter - rupt requests, before disabling the spi circuit (before setti ng ena (d0/0x301708) to 0). ? ena : spi enable bit in the spi control register 1 (d0/0x301708)
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 3 direction control serial interface (dcsio) v. 3.1 outline of dcsio the s 1c33e08 has a built-in dcsio module that is composed of two bidirectional single-wire serial buses. it features a simple structure for high-speed and efficient data transfer. by using one channel for clock output, an i 2 c interface can be realized with software control. the following shows its features: ? maximum transfer rate: 400 kbps (when a 48-mhz system clock is used) ? data width: 8 bits ? programmable bit-rate configuration ? supports clock stretch (software control wait cycle insertion). clock can be controlled as a bit stream. ? data transfer direction (msb first/lsb first) is selectable. ? monitors both lines even in output mode and records output data as received data. ? supports two interrupt sources (receive data full and transmit data empty). ? supports single master mode only. any transfer protocol may be used without constraints. multiple slave devices are connectable to the serial bus (no master device is connectable). figure v. 3.1.1 shows the structure of the dcsio module. mclk to itc sramc dcsio0 line a interface (shift register a) dcsio1 line b interface (shift register b) line b transmit data register line b receive data register interrupt control internal bus interface clock control/ transfer control line a transmit data register line a receive data register figure v. 3.1.1 structure of dcsio module
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-2 epson s1c33e08 technical manual v. 3.2 i/o pins of dcsio table v. 3.2.1 lists the i/o pins used by the dcsio module. table v. 3.2.1 dcsio pin configuration pin name dcsio0 dcsio1 i/o i/o i/o function line a input/output (data input/output or cloc k output) line b input/output (data input/output or cloc k output) dcsio0 pin this is the input/output pin of the line a serial bus. dcsio1 pin this is the input/output pin of the line b serial bus. note : the dcsio input/output pins are shared with general-purpose i/o ports or other peripheral circuit inputs/outputs, so that functionality in the initial state is set to other than the dcsio input/output. before the dcsio input/output signals assigned to these pins can be used, the function of these pins must be switched for the dcsio input/output by setting the corresponding port function select registers. for details of pin functions and how to switch over, see section i.3.3, switching over the multiplexed pin functions.
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 3.3 dcsio operating clock the dcsio module use the dcsio_clk clock (= mclk) generated by the cmu as the operating clock. the transfer clock is generated in the dcsio module by dividing dcsio_clk. controlling the supply of the operating clock dcsio_clk is supplied to the dcsio module with default settings. it can be turned off using dcsio_cke (d10/0x301b04) to reduce the amount of power consumed on the chip if the dcsio module is not used. ? dcsio_cke : dcsio clock control bit in the gated clock control register 1 (d10/0x301b04) setting dcsio_cke (d 10/0x301b04) to 0 (1 by default) turns off the clock supply to the dcsio module. when the clock supply is turned off, the dcsio module control registers cannot be accessed. for details on how to set and control the clock, refer to section iii. 1, clock management unit (cmu). note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be removed by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless rewriting said registers. clock state in standby mode the clock supply to the dcsio module stops depending on type of standby mode. halt mode: the operating clock is supplied the same way as in normal mode. sleep mode: the operating clock supply stops. therefore, the dcsio module also stops operating in sleep mode.
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-4 epson s1c33e08 technical manual v. 3.4 setting dcsio module when performing data transfers via the dcsio bus, the following settings must be made before data transfer is actually begun: 1. setting input/output pins 2. setting base line and transfer rate 3 . setting data transfer direction (msb first/lsb first) 4. setting interrupts and idma/hsdma the following explains the content of each setting. for details on interrupt/dma settings, refer to section v. 3.6, dcsio interrupts and dma. note : always make sure the dcsio module is inactive ( dcsioen (d 0/0x301800) = 0) before these settings are made. a change of settings during operation may cause a malfunction. ? dcsioen : dcsio enable bit in the dcsio control register (d0/0x301800) setting input/output pins the dcsio 0 and dcsio1 pins are used for dcsio. configure the port function select registers to enable these pin functions. for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. set line a and line b in output mode using dira[ 1 : 0 ] (d[ 3 : 2 ]/ 0 x 30181 c) and dirb[ 1 : 0 ] (d[ 1 : 0 ]/ 0 x 30181 c), respectively. as shown in table v. 3.4.1, either open-drain or push-pull is selectable for output. ? dira[1:0] : line a direction select bits in the dcsio port direction control register (d[3:2]/0x30181c) ? dirb[1:0] : line b direction select bits in the dcsio port direction control register (d[1:0]/0x30181c) table v. 3.4.1 selecting input/output mode dira0/dirb0 ? 1 0 input/output mode input only input/push-pull output input/open-drain output dira1/dirb1 1 0 0 (default: 0b00 = input/open-drain output) setting base line and transfer rate first, select either line a (dcsio 0 ) or line b (dcsio1 ) as the base line (normally used for a clock output) using basesel (d 2/0x301800 ). set basesel (d2/0x301800 ) to 1 when using line a as the base line, or set it to 0 when using line b as the base line. ? basesel : base line select bit in the dcsio control register (d2/0x301800) next, configure the transfer rate of the base line using divrt[ 7:0] (d[15:8]/0x301800). ? divrt[7:0] : dcsio system clock baud rate setup bits in the dcsio control register (d[15:8]/0x301800) f dcsio_clk divrt = 2 bps divrt: divrt[ 7:0] (d[15:8]/0x301800 ) set value (cannot be set to less than two) f dcsio_clk : dcsio input clock frequency (= mclk hz) bps: transfer rate (bits/second) for example, to configure the transfer rate to 400 kbps when the cpu runs with a 48 mhz clock, set divrt[ 7:0] (d[15:8]/0x301800) to 60 (0x3c). the transfer rate of the other line (non-base line) can be selected as shown in table v. 3.4.2 using advrate (d3/0x301800). ? advrate : non-base line transfer rate setup bit in the dcsio control register (d3/0x301800) table v. 3.4.2 transfer rate of non-base line advrate 1 0 transfer rate base line 1/8 = base line
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 figure v. 3.4.1 shows the data formats according to the advrate (d3/0x301800 ) set value. d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 transfer clock dcsio0(o) dcsio1(o) advrate = 0 (= base line), basesel = 0 (line b) d7' d6' d5 ' d4' d3' d2' d1 ' d0' d7 ' d6' d5' d4 ' d3' d2' d1' d0 ' d7' d6' d5' d4' d3' d2 ' d1' d0' transfer clock dcsio0(o) dcsio1(o) advrate = 1 (base line 1/8), basesel = 0 (line b) d7' d6' d5 ' d4' d3' d2' d1 ' d0' d7 ' d6' d5' d2' d1' d0 ' d7' d6' d5' d4' d3' d2 ' d1' d0' d7 d0 figure v. 3.4.1 dcsio data formats (msb first) when advrate (d 3/0x301800 ) is set to 1 (base line 1/8 ), the base line transmits the same 8 -bit data eight times while the non-base line performs one 8 -bit data transfer. furthermore, the txbe (d1/0x301818 ) and rxbf (d2/0x301818 ) flags (see section v.3.5 ) will be active depending on the non-base line condition only. setting data transfer direction (msb first/lsb first) use lsbfirst (d 1/0x301800 ) to select whether data is input/output from the msb first or the lsb first. when lsbfirst (d 1/0x301800 ) = 0 (default), msb first is selected and when lsbfirst (d1/0x301800 ) is set to 1 , lsb first is selected. ? lsbfirst : lsb first select bit in the dcsio control register (d1/0x301800) example of transmit/receive bit configurations the following shows example of transmit/receive bit configurations. example 1 bit 8 bit 7 bit 1 dcsio0 dcsio1 transmission pin dcsio0 dcsio1 dira/dirb 00 00 advrate 1 (bl 1/8) basesel 0 (b) lsbfirst 0 (msb) txd bit[8:1] 0x3c rxd bit[8:1] C reception pin dcsio0 dcsio1 dira/dirb 00 00 advrate 1 (bl 1/8) basesel 0 (b) lsbfirst 0 (msb) txd 0xff 0x3c rxd bit[8:1] C example 2 dcsio0 dcsio1 transmission pin dcsio0 dcsio1 dira/dirb 00 00 advrate 0 (bl) basesel 0 (b) lsbfirst 0 (msb) txd 0xc0 0xfc rxd 0xf0 C reception pin dcsio0 dcsio1 dira/dirb 00 00 advrate 0 (bl) basesel 0 (b) lsbfirst 0 (msb) txd 0xff 0xfc rxd 0xf0 C
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-6 epson s1c33e08 technical manual example 3 dcsio0 dcsio1 transmission pin dcsio0 dcsio1 dira/dirb 00 00 advrate 0 (bl) basesel 0 (b) lsbfirst 0 (msb) txd 0x03 0x3f rxd 0x0f or 0x07 ? 1 C reception pin dcsio0 dcsio1 dira/dirb 00 00 advrate 0 (bl) basesel 0 (b) lsbfirst 0 (msb) txd 0xff 0x3f rxd 0x0f or 0x07 ? 1 C example 4 dcsio0 dcsio1 transmission pin dcsio0 dcsio1 dira/dirb 00 00 advrate 0 (bl) basesel 0 (b) lsbfirst 0 (msb) txd 0xff 0x3c rxd 0xff or 0x3c ? 2 C reception pin dcsio0 dcsio1 dira/dirb 00 00 advrate 0 (bl) basesel 0 (b) lsbfirst 0 (msb) txd 0xff 0x3c rxd 0xff or 0x3c ? 2 C ? 2 ? 2 example 5 dcsio0 dcsio1 transmission pin dcsio0 dcsio1 dira/dirb 00 00 advrate 0 (bl) basesel 0 (b) lsbfirst 0 (msb) txd 0x00 0x3c rxd 0x00 C reception pin dcsio0 dcsio1 dira/dirb 00 00 advrate 0 (bl) basesel 0 (b) lsbfirst 0 (msb) txd 0xff 0x3c rxd 0x00 or 0xc3 ? 2 C ? 2 ? 2 ?1 note that the open-drain output signals may rise very slowly when they change from 0 to 1 , and the rising waveform depends on the pull-up resistor. ?2 note that the receive data and high-level open-drain output signals outside the range indicated by the dashed lines are controlled by external devices.
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 3.5 control of data transfer preparation for data transfer perform the following procedure before starting data transfer: 1 . set up the dcsio conditions as described in the previous section. 2 . set up the interrupt and dma conditions using the itc registers and the dcsio interrupt control register (explained later). when using the dcsio interrupt, the cause of dcsio interrupt flag in the itc must be cleared before enabling the interrupt. 3 . write 1 to the dcsioen (d0/0x301800) to turn the dcsio circuit on. the dcsio circuit starts frequency division of the source clock. ? dcsioen : dcsio enable bit in the dcsio control register (d0/0x301800) the following explains how to control data transfer assuming that line a is used for data transfer, line b is used for clock output, and the transfer rate of line a is set to line b (base line) 1/8. data transmission write a transmit data to txda[ 7:0 ] (d[23:16 ]/0x301804 ) and a bit stream of the clock (e.g., 00001111 ) to txdb[ 7:0 ] (d[7:0 ]/0x301804 ). be sure to write these data simultaneously as these bits are assigned in the same register. ? txda[7:0] : line a transmit data bits in the dcsio data load register (d[23:16]/0x301804) ? txdb[7:0] : line b transmit data bits in the dcsio data load register (d[7:0]/0x301804) dcsio starts data transmission by writing data to the dcsio dat a load register (d[ 23:16]/0x301804). the dcsio circuit loads the data written to the register into the respective shift registers. the data bits in the shift registers are shifted one by one at the rising edge of the transfer clock and are output from the dcsio 0 and dcsio 1 pins. data is output from the msb or the lsb according to the lsbfirst (d1/0x301800 ) set value. ? lsbfirst : lsb first select bit in the dcsio control register (d1/0x301800) the dcsio circuit provides txbe (d 1/0x301818 ) to indicate the dcsio data load register (0x301804) status. this flag is reset to 0 (not empty) when data is written to the dcsio data load register (0x301804) and is set to 1 (empty) when the written data is loaded into the shift register. an interrupt can be generated simultaneously with this flag set to 1 . check to see if the txbe (d1/0x301818 ) is set to 1 by polling or using this interrupt before the next transmit data can be written to the dcsio data load register ( 0x301804). ? txbe : transmit data empty flag in the dcsio status register (d1/0x301818) the dcsio circuit continues data output until the 8-bit data has been transmitted. advrate (d 3/0x301800 ) is set to 1 (base line 1/8 ) in this example, therefore, line b transmits the contents of txdb[ 7:0] (d[7:0]/0x301804) 8 times while line a transmits an 8-bit data. if the next transmit data exists in the dcsio data load register ( 0x301804 ) when a data transfer has finished, the dcsio circuit repeats the same transmit operation as above. if no data exists, data transfer is terminated. the dcsio 0 and dcsio1 pins maintain the status of the last bit transmitted. it continues until the next data transfer is started, 0 is written to dcsioen (d0/0x301800 ), or the s1c33e08 is reset. the transmitter/receiver status sets/resets busy (d 0/0x301818 ). busy (d0/0x301818 ) is set to 1 when data is being transferred and reset to 0 upon completion of a data transfer. use this flag to check if a data transfer has completed. ? busy : dcsio busy flag in the dcsio status register (d0/0x301818)
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-8 epson s1c33e08 technical manual (divrt[ 7:0] = 2 , base line = b, a = b 1/8, msb first) mclk dcsioen tr ansf er cloc k txd a[7:0] shift register a dcsio0 pin txdb[7:0] shift register b dcsio1 pin busy txbe interr upt wr ite the ne xt data can be wr itten. 01011111 01011111 wr ite 00001111 00001111 00011110 00111100 01111000 11110000 11100001 11000011 10000111 00001111 10111110 1 mclk cycle dela y 1 mclk cycle dela y figure v. 3.5.1 data transmit timing chart (at start of transmission) mclk dcsioen tr ansf er cloc k txd a[7:0] shift register a dcsio0 pin txdb[7:0] shift register b dcsio1 pin busy txbe interr upt 10101111 00001111 00001111 01011111 01011111 00001111 00011110 00111100 01111000 11110000 11100001 11000011 10000111 figure v. 3.5.2 data transmit timing chart (at end of transmission)
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 data reception the dcsio module monitors both lines and records the line status as receive data regardless of how dira (d[3:2]/0x30181 c) and dirb (d[1:0]/0x30181 c) are configured. a receive operation starts at the same time a data transmission starts, so writing to the dcsio data load register ( 0x301804 ) is also used as a trigger. the data bits are fetched in the shift register one by one at the rising edge of the transfer clock from the msb or lsb according to the lsbfirst (d1/0x301800 ) set value. when an 8 -bit data is received in the shift register, the received data is loaded to rxda[7:0 ] (d[23:16 ]/ 0x301808 ) in line a or rxdb[7:0] (d[7:0]/0x301808) in line b. ? rxda[7:0] : line a receive data bits in the dcsio receive data register (d[23:16]/0x301808) ? rxdb[7:0] : line b receive data bits in the dcsio receive data register (d[7:0]/0x301808) at the same time, rxbf (d 2/0x301818 ) is set to 1 (data full) to indicate that the receive data can be read from the dcsio receive data register ( 0x301808 ) and a data receive interrupt can be generated. ? rxbf : receive data full flag in the dcsio status register (d2/0x301818) check to see if the rxbf (d 2/0x301818 ) is set to 1 by polling or using the interrupt and read data from the dcsio receive data register ( 0x301808 ). when data is read from the dcsio receive data register (0x301808), rxbf (d2/0x301818) is cleared to 0. to receive data successively, write 0 xff to txda[7:0 ] (d[23:16 ]/0x301804 ) every time an 8 -bit data is received. the dcsio circuit continues the receive operation when data has been written to the dcsio data load register ( 0x301804). busy (d 0/0x301818) is set to 1 when data is being received. (divrt[ 7:0] = 2 , base line = b, a = b 1/8, msb first) mclk dcsioen tr ansf er cloc k txd a[7:0] dcsio0 pin shift register a rxd a[7:0] txdb[7:0] shift register b dcsio1 pin busy txbe rxbf interr upt wr ite the ne xt data can be wr itten. 11111111 11111111 pre vious receiv ed data wr ite 00001111 00001111 11111110 tr ansmit data empty 00001111 00011110 00111100 01111000 11110000 11100001 11000011 10000111 1 mclk cycle dela y figure v. 3.5.3 data receive timing chart (at start of reception)
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-10 epson s1c33e08 technical manual mclk dcsioen tr ansf er cloc k txd a[7:0] dcsio0 pin shift register a rxd a[7:0] txdb[7:0] shift register b dcsio1 pin busy txbe rxbf interr upt 10xxxxxx (t0, r7Cr1) 00001111 0xxxxxx0 (r7Cr0) receiv e data full 11111111 pre vious receiv ed data 0xxxxxx0 00001111 00011110 00111100 01111000 11110000 11100001 11000011 10000111 figure v. 3.5.4 data receive timing chart (at end of reception) terminating data transfer after all data has been transmitted/received, write 0 to dcsioen (d0/0x301800 ) to turn the dcsio circuit off.
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 3.6 dcsio interrupts and dma causes of dcsio interrupt the dcsio module can generate the following two types of interrupts: ? transmit data empty ? receive data full this interrupt request circuit is configured as figure v. 3.6.1 and it allows selection of one or more causes of interrupt. interr upt request (int_dcsio) inten(d0/0x301814) txbeen(d1/0x301814) tr ansmit data empty (txbe) rxbfen(d2/0x301814) receiv e data full (rxbf) figure v. 3.6.1 dcsio interrupt request circuit to output the dcsio interrupt requests, enable interrupts of the causes described below and set inten (d 0/ 0x301814) to 1 . when inten (d0/0x301814) is set to 0, no dcsio interrupt request is output. ? inten : dcsio interrupt request enable bit in the dcsio interrupt control register (d0/0x301814) transmit data empty this cause of interrupt occurs when the transmit data set in the dcsio data load register ( 0x301804 ) is transferred to the shift register, in which case txbe (d 1/0x301818 ) is set to 1 . set txbeen (d1/0x301814 ) to 1 to output an interrupt request by this cause of interrupt. ? txbe : transmit data empty flag in the dcsio status register (d1/0x301818) ? txbeen : transmit data empty interrupt enable bit in the dcsio interrupt control register (d1/0x301814) receive data full this cause of interrupt occurs when the data received in the shift register is loaded into the dcsio receive data register ( 0x301808 ), in which case rxbf (d2/0x301818 ) is set to 1 . set rxbfen (d2/0x301814 ) to 1 to output an interrupt request by this cause of interrupt. ? rxbf : receive data full flag in the dcsio status register (d2/0x301818) ? rxbfen : receive data full interrupt enable bit in the dcsio interrupt control register (d2/0x301814) the dcsio interrupt request is sent to the itc as the port 11 input interrupt (fpt11 ) signal and it sets the cause-of-interrupt flag fp 11 (d3/0x3002a9 ) in the itc to 1 . however, int_dcsio must be selected for the port 11 input interrupt. control registers of the interrupt controller table v. 3.6.1 shows the interrupt controller's control registers provided for the dcsio interrupt. table v. 3.6.1 control register of interrupt controller interrupt dcsio interr upt cause-of-interrupt fla g fp11(d3/0x3002a9) interrupt priority register pp11l[2:0](d[6:4]/0x3002a1) interrupt enable register ep11(d3/0x3002a6) when a cause of interrupt described above occurs, the cause-of-interrupt flag is set to 1 . if the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit for that cause of interrupt set to 0 . the cause-of-interrupt flag is set to 1 whenever interrupt conditions are met, regardless of the setting of the interrupt enable register (even if it is set to 0).
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-12 epson s1c33e08 technical manual the interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7 . an interrupt request to the cpu is accepted only when no other interrupt request of a higher priority has been generated. in addition, only when the psr's ie bit = 1 (interrupts enabled) and the set value of the il is smaller than the input interrupt level set by the interrupt priority register, will the input interrupt request actually be accepted by the cpu. for details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to section iii.2, interrupt controller (itc). note : the dcsio interrupt request signal is input to the port 11 input interrupt (fpt11) system. the port 11 input interrupt circuit is configured by selecting a port (signal) to be used for generating an interrupt from p93, int_dcsio, p83, and p73. when using the dcsio interrupt, set sptb[1:0] (d[7:6]/0x3003c4) to 10 to select int_dcsio. this setting enables the int_dcsio signal to be sent to the itc as the port 11 input interrupt signal. furthermore, septb (d3/0x3003c7) for selecting a trigger mode of the fpt11 input signal should be set to 0 (level) and spptb (d3/ 0x3003c6) for selecting a polarity of the fpt11 input signal should be set to 1 (high level). ? sptb[1:0] : fpt11 interrupt input port select bits in the port input interrupt select register 3 (d[7:6]/0x3003c4) ? spptb : fpt11 input polarity select bit in the port input interrupt polarity select register 2 (d3/0x3003c6) ? septb : fpt11 edge/level select bit in the port input interrupt edge/level select register 2 (d3/0x3003c7) intelligent dma the dcsio interrupt request can be used to invoke intelligent dma (idma). this enables data transfer between memory and the transmit/receive data registers to be performed using dma. the idma channel numbers set for the cause of dcsio interrupt i s 0x29. the idma request and enable bits shown in table v. 3.6.2 must be set to 1 for idma to be invoked. transfer conditions, etc. on the idma side must also be set in advance. table v. 3.6.2 control bits for idma transfer interrupt dcsio interr upt idma request bit rp11(d3/0x3002a c) idma enable bit dep11(d3/0x3002ae) if a cause of interrupt occurs when the idma request and enable bits are set to 1 , idma is invoked. no interrupt request is generated at that point. an interrupt request is generated upon completion of the dma transfer. the bits can also be set so as not to generate an interrupt, with only a dma transfer performed. for details on dma transfer and how to control interrupts upon completion of dma transfer, refer to section ii.2, intelligent dma (idma). high-speed dma the dcsio interrupt (fpt 11 interrupt) can also invoke high-speed dma (hsdma). the following shows the hsdma channel number and trigger set-up bit corresponding to the dcsio interrupt: table v. 3.6.3 hsdma trigger set-up bits interrupt dcsio interr upt hsdma ch. 3 t rigger set-up bits hsd3s[3:0] (d[7:4]) / hsdma ch.2C3 tr igger set-up register (0x300299) for hsdma to be invoked by a dcsio interrupt (fpt 11 interrupt) request, the trigger set-up bits for hsdma ch.3 should be set to 1101. the hsdma channel is invoked through generation of the cause of interrupt. for details on hsdma transfer, refer to section ii. 1, high-speed dma (hsdma). trap vectors the default trap-vector address of the cause of dcsio interrupt is 0xc0015c. the base address of the trap table can be changed using the ttbr register.
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 3.7 details of control registers table v. 3.7.1 list of dcsio registers address 0x00301800 0x00301804 0x00301808 0x00301814 0x00301818 0x0030181c function sets dcsio transfer conditions. transmit data receive data controls dcsio interrupts. dcsio status controls data input/output direction. register name dcsio control register (pdcsio_ctl) dcsio data load register (pdcsio_load) dcsio receive data register (pdcsio_rcv) dcsio interrupt control register (pdcsio_int) dcsio status register (pdcsio_stat) dcsio port direction control register (pdcsio_dir) siz e 32 32 32 32 32 32 the following describes each dcsio control register. the dcsio control registers are mapped in the 32 -bit device area from 0x301800 to 0x30181c , and can be accessed in units of words, half-words, or bytes except for 0x301804. notes : ? the dcsio data load register (0x301804 ) allow accessing in word size only. do not read/ write the registers in half-word or byte size. ? when setting the dcsio control registers, be sure to write a 0 , and not a 1 , for all reserved bits.
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-14 epson s1c33e08 technical manual 0x301800: dcsio control register (pdcsio_ctl) name address register name bit function setting init. r/w remarks C divrt7 divrt6 divrt5 divrt4 divrt3 divrt2 divrt1 divrt0 C advrate basesel lsbfirst dcsioen d31C16 d15 d14 d13 d12 d11 d10 d9 d8 d7C4 d3 d2 d1 d0 reserved dcsio system clock baud rate setup (divrt must be 2 or more.) reserved non-base line transfer rate setup base line selection lsb first selection dcsio enable C 0 0 0 0 0 0 0 0 C 0 0 0 0 C r/w C r/w r/w r/w r/w 0 when being read. 0 when being read. 00301800 (w) dcsio control register (pdcsio_ctl) C baud rate = f mclk /(divrt 2) C 0 1 a b 0 1 base 1/8 = base line 0 1 lsb first msb first 0 1 enabled disabled d[31:16] reserved d[15:8] divrt[7:0]: dcsio system clock baud rate setup bits sets the transfer rate for the base line. (default: 0x0) f dcsio_clk divrt = 2 bps divrt: divrt[ 7:0 ] set value (cannot be set to less than two) f dcsio_clk : dcsio input clock frequency (= mclk hz) bps: transfer rate (bits/second) d[7:4] reserved d3 advrate: non-base line transfer rate setup bit sets the transfer rate for the non-base line. 1 (r/w): base line 1/8 0 (r/w): same as base line (default) when advrate is set to 1 (base line 1/8 ), the base line transmits the same 8 -bit data 8 times while the non-base line performs an 8 -bit data transfer. d2 basesel: base line select bit selects the base line. 1 (r/w): line a (dcsio0) 0 (r/w): line b (dcsio1 ) (default) normally, select the line to be used for clock output as the base line. d1 lsbfirst: lsb first select bit selects either msb first or lsb first as the data direction. 1 (r/w): lsb first 0 (r/w): msb first (default) this setting applies to both line a and line b. d0 dcsioen: dcsio enable bit enables/disables operation of the dcsio module. 1 (r/w): enable (on) 0 (r/w): disable (off) (default) when dcsioen is set to 1, the dcsio module starts operating and data transfer is enabled. when dcsioen is set to 0 , the dcsio module goes off. make sure that this bit is 0 before setting up data transfer conditions using the dcsio registers.
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301804: dcsio data load register (pdcsio_load) name address register name bit function setting init. r/w remarks C txda7 txda6 txda5 txda4 txda3 txda2 txda1 txda0 C txdb7 txdb6 txdb5 txdb4 txdb3 txdb2 txdb1 txdb0 d31C24 d23 d22 d21 d20 d19 d18 d17 d16 d15C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved line a transmit data reserved line b transmit data C 1 1 1 1 1 1 1 1 C 1 1 1 1 1 1 1 1 C r/w C r/w 0 when being read. 0 when being read. 00301804 (w) dcsio data load register (pdcsio_load) C 0x0 to 0xff C 0x0 to 0xff note : this register allow accessing in word size only. do not read/write the registers in half-word or byte size. sets transmit data. the data transmission begins by writing data to this register. txbe (d 1/0x301818 ) is set to 1 (empty) when the line a and line b data written to this register are transferred to the respective shift registers. a cause of transmit data empty interrupt is simultaneously generated. the next transmit data can be written to the register at any time thereafter, even when the dcsio is sending data. the serial-converted data is output from the dcsio x pin beginning with the msb or lsb selected with lsbfirst (d1/0x301800 ), in which the bits set to 1 are output as high-level signals and those set to 0 output as low-level signals. writing to this register also starts a data receive operation (transmission and reception are performed simultaneously using the same shift register). the transmit data for the receive line should be set to 0 xff. d[31:24] reserved d[23:16] txda[7:0]: line a transmit data bits sets transmit data for line a. (default: 0xff) d[15:8] reserved d[7:0] txdb[7:0]: line b transmit data bits sets transmit data for line b. (default: 0xff)
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-16 epson s1c33e08 technical manual 0x301808: dcsio receive data register (pdcsio_rcv) name address register name bit function setting init. r/w remarks C rxda7 rxda6 rxda5 rxda4 rxda3 rxda2 rxda1 rxda0 C rxdb7 rxdb6 rxdb5 rxdb4 rxdb3 rxdb2 rxdb1 rxdb0 d31C24 d23 d22 d21 d20 d19 d18 d17 d16 d15C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved line a receive data reserved line b receive data C 1 1 1 1 1 1 1 1 C 1 1 1 1 1 1 1 1 C r C r 0 when being read. 0 when being read. 00301808 (w) dcsio receive data register (pdcsio_rcv) C 0x0 to 0xff C 0x0 to 0xff stores received data. when a receive operation is completed and the line a and line b data received in the shift registers are loaded to this register, rxbf (d 2/0x301818 ) is set to 1 (data full). at the same time, a cause of receive data full interrupt occurs. thereafter, the data can be read out at any time before a receive operation for the next data is completed. if the next data receive operation is completed before this register is read out, the data in it is overwritten with the newly received data. the serial data input from the dcsio x pin is converted into parallel data, with the high-level signals changed to 1s and the low-level signals changed to 0 s. the resulting data is stored in this register. this register is a read-only register, so no data can be written to it. d[31:24] reserved d[23:16] rxda[7:0]: line a receive data bits line a receive data is stored. (default: 0xff) d[15:8] reserved d[7:0] rxdb[7:0]: line b receive data bits line b receive data is stored. (default: 0xff)
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301814: dcsio interrupt control register (pdcsio_int) name address register name bit function setting init. r/w remarks C C rxbfen txbeen inten d31C3 d2 d1 d0 reserved receive data full interrupt enable transmit data empty int. enable dcsio interrupt request enable C 0 0 0 C r/w r/w r/w 0 when being read. 00301814 (w) 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled dcsio interrupt control register (pdcsio_int) d[31:3] reserved d2 rxbfen: receive data full interrupt enable bit enables/disables dcsio interrupt caused by receive data full. 1 (r/w): enable 0 (r/w): disable (default) when rxbfen is set to 1 , dcsio (receive data full) interrupt requests to the itc are enabled. a receive data full interrupt request occurs when the data received in the shift register is loaded to the dcsio receive data register ( 0x301808 ) (receive operation completed). at this time the cause-of- interrupt flag fp 11 (d3/0x3002a9 ) in the itc is set to 1 if both rxbfen and inten (d0 ) have been set to 1 (enabled). when rxbfen is set to 0 , dcsio interrupts caused by receive data full are not generated. d1 txbeen: transmit data empty interrupt enable bit enables/disables dcsio interrupt caused by transmit data empty. 1 (r/w): enable 0 (r/w): disable (default) when txbeen is set to 1 , dcsio (transmit data empty) interrupt requests to the itc are enabled. a transmit data empty interrupt request occurs when the data written to the dcsio data load register (0x301804 ) is transferred to the shift register (transmit operation started). at this time the cause-of- interrupt flag fp 11 (d3/0x3002a9 ) in the itc is set to 1 if both txbeen and inten (d0 ) have been set to 1 (enabled). when txbeen is set to 0, dcsio interrupts caused by transmit data empty are not generated d0 inten: dcsio interrupt request enable bit enables/disables dcsio interrupt requests to the itc. 1 (r/w): enable 0 (r/w): disable (default) when inten is set to 1 , dcsio interrupt requests to the itc are enabled. an interrupt request is generated and the cause-of-interrupt flag fp 11 (d3/0x3002a9 ) is set to 1 when an enabled cause of dcsio interrupt occurs. when inten is set to 0 , a dcsio interrupt request to the itc is not generated even if the dcsio interrupt for each cause is enabled.
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-18 epson s1c33e08 technical manual 0x301818: dcsio status register (pdcsio_stat) name address register name bit function setting init. r/w remarks C C rxbf txbe busy d31C3 d2 d1 d0 reserved receive data full flag transmit data empty flag dcsio busy flag C 0 0 0 C r r r 0 when being read. 00301818 (w) 1 empty 0 not empty 1 full 0 not full 1 busy 0 idle dcsio status register (pdcsio_stat) d[31:3] reserved d2 rxbf: receive data full flag indicates the dcsio receive data register ( 0x301808) status. 1 (r): data full 0 (r): not full (default) rxbf is set to 1 when the data received in the shift register is loaded to the dcsio receive data register ( 0x301808 ) (receive operation completed), indicating that the received data can be read out. this bit is reset to 0 when the data is read out. d1 txbe: transfer data empty flag indicates the dcsio data load register ( 0x301804) status. 1 (r): empty 0 (r): not empty (default) txbe is cleared to 0 when transmit data is written to the dcsio data load register (0x301804) and is set to 1 when the written data is transferred to the shift register (transmit operation started). transmit data can be written to the dcsio data load register ( 0x301804) when this bit = 1. d0 busy: dcsio busy flag indicates the dcsio transmit/receive operation status. 1 (r): busy 0 (r): idle (default) busy is set to 1 when the dcsio starts data transmission/reception and stays 1 while data transmission/reception is in progress. busy is cleared to 0 upon completion of transmit/receive operation.
v peripheral modules 3 (interface): direction control serial interface (dcsio) s1c33e08 technical manual epson v-3-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30181c: dcsio port direction control register (pdcsio_dir) name address register name bit function setting init. r/w remarks C dira1 dira0 dirb1 dirb0 d31C4 d3 d2 d1 d0 reserved line a direction select line b direction select C 0 0 0 0 C r/w r/w 0 when being read. 0030181c (w) 1 ? 01 00 dira[1:0] i/o input only input/push-pull output input/open-drain output 1 ? 01 00 dirb[1:0] i/o input only input/push-pull output input/open-drain output dcsio port direction control register (pdcsio_dir) C this register is used to select the data input/output direction for line a and line b individually as shown in table v. 3.7.2. table v. 3.7.2 selecting data input/output direction dira0/dirb0 ? 1 0 input/output mode input only input/push-pull output input/open-drain output dira1/dirb1 1 0 0 (default: 0b00 = input/open-drain output) d[31:4] reserved d[3:2] dira[1:0]: line a direction select bits selects the data input/output direction for line a. d[1:0] dirb[1:0]: line b direction select bits selects the data input/output direction for line b.
v peripheral modules 3 (interface): direction control serial interface (dcsio) v-3-20 epson s1c33e08 technical manual v. 3.8 precautions ? be sure to use 32 -bit access instructions for reading/writing from/to the dcsio data load register (0x301804). transmit data for line a and line b must be written simultaneously. ? to prevent malfunctions, write 0x0 to the dcsio interrupt control register (0x301814) to disable all the dcsio interrupt requests, before disabling the dcsio circuit (before setting dcsioen (d0/0x301800) to 0). ? dcsioen : dcsio enable bit in the dcsio control register (d0/0x301800) ? when using the dcsio ports as input/open-drain output ports (default configuration), be sure to enable the internal pull-up resistor (refer to section iii. 4.4, pin control registers ) or to connect an external pull-up resistor to the pin.
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 4 card interface (card) v. 4.1 outline of the card interface the card interface (card) generates control signals for the card interfaces listed below. ? #smrd and #smwr signals for smartmedia (nand flash) ? #cfce1 and #cfce2 signals for compactflash ? #iord, #iowr, #oe and #we signals for pc card each device may be located in any of the #ce 4 , #ce7 , #ce9 , or #ce11 areas. the data and address signals of each device can be connected directly to the external bus of the sramc. use general-purpose input/output ports to control the signals s pecific to each card. the pc card interface can accommodate up to two channels by locating each channel in different areas. this interface incorporates an ecc (error correction code) generator for 8- and 16 -bit card devices.
v peripheral modules 3 (interface): card interface (card) v-4-2 epson s1c33e08 technical manual v. 4.2 card interface pins the card interface has six ports (card 0 to card5 ) to output each interface signal listed above. note, however, that these pins are shared with general-purpose i/o ports or other peripheral circuit input/output pins. in the initial state, these pins are set for functions other than the card interface. before the pins can be used as card0 to card5 ports, the pin functions must be switched over by setting the corresponding port function se - lect register. for details on how to switch over the pin functions, see section i. 3.3, switching over the multiplexed pin func - tions. selecting the card interface pin functions the card 0 to card5 ports each are assigned two card interface signals, either of which can be selected for output from the respective ports. table v. 4.2.1 lists the signals assigned to each port. table v. 4.2.1 relationship between ports and card interface signals pin name card0 card1 card2 card3 card4 card5 function 0 (default) #smrd #smwr #iord #io wr #oe #we function select bit cardio0 (d0/0x300302) cardio1 (d1/0x300302) cardio2 (d2/0x300302) cardio3 (d3/0x300302) cardio4 (d4/0x300302) cardio5 (d5/0x300302) function 1 #cfce1 #cfce2 #smrd #smwr #cfce1 #cfce2 ? cardio x : card x port function select bit in the card i/f output port configuration register (d x /0x300302) cardio x (d x/0x300302 ) is initially set to 0 , with function 0 selected. to use function 1 , set cardio x (d x / 0x300302) to 1.
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 4.3 card area v. 4.3.1 selecting the area the following #ce areas can be used as memory areas for cards. #ce4 area: area 4 (0x100000 to 0x1 fffff, 1 mb) or area 14 (0x3000000 to 0x3 ffffff, 16mb) #ce7 area: area 7 (0x400000 to 0x5 fffff, 2 mb) or area 19 (0x10000000 to 0x1 fffffff, 256mb) #ce9 area: area 9 (0x800000 to 0 xbfffff, 4 mb) or area 22 (0x80000000 to 0 xffffffff, 2gb) #ce11 area: area 11 (0x1000000 to 0x17 fffff, 8 mb) or area 12 (0x1800000 to 0x1 ffffff, 8mb) one of the four areas above can be selected for each card interface. the following describes the control bits used to select any area and the bit settings. smartmedia (nand flash) ? cardsmt[1:0] : smartmedia/nand flash area configuration bits in the card i/f area configuration register (d[1:0]/0x300300) compactflash ? cardcf[1:0] : cf area configuration bits in the card i/f area configuration register (d[3:2]/0x300300) pc card 1 ? cardpc1[1:0] : pc card 1 area configuration bits in the card i/f area configuration register (d[5:4]/0x300300) pc card 2 ? cardpc2[1:0] : pc card 2 area configuration bits in the card i/f area configuration register (d[7:6]/0x300300) table v. 4.3.1.1 area selection contr ol bit settings 11 10 01 00 area #ce11 (area 11, 12) #ce9 (area 9, 22) #ce7 (area 7, 19) #ce4 (area 4, 14) (default: 0b00 = #ce4) v. 4.3.2 setting area access conditions depending on the device used, access conditions must be set for the area assigned to the card. use the sramc reg - isters to set these conditions as suitable for the specifications of the connected card. for details of access conditions and the sramc registers, see section ii. 3, sram controller (sramc).
v peripheral modules 3 (interface): card interface (card) v-4-4 epson s1c33e08 technical manual v. 4.4 card interface control signals this section describes the logic used to generate each card interface signal, and shows an example of connecting a card. v. 4.4.1 smartmedia interface figure v. 4.4.1.1 shows the logic used to generate smartmedia interface signals. figure v.4.4.1.2 shows an example of connecting the s1c33e08 and a smartmedia card (nand flash). #rd specified #ce x #wrl #smrd #smwr figure v. 4.4.1.1 smartmedia interface signal generation circuit s1c33e08 smar tmedia card (nand flash) d[15:0] or d[7:0] #ce #re #we cle ale r y/#by #wp #ce x #smrd #smwr (softw are control) p ?? i/o[15:0] (16-bit flash) or i/o[7:0] (8-bit flash) figure v. 4.4.1.2 example of connecting a smartmedia card for smartmedia and compactflash, a middleware is available for use in developing s 1c33 family applications. for details of the system and applications that can be implemented, refer to the manual included with the middle - ware. the s1c33e08 supports system boot from a nand flash. see appendix for details on booting.
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 4.4.2 compactflash interface figure v. 4.4.2.1 shows the logic used to generate compactflash interface signals. figure v.4.4.2.2 shows an ex - ample of connecting the s1c33e08 and a compactflash card. a4 specified #ce x #ce1 #ce2 figure v. 4.4.2.1 compactflash interface signal generation circuit s1c33e08 compactflash card #ce1 #ce2 a[3:1] d[15:0] #rd #wrl #w ait intrq /cd1 /cd2 (softw are control) p ?? /ce1 /ce2 a[2:0] d[15:0] /iord /io wr iord y figure v. 4.4.2.2 example of connecting a compactflash card for smartmedia and compactflash, a middleware is available for use in developing s 1c33 family applications. for details of the system and applications that can be implemented, refer to the manual included with the middle - ware. v. 4.4.3 pc card interface figure v. 4.4.3.1 shows the logic used to generate pc card interface signals. figure v.4.4.3.2 shows an example of connecting the s1c33e08 and a pc card. #rd specified #ce x #wr a19 #iord #io wr #oe #we figure v. 4.4.3.1 pc card interface signal generation circuit
v peripheral modules 3 (interface): card interface (card) v-4-6 epson s1c33e08 technical manual example connection 1 area used: area 7 device size: 8 bits (only accessible in units of bytes) attribute memory space: 0x480000 to 0x4 fffff, 512 kb (common memory not used) i/o space: 0x400000 to 0x47 ffff, 512kb s1c33e08 pc card v ss v dd #ce x a[20:0] d[15:0] #oe #we #iord #io wr #w ait (softw are control) p ?? reg# ce2# ce1# a[20:0] d[15:0] oe# we# iord# io wr# w ait# ireq# example connection 2 area used: area 7 device size: 16 bits (only accessible in units of half-words) attribute memory space: 0x480000 to 0x4 fffff, 512 kb (common memory not used) i/o space: 0x400000 to 0x47 ffff, 512kb s1c33e08 pc card (softw are control) p ?? #ce x #ce x a[20:0] d[15:0] #oe #we #iord #io wr #w ait (softw are control) p ?? reg# ce2# ce1# a[20:0] d[15:0] oe# we# iord# io wr# w ait# ireq# ? since this example connection only supports access in units of half-words, pc cards with only 16-bit registers can be used. pc cards with 8-bit registers cannot be used. figure v. 4.4.3.2 example of connecting a pc card precautions on using the pc card interface ? this interface supports 16 -bit pc cards, such as ata (cf), lan (ethernet, wireless), and modem that are connected as an i/o card. sram cards, etc. are not supported. ? live or hot-line card insertion and removal are not supported. power must be turned off before inserting or removing a card. automatic recognition of cards is also not supported. ? dma, zv, and cardbus are also not supported. ? to accommodate differences in power supply voltage between the pc card (5 v or 3.3 v) and the s1c33e08, use a buffer ic (e.g., s 1c37120).
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 4.5 card interface operating clock the card interface module is clocked by the card_clk clock (= mclk) supplied by the cmu. when initially reset, this clock is selected for supply to the card interface. however, when the card interface is idle or not in use, clock supply from the cmu may be turned off to reduce current consumed on the chip. use card_cke (d 4/ 0x301b04) of the cmu for this control. ? card_cke : card i/f clock control bit in the gated clock control register 1 (d4/0x301b04) setting card_cke (d4/0x301b04) to 0 stops clock supply from the cmu to the card interface. for details of the generation and control of the clock, see section iii. 1, clock management unit (cmu). note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be re - moved by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless re - writing said registers.
v peripheral modules 3 (interface): card interface (card) v-4-8 epson s1c33e08 technical manual v. 4.6 ecc generator in order to improve the card interface reliability, an ecc (error correction code) generator is embedded in this module. the ecc generator generates a 22 -bit ecc parity data, which consists of a 6 -bit column parity code (cp) and a 16 -bit line parity code (lp), for each 256 bytes (in the case of 8 -bit devices) or 128 words (in the case of 16 -bit devices) of card data area. when reading data from a card, software can compare the ecc data read from the card with the data generated by the ecc generator. it makes it possible to detect two bit errors and correct one bit errors. when writing data to a card, software can write the ecc data generated by the ecc generator to the redundant area of the card. ecc algorithm the card data is treated as bit streams, and ecc parity data is generated as follows: ^ denotes the xor (exclusive or) operation. ecc for 8 -bit card device: cp[0] = din[0] ^ din[2] ^ din[4] ^ din[6] ^ org[0] cp[1] = din[1] ^ din[3] ^ din[5] ^ din[7] ^ org[1] cp[2] = din[0] ^ din[1] ^ din[4] ^ din[5] ^ org[2] cp[3] = din[2] ^ din[3] ^ din[6] ^ din[7] ^ org[3] cp[4] = din[0] ^ din[1] ^ din[2] ^ din[3] ^ org[4] cp[5] = din[4] ^ din[5] ^ din[6] ^ din[7] ^ org[5] dall = din[0] ^ din[1] ^ din[2] ^ din[3] ^ din[4] ^ din[5] ^ din[6] ^ din[7] count [8:0] = count [8:0] +1 lp[0] = ( ~count[0] & dall ) ^ org[0] lp[2] = ( ~count[1] & dall ) ^ org[2] lp[4] = ( ~count[2] & dall ) ^ org[4] lp[6] = ( ~count[3] & dall ) ^ org[6] lp[8] = ( ~count[4] & dall ) ^ org[8] lp[10] = ( ~count[5] & dall ) ^ org[10] lp[12] = ( ~count[6] & dall ) ^ org[12] lp[14] = ( ~count[7] & dall ) ^ org[14] lp[1] = ( count[0] & dall ) ^ org[1] lp[3] = ( count[1] & dall ) ^ org[3] lp[5] = ( count[2] & dall ) ^ org[5] lp[7] = ( count[3] & dall ) ^ org[7] lp[9] = ( count[4] & dall ) ^ org[9] lp[11] = ( count[5] & dall ) ^ org[11] lp[13] = ( count[6] & dall ) ^ org[13] lp[15] = ( count[7] & dall ) ^ org[15] ecc for 16 -bit card device: cp[0] = din[0] ^ din[2] ^ din[4] ^ din[6] ^ din[8] ^ din[10] ^ din[12] ^ din[14] ^ org[0] cp[1] = din[1] ^ din[3] ^ din[5] ^ din[7] ^ din[9] ^ din[11] ^ din[13] ^ din[15] ^ org[1] cp[2] = din[0] ^ din[1] ^ din[4] ^ din[5] ^ din[8] ^ din[9] ^ din[12] ^ din[13] ^ org[2] cp[3] = din[2] ^ din[3] ^ din[6] ^ din[7] ^ din[10] ^ din[11] ^ din[14] ^ din[15] ^ org[3] cp[4] = din[0] ^ din[1] ^ din[2] ^ din[3] ^ din[8] ^ din[9] ^ din[10] ^ din[11] ^ org[4] cp[5] = din[4] ^ din[5] ^ din[6] ^ din[7] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ org[5] dall_low = din[0] ^ din[1] ^ din[2] ^ din[3] ^ din[4] ^ din[5] ^ din[6] ^ din[7] dall_high = din[8] ^ din[9] ^ din[10] ^ din[11] ^ din[12] ^ din[13] ^ din[14] ^ din[15] dall = dall_low ^ dall_high count [8:0] = count [8:0] +2 lp[0] = ( dall_low ) ^ org[0] lp[2] = ( ~count[1] & dall ) ^ org[2] lp[4] = ( ~count[2] & dall ) ^ org[4] lp[6] = ( ~count[3] & dall ) ^ org[6] lp[8] = ( ~count[4] & dall ) ^ org[8] lp[10] = ( ~count[5] & dall ) ^ org[10] lp[12] = ( ~count[6] & dall ) ^ org[12] lp[14] = ( ~count[7] & dall ) ^ org[14] lp[1] = ( dall_high ) ^ org[1] lp[3] = ( count[1] & dall ) ^ org[3] lp[5] = ( count[2] & dall ) ^ org[5] lp[7] = ( count[3] & dall ) ^ org[7] lp[9] = ( count[4] & dall ) ^ org[9] lp[11] = ( count[5] & dall ) ^ org[11] lp[13] = ( count[6] & dall ) ^ org[13] lp[15] = ( count[7] & dall ) ^ org[15]
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 data read flowchart figure v. 4.6.1 shows a card data read flowchart. star t end initialization reset ecc generator command input to card address input to card enab le ecc generator read card data card ready? no ye s disab le ecc generator read ecc data from registers error detection ecc ready? no ye s read another page? ye s no figure v. 4.6.1 data read flowchart notes : ? eccrst (d0/0x300311 ) should be set before using the ecc function. ? eccrst : ecc circuit reset bit in the ecc reset/ready register (d0/0x300311) ? the eccen (d0/0x300312 ) should be set only while reading or writing card data. it should be disabled during command input, address input or status reading. ? eccen : ecc circuit enable bit in the ecc enable register (d0/0x300312)
v peripheral modules 3 (interface): card interface (card) v-4-10 epson s1c33e08 technical manual data write flowchart figure v. 4.6.2 shows a card data write flowchart. star t end initialization reset ecc generator command input to card command input to card address input to card enab le ecc generator wr ite card data wr ite ecc code to card card ready? no ye s ecc ready? no ye s wr ite another page? ye s no figure v. 4.6.2 data write flowchart notes : ? eccrst (d0/0x300311 ) should be set before using the ecc function. ? the eccen (d0/0x300312 ) should be set only while reading or writing card data. it should be disabled during command input, address input or status reading.
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 4.7 details of control registers table v. 4.7.1 card interface control register list address 0x00300300 0x00300302 0x00300310 0x00300311 0x00300312 0x00300313 0x00300314 0x00300316 0x00300317 0x00300318 0x0030031a 0x0030031b function allocates card space. selects the function of signal output ports for card control. selects ecc trigger area. resets ecc circuits and indicates ecc ready status. enables ecc circuits. selects device size. area 0 column parity data area 0 line parity data (low-order byte) area 0 line parity data (high-order byte) area 1 column parity data area 1 line parity data (low-order byte) area 1 line parity data (high-order byte) register name card i/f area configuration register (pcardsetup) card i/f output port configuration register (pcardfuncsel05) ecc trigger area select register (pecctrigsel) ecc reset/ready register (peccrstrdy) ecc enable register (peccena) ecc mode register (peccmd) area 0 ecc column parity data register (pecc0cp) area 0 ecc line parity register 0 (pecc0lpl) area 0 ecc line parity register 1 (pecc0lph) area 1 ecc column parity data register (pecc1cp) area 1 ecc line parity register 0 (pecc1lpl) area 1 ecc line parity register 1 (pecc1lph) siz e 8 8 8 8 8 8 8 8 8 8 8 8 the following describes each card interface control register. the card interface control registers are mapped to the 8 -bit device area at addresses 0x300300 to 0x30031 b, and can be accessed in units of bytes. note : when setting the card interface control registers, be sure to write a 0, and not a 1, for all reserved bits.
v peripheral modules 3 (interface): card interface (card) v-4-12 epson s1c33e08 technical manual 0x300300: card i/f area configuration register (pcardsetup) name address register name bit function setting init. r/w remarks cardpc21 cardpc20 cardpc11 cardpc10 cardcf1 cardcf0 cardsmt1 cardsmt0 d7 d6 d5 d4 d3 d2 d1 d0 pc card 2 area configuration pc card 1 area configuration cf area configuration smartmedia/nand flash area configuration 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300300 (b) card i/f area configuration register (pcardsetup) 11 10 01 00 bit[1:0] #ce area #ce11 (area 11, 12) #ce9 (area 9, 22) #ce7 (area 7, 19) #ce4 (area 4, 14) this register sets the area in which to allocate each card space. table v. 4.7.2 lists the settings of each card interface control bit used to select this area. table v. 4.7.2 area selection contr ol bit settings 11 10 01 00 area #ce11 (area 11, 12) #ce9 (area 9, 22) #ce7 (area 7, 19) #ce4 (area 4, 14) (default: 0b00 = #ce4) d[7:6] cardpc2[1:0]: pc card 2 area configuration bits these bits select the area used for pc card 2. d[5:4] cardpc1[1:0]: pc card 1 area configuration bits these bits select the area used for pc card 1. d[3:2] cardcf[1:0]: cf area configuration bits these bits select the area used for the compactflash card. d[1:0] cardsmt[1:0]: smartmedia area configuration bits these bits select the area used for the smartmedia card (nand flash).
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300302: card i/f output port configuration register (pcardfuncsel05) name address register name bit function setting init. r/w remarks C cardio5 cardio4 cardio3 cardio2 cardio1 cardio0 d7C6 d5 d4 d3 d2 d1 d0 reserved card5 port function select card4 port function select card3 port function select card2 port function select card1 port function select card0 port function select C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300302 (b) card i/f output port configuration register (pcardfuncsel05) C 1 #cfce2 0 #we 1 #cfce1 0 #oe 1 #smwr 0 #iowr 1 #smrd 0 #iord 1 #cfce2 0 #smwr 1 #cfce1 0 #smrd table v. 4.7.3 relationship between ports and card interface signals pin name card0 card1 card2 card3 card4 card5 function 0 (default) #smrd #smwr #iord #io wr #oe #we function 1 #cfce1 #cfce2 #smrd #smwr #cfce1 #cfce2 d[7:6] reserved d5 cardio5: card5 port function select bit this bit selects the signal to output from the card 5 pin. 1 (r/w): #cfce2 0 (r/w): #we (default) d4 cardio4: card4 port function select bit this bit selects the signal to output from the card 4 pin. 1 (r/w): #cfce1 0 (r/w): #oe (default) d3 cardio3: card3 port function select bit this bit selects the signal to output from the card 3 pin. 1 (r/w): #smwr 0 (r/w): #iowr (default) d2 cardio2: card2 port function select bit this bit selects the signal to output from the card 2 pin. 1 (r/w): #smrd 0 (r/w): #iord (default) d1 cardio1: card1 port function select bit this bit selects the signal to output from the card 1 pin. 1 (r/w): #cfce2 0 (r/w): #smwr (default) d0 cardio0: card0 port function select bit this bit selects the signal to output from the card 0 pin. 1 (r/w): #cfce1 0 (r/w): #smrd (default)
v peripheral modules 3 (interface): card interface (card) v-4-14 epson s1c33e08 technical manual 0x300310: ecc trigger area select register (pecctrigsel) name address register name bit function setting init. r/w remarks C eccsel2 eccsel1 eccsel0 d7C3 d2 d1 d0 reserved external memory area select for triggering ecc C 0 0 0 C r/w 0 when being read. 00300310 (b) ecc trigger area select register (pecctrigsel) C eccsel[2:0] 111 110 101 100 011 010 001 000 #ce area #ce11 #ce10 #ce9 #ce8 #ce7 #ce6 #ce5 #ce4 d[7:3] reserved d[2:0] eccsel[2:0]: external memory area select bits for triggering ecc selects a card area in which the ecc function is used. table v. 4.7.4 selecting an ecc trigger area eccsel0 1 0 1 0 1 0 1 0 eccsel1 1 1 0 0 1 1 0 0 eccsel2 1 1 1 1 0 0 0 0 area #ce11 #ce10 #ce9 #ce8 #ce7 #ce6 #ce5 #ce4 (default: 0b000 = #ce4)
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300311: ecc reset/ready register (peccrstrdy) name address register name bit function setting init. r/w remarks C eccrdy1 eccrst eccrdy0 d7C2 d1 d0 reserved area 1 parity data ready status ecc circuit reset area 0 parity data ready status C 0 C 0 C r w r 0 when being read. 00300311 (b) ecc reset/ready register (peccrstrdy) C 1 ready 0 busy 1 reset 0 invalid 1 ready 0 busy d[7:2] reserved d1 eccrdy1: area 1 parity data ready status bit indicates whether the parity data for area 1 is ready for reading or not. 1 (r): ready for read 0 (r): not ready (default) when 1 is read from eccrdy1 , the ecc generator has generated the column and line parity data for area 1 and it is ready for reading. when 0 is read, the column and line parity data has not been gener - ated. make sure that this bit is 1 before reading the ecc data registers for area 1. d0 eccrst: ecc circuit reset bit (w) eccrdy0: area 0 parity data ready status bit (r) resets the ecc generator and indicates whether the parity data for area 0 is ready for reading or not. 1 (w): reset 0 (w): invalid 1 (r): ready for read 0 (r): not ready (default) when writing (eccrst): writing 1 to this bit resets the ecc generator. this operation is required in every page before reading or writing data (before setting eccen (d0/0x300312) to 1). when reading (eccrdy 0): when 1 is read from this bit (eccrdy0 ), the ecc generator has generated the column and line parity data for area 0 and it is ready for reading. when 0 is read, the column and line parity data has not been generated. make sure that this bit is 1 before reading the ecc data registers for area 0. ? area 0 means the first transferred 256 -byte (in 8 -bit device) or 128 -word (in 16 -bit device) card data after the ecc circuit is enabled. area 1 means the second transferred 256 -byte (in 8 -bit device) or 128 -word (in 16 -bit de - vice) card data.
v peripheral modules 3 (interface): card interface (card) v-4-16 epson s1c33e08 technical manual 0x300312: ecc enable register (peccena) name address register name bit function setting init. r/w remarks C eccen d7C1 d0 reserved ecc circuit enable C 0 C r/w 0 when being read. 00300312 (b) ecc enable register (peccena) C 1 enabled 0 disabled d[7:1] reserved d0 eccen: ecc circuit enable bit enables the ecc generator. 1 (r/w): enable 0 (r/w): disable (default) set eccen to 1 before reading or writing data from/to a page and set to 0 after 512 -byte data is read/ written from/to the page. (this ecc generator supports 512 -byte mode only.) this bit must be set to 0 during command cycles, address cycles, and status output cycles.
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300313: ecc mode register (peccmd) name address register name bit function setting init. r/w remarks C mode d7C1 d0 reserved card device mode C 0 C r/w 0 when being read. 00300313 (b) ecc mode register (peccmd) C 1 16 bits 0 8 bits d[7:1] reserved d0 mode: card device mode select bit selects the card device size. 1 (r/w): 16 -bit device 0 (r/w): 8 -bit device (default) set mode to 1 when using a 16 -bit device or set to 0 when using an 8 -bit device.
v peripheral modules 3 (interface): card interface (card) v-4-18 epson s1c33e08 technical manual 0x300314: area 0 ecc column parity data register (pecc0cp) name address register name bit function setting init. r/w remarks 0x0 to 0x3f C C cp05 cp04 cp03 cp02 cp01 cp00 C C d7 d6 d5 d4 d3 d2 d1 d0 area 0 column parity data unused bit unused bit 1 1 1 1 1 1 1 1 r r r 1 when being read. 00300314 (b) area 0 ecc column parity data register (pecc0cp) d[7:2] cp0[5:0]: area 0 column parity data bits the column parity data that is generated by the ecc generator from the 256 -byte card data in area 0 is stored in this register. the data read from this register is valid when eccrdy 0 (d0/0x300311) is read as 1. d[1:0] reserved
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300316: area 0 ecc line parity register 0 (pecc0lpl) 0x300317: area 0 ecc line parity register 1 (pecc0lph) name address register name bit function setting init. r/w remarks 0x0 to 0xff (low-order 8 bits) lp07 lp06 lp05 lp04 lp03 lp02 lp01 lp00 d7 d6 d5 d4 d3 d2 d1 d0 area 0 ecc line parity lp00 = lsb 1 1 1 1 1 1 1 1 r 00300316 (b) area 0 ecc line parity register 0 (pecc0lpl) 0x0 to 0xff (high-order 8 bits) lp015 lp014 lp013 lp012 lp011 lp010 lp09 lp08 d7 d6 d5 d4 d3 d2 d1 d0 area 0 ecc line parity lp015 = msb 1 1 1 1 1 1 1 1 r 00300317 (b) area 0 ecc line parity register 1 (pecc0lph) d[7:0]/0x300316 lp0[7:0]: area 0 ecc line parity (low-order 8 bits) d[7:0]/0x300317 lp0[15:8]: area 0 ecc line parity (high-order 8 bits) the line parity data that is generated by the ecc generator from the 256 -byte card data in area 0 is stored in these registers. the data read from these registers are valid when eccrdy 0 (d0/0x300311) is read as 1.
v peripheral modules 3 (interface): card interface (card) v-4-20 epson s1c33e08 technical manual 0x300318: area 1 ecc column parity data register (pecc1cp) name address register name bit function setting init. r/w remarks 0x0 to 0x3f C C cp15 cp14 cp13 cp12 cp11 cp10 C C d7 d6 d5 d4 d3 d2 d1 d0 area 1 column parity data unused bit unused bit 1 1 1 1 1 1 1 1 r r r 1 when being read. 00300318 (b) area 1 ecc column parity data register (pecc1cp) d[7:2] cp1[5:0]: area 1 column parity data bits the column parity data that is generated by the ecc generator from the 256 -byte card data in area 1 is stored in this register. the data read from this register is valid when eccrdy 1 (d1/0x300311) is read as 1. d[1:0] reserved
v peripheral modules 3 (interface): card interface (card) s1c33e08 technical manual epson v-4-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30031a: area 1 ecc line parity register 0 (pecc1lpl) 0x30031b: area 1 ecc line parity register 1 (pecc1lph) name address register name bit function setting init. r/w remarks 0x0 to 0xff (low-order 8 bits) lp17 lp16 lp15 lp14 lp13 lp12 lp11 lp10 d7 d6 d5 d4 d3 d2 d1 d0 area 1 ecc line parity lp10 = lsb 1 1 1 1 1 1 1 1 r 0030031a (b) area 1 ecc line parity register 0 (pecc1lpl) 0x0 to 0xff (high-order 8 bits) lp115 lp114 lp113 lp112 lp111 lp110 lp19 lp18 d7 d6 d5 d4 d3 d2 d1 d0 area 1 ecc line parity lp115 = msb 1 1 1 1 1 1 1 1 r 0030031b (b) area 1 ecc line parity register 1 (pecc1lph) d[7:0]/0x30031a lp1[7:0]: area 1 ecc line parity (low-order 8 bits) d[7:0]/0x30031b lp1[15:8]: area 1 ecc line parity (high-order 8 bits) the line parity data that is generated by the ecc generator from the 256 -byte card data in area 1 is stored in these registers. the data read from these registers are valid when eccrdy 1 (d1/0x300311) is read as 1.
v peripheral modules 3 (interface): card interface (card) v-4-22 epson s1c33e08 technical manual v. 4.8 precautions the pc card interface (card) is subject to the following limitations: ? the interface supports 16 -bit pc cards, such as ata (cf), lan (ethernet, wireless), or modem connected as an i/o card. sram cards, etc. are not supported. ? live or hot-line card insertion and removal are not supported. power must be turned off before inserting or re - moving a card. the automatic recognition of cards is also not supported. ? dma, zv, and cardbus are also not supported. ? to accommodate differences in power supply voltage between the pc card (5 v or 3.3 v) and the s1c33e08 , use a buffer ic (e.g., s 1c37120). ? the ecc generator supports two data organization modes: 512-byte 8 -bit mode and 256 -word 16 -bit mode. 256-byte 8-bit mode is not supported as it is a seldom-used feature. ? the card i/o signals must be connected to the d[15:0] pins when using the ecc function. ? eccrst (d0/0x300311) should be set before using the ecc function. ? eccrst : ecc circuit reset bit in the ecc reset/ready register (d0/0x300311) ? the eccen (d0/0x300312 ) should be set only while reading or writing card data. it should be disabled during command input, address input or status reading. ? eccen : ecc circuit enable bit in the ecc enable register (d0/0x300312)
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 5 i 2 s interface (i 2 s) v. 5.1 outline of i 2 s module the s 1c33e08 has a built-in i 2 s module that outputs 16 -bit pcm data in the i 2 s (inter-ic sound) format. an audio output circuit can be simply configured by connecting an external dac to the i 2 s bus. the following shows the features of the i 2 s module: ? 16-bit pcm data output ? an 8 -word 32-bit fifo is included. ? stereo, mono (l and r), and mute modes are software selectable. ? clock polarity is software configurable. ? data shift direction (msb first/lsb first) is software selectable. ? fifo empty can issue a dma request (dual channel or single cha nnel) or an interrupt request. figure v. 5.1.1 shows the structure of the i 2 s module. mclk to itc to hsdma sramc i2s_sdo i2s_sck i2s_ws i2s_mclk 16-bit shift register dma request/interrupt control fifo l channel data (8 samples) fifo control fifo r channel data (8 samples) internal bus interface clock control/ output control figure v. 5.1.1 structure of i 2 s module note : the mp3 decoder bios (mp3 decoder module) uses the i 2 s module, therefore, the i 2 s module cannot be used while the mp3 decoder is active.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-2 epson s1c33e08 technical manual v. 5.2 output pins of i 2 s module table v. 5.2.1 lists the output pins used by the i 2 s module. table v. 5.2.1 i 2 s interface pin configuration pin name i2s_sdo i2s_ws i2s_sck i2s_mclk i/o o o o o function ser ial data output w ord-select (lrclk) signal output bit cloc k output master cloc k output i2s_sdo pin this pin outputs serial pcm data. i2s_ws pin this pin outputs the word-select (lrclk) signal that indicates the channel (l or r) of the data being output. i2s_sck pin this pin outputs the synchronous clock (bit clock) for serial data. i2s_mclk pin this pin outputs the i 2 s master clock. note : the i 2 s interface output pins are shared with general-purpose i/o ports or other peripheral circuit inputs/outputs, so that functionality in the initial state is set to other than the i 2 s interface output. before the i 2 s interface output signals assigned to these pins can be used, the function of these pins must be switched for the i 2 s interface by setting the corresponding port function select reg - isters. for details of pin functions and how to switch over, see section i.3.3, switching over the multi - plexed pin functions.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 5.3 i 2 s module operating clock the i 2 s module use the i 2 s_clk clock (= mclk) generated by the cmu as the operating clock. the transfer clock is generated in the i 2 s module by dividing i 2s_clk. controlling the supply of the operating clock i 2 s_clk is supplied to the i 2 s module with default settings. it can be turned off using i 2 s_cke (d 11 / 0 x 301 b 04 ) to reduce the amount of power consumed on the chip if the i 2 s module is not used. ? i2s_cke : i 2 s clock control bit in the gated clock control register 1 (d11/0x301b04) setting i 2s_cke (d 11/0x301b04) to 0 (1 by default) turns off the clock supply to the i 2 s module. when the clock supply is turned off, the i 2 s module control registers cannot be accessed. for details on how to set and control the clock, refer to section iii. 1, clock management unit (cmu). note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be re - moved by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless re - writing said registers. clock state in standby mode the clock supply to the i 2 s module stops depending on type of standby mode. halt mode: the operating clock is supplied the same way as in normal mode. sleep mode: the operating clock supply stops. therefore, the i 2 s module also stops operating in sleep mode.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-4 epson s1c33e08 technical manual v. 5.4 setting i 2 s module when performing data transfers via the i 2 s bus, the following settings must be made before data transfer is actually begun: 1. setting output pins 2. setting i 2 s interface clocks 3. setting the output data format and timing 4. setting hsdma 5. setting interrupts the following explains the content of each setting. for details on interrupt settings, refer to section v. 5.6, i 2 s in - terrupt. note : always make sure the i 2 s module is inactive (i 2 sen (d7/0x301c00) = 0) before these settings are made. a change of settings during operation may cause a malfunction. ? i2sen : i 2 s module enable bit in the i 2 s control register (d7/0x301c00) setting output pins configure the port function select registers to enable the i 2 s output functions. for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. setting the i 2 s interface clocks the i 2 s module outputs the following three clocks to the slave device (dac) (some dacs use two clocks): 1. i2s_mclk (master clock) 2. i2s_ws (lrclk clock) 3. i2s_sck (bit clock) d0 d15 d2 d1 d0 d15 d14 d2 d1 d14 d0 i2s_mclk i2s_ws (lrclk) i2s_sck i2s_sdo (l channel) (r channel) figure v. 5.4.1 i 2 s interface clocks the following shows how to configure the clocks: divide ratio for i 2 s_mclk (master clock) the i 2 s module generates the i2 s_mclk by dividing the operating clock (mclk generated by the cmu). specify the divide ratio using i 2smclk[5:0] (d[5:0]/0x301c04). ? i2smclk[5:0] : i2s_mclk divide ratio select bits in the i 2 s mclk divide ratio register (d[5:0]/0x301c04) table v. 5.4.1 setting i2 s_mclk (master clock) i2smclk[5:0] 111111 111110 111101 : 000010 000001 000000 i2s_mclk mclk (cmu) /64 mclk (cmu) /63 mclk (cmu) /62 : mclk (cmu) /3 mclk (cmu) /2 mclk (cmu) /1 (default: 0b000000 = mclk/1)
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 divide ratio for i 2 s_ws (lrclk clock) lrclk is the clock output as the word-select signal and is generated by dividing i 2s_mclk. specify the divide ratio using lrclk[ 2:0] (d[2:0]/0x301c08). ? lrclk[2:0] : lrclk divide ratio select bits in the i 2 s audio clock divide ratio register (d[2:0]/0x301c08) table v. 5.4.2 setting lrclk lrclk0 1 0 1 0 1 0 1 0 lrclk i2s_mclk/512 i2s_mclk/448 i2s_mclk/384 i2s_mclk/320 i2s_mclk/256 i2s_mclk/192 i2s_mclk/128 i2s_mclk/64 lrclk1 1 1 0 0 1 1 0 0 lrclk2 1 1 1 1 0 0 0 0 (default: 0b000 = i2s_mclk/64) configure lrclk to the pcm sampling frequency. the bit clock is configured to lrclk 32 [hz]. for example, the bit clock frequency is 1.536 mhz when lr - clk is set to 48 khz. selecting the word clock the i 2 s_ws (lrclk) signal represents the current output channel (l or r) with its level (low or high). use wclkmd (d3/0x301c00 ) to select the relationship between the signal level and the channel. ? wclkmd : i 2 s output word clock mode select bit in the i 2 s control register (d3/0x301c00) i2s_ws (lrclk) wclkmd = 0 (def ault) (l channel) (r channel) i2s_ws (lrclk) wclkmd = 1 (l channel) (r channel) figure v. 5.4.2 selecting word clock mode i 2 s_sck (bit clock) polarity use bclkpol (d 2/0x301c00 ) to select the bit clock polarity. ? bclkpol : i 2 s output bit clock polarity select bit in the i 2 s control register (d2/0x301c00) i2s_sck i2s_sdo bclkpol = 0 (def ault) output is shifted at the f alling edge . the e xter nal da c samples the data at the r ising edge . i2s_sck i2s_sdo bclkpol = 1 output is shifted at the r ising edge . the e xter nal da c samples the data at the f alling edge . figure v. 5.4.3 selecting the bit clock polarity
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-6 epson s1c33e08 technical manual setting the output data format and timing use dtform (d 0/0x301c00 ) to select either msb first or lsb first as the data output direction. setting dtform (d 0/0x301c00) to 0 (default) selects msb first and setting 1 selects lsb first. the output channel mode and hsdma mode do not affect the output data format and it is always treated in 16 bit units. ? dtform : i 2 s output data format select bit in the i 2 s control register (d0/0x301c00) i2s_ws (lrclk) i2s_sck i2s_sdo dtform = 0 (def ault) i2s_ws (lrclk) i2s_sck i2s_sdo dtform = 1 d0 d15 d2 d1 d0 d15 d14 d2 d1 d14 d0 d15 d0 d13 d14 d15 d0 d1 d13 d14 d1 d15 figure v. 5.4.4 selecting output data format in the default setting, the first bit of each data is output after one i 2 s_sck clock delay from the i2 s_ws signal edge. this timing can be changed by writing 1 to dttmg (d1/0x301c00 ) so that each data output will start at the i2s_ws signal edge. ? dttmg : i 2 s output data timing select bit in the i 2 s control register (d1/0x301c00) i2s_ws (lrclk) i2s_sck i2s_sdo dttmg = 0 (def ault) 1-cloc k dela y i2s_ws (lrclk) i2s_sck i2s_sdo dttmg = 1 1-cloc k dela y d0 d15 d2 d1 d0 d15 d14 d2 d1 d14 d0 d15 d14 d1 d0 d15 d14 d13 d1 d0 d13 d15 figure v. 5.4.5 selecting data output timing
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 setting hsdma the i 2 s module has an embedded 8 -word fifo for storing pcm data and is able to output dma requests to write data when the fifo is not full. the i 2 s module has two dma request signal paths corresponding to l and r channels and these signals are directly input to hsdma. when transferring l and r data together, one dma request signal only is used, or when transferring l and r data individually, two signals are used. i 2shsdma (d0/0x301c10) is used for this selection. ? i2shsdma : i 2 s hsdma mode select bit in the i 2 s hsdma mode select register (d0/0x301c10) when one dma request signal is used (i 2shsdma = 0 , default) when one data in the fifo is loaded to the shift register, the l channel dma request signal to the hsdma ch.0 is asserted. program hsdma so that up to eight 32 -bit data will be transferred to the fifo (0x301c20) using the requests as triggers. the 32 -bit data consists of an l channel data of upper 16 bits and an r channel data of lower 16 bits. the following shows standard settings for hsdma ch. 0 . for details of hsdma, see section ii. 1 , high-speed dma (hsdma). 1 . hsdma std/adv mode select register (0x30119c) = 0x1 set hsdma in advanced mode to perform 32 -bit data transfer. 2. hsdma ch.0 control register for adv mode (0x301162) = 0x1 set the transfer data size to word ( 32 bits). 3. hsdma ch.0 source address setup registers for adv mode (0x301164, 0x301166) = pcm data address specify the pcm data start address in the memory as the source address. 4. hsdma ch.0 destination address setup registers for adv mode (0x301168, 0x30116a) = 0x301c20 specify the data write address of the i 2 s fifo as the destination address. 5. hsdma ch.0 transfer counter register (0x301120) = 0x8 to pcm data size configure the transfer counter with the word length to be transferred. be sure not to set a value of less than 8 . the i 2 s module fills the fifo with output data until it becomes full before outputting. after that, every time word data is read out from the fifo, the i 2 s module outputs a dma request until the fifo becomes full again. 6. hsdma ch.0 control register (0x301122) = 0x80 select dual-address mode. 7. hsdma ch.0 high-order source address setup register (0x301126) = 0x3000 select address incremented without initialization for the source address control. 8. hsdma ch.0 high-order destination address setup register (0x30112a) = 0x0000 set hsdma in single transfer mode to transfer one word per transfer by one trigger. select address fixed for the destination address control. 9. hsdma ch.0C1 trigger set-up register (0x300298) = 0x ? 9 select i 2 s as the trigger source for hsdma ch. 0 . a trigger source for hsdma ch. 1 should be set to ? (upper four bits).
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-8 epson s1c33e08 technical manual when two dma request signals are used (i 2shsdma = 1) this mode should be selected when pcm data in the memory are separated into l and r channels. in this mode, an l channel dma request and an r channel dma request occur when data in the fifo is loaded to the shift register and the fifo becomes less than full. in this mode, 16-bit data for each channel can be transferred and written to t he fifo individually. the l channel dma request signal is output to hsdma ch. 0 and the r channel dma request signal is output to hsdma ch. 1 . therefore, hsdma ch.0 and ch.1 should be programmed as shown below. for details of hsdma, see section ii.1, high-speed dma (hsdma). 1 . hsdma std/adv mode select register (0x30119c) = 0x1 set hsdma in advanced mode. standard mode can be set for 16 -bit data transfer. 2. hsdma ch.0 source address setup registers for adv mode (0x301164, 0x301166) = l channel data address hsdma ch.1 source address setup registers for adv mode (0x301174, 0x301176) = r channel data address specify the l and r channel pcm data start addresses in the mem ory as the source addresses. 3. hsdma ch.0 destination address setup registers for adv mode (0x301168, 0x30116a) = 0x301c20 hsdma ch.1 destination address setup registers for adv mode (0x301178, 0x30117a) = 0x301c22 specify the data write address of the i 2 s fifo for each channel. 4. hsdma ch.0 transfer counter register (0x301120) = 0x8 to left channel pcm data size hsdma ch.1 transfer counter register (0x301130) = 0x8 to right channel pcm data size configure the transfer counters with the data length to be transferred. be sure not to set a value of less than 8 as the i 2 s fifo size is 8 words. 5. hsdma ch.0 control register (0x301122) = 0x80 hsdma ch.1 control register (0x301132) = 0x80 select dual-address mode. 6. hsdma ch.0 high-order source address setup register (0x301126) = 0x7000 hsdma ch.1 high-order source address setup register (0x301136) = 0x7000 set the transfer data size to half-word ( 16 bits). select address incremented without initialization for the source address control. 7. hsdma ch.0 high-order destination address setup register (0x30112a) = 0x0000 hsdma ch.1 high-order destination address setup register (0x30113a) = 0x0000 set hsdma in single transfer mode to transfer 16 bits per transfer by one trigger. select address fixed for the destination address control. 8. hsdma ch.0C1 trigger set-up register (0x300298) = 0x99 select i 2 s as the trigger source for hsdma ch.0 and ch.1.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 5.5 data output control the following shows pcm data output procedure: 1 . set up the i 2 s and hsdma conditions as described in the previous section. 2 . when hsdma ch.0 and ch.1 cannot be used for i 2 s, set up the interrupt conditions using the itc registers (explained later). when using the i 2 s interrupt, the cause-of-interrupt flag in the itc must be cleared before en - abling the interrupt. 3 . write 1 to the i2sen (d7/0x301c00) to turn the i 2 s circuit on. the i 2 s circuit starts frequency division of the source clock. ? i2sen : i 2 s module enable bit in the i 2 s control register (d7/0x301c00) 4 . set the output channel mode using chmd[1:0] (d[5:4]/0x301c00). ? chmd[1:0] : i 2 s output channel mode select bits in the i 2 s control register (d[5:4]/0x301c00) table v. 5.5.1 selecting output channel mode chmd0 1 0 1 0 output channel mode mute mono (l) mono (r) stereo l channel 0 data output 0 data output r channel 0 0 data output data output chmd1 1 1 0 0 (default: 0b00 = stereo) the output channel mode can be switched even if data is being output. in this case, the mode changes after the current word output has finished. 5 . write the first pcm word to the fifo. when writing a 32 -bit data for l and r channels together, perform word write to 0x301c20. when writing data for each channel individually, write a 16 -bit l channel data to 0x301c20 and a 16 -bit r channel data to 0x301c22 using a half-word access instruction. note that the newest data of the fifo are overwritten if two or more words are written to the fifo before 1 is written to i2 sstart (d0/0x301c0c). 0x301c20 d31 d0 (l channel data) (r channel data) 32-bit wr ite 0x301c22 0x301c20 d15 d15 d0 d0 (l channel data) (r channel data) 16-bit wr ite figure v. 5.5.1 writing to fifo 6 . write 1 to i2souten (d6/0x301c00) to enable i 2 s output. ? i2souten : i 2 s output enable bit in the i 2 s control register (d6/0x301c00) when i 2 souten (d6/0x301c00 ) = 0 , the i2 s_mclk, i2 s_ws, and i2 s_sdo pins are fixed at 0 . the i2 s_sck pin is fixed at 0 (when bclkpol (d2/0x301c00) = 0) or 1 (when bclkpol (d2/0x301c00) = 1). when i 2souten (d6/0x301c00) is set to 1, all output pins enter standby status. ? bclkpol : i 2 s output bit clock polarity select bit in the i 2 s control register (d2/0x301c00) 7 . write 1 to i2 sstart (d0/0x301c0c) to start output. ? i2sstart : i 2 s start/stop control bit in the i 2 s start register (d0/0x301c0c) the i 2 s circuit loads one word of data in the fifo to the shift register and it starts serial output in sync with the i 2 s_ws signal. the data in the shift register is shifted at the i2 s_sck clock edge and is output from the l channel first. when an output of one word has finished, the next data is read out from the fifo and the same operation repeats. when the i 2 s module has finished outputting the last data in the fifo, i 2sfifoef (d0/0x301c14) is set to 1. ? i2sfifoef : i 2 s fifo empty flag in the i 2 s fifo status register (d0/0x301c14)
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-10 epson s1c33e08 technical manual every time word data is read out from the fifo and the fifo turns lack from full, a dma request is output to hsdma. if the dma transfer conditions described in the previous section has been set and dma is enabled, the following data is written to the fifo in a dma transfer. when data is written to the fifo, i 2sfifoef (d0/0x301c14) is reset to 0 and the data output continues. the fifo size is 8 words so up to 8 samples of pcm data can be written to it. if writing data exceeds 8 words, the newest data of the fifo are overwritten. every time the fifo changes from full into lack, an interrupt can be generated. by using this interrupt, data can be written to the fifo in an interrupt handler routine. for more information on the interrupt, see section v. 5.6, i 2 s interrupt. i 2 sbusy (d7/0x301c0 c) is set to 1 while data is being output. this flag can be used to check the output sta - tus. ? i2sbusy : i 2 s module busy flag in the i 2 s start register (d7/0x301c0c) 8 . to stop output, write 0 to i2 sstart (d0/0x301c0c). when i 2 sstart (d0/0x301c0 c) is set to 0 , the i 2 s module will stop data output after the remaining data stored in the fifo are all output. when the i 2 s stops, i2 sbusy (d7/0x301c0c) is reset to 0. 9 . to disable output, write 0 to i2 souten (d6/0x301c00 ) after writing 0 to i2 sstart (d0/0x301c0 c) to stop the current output. finally, write 0 to i2sen (d7/0x301c00) to turn the i 2 s circuit off. i2s_mclk pin i2sst ar t i2sbusy i2s_ws (lrclk) pin i2s_sck pin i2s_sdo pin i2sfifoef dma request i 2 s interr upt (r channel) (l channel) d15 d14 d1 d0 d15 d14 d1 d0 d15 d14 when i2sst ar t is set to 1 i2s_mclk pin i2sst ar t i2sbusy i2s_ws (lrclk) pin i2s_sck pin i2s_sdo pin i2sfifoef dma request i 2 s interr upt d15 d1 d0 d15 d14 d1 d0 d15 d14 d1 d15 d14 d1 d14 d1 d0 d0 when i2sst ar t is set to 0 (chmd[1:0] = 0b00 , wclkmd = 0, bclkpol = 0, dttmg = 0, dtform = 0) figure v. 5.5.2 data output timing chart ? output when mute or mono mode is selected when mute mode is selected using chmd[ 1:0 ] (d[5:4]/0x301c00 ), the i2 s_sdo pin is fixed at 0 . however, the fifo and shift register run the same as stereo mode and three clock signals are output normally. also in mono mode, the i2 s_sdo pin is fixed at 0 during the output period for the unselected channel. the fifo data is read out normally, therefore a dma request or interrupt caused by a fifo empty occurs. if chmd[ 1:0 ] (d[5:4]/0x301c00 ) is changed when data is being output, the mode changes after the current word output has finished.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 v. 5.6 i 2 s interrupt the i 2 s module can generate an interrupt every time the fifo is not full by loading one data in the fifo to the shift register. control registers of the interrupt controller table v. 5.6.1 shows the interrupt controller's control registers provided for the i 2 s interrupt. table v. 5.6.1 control register of interrupt controller interrupt i 2 s interr upt cause-of-interrupt fla g fi2s(d2/0x3002aa) interrupt priority register pi2s[2:0](d[2:0]/0x3002a4) interrupt enable register ei2s(d2/0x3002a7) when a cause of fifo empty interrupt occurs, the cause-of-interrupt flag listed above is set to 1 . if the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit for that cause of interrupt set to 0 . the cause-of-interrupt flag is set to 1 whenever interrupt conditions are met, regardless of the setting of the interrupt enable register (even if it is set to 0). the interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7 . an interrupt request to the cpu is accepted only when no other interrupt request of a higher priority has been generated. in addition, only when the psr's ie bit = 1 (interrupts enabled) and the set value of the il is smaller than the input interrupt level set by the interrupt priority register, will the input interrupt request actually be ac - cepted by the cpu. for details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to section iii.2, interrupt controller (itc). intelligent dma the i 2 s interrupt request can be used to invoke intelligent dma (idma). this enables data transfer between memory and the fifo to be performed using dma. the idma channel numbers set for the cause of i 2 s interrupt is 0x2e. the idma request and enable bits shown in table v. 5.6.2 must be set to 1 for idma to be invoked. transfer conditions, etc. on the idma side must also be set in advance. table v. 5.6.2 control bits for idma transfer interrupt i 2 s interr upt idma request bit ri2s(d0/0x3002ad) idma enable bit dei2s(d0/0x3002af) if a cause of interrupt occurs when the idma request and enable bits are set to 1 , idma is invoked. no inter - rupt request is generated at that point. an interrupt request is generated upon completion of the dma transfer. the bits can also be set so as not to generate an interrupt, with only a dma transfer performed. for details on dma transfer and how to control interrupts upon completion of dma transfer, refer to section ii.2, intelligent dma (idma). high-speed dma the cause of i 2 s interrupt cannot invoke high-speed dma (hsdma). dma transfer can be performed using the dma request signals that are directly output to hsdma from the i 2 s module. for the hsdma settings, see section v. 5.4, setting i 2 s module. trap vectors the default trap-vector address of the cause of i 2 s interrupt is 0xc00178. the base address of the trap table can be changed using the ttbr register.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-12 epson s1c33e08 technical manual v. 5.7 details of control registers table v. 5.7.1 list of i 2 s registers address 0x00301c00 0x00301c04 0x00301c08 0x00301c0c 0x00301c10 0x00301c14 0x00301c20 function sets i 2 s signals and controls module. sets i2s_mclk clock. sets lrclk clock. output control and status sets hsdma mode. fifo empty status fifo data write address register name i 2 s control register (pi2s_control) i 2 s mclk divide ratio register (pi2s_dv_mclk) i 2 s audio clock divide ratio register (pi2s_dv_lrclk) i 2 s start register (pi2s_start) i 2 s hsdma mode select register (pi2s_hsdmamd) i 2 s fifo status register (pi2s_fifo_empty) i 2 s fifo register (pi2s_fifo) siz e 32 32 32 32 32 32 32 the following describes each i 2 s control register. the i 2 s control registers are mapped in the 32 -bit device area from 0x301c00 to 0x301c20 . addresses 0x301c00 to 0x301c14 can be accessed in units of words, half-words, or bytes and address 0x301c20 can be accessed in units of words or half-words. note : when setting the i 2 s control registers, be sure to write a 0, and not a 1, for all reserved bits.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301c00: i 2 s control register (pi2s_control) name address register name bit function setting init. r/w remarks C i2sen i2souten chmd1 chmd0 wclkmd bclkpol dttmg dtform d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved i 2 s module enable i 2 s output enable i 2 s output channel mode i 2 s output word clock mode i 2 s output bit clock polarity i 2 s output data timing i 2 s output data format 1 enabled 0 disabled 1 enabled 0 disabled 1 l: high r: low 0 l: low r: high 1 negative 0 positive 1 not delayed 0 delayed 1 lsb first 0 msb first C 0 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00301c00 (w) 11 10 01 00 chmd[1:0] mode mute mono left mono right stereo i 2 s control register (pi2s_contrl) C d[31:8] reserved d7 i2sen: i 2 s enable bit enables/disables operation of the i 2 s module. 1 (r/w): enable (on) 0 (r/w): disable (off) (default) when i 2sen is set to 1, the i 2 s module starts operating and data transfer is enabled. when i 2sen is set to 0, the i 2 s module goes off. make sure that this bit is 0 before setting up data transfer conditions using the i 2 s registers. d6 i2souten: i 2 s output enable bit enables/disables output of the i 2 s signals. 1 (r/w): enable (on) 0 (r/w): disable (off) (default) when i 2 souten = 0 , the i2 s_mclk, i2 s_ws, and i2 s_sdo pins are fixed at 0 . the i2 s_sck pin is fixed at 0 (when bclkpol (d2) = 0) or 1 (when bclkpol (d2) = 1). when i 2souten is set to 1, all output pins enter standby status. d[5:4] chmd[1:0]: i 2 s output channel mode select bits selects the i 2 s output channel mode. table v. 5.7.2 selecting output channel mode chmd0 1 0 1 0 output channel mode mute mono (l) mono (r) stereo l channel 0 data output 0 data output r channel 0 0 data output data output chmd1 1 1 0 0 (default: 0b00 = stereo) the output channel mode can be switched even if data is being output. in this case, the mode changes after the current word output has finished. when mute mode is selected, the i 2 s_sdo pin is fixed at 0 . however, the fifo and shift register run the same as stereo mode and three clock signals are output normally. also in mono mode, the i 2s_sdo pin is fixed at 0 during the output period for the unselected channel. the fifo data is read out normally, therefore a dma request or interrupt occurs.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-14 epson s1c33e08 technical manual d3 wclkmd: i 2 s output word clock mode select bit selects the i 2 s_ws (lrclk) signal level for indicating a channel. 1 (r/w): high = l channel, low = r channel 0 (r/w): high = r channel, low = l channel (default) i2s_ws (lrclk) wclkmd = 0 (def ault) (l channel) (r channel) i2s_ws (lrclk) wclkmd = 1 (l channel) (r channel) figure v. 5.7.1 selecting word clock mode d2 bclkpol: i 2 s output bit clock polarity select bit selects the bit clock polarity. 1 (r/w): active low 0 (r/w): active high (default) when bclkpol is 0 , the i2 s_sdo output changes at the falling edge of i2 s_sck and the external dac samples the data bit at the rising edge of i 2s_sck. when bclkpol is set to 1 , the i2 s_sdo output changes at the rising edge of i2 s_sck and the exter - nal dac samples the data bit at the falling edge of i 2s_sck. i2s_sck i2s_sdo bclkpol = 0 (def ault) output is shifted at the f alling edge . the e xter nal da c samples the data at the r ising edge . i2s_sck i2s_sdo bclkpol = 1 output is shifted at the r ising edge . the e xter nal da c samples the data at the f alling edge . figure v. 5.7.2 selecting bit clock polarity d1 dttmg: i 2 s output data timing select bit selects the data bit output timing. 1 (r/w): i2s_ws edge 0 (r/w): 1 clock delay from i2 s_ws edge (default) in the default setting, the first bit of each data is output after one i 2 s_sck clock delay from the i2 s_ws signal edge. this timing can be changed by writing 1 to dttmg so that each data output will start at the i2s_ws signal edge. i2s_ws (lrclk) i2s_sck i2s_sdo dttmg = 0 (def ault) 1-cloc k dela y i2s_ws (lrclk) i2s_sck i2s_sdo dttmg = 1 1-cloc k dela y d0 d15 d2 d1 d0 d15 d14 d2 d1 d14 d0 d15 d14 d1 d0 d15 d14 d13 d1 d0 d13 d15 figure v. 5.7.3 selecting data output timing
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d0 dtform: i 2 s output data format select bit selects either msb first or lsb first as the data output direction. 1 (r/w): lsb first 0 (r/w): msb first (default) the output channel mode and hsdma mode do not affect the output data format and it is always treat - ed in 16 bit units. i2s_ws (lrclk) i2s_sck i2s_sdo dtform = 0 (def ault) i2s_ws (lrclk) i2s_sck i2s_sdo dtform = 1 d0 d15 d2 d1 d0 d15 d14 d2 d1 d14 d0 d15 d0 d13 d14 d15 d0 d1 d13 d14 d1 d15 figure v. 5.7.4 selecting data format
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-16 epson s1c33e08 technical manual 0x301c04: i 2 s mclk divide ratio register (pi2s_dv_mclk) name address register name bit function setting init. r/w remarks C i2smclk5 i2smclk4 i2smclk3 i2smclk2 i2smclk1 i2smclk0 d31C6 d5 d4 d3 d2 d1 d0 reserved i2s_mclk divide ratio selection C 0 0 0 0 0 0 C r/w 0 when being read. 00301c04 (w) 111111 111110 | 000001 000000 i2smclk[5:0] i2s_mclk mclk (cmu) /64 mclk (cmu) /63 | mclk (cmu) /2 mclk (cmu) /1 i 2 s mclk divide ratio register (pi2s_dv_mclk) C d[31:6] reserved d[5:0] i2smclk[5:0]: i2s_mclk divide ratio select bits configures the i 2 s master clock (i2s_mclk). the i 2 s module generates the i 2 s_mclk by dividing the operating clock (mclk generated by the cmu). specify the divide ratio using i 2smclk[5:0]. table v. 5.7.3 setting i2 s_mclk (master clock) i2smclk[5:0] 111111 111110 111101 : 000010 000001 000000 i2s_mclk mclk (cmu) /64 mclk (cmu) /63 mclk (cmu) /62 : mclk (cmu) /3 mclk (cmu) /2 mclk (cmu) /1 (default: 0b000000 = mclk/1)
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301c08: i 2 s audio clock divide ratio register (pi2s_dv_lrclk) name address register name bit function setting init. r/w remarks C lrclk2 lrclk1 lrclk0 d31C3 d2 d1 d0 reserved lrclk divide ratio selection C 0 0 0 C r/w 0 when being read. 00301c08 (w) 111 110 101 100 011 010 001 000 lrclk[2:0] lrclk i2s_mclk/512 i2s_mclk/448 i2s_mclk/384 i2s_mclk/320 i2s_mclk/256 i2s_mclk/192 i2s_mclk/128 i2s_mclk/64 i 2 s audio clock divide ratio register (pi2s_dv_lrclk) C d[31:3] reserved d[2:0] lrclk[2:0]: lrclk divide ratio select bits configures the lrclk clock (i 2s_ws signal). lrclk is generated by dividing i 2 s_mclk. specify the divide ratio using lrclk[2:0]. table v. 5.7.4 setting lrclk lrclk0 1 0 1 0 1 0 1 0 lrclk i2s_mclk/512 i2s_mclk/448 i2s_mclk/384 i2s_mclk/320 i2s_mclk/256 i2s_mclk/192 i2s_mclk/128 i2s_mclk/64 lrclk1 1 1 0 0 1 1 0 0 lrclk2 1 1 1 1 0 0 0 0 (default: 0b000 = i2s_mclk/64) configure lrclk to the pcm sampling frequency. the bit clock is configured to lrclk 32 [hz]. for example, the bit clock frequency is 1.536 mhz when lrclk is set to 48 khz.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-18 epson s1c33e08 technical manual 0x301c0c: i 2 s start register (pi2s_start) name address register name bit function setting init. r/w remarks C i2sbusy C i2sstart d31C8 d7 d6C1 d0 reserved i 2 s module busy flag reserved i 2 s start/stop 1 busy 0 idle 1 start 0 stop C 0 C 0 C r C r/w 0 when being read. 0 when being read. 00301c0c (w) i 2 s start register (pi2s_start) C C d[31:8] reserved d7 i2sbusy: i 2 s busy flag indicates the data output status of the i 2 s module. 1 (r): busy 0 (r): idle (default) i 2 sbusy is set to 1 when the i 2 s module starts data output and stays 1 while data is being output. this flag is cleared to 0 upon completion of the output operation. d[6:1] reserved d0 i2sstart: i 2 s start/stop control bit starts/stops the i 2 s output. 1 (r/w): start 0 (r/w): stop (default) writing 1 to i2 sstart starts serial output. writing 0 to i2 sstart stops output operation after the current word output has finished.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301c10: i 2 s hsdma mode select register (pi2s_hsdmamd) name address register name bit function setting init. r/w remarks C i2shsdma d31C1 d0 reserved i 2 s hsdma mode selection 1 16 bits 2 ch. 0 32 bits 1 ch. C 0 C r/w 0 when being read. 00301c10 (w) i 2 s hsdma mode select register (pi2s_hsdmamd) C d[31:1] reserved d0 i2shsdma: i 2 s hsdma mode select bit sets the hsdma mode. 1 (r/w): 16 bits 2 channels 0 (r/w): 32 bits 1 channel (default) select 32 bits 1 channel mode when 32 -bit pcm data that contains l and r channel samples is pre - pared in the memory. select 16 bits 2 channels mode when 16 -bit pcm data for each channel is pre - pared individually. the i 2 s module has two dma request signal outputs to hsdma (used to request l and r channel data). in the default setting (i 2 shsdma = 0 ), the dma request signal for the l channel is enabled and it is asserted when the fifo is not full. this signal invokes hsdma ch. 0 to transfer 32 -bit l&r data to the fifo in the set conditions. when i 2 shsdma is set to 1 , two dma request signals separated into l and r channels are enabled. in this case, both l and r channel dma request signals are asserted when the fifo is not full. these signals invoke hsdma ch. 0 and ch.1 . hsdma ch.0 writes 16 -bit l data to the l data field of the fifo in the set conditions and hsdma ch.1 writes 16 -bit r data to the r data field of the fifo. hsdma must be configured so that dma transfer above can be performed.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) v-5-20 epson s1c33e08 technical manual 0x301c14: i 2 s fifo status register (pi2s_fifo_empty) name address register name bit function setting init. r/w remarks C i2sfifoef d31C1 d0 reserved i 2 s fifo empty flag 1 empty 0 not empty C 0 C r 0 when being read. 00301c14 (w) i 2 s fifo status register (pi2s_fifo_empty) C d[31:1] reserved d0 i2sfifoef: i 2 s fifo empty flag indicates the fifo status. 1 (r): empty 0 (r): not empty (default) i 2 sfifoef is reset to 0 when pcm data is written to the fifo and is set to 1 when the i 2 s module has finished outputting the last data is in the fifo.
v peripheral modules 3 (interface): i 2 s interface (i 2 s) s1c33e08 technical manual epson v-5-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301c20: i 2 s fifo register (pi2s_fifo) name address register name bit function setting init. r/w remarks i2sfifo[31:0] d31C0 pcm data for writing to fifo 0 w 0 when being read. 00301c20 (w) i 2 s fifo register (pi2s_fifo) note : this register must be accessed using a word (32-bit) access instruction or a half-word (16-bit) ac - cess instruction. d[31:0] i2sfifo[31:0]: pcm data for writing to fifo write data to the fifo through this address. when writing a 32 -bit data for l and r channels together, perform word write to 0x301c20. when writing data for each channel individually, write a 16 -bit l channel data to 0x301c20 and a 16-bit r channel data to 0x301c22 using a half-word access instruction. the fifo size is 8 words so up to 8 samples of pcm data can be written to it. if writing data exceeds 8 words, the newest data of the fifo are overwritten. 0x301c20 d31 d0 (l channel data) (r channel data) 32-bit wr ite 0x301c22 0x301c20 d15 d15 d0 d0 (l channel data) (r channel data) 16-bit wr ite figure v. 5.7.5 writing to fifo
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i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual vi peripheral m odules 4 ( port s)

vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vi. 1 general-purpose i/o ports (gpio) vi.1.1 structure of i/o port the s 1 c 33 e 08 contains 74 i/o ports (p 0 [ 7 : 0 ], p 1 [ 7 : 0 ], p 2 [ 7 : 0 ], p 3 [ 6 : 0 ], p 4 [ 7 : 0 ], p 5 [ 7 : 0 ], p 6 [ 7 : 0 ], p 7 [ 4 : 0 ], p8[5:0 ], and p9[7:0 ]) that can be directed for input or output through the use of a program. although each pin is used for input/output from/to the internal peripheral circuits, some pins can be used as general-purpose input/output ports unless they are used for the peripheral circuits. figure vi. 1.1.1 shows the structure of a typical i/o port. v ddh v ss internal data bus p xx data register peripheral circuit input peripheral circuit output i/o control register peripheral circuit i/o control function select register i/o control signal figure vi. 1.1.1 structure of i/o port note : a pull-up resistor is provided for each pin and it can be enabled/disabled by software control. re - fer to section iii.4.4, pin control registers, for how to control the pull-up resistor. when the port is in output mode, the port pin is not pulled up regardless of how the pull-up control bit is set. vi.1.2 selecting the i/o pin functions the i/o ports concurrently serve as the input/output pins for peripheral circuits or bus signals. whether they are used as i/o ports or for peripheral circuits/bus signals can be selected bit-for-bit using the port function select regis - ters. all pins not used for peripheral circuits/bus signals can be used as general-purpose i/o ports. each i/o port pin (p xx ) is initialized for a default function at initial reset. for the pin that has two or more functions assigned, the port extended function select bits (cfp xx[1:0 ]) provided for each i/o port pin can be used to select the desired function. for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin func - tions. the subsequent sections explain the port functions assuming that the pin has been set as a general-purpose i/o port. notes : ? to use the p15Cp17 and p34Cp36 pins that are configured as the debug interface pins by de - fault for general-purpose inputs/outputs, clear trcmux (d 0/0x300014) to 0. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) note, however, that the pc trace function of the debugger cannot be used when trcmux (d0/0x300014) is set to 0. ? the mp3 decoder bios (mp3 decoder module) uses the p04 , p05 , p06 , and p07 ports for the i 2 s signal input/outputs. therefore, these ports cannot be used in the user program.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-2 epson s1c33e08 technical manual vi.1.3 i/o control register and i/o modes the i/o ports are directed for input or output modes by writing data to ioc x corresponding to each port bit. ? ioc0[7:0] : p07Cp00 i/o control bits in the p0 i/o control register (d[7:0]/0x300381) ? ioc1[7:0] : p17Cp10 i/o control bits in the p1 i/o control register (d[7:0]/0x300383) ? ioc2[7:0] : p27Cp20 i/o control bits in the p2 i/o control register (d[7:0]/0x300385) ? ioc3[6:0] : p36Cp30 i/o control bits in the p3 i/o control register (d[6:0]/0x300387) ? ioc4[7:0] : p47Cp40 i/o control bits in the p4 i/o control register (d[7:0]/0x300389) ? ioc5[7:0] : p57Cp50 i/o control bits in the p5 i/o control register (d[7:0]/0x30038b) ? ioc6[7:0] : p67Cp60 i/o control bits in the p6 i/o control register (d[7:0]/0x30038d) ? ioc8[5:0] : p85Cp80 i/o control bits in the p8 i/o control register (d[5:0]/0x300391) ? ioc9[7:0] : p97Cp90 i/o control bits in the p9 i/o control register (d[7:0]/0x300393) to set an i/o port for input, write 0 to the i/o control bit. i/o ports set for input mode are placed in the high-imped - ance state, and thus function as input ports. the port pin is pulled up when the pull-up resistor is enabled using the pin control register. in the input mode, the state of the input pin is read directly, so the data is 1 when the pin state is high (v ddh level) or 0 when the pin state is low (v ss level). even in the input mode, data can be written to the data register without affecting the pin state. to set an i/o port for output, write 1 to the i/o control bit. i/o port set for output function as output ports. when the port output data is 1 , the port outputs a high level (v ddh level); when the data is 0 , the port outputs a low level (v ss level). when the port is in output mode, the port pin is not pulled up even if the pull-up resistor is enabled. note : the p7 x port has no i/o control register, as it is input only port.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vi.1.4 input interrupt the i/o ports support 16 system of port input interrupts and two systems of key input interrupts. vi.1.4.1 port input interrupt the port input interrupt circuit has 16 interrupt systems (fpt15Cfpt0 ) and a port can be selected for generating each cause of interrupt. the interrupt condition can also be selected from between input signal edge and input signal level. figure vi. 1.4.1.1 shows the configuration of the port input interrupt circuit. fpt8 fpt9 fpt10 internal data bus fpt11 fpt12 fpt13 p43 p53 p67 p97 input polarity selection spptf edge/level selection septf address address fpt14 fpt15 fpt15 fpt14 fpt13 fpt12 fpt11 fpt10 fpt9 fpt8 input port selection sptf fpt7 fpt7 fpt6 fpt6 fpt5 fpt5 fpt4 fpt4 fpt3 fpt3 fpt2 fpt2 fpt1 fpt1 fpt0 fpt0 interrupt request interrupt signal generation figure vi. 1.4.1.1 configuration of port input interrupt circuit
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-4 epson s1c33e08 technical manual selecting input pins the causes of interrupt allow selection of an input pin from the four predefined pins independently. table vi. 1.4.1.1 shows the control bits and the selectable pins for each cause of interrupt. table vi. 1.4.1.1 selecting pins for port input interrupts cause of interrupt fpt15 fpt14 fpt13 fpt12 fpt11 fpt10 fpt9 fpt8 fpt7 fpt6 fpt5 fpt4 fpt3 fpt2 fpt1 fpt0 11 p97 p96 p95 p94 p93 p92 p91 p90 p63 p62 p61 p60 p33 p32 p31 p30 contr ol bit sptf[1:0] (d[7:6])/p or t input interr upt select register 4 (0x3003c5) spte[1:0] (d[5:4])/p or t input interr upt select register 4 (0x3003c5) sptd[1:0] (d[3:2])/p or t input interr upt select register 4 (0x3003c5) sptc[1:0] (d[1:0])/p or t input interr upt select register 4 (0x3003c5) sptb[1:0] (d[7:6])/p or t input interr upt select register 3 (0x3003c4) spt a[1:0] (d[5:4])/p or t input interr upt select register 3 (0x3003c4) spt9[1:0] (d[3:2])/p or t input interr upt select register 3 (0x3003c4) spt8[1:0] (d[1:0])/p or t input interr upt select register 3 (0x3003c4) spt7[1:0] (d[7:6])/p or t input interr upt select register 2 (0x3003c1) spt6[1:0] (d[5:4])/p or t input interr upt select register 2 (0x3003c1) spt5[1:0] (d[3:2])/p or t input interr upt select register 2 (0x3003c1) spt4[1:0] (d[1:0])/p or t input interr upt select register 2 (0x3003c1) spt3[1:0] (d[7:6])/p or t input interr upt select register 1 (0x3003c0) spt2[1:0] (d[5:4])/p or t input interr upt select register 1 (0x3003c0) spt1[1:0] (d[3:2])/p or t input interr upt select register 1 (0x3003c0) spt0[1:0] (d[1:0])/p or t input interr upt select register 1 (0x3003c0) 10 p67 p66 p65 p64 int_dcsi o int_usb usb_pdreq int_spi p17 p16 p15 p14 p13 p12 p11 p10 01 p53 p52 p51 p50 p83 p82 p81 p80 p27 p26 p25 p24 p23 p22 p21 p20 00 p43 p42 p41 p40 p73 p72 p71 p70 p07 p06 p05 p04 p03 p02 p01 p00 spt settings note : the fpt8, fpt9, fpt10, and fpt11 interrupt systems are shared with the spi, usb, and dc - sio interrupts. when using the spi, usb, or dcsio interrupts, set the spt bits to 0b10. in this case, the port input interrupt control registers and signals are used for the spi, usb, or dcsio interrupts. conditions for port input-interrupt generation each port input interrupt can be generated by the edge or level of the input signal. sept x (d x/0x3003c3 , d x - 8/0x3003c7 ) is used for this selection. when sept x is set to 1 , the fpt x interrupt will be generated at the signal edge. when sept x is set to 0, the fpt x interrupt will be generated by the input signal level. ? sept[7:0] : fpt x edge/level select bits in the port input interrupt edge/level select register 1 (d x /0x3003c3) ? sept[f:8] : fpt x edge/level select bits in the port input interrupt edge/level select register 2 (d x - 8/0x3003c7) furthermore, the signal polarity can be selected using sppt x (d x/0x3003c2, d x - 8/0x3003c6). ? sppt[7:0] : fpt x input polarity select bits in the port input interrupt polarity select register 1 (d x /0x3003c2) ? sppt[f:8] : fpt x input polarity select bits in the port input interrupt polarity select register 2 (d x - 8/0x3003c6) with these registers, the port input interrupt condition is decided as shown in table vi. 1.4.1.2. table vi. 1.4.1.2 port input interrupt condition sept x 1 1 0 0 sppt x 1 0 1 0 fpt x interrupt condition rising edge f alling edge high le ve l lo w le ve l when the input signal goes to the selected status, the cause-of-interrupt flag fp x is set to 1 and, if other inter - rupt conditions set by the interrupt controller are met, an interrupt is generated.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vi.1.4.2 key input interrupt the key input interrupt circuit has two interrupt systems (fpk 1 and fpk0 ) and a port group can be selected for generating each cause of interrupt. the interrupt condition can also be set by software. figure vi. 1.4.2.1 shows the configuration of the key input interrupt circuit. internal data bus p04, p14, p24, p44, p64, p54, p84, p94 p03, p13, p23, p43, p63, p53, p83, p93 p02, p12, p22, p42, p62, p52, p82, p92 p00 p10 p20 p40 p60 p50 p80 p90 input comparison register scpk0 input mask register smpk0 address address p01, p11, p21, p41, p61, p51, p81, p91 p00, p10, p20, p40, p60, p50, p80, p90 input port selection sppk0 fpk0 interrupt request interrupt signal generation fpk0 system p07, p17, p27, p33, p67, p73, C , p97 p06, p16, p26, p32, p66, p72, C , p96 p04 p14 p24 p30 p64 p70 p84 p94 input comparison register scpk1 input mask register smpk1 address address p05, p15, p25, p31, p65, p71, p85, p95 p04, p14, p24, p30, p64, p70, p84, p94 input port selection sppk1 fpk1 interrupt request interrupt signal generation fpk1 system figure vi. 1.4.2.1 configuration of key input interrupt circuit
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-6 epson s1c33e08 technical manual selecting input pins for the fpk 1 interrupt system, a four-bit input pin group (two input pins when using p8[5:4 ]) can be selected from the eight predefined groups. for the fpk 0 system, a five-bit input pin group can be selected. table vi. 1.4.2.1 shows the control bits and the selectable groups for each cause of interrupt. table vi. 1.4.2.1 selecting pins for key input interrupts cause of interrupt fpk1 fpk0 111 p9[7:4] p9[4:0] contr ol bit sppk1[2:0] (d[6:4]) ke y input interr upt select sppk0[2:0] (d[2:0]) register (0x3003d0) 110 p8[5:4] p8[4:0] 101 p7[3:0] p5[4:0] 100 p6[7:4] p6[4:0] 011 p3[3:0] p4[4:0] 010 p2[7:4] p2[4:0] 001 p1[7:4] p1[4:0] 000 p0[7:4] p0[4:0] sppk settings conditions for key input-interrupt generation the key input interrupt circuit has the input mask bits smpk 0[4:0 ] (d[4:0 ]/0x3003d4 ) for fpk0 and smpk1[3:0 ] (d[3:0]/0x3003d5 ) for fpk1 , and the input comparison bits scpk0[4:0 ] (d[4:0]/0x3003d2 ) for fpk0 and scpk1[3:0] (d[3:0]/0x3003d3) for fpk1 to set input-interrupt conditions. ? smpk0[4:0] : fpk0 input mask bits in the key input interrupt (fpk0) input mask register (d[4:0]/0x3003d4) ? smpk1[3:0] : fpk1 input mask bits in the key input interrupt (fpk1) input mask register (d[3:0]/0x3003d5) ? scpk0[4:0] : fpk0 input comparison bits in the key input interrupt (fpk0) input comparison register (d[4:0]/0x3003d2) ? scpk1[3:0] : fpk1 input comparison bits in the key input interrupt (fpk1) input comparison register (d[3:0]/0x3003d3) the input mask bit (smpk) is used to mask the input pin that is not used for an interrupt. this bit masks each input pin, whereas the interrupt enable bit of the interrupt controller masks the cause of interrupt for each inter - rupt group. the input comparison bit (scpk) is used to select whether an interrupt for each input port is to be generated at the rising or falling edge of the input. a change in state occurs so that the input pin enabled for interrupt by the interrupt mask bit (smpk) and the content of the input comparison bit (scpk) become unmatched after being matched, the cause-of-interrupt flag (fk) is set to 1 and, if other interrupt conditions are met, an interrupt is generated. figure vi. 1.4.2.2 shows cases in which a fpk0 interrupt is generated. here, it is assumed that the p0[4:0 ] pins are selected for the input-pin group and the control register of the interrupt controller is set so as to enable gen - eration of a fpk0 interrupt. input mask register smpk0 input comparison register scpk0 smpk04 1 smpk03 1 smpk02 1 smpk01 1 smpk00 0 input port p0 (1) (initial value) interrupt generation p04 1 scpk04 1 scpk03 1 scpk02 0 scpk01 1 scpk00 0 with the settings shown above, fpk0 interrupt is generated under the condition shown below. (2) p04 1 (3) p04 1 (4) p04 1 p03 1 p02 0 p01 1 p00 0 p03 1 p02 0 p01 1 p00 1 p03 0 p02 0 p01 1 p00 0 p03 0 p02 1 p01 1 p00 0 because interrupt has been disabled for p00, an interrupt will be generated when non-conformity occurs between the contents of the four bits p01Cp04 and the four input comparison bits scpk0[4:1]. figure vi. 1.4.2.2 fpk0 interrupt generation example (when p0[4:0 ] is selected by sppk0[2:0])
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 since p 00 is masked from interrupt by smpk00 (d0/0x3003d4), no interrupt occurs at that point (2 ) above. next, because p 03 becomes 0 at (3 ), an interrupt is generated due to the lack of a match between the data of the input pin p 0[4:1 ] that is enabled for interrupt and that of the input comparison register scpk0[4:1 ] (d[4:1]/ 0x3003d2). since only a change in states in which the input data and the content of scpk x (d[4:0]/0x3003d2 , d[3:0]/ 0x3003d3 ) become unmatched after being matched constitutes an interrupt generation condition as described above, no interrupt is generated when a change in states from one unmatched state to another, as in ( 4 ), occurs. consequently, if another interrupt is to be generated again following the occurrence of an interrupt, the state of the input pin must be temporarily restored to the same content as that of scpk x , or scpk x must be set again. note that the input pins masked from interrupt by smpk x (d[4:0]/0x3003d4 , d[3:0]/0x3003d5 ) do not affect interrupt generation conditions. an interrupt is generated for fpk 1 in the same way as described above. vi.1.4.3 control registers of the interrupt controller table vi. 1.4.3.1 shows the control registers of the interrupt controller that are provided for each input-interrupt sys - tem. table vi. 1.4.3.1 control registers of interrupt controller system fpt15 fpt14 fpt13 fpt12 fpt11 fpt10 fpt9 fpt8 fpt7 fpt6 fpt5 fpt4 fpt3 fpt2 fpt1 fpt0 fpk1 fpk0 cause-of-interrupt fla g fp15(d7/0x3002a9) fp14(d6/0x3002a9) fp13(d5/0x3002a9) fp12(d4/0x3002a9) fp11(d3/0x3002a9) fp10(d2/0x3002a9) fp9(d1/0x3002a9) fp8(d0/0x3002a9) fp7(d6/0x300287) fp6(d5/0x300287) fp5(d4/0x300287) fp4(d3/0x300287) fp3(d3/0x300280) fp2(d2/0x300280) fp1(d1/0x300280) fp0(d0/0x300280) fk1(d5/0x300280) fk0(d4/0x300280) interrupt priority register pp15l[2:0](d[6:4]/0x3002a3) pp14l[2:0](d[2:0]/0x3002a3) pp13l[2:0](d[6:4]/0x3002a2) pp12l[2:0](d[2:0]/0x3002a2) pp11l[2:0](d[6:4]/0x3002a1) pp10l[2:0](d[2:0]/0x3002a1) pp9l[2:0](d[6:4]/0x3002a0) pp8l[2:0](d[2:0]/0x3002a0) pp7l[2:0](d[6:4]/0x30026d) pp6l[2:0](d[2:0]/0x30026d) pp5l[2:0](d[6:4]/0x30026c) pp4l[2:0](d[2:0]/0x30026c) pp3l[2:0](d[6:4]/0x300261) pp2l[2:0](d[2:0]/0x300261) pp1l[2:0](d[6:4]/0x300260) pp0l[2:0](d[2:0]/0x300260) pk1l[2:0](d[6:4]/0x300262) pk0l[2:0](d[2:0]/0x300262) interrupt enable register ep15(d7/0x3002a6) ep14(d6/0x3002a6) ep13(d5/0x3002a6) ep12(d4/0x3002a6) ep11(d3/0x3002a6) ep10(d2/0x3002a6) ep9(d1/0x3002a6) ep8(d0/0x3002a6) ep7(d6/0x300277) ep6(d5/0x300277) ep5(d4/0x300277) ep4(d3/0x300277) ep3(d3/0x300270) ep2(d2/0x300270) ep1(d1/0x300270) ep0(d0/0x300270) ek1(d5/0x300270) ek0(d4/0x300270) when the interrupt generation condition described above is met, the corresponding cause-of-interrupt flag is set to 1 . if the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated. interrupts due to a cause of interrupt can be disabled by leaving the interrupt enable register bit for that cause of interrupt set to 0 . the cause-of-interrupt flag is set to 1 whenever interrupt generation conditions are met, regardless of the setting of the interrupt enable register. the interrupt priority register sets the interrupt priority level ( 0 to 7 ) for each interrupt system. an interrupt request to the cpu is accepted only when no other interrupt request of a higher priority has been generated. in addition, only when the psr's ie bit = 1 (interrupts enabled) and the set value of the il is smaller than the input interrupt level set using the interrupt priority register will the input interrupt request actually be accepted by the cpu. for details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to section iii.2, interrupt controller (itc).
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-8 epson s1c33e08 technical manual intelligent dma the port input interrupt system can invoke an intelligent dma (idma) through the use of its cause of inter - rupt. this enables the port inputs to be used as a trigger to perform dma transfer. the following shows the idma channel numbers assigned to each cause of interrupt: idma ch. idma ch. fpt 0 input interrupt: 1 fpt8 input interrupt: 38 fpt 1 input interrupt: 2 fpt9 input interrupt: 39 fpt 2 input interrupt: 3 fpt10 input interrupt: 40 fpt 3 input interrupt: 4 fpt11 input interrupt: 41 fpt 4 input interrupt: 28 fpt12 input interrupt: 42 fpt 5 input interrupt: 29 fpt13 input interrupt: 43 fpt 6 input interrupt: 30 fpt14 input interrupt: 44 fpt 7 input interrupt: 31 fpt15 input interrupt: 45 for idma to be invoked, the idma request and idma enable bits shown in table vi. 1.4.3.2 must be set to 1 in advance. transfer conditions, etc. must also be set on the idma side in advance. table vi. 1.4.3.2 control bits for idma transfer system fpt15 fpt14 fpt13 fpt12 fpt11 fpt10 fpt9 fpt8 fpt7 fpt6 fpt5 fpt4 fpt3 fpt2 fpt1 fpt0 idma request bit rp15(d7/0x3002a c) rp14(d6/0x3002a c) rp13(d5/0x3002a c) rp12(d4/0x3002a c) rp11(d3/0x3002a c) rp10(d2/0x3002a c) rp9(d1/0x3002a c) rp8(d0/0x3002a c) rp7(d7/0x300293) rp6(d6/0x300293) rp5(d5/0x300293) rp4(d4/0x300293) rp3(d3/0x300290) rp2(d2/0x300290) rp1(d1/0x300290) rp0(d0/0x300290) idma enable bit dep15(d7/0x3002ae) dep14(d6/0x3002ae) dep13(d5/0x3002ae) dep12(d4/0x3002ae) dep11(d3/0x3002ae) dep10(d2/0x3002ae) dep9(d1/0x3002ae) dep8(d0/0x3002ae) dep7(d7/0x300297) dep6(d6/0x300297) dep5(d5/0x300297) dep4(d4/0x300297) dep3(d3/0x300294) dep2(d2/0x300294) dep1(d1/0x300294) dep0(d0/0x300294) if the idma request and enable bits are set to 1 , idma is invoked through generation of a cause of interrupt. no interrupt request is generated at that point. an interrupt request is generated after the dma transfer is com - pleted. the registers can also be set so as not to generate an interrupt, with only dma transfers performed. for details on idma transfers and interrupt control upon completion of idma transfer, refer to section ii. 2, intelligent dma (idma). trap vectors the trap-vector address of each input default cause of interrupt is set as follows: fpt 0 input interrupt: 0xc00040 fpt7 input interrupt: 0xc0011c fpt 1 input interrupt: 0xc00044 fpt8 input interrupt: 0xc00150 fpt 2 input interrupt: 0xc00048 fpt9 input interrupt: 0xc00154 fpt 3 input interrupt: 0xc0004 c fpt10 input interrupt: 0xc00158 fpk 0 input interrupt: 0xc00050 fpt11 input interrupt: 0xc0015c fpk 1 input interrupt: 0xc00054 fpt12 input interrupt: 0xc00160 fpt 4 input interrupt: 0xc00110 fpt13 input interrupt: 0xc00164 fpt 5 input interrupt: 0xc00114 fpt14 input interrupt: 0xc00168 fpt 6 input interrupt: 0xc00118 fpt15 input interrupt: 0xc0016c the base address of the trap table can be changed using the ttbr register.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vi.1.5 i/o port operating clock the gpio module is clocked by the port operating clocks supplied by the cmu. the cmu provides the clock paths with a control bit shown below for the gpio. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) gpio clock (port_clk) this clock (mclk) is used for the gpio circuit and is required for accessing the gpio control registers. gpio_cke (d8/0x301b04 ) is used for clock supply control (default: on). ? gpio_cke : gpio normal clock control bit in the gated clock control register 1 (d8/0x301b04) (2 ) gpio no stop clock (port_nostop_clk) this clock (mclk) is used for reading input ports and generating input interrupts. this clock can be automati - cally turned off in halt mode (see section iii. 1.9.2 ) by setting gpionstp_hcke (d27/0x301b04 ) to 0 (de - fault: on). ? gpionstp_hcke : gpio no stop clock control (halt) bit in the gated clock control register 1 (d27/0x301b04) note, however, that the gpio no stop clock is required in halt mode when using an input interrupt to cancel halt mode. for details of the generation and control of the port operating clock, see section iii. 1, clock management unit (cmu). note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be re - moved by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless re - writing said registers.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-10 epson s1c33e08 technical manual vi.1.6 details of control registers table vi. 1.6.1 list of i/o port registers address 0x00300380 0x00300381 0x00300382 0x00300383 0x00300384 0x00300385 0x00300386 0x00300387 0x00300388 0x00300389 0x0030038a 0x0030038b 0x0030038c 0x0030038d 0x0030038e 0x00300390 0x00300391 0x00300392 0x00300393 0x003003a0 0x003003a1 0x003003a2 0x003003a3 0x003003a4 0x003003a5 0x003003a6 0x003003a7 0x003003a8 0x003003a9 0x003003aa 0x003003ab 0x003003ac 0x003003ad 0x003003ae 0x003003af 0x003003b0 0x003003b1 0x003003b2 0x003003b3 0x003003c0 0x003003c1 0x003003c2 0x003003c3 0x003003c4 0x003003c5 0x003003c6 0x003003c7 0x003003d0 0x003003d2 0x003003d3 0x003003d4 0x003003d5 function p0 port data read/write register controls p0 port input/output direction. p1 port data read/write register controls p1 port input/output direction. p2 port data read/write register controls p2 port input/output direction. p3 port data read/write register controls p3 port input/output direction. p4 port data read/write register controls p4 port input/output direction. p5 port data read/write register controls p5 port input/output direction. p6 port data read/write register controls p6 port input/output direction. p7 port data read/write register p8 port data read/write register controls p8 port input/output direction. p9 port data read/write register controls p9 port input/output direction. sets p00Cp03 port pin function. sets p 04Cp07 port pin function. sets p 10Cp13 port pin function. sets p14Cp17 port pin function. sets p20Cp23 port pin function. sets p24Cp27 port pin function. sets p30Cp33 port pin function. sets p34Cp36 port pin function. sets p40Cp43 port pin function. sets p44Cp47 port pin function. sets p50Cp53 port pin function. sets p54Cp57 port pin function. sets p60Cp63 port pin function. sets p64Cp67 port pin function. sets p70Cp73 port pin function. sets p74 port pin function. sets p80Cp83 port pin function. sets p84Cp85 port pin function. sets p90Cp93 port pin function. sets p94Cp97 port pin function. selects ports used for fpt0Cfpt3 port input interrupts. selects ports used for fpt4Cfpt7 port input interrupts. selects signal polarity to generate fpt0Cfpt7 port input interrupts. selects fpt0Cfpt7 port interrupt trigger condition. selects ports used for fpt8Cfpt11 port input interrupts. selects ports used for fpt12Cfpt15 port input interrupts. selects signal polarity to generate fpt8Cfpt15 port input interrupts. selects fpt8Cfpt15 port interrupt trigger condition. selects ports used for key input interrupts. sets fpk0 interrupt trigger edge condition. sets fpk1 interrupt trigger edge condition. enables/disables ports for generating fpk0 interrupts. enables/disables ports for generating fpk1 interrupts. register name p0 port data register (pp0_p0d) p0 i/o control register (pp0_ioc0) p1 port data register (pp1_p1d) p1 i/o control register (pp1_ioc1) p2 port data register (pp2_p2d) p2 i/o control register (pp2_ioc2) p3 port data register (pp3_p3d) p3 i/o control register (pp3_ioc3) p4 port data register (pp4_p4d) p4 i/o control register (pp4_ioc4) p5 port data register (pp5_p5d) p5 i/o control register (pp5_ioc5) p6 port data register (pp6_p6d) p6 i/o control register (pp6_ioc6) p7 port data register (pp7_p7d) p8 port data register (pp8_p8d) p8 i/o control register (pp8_ioc8) p9 port data register (pp9_p9d) p9 i/o control register (pp9_ioc9) p00Cp03 port function select register (pp0_03_cfp) p04Cp07 port function select register (pp0_47_cfp) p10Cp13 port function select register (pp1_03_cfp) p14Cp17 port function select register (pp1_47_cfp) p20Cp23 port function select register (pp2_03_cfp) p24Cp27 port function select register (pp2_47_cfp) p30Cp33 port function select register (pp3_03_cfp) p34Cp36 port function select register (pp3_46_cfp) p40Cp43 port function select register (pp4_03_cfp) p44Cp47 port function select register (pp4_47_cfp) p50Cp53 port function select register (pp5_03_cfp) p54Cp57 port function select register (pp5_47_cfp) p60Cp63 port function select register (pp6_03_cfp) p64Cp67 port function select register (pp6_47_cfp) p70Cp73 port function select register (pp7_03_cfp) p74 port function select register (pp7_4_cfp) p80Cp83 port function select register (pp8_03_cfp) p84Cp85 port function select register (pp8_45_cfp) p90Cp93 port function select register (pp9_03_cfp) p94Cp97 port function select register (pp9_47_cfp) port input interrupt select register 1 (ppintsel_spt03) port input interrupt select register 2 (ppintsel_spt47) port input interrupt polarity select register 1 (ppintpol_spp07) port input interrupt edge/level select register 1 (ppintel_sept07) port input interrupt select register 3 (ppintsel_spt811) port input interrupt select register 4 (ppintsel_spt1215) port input interrupt polarity select register 2 (ppintpol_spp815) port input interrupt edge/level select register 2 (ppintel_sept815) key input interrupt select register (pkintsel_sppk01) key input interrupt (fpk0) input comparison register (pkintcomp_scpk0) key input interrupt (fpk1) input comparison register (pkintcomp_scpk1) key input interrupt (fpk0) input mask register (pkintcomp_smpk0) key input interrupt (fpk1) input mask register (pkintcomp_smpk1) siz e 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 the following describes each i/o port control register. the i/o port control registers are mapped in the 8 -bit device area from 0x300380 to 0x3003d5, and can be accessed in units of bytes.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300380C0x300392: p x port data registers (pp x _p x d) name address register name bit function setting init. r/w remarks p x 7d p x 6d p x 5d p x 4d p x 3d p x 2d p x 1d p x 0d d7 d6 d5 d4 d3 d2 d1 d0 p x 7 i/o port data p x 6 i/o port data p x 5 i/o port data p x 4 i/o port data p x 3 i/o port data p x 2 i/o port data p x 1 i/o port data p x 0 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 00300380 | 00300392 (b) 1 high 0 low p x port data register (pp x _p x d) note : the letter x in bit names, etc., denotes a port number from 0 to 6 and 8, 9. 0x300380 p0 port data register (pp0_p0d) 0x300382 p1 port data register (pp1_p1d) 0x300384 p2 port data register (pp2_p2d) 0x300386 p3 port data register (pp3_p3d) 0x300388 p4 port data register (pp4_p4d) 0x30038a p5 port data register (pp5_p5d) 0x30038c p6 port data register (pp6_p6d) 0x300390 p8 port data register (pp8_p8d) 0x300392 p9 port data register (pp9_p9d) these registers are used to read data from i/o-port pins or to set output data. (default: external pin status) 1 (r/w): high level 0 (r/w): low level when an i/o port is set for output, the data written to the register is directly output to the i/o port pin. if the data written to the port is 1 , the port pin is set high (v dd or v ddh level); if the data is 0 , the port pin is set low (v ss level). even in input mode, data can be written to the port data register. when the register is read, the voltage level on the port pin is read out regardless of whether an i/o port is set for input or output mode. if the pin voltage is high (v dd or v ddh level), 1 is read out as input data; if the pin voltage is low (v ss level), 0 is read out as input data.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-12 epson s1c33e08 technical manual 0x30038e: p7 port data register (pp7_p7d) name address register name bit function setting init. r/w remarks C p74d p73d p72d p71d p70d d7C5 d4 d3 d2 d1 d0 reserved p74 input port data p73 input port data p72 input port data p71 input port data p70 input port data C ext. ext. ext. ext. ext. C r r r r r 0 when being read. ext.: the initial value depends on the external pin status. 0030038e (b) 1 high 0 low p7 port data register (pp7_p7d) C this register is used to read data from p 7 i/o-port pins. (default: external pin status) 1 (r): high level 0 (r): low level the voltage level on the port pin is read out. if the pin voltage is high (av dd and v ddh level), 1 is read out as input data; if the pin voltage is low (v ss level), 0 is read out as input data. note : the p7 port has no output function, therefore this register is a read only register.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300381C0x300393: p x i/o control registers (pp x _ioc x ) name address register name bit function setting init. r/w remarks ioc x 7 ioc x 6 ioc x 5 ioc x 4 ioc x 3 ioc x 2 ioc x 1 ioc x 0 d7 d6 d5 d4 d3 d2 d1 d0 p x 7 i/o control p x 6 i/o control p x 5 i/o control p x 4 i/o control p x 3 i/o control p x 2 i/o control p x 1 i/o control p x 0 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300381 | 00300393 (b) 1 output 0 input p x i/o control register (pp x _ioc x ) note : the letter x in bit names, etc., denotes a port number from 0 to 6 and 8, 9. 0x300381 p0 i/o control register (pp0_ioc0) 0x300383 p1 i/o control register (pp1_ioc1) 0x300385 p2 i/o control register (pp2_ioc2) 0x300387 p3 i/o control register (pp3_ioc3) 0x300389 p4 i/o control register (pp4_ioc4) 0x30038b p5 i/o control register (pp5_ioc5) 0x30038d p6 i/o control register (pp6_ioc6) 0x300391 p8 i/o control register (pp8_ioc8) 0x300393 p9 i/o control register (pp9_ioc9) directs an i/o port for input or output and indicates the i/o c ontrol signal value of the port. 1 (r/w): output mode 0 (r/w): input mode (default) each i/o control register bit corresponds to each i/o port. when ioc x is set to 1 , the corresponding i/o port is di - rected for output; if it is set to 0, the i/o port is directed for input. when the pin is used for a peripheral function, the input/output direction depends on the peripheral function. when the register is read, the i/o control signal value for the port pin is read out. when i/o port function is se - lected using the port function select register, the value written to the ioc register is read out as is. when peripheral function is selected, the read value depends on the peripheral circuit status and may not indicate the value written to ioc x .
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-14 epson s1c33e08 technical manual 0x3003a0C0x3003b3: p xx port function select registers (pp x _ xx _cfp) name address register name bit function setting init. r/w remarks cfp x 31 cfp x 30 or cfp x 71 cfp x 70 cfp x 21 cfp x 20 or cfp x 61 cfp x 60 cfp x 11 cfp x 10 or cfp x 51 cfp x 50 cfp x 01 cfp x 00 or cfp x 41 cfp x 40 d7 d6 d5 d4 d3 d2 d1 d0 p x 3/p x7 port extended function p x 2/p x6 port extended function p x 1/p x5 port extended function p x 0/p x4 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a0 | 003003b3 (b) p x 0Cp x 3 port function select register (pp x _ 03 _cfp) or p x 4Cp x 7 port function select register (pp x _ 47 _cfp) cfp x3/7[1:0] function pin function 3 pin function 2 pin function 1 pin function 0 cfp x2/6[1:0] function pin function 3 pin function 2 pin function 1 pin function 0 cfp x1/5[1:0] function pin function 3 pin function 2 pin function 1 pin function 0 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp x0/4[1:0] function pin function 3 pin function 2 pin function 1 pin function 0 note : the letter x in bit names, etc., denotes a port number from 0 to 9. 0x3003a0 p00Cp03 port function select register (pp0_03_cfp) 0x3003a1 p04Cp07 port function select register (pp0_47_cfp) 0x3003a2 p10Cp13 port function select register (pp1_03_cfp) 0x3003a3 p14Cp17 port function select register (pp1_47_cfp) 0x3003a4 p20Cp23 port function select register (pp2_03_cfp) 0x3003a5 p24Cp27 port function select register (pp2_47_cfp) 0x3003a6 p30Cp33 port function select register (pp3_03_cfp) 0x3003a7 p34Cp36 port function select register (pp3_46_cfp) 0x3003a8 p40Cp43 port function select register (pp4_03_cfp) 0x3003a9 p44Cp47 port function select register (pp4_47_cfp) 0x3003aa p50Cp53 port function select register (pp5_03_cfp) 0x3003ab p54Cp57 port function select register (pp5_47_cfp) 0x3003ac p60Cp63 port function select register (pp6_03_cfp) 0x3003ad p64Cp67 port function select register (pp6_47_cfp) 0x3003ae p70Cp73 port function select register (pp7_03_cfp) 0x3003af p74 port function select register (pp7_4_cfp) 0x3003b0 p80Cp83 port function select register (pp8_03_cfp) 0x3003b1 p84Cp85 port function select register (pp8_45_cfp) 0x3003b2 p90Cp93 port function select register (pp9_03_cfp) 0x3003b3 p94Cp97 port function select register (pp9_47_cfp) these bits select the function of each i/o port pin. (default: 0b00 = pin function 0) the i/o ports concurrently serve as the input/output pins for peripheral circuits or bus signals. whether they are used as i/o ports or for peripheral circuits/bus signals can be selected bit-for-bit using these registers. all pins not used for peripheral circuits/bus signals can be used as general-purpose i/o ports. for details of pin functions, see section i. 3.3, switching over the multiplexed pin functions.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3003c0: port input interrupt select register 1 (ppintsel_spt03) 0x3003c1: port input interrupt select register 2 (ppintsel_spt47) 0x3003c4: port input interrupt select register 3 (ppintsel_spt811) 0x3003c5: port input interrupt select register 4 (ppintsel_spt1215) name address register name bit function setting init. r/w remarks spt31 spt30 spt21 spt20 spt11 spt10 spt01 spt00 d7 d6 d5 d4 d3 d2 d1 d0 fpt3 interrupt input port selectio n fpt2 interrupt input port selectio n fpt1 interrupt input port selectio n fpt0 interrupt input port selectio n 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c0 (b) port input interrupt select register 1 (ppintsel _spt03) spt3[1:0] port p33 p13 p23 p03 spt2[1:0] port p32 p12 p22 p02 spt1[1:0] port p31 p11 p21 p01 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 spt0[1:0] port p30 p10 p20 p00 spt71 spt70 spt61 spt60 spt51 spt50 spt41 spt40 d7 d6 d5 d4 d3 d2 d1 d0 fpt7 interrupt input port selectio n fpt6 interrupt input port selectio n fpt5 interrupt input port selectio n fpt4 interrupt input port selectio n 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c1 (b) port input interrupt select register 2 (ppintsel _spt47) spt7[1:0] port p63 p17 p27 p07 spt6[1:0] port p62 p16 p26 p06 spt5[1:0] port p61 p15 p25 p05 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 spt4[1:0] port p60 p14 p24 p04 sptb1 sptb0 spta1 spta0 spt91 spt90 spt81 spt80 d7 d6 d5 d4 d3 d2 d1 d0 fpt11 interrupt input port selection fpt10 interrupt input port selection fpt9 interrupt input port selectio n fpt8 interrupt input port selectio n 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c4 (b) port input interrupt select register 3 (ppintsel _spt811) sptb[1:0] port p93 int_dcsio p83 p73 spta[1:0] port p92 int_usb p82 p72 spt9[1:0] port p91 usb_pdreq p81 p71 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 spt8[1:0] port p90 int_spi p80 p70
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-16 epson s1c33e08 technical manual name address register name bit function setting init. r/w remarks sptf1 sptf0 spte1 spte0 sptd1 sptd0 sptc1 sptc0 d7 d6 d5 d4 d3 d2 d1 d0 fpt15 interrupt input port selection fpt14 interrupt input port selection fpt13 interrupt input port selection fpt12 interrupt input port selection 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c5 (b) port input interrupt select register 4 (ppintsel _spt1215) sptf[1:0] port p97 p67 p53 p43 spte[1:0] port p96 p66 p52 p42 sptd[1:0] port p95 p65 p51 p41 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 sptc[1:0] port p94 p64 p50 p40 spt x [1:0]: fpt x interrupt input port select bits selects an input pin used to generate the fpt x port input interrupt. table vi. 1.6.2 selecting pins for port input interrupts interrupt system fpt15 fpt14 fpt13 fpt12 fpt11 fpt10 fpt9 fpt8 fpt7 fpt6 fpt5 fpt4 fpt3 fpt2 fpt1 fpt0 11 p97 p96 p95 p94 p93 p92 p91 p90 p63 p62 p61 p60 p33 p32 p31 p30 10 p67 p66 p65 p64 int_dcsio int_usb usb_pdreq int_spi p17 p16 p15 p14 p13 p12 p11 p10 01 p53 p52 p51 p50 p83 p82 p81 p80 p27 p26 p25 p24 p23 p22 p21 p20 00 p43 p42 p41 p40 p73 p72 p71 p70 p07 p06 p05 p04 p03 p02 p01 p00 spt settings (default: 0b00) note : the fpt8, fpt9, fpt10, and fpt11 interrupt systems are shared with the spi, usb, and dc - sio interrupts. when using the spi, usb, or dcsio interrupts, set the spt bits to 0b10. in this case, the port input interrupt control registers and signals are used for the spi, usb, or dcsio interrupts.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3003c2: port input interrupt polarity select register 1 (ppintpol_spp07) 0x3003c6: port input interrupt polarity select register 2 (ppintpol_spp815) name address register name bit function setting init. r/w remarks 1 high level or rising edge 0 low level or falling edge sppt7 sppt6 sppt5 sppt4 sppt3 sppt2 sppt1 sppt0 d7 d6 d5 d4 d3 d2 d1 d0 fpt7 input polarity selection fpt6 input polarity selection fpt5 input polarity selection fpt4 input polarity selection fpt3 input polarity selection fpt2 input polarity selection fpt1 input polarity selection fpt0 input polarity selection 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 003003c2 (b) port input interrupt polarity select register 1 (ppintpol _spp07) 1 high level or rising edge 0 low level or falling edge spptf sppte spptd spptc spptb sppta sppt9 sppt8 d7 d6 d5 d4 d3 d2 d1 d0 fpt15 input polarity selection fpt14 input polarity selection fpt13 input polarity selection fpt12 input polarity selection fpt11 input polarity selection fpt10 input polarity selection fpt9 input polarity selection fpt8 input polarity selection 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 003003c6 (b) port input interrupt polarity select register 2 (ppintpol _spp815) these registers are used to select the input signal polarity for generating port input interrupts. 1 (r/w): high level or rising edge (default) 0 (r/w): low level or falling edge sppt x is the input polarity select bit corresponding to the fpt x interrupt. when sppt x is set to 1 , the fpt x in - terrupt will be generated by a high level input or at the rising edge. when sppt x is set to 0 , the interrupt will be generated by a low level input or at the falling edge. an edge or a level interrupt is selected by sept x (0x3003c3, 0x3003c7). d[7:0]/0x3003c2 sppt[7:0]: fpt[7:0] interrupt polarity select bits selects input signal polarity to generate an fpt[ 7:0] interrupt. d[7:0]/0x3003c6 sppt[f:8]: fpt[15:8] interrupt polarity select bits selects input signal polarity to generate an fpt[ 15:8] interrupt.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-18 epson s1c33e08 technical manual 0x3003c3: port input interrupt edge/level select register 1 (ppintel_sept07) 0x3003c7: port input interrupt edge/level select register 2 (ppintel_sept815) name address register name bit function setting init. r/w remarks 1 edge 0 level sept7 sept6 sept5 sept4 sept3 sept2 sept1 sept0 d7 d6 d5 d4 d3 d2 d1 d0 fpt7 edge/level selection fpt6 edge/level selection fpt5 edge/level selection fpt4 edge/level selection fpt3 edge/level selection fpt2 edge/level selection fpt1 edge/level selection fpt0 edge/level selection 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 003003c3 (b) port input interrupt edge/level select register 1 (ppintel _sept07) 1 edge 0 level septf septe septd septc septb septa sept9 sept8 d7 d6 d5 d4 d3 d2 d1 d0 fpt15 edge/level selection fpt14 edge/level selection fpt13 edge/level selection fpt12 edge/level selection fpt11 edge/level selection fpt10 edge/level selection fpt9 edge/level selection fpt8 edge/level selection 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 003003c7 (b) port input interrupt edge/level select register 2 (ppintel _sept815) these registers are used to select an edge trigger or a level sense condition for generating port input interrupts. 1 (r/w): edge (default) 0 (r/w): level sept x is the edge/level select bit corresponding to the fpt x interrupt. when sept x is set to 1 , the fpt x inter - rupt will be generated at the signal edge. either falling edge or rising edge can be selected by sppt x (0x3003c2, 0x3003c6 ). when sept x is set to 0 , the interrupt will be generated by the level (high or low) specified with sppt x . d[7:0]/0x3003c3 sept[7:0]: fpt[7:0] edge/level select bits selects an edge trigger or a level sense for the fpt[ 7:0] interrupt. d[7:0]/0x3003c7 sept[f:8]: fpt[15:8] edge/level select bits selects an edge trigger or a level sense for the fpt[ 15:8] interrupt.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3003d0: key input interrupt select register (pkintsel_sppk01) name address register name bit function setting init. r/w remarks C sppk12 sppk11 sppk10 C sppk02 sppk01 sppk00 d7 d6 d5 d4 d3 d2 d1 d0 reserved fpk1 interrupt input port selectio n reserved fpk0 interrupt input port selectio n C 0 0 0 C 0 0 0 C r/w C r/w 0 when being read. 0 when being read. 003003d0 (b) key input interrupt select register (pkintsel _sppk01) sppk1[2:0] port p9[7:4] p8[5:4] p7[3:0] p6[7:4] p3[3:0] p2[7:4] p1[7:4] p0[7:4] 111 110 101 100 011 010 001 000 C sppk0[2:0] port p9[4:0] p8[4:0] p5[4:0] p6[4:0] p4[4:0] p2[4:0] p1[4:0] p0[4:0] 111 110 101 100 011 010 001 000 C this register is used to select an input-pin group for generating key interrupts. table vi. 1.6.3 selecting pins for key input interrupts interrupt system fpk1 fpk0 111 p9[7:4] p9[4:0] 110 p8[5:4] p8[4:0] 101 p7[3:0] p5[4:0] 100 p6[7:4] p6[4:0] 011 p3[3:0] p4[4:0] 010 p2[7:4] p2[4:0] 001 p1[7:4] p1[4:0] 000 p0[7:4] p0[4:0] sppk settings (default: 0b000) d7 reserved d[6:4] sppk1[2:0]: fpk1 interrupt input port select bits selects an input-pin group for the fpk 1 interrupt. d3 reserved d[2:0] sppk0[2:0]: fpk0 interrupt input port select bits selects an input-pin group for the fpk 0 interrupt.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-20 epson s1c33e08 technical manual 0x3003d2: key input interrupt (fpk0) input comparison register (pkintcomp_scpk0) 0x3003d3: key input interrupt (fpk1) input comparison register (pkintcomp_scpk1) name address register name bit function setting init. r/w remarks C scpk04 scpk03 scpk02 scpk01 scpk00 d7C5 d4 d3 d2 d1 d0 reserved fpk04 input comparison fpk03 input comparison fpk02 input comparison fpk01 input comparison fpk00 input comparison C C 0 0 0 0 0 C r/w r/w r/w r/w r/w 0 when being read. 003003d2 (b) 1 high 0 low key input interrupt (fpk0) input comparison register (pkintcomp _scpk0) C scpk13 scpk12 scpk11 scpk10 d7C4 d3 d2 d1 d0 reserved fpk13 input comparison fpk12 input comparison fpk11 input comparison fpk10 input comparison C C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 003003d3 (b) 1 high 0 low key input interrupt (fpk1) input comparison register (pkintcomp _scpk1) d[4:0]/0x3003d2 scpk0[4:0]: fpk0[4:0] input comparison bits sets the conditions for generating fpk 0 key-input interrupts (timing of interrupt generation). 1 (r/w): falling edge 0 (r/w): rising edge (default) scpk 0[4:0 ] is compared with the input state of five bits of the fpk0 input ports, and when a change in states from a matched to an unmatched state occurs in either, an interrupt is generated (except for the inputs disabled from interrupt by smpk0[4:0] (d[4:0]/0x3003d4)). d[3:0]/0x3003d3 scpk1[3:0]: fpk1[3:0] input comparison bits sets the conditions for generating fpk 1 key-input interrupts (timing of interrupt generation). 1 (r/w): falling edge 0 (r/w): rising edge (default) scpk 1[3:0 ] is compared with the input state of four bits of the fpk1 input ports, and when a change in states from a matched to an unmatched state occurs in either, an interrupt is generated (except for the inputs disabled from interrupt by smpk1[3:0] (d[3:0]/0x3003d5)).
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) s1c33e08 technical manual epson vi-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x3003d4: key input interrupt (fpk0) input mask register (pkintcomp_smpk0) 0x3003d5: key input interrupt (fpk1) input mask register (pkintcomp_smpk1) name address register name bit function setting init. r/w remarks C smpk04 smpk03 smpk02 smpk01 smpk00 d7C5 d4 d3 d2 d1 d0 reserved fpk04 input mask fpk03 input mask fpk02 input mask fpk01 input mask fpk00 input mask C C 0 0 0 0 0 C r/w r/w r/w r/w r/w 0 when being read. 003003d4 (b) 1 interrupt enabled 0 interrupt disabled key input interrupt (fpk0) input mask register (pkintcomp _smpk0) C smpk13 smpk12 smpk11 smpk10 d7C4 d3 d2 d1 d0 reserved fpk13 input mask fpk12 input mask fpk11 input mask fpk10 input mask C C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 003003d5 (b) 1 interrupt enabled 0 interrupt disabled key input interrupt (fpk1) input mask register (pkintcomp _smpk1) d[4:0]/0x3003d4 smpk0[4:0]: fpk0[4:0] input mask bits sets conditions for generating fpk 0 key-input interrupts (interrupt enabled/disabled). 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) smpk 0 x is an input mask bit for each fpk0 key-input interrupt port. interrupts for bits set to 1 are en - abled, and interrupts for bits set to 0 are disabled. a change in the state of an input pin that is disabled from interrupt does not affect interrupt generation. d[3:0]/0x3003d5 smpk1[3:0]: fpk1[3:0] input mask bits sets conditions for generating fpk 1 key-input interrupts (interrupt enabled/disabled). 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (default) smpk 1 x is an input mask bit for each fpk1 key-input interrupt port. interrupts for bits set to 1 are en - abled, and interrupts for bits set to 0 are disabled. a change in the state of an input pin that is disabled from interrupt does not affect interrupt generation.
vi peripheral modules 4 (ports): general-purpose i/o ports (gpio) vi-1-22 epson s1c33e08 technical manual vi.1.7 precautions ? after an initial reset, the cause-of-interrupt flags become indeterminate. to prevent generation of an unwanted interrupt or idma request, be sure to reset the flags in a program. ? to prevent regeneration of interrupts due to the same cause of interrupt following the occurrence of an interrupt, always be sure to reset the cause-of-interrupt flag before resetting the psr or executing the reti instruction. ? when using an port input interrupt as the trigger to restart from the sleep mode, an interrupt will occur due to the input signal level even if edge interrupt is specified as an interrupt condition. the signal level to restart the cpu is as follows according to the signal edge selected: if a rising-edge interrupt is set, the cpu restarts when the i nput signal goes to a high level. if a falling-edge interrupt is set, the cpu restarts when the input signal goes to a low level. when a falling edge interrupt is selected to restart after the slp instruction is executed, the operation is as follows. if the interrupt port is already at a low level when the slp instruction is executed, the cpu enters sleep mode instantaneously and restarts immediately afterward. if the interrupt port is at a high level when the slp instruction is executed, the sleep mode continues until the port goes low. therefore, design the system assuming that the cpu can restart normally due to the signal level at the interrupt port, not an edge interrupt, when restarting the cpu from sleep mode using a port input interrupt. ? to use the p15Cp17 and p34Cp36 pins that are configured as the debug interface pins by default for general- purpose inputs/outputs, clear trcmux (d 0/0x300014) to 0. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) note, however, that the pc trace function of the debugger cannot be used when trcmux (d 0/0x300014 ) is set to 0. ? even if the port input interrupt condition is set to falling edge, the input pulse width must be longer than 1 cycle of the port operating clock (= mclk) to be certain an interrupt will be generated.
vi peripheral modules 4 (ports): extended general-purpose i/o ports (egpio) s1c33e08 technical manual epson vi-2-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vi. 2 extended general-purpose i/o ports (egpio) vi.2.1 structure of egpio port the s 1c33e08 contains 17 extended i/o ports (pa[4:0 ], pb[3:0 ], and pc[7:0 ]) to implement extended peripheral functions that cannot be included in the standard gpio module. when the extended functions assigned to the i/o pins are not used, the i/o pins can be used as general-purpose i/o ports. figure vi. 2.1.1 shows the structure of a typical i/o port. v ddh v ss internal data bus p xx data register peripheral circuit input peripheral circuit output i/o control register peripheral circuit i/o control function select register i/o control signal figure vi. 2.1.1 structure of i/o port notes : ? the pa[4:0] and pb[3:0 ] ports are not available in the qfp24-144 pin package model. ? a pull-up resistor is provided for pa and pb port pins and it can be enabled/disabled by software control. refer to section iii. 4.4, pin control registers, for how to control the pull-up resistor. when the port is in output mode, the port pin is not pulled up regardless of how the pull-up control bit is set. vi.2.2 selecting the i/o pin functions the i/o ports concurrently serve as the input/output pins for peripheral circuits or bus signals. whether they are used as i/o ports or for peripheral circuits/bus signals can be selected bit-for-bit using the port function select registers. all pins not used for peripheral circuits/bus signals can be used as general-purpose i/o ports. each i/o port pin (p xx ) is initialized for a default function at initial reset. for the pin that has two or more functions assigned, the port extended function select bits (cfp xx[1:0 ]) provided for each i/o port pin can be used to select the desired function. for details of pin functions and how to switch over, see section i. 3.3, switching over the multiplexed pin functions. the subsequent sections explain the port functions assuming that the pin has been set as a general-purpose i/o port.
vi peripheral modules 4 (ports): extended general-purpose i/o ports (egpio) vi-2-2 epson s1c33e08 technical manual vi.2.3 i/o control register and i/o modes the i/o ports are directed for input or output modes by writing data to ioc x corresponding to each port bit. ? ioca[4:0] : pa4Cpa0 i/o control bits in the pa i/o control register (d[4:0]/0x300c00) ? iocb[3:0] : pb3Cpb0 i/o control bits in the pb i/o control register (d[3:0]/0x300c02) ? iocc[7:0] : pc7Cpc0 i/o control bits in the pc i/o control register (d[7:0]/0x300c04) to set an i/o port for input, write 0 to the i/o control bit. i/o ports set for input mode are placed in the high- impedance state, and thus function as input ports. the port pin is pulled up when the pull-up resistor is enabled using the pin control register. in the input mode, the state of the input pin is read directly, so the data is 1 when the pin state is high (v ddh level) or 0 when the pin state is low (v ss level). even in the input mode, data can be written to the data register without affecting the pin state. to set an i/o port for output, write 1 to the i/o control bit. i/o port set for output function as output ports. when the port output data is 1 , the port outputs a high level (v ddh level); when the data is 0 , the port outputs a low level (v ss level). when the port is in output mode, the port pin is not pulled up even if the pull-up resistor is enabled. at initial reset, the i/o control register is set to 0 (input mode).
vi peripheral modules 4 (ports): extended general-purpose i/o ports (egpio) s1c33e08 technical manual epson vi-2-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vi.2.4 egpio operating clock the egpio module is clocked by the egpio_clk clock (= mclk) supplied by the cmu. when initially reset, this clock is selected for supply to the egpio port. however, when all the egpio ports are idle or not in use, clock supply from the cmu may be turned off to reduce current consumed on the chip. use egpio_cke (d 12 / 0 x 301 b 04 ) of the cmu for this control. ? egpio_cke : egpio clock control bit in the gated clock control register 1 (d12/0x301b04) setting egpio_cke (d12/0x301b04) to 0 stops clock supply from the cmu to the egpio port. when the cmu stop supplying the clock to the egpio port, all the egpio port registers are disabled for writing. however, input pin levels can be read correctly. for details of the generation and control of the clock, see section iii. 1, clock management unit (cmu). note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be removed by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless rewriting said registers.
vi peripheral modules 4 (ports): extended general-purpose i/o ports (egpio) vi-2-4 epson s1c33e08 technical manual vi.2.5 details of control registers table vi. 2.5.1 list of egpio registers address 0x00300c00 0x00300c01 0x00300c02 0x00300c03 0x00300c04 0x00300c05 0x00300c20 0x00300c21 0x00300c22 0x00300c24 0x00300c25 function controls pa port input/output direction. pa port data read/write register controls pb port input/output direction. pb port data read/write register controls pc port input/output direction. pc port data read/write register sets pa0Cpa3 port pin function. sets p a4 port pin function. sets p b0Cpb3 port pin function. sets pc0Cpc3 port pin function. sets pc4Cpc7 port pin function. register name pa i/o control register (ppa_ioc) pa port data register (ppa_data) pb i/o control register (ppb_ioc) pb port data register (ppb_data) pc i/o control register (ppc_ioc) pc port data register (ppc_data) pa0Cpa3 port function select register (ppa_cfp0) pa4 port function select register (ppa_cfp1) pb0Cpb3 port function select register (ppb_cfp0) pc0Cpc3 port function select register (ppc_cfp0) pc4Cpc7 port function select register (ppc_cfp1) siz e 8 8 8 8 8 8 8 8 8 8 8 the following describes each egpio control register. the egpio control registers are mapped in the 8 -bit device area from 0x300c00 to 0x300c25, and can be accessed in units of bytes.
vi peripheral modules 4 (ports): extended general-purpose i/o ports (egpio) s1c33e08 technical manual epson vi-2-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300c00C0x300c04: p x i/o control registers (pp x _ioc) name address register name bit function setting init. r/w remarks ioc x 7 ioc x 6 ioc x 5 ioc x 4 ioc x 3 ioc x 2 ioc x 1 ioc x 0 d7 d6 d5 d4 d3 d2 d1 d0 p x 7 i/o control p x 6 i/o control p x 5 i/o control p x 4 i/o control p x 3 i/o control p x 2 i/o control p x 1 i/o control p x 0 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c00 | 00300c04 (b) 1 output 0 input p x i/o control register (pp x _ioc) note : the letter x in bit names, etc., denotes a port number from a to c. 0x300c00 pa i/o control register (ppa_ioc) 0x300c02 pb i/o control register (ppb_ioc) 0x300c04 pc i/o control register (ppc_ioc) directs an i/o port for input or output and indicates the i/o c ontrol signal value of the port. 1 (r/w): output mode 0 (r/w): input mode (default) each i/o control register bit corresponds to each i/o port. when ioc x is set to 1 , the corresponding i/o port is directed for output; if it is set to 0, the i/o port is directed for input. when the pin is used for a peripheral function, the input/output direction depends on the peripheral function. when the register is read, the i/o control signal value for the port pin is read out. when i/o port function is selected using the port function select register, the value written to the ioc register is read out as is. when peripheral function is selected, the read value depends on the peripheral circuit status and may not indicate the value written to ioc x .
vi peripheral modules 4 (ports): extended general-purpose i/o ports (egpio) vi-2-6 epson s1c33e08 technical manual 0x300c01C0x300c05: p x port data registers (pp x _data) name address register name bit function setting init. r/w remarks p x 7d p x 6d p x 5d p x 4d p x 3d p x 2d p x 1d p x 0d d7 d6 d5 d4 d3 d2 d1 d0 p x 7 i/o port data p x 6 i/o port data p x 5 i/o port data p x 4 i/o port data p x 3 i/o port data p x 2 i/o port data p x 1 i/o port data p x 0 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 00300c01 | 00300c05 (b) 1 high 0 low p x port data register (pp x _data) note : the letter x in bit names, etc., denotes a port number from a to c. 0x300c01 pa port data register (ppa_data) 0x300c03 pb port data register (ppb_data) 0x300c05 pc port data register (ppc_data) these registers are used to read data from i/o-port pins or to set output data. (default: external pin status) 1 (r/w): high level 0 (r/w): low level when an i/o port is set for output, the data written to the register is directly output to the i/o port pin. if the data written to the port is 1, the port pin is set high (v ddh level); if the data is 0 , the port pin is set low (v ss level). even in input mode, data can be written to the port data register. when the register is read, the voltage level on the port pin is read out regardless of whether an i/o port is set for input or output mode. if the pin voltage is high (v ddh level), 1 is read out as input data; if the pin voltage is low (v ss level), 0 is read out as input data.
vi peripheral modules 4 (ports): extended general-purpose i/o ports (egpio) s1c33e08 technical manual epson vi-2-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300c20C0x300c25: p xx port function select registers (pp x _cfp0/1) name address register name bit function setting init. r/w remarks cfp x 31 cfp x 30 or cfp x 71 cfp x 70 cfp x 21 cfp x 20 or cfp x 61 cfp x 60 cfp x 11 cfp x 10 or cfp x 51 cfp x 50 cfp x 01 cfp x 00 or cfp x 41 cfp x 40 d7 d6 d5 d4 d3 d2 d1 d0 p x 3/p x7 port extended function p x 2/p x6 port extended function p x 1/p x5 port extended function p x 0/p x4 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c20 | 00300c25 (b) p x 0Cp x 3 port function select register (pp x _cfp0) or p x 4Cp x 7 port function select register (pp x _cfp1) cfp x3/7[1:0] function pin function 3 pin function 2 pin function 1 pin function 0 cfp x2/6[1:0] function pin function 3 pin function 2 pin function 1 pin function 0 cfp x1/5[1:0] function pin function 3 pin function 2 pin function 1 pin function 0 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp x0/4[1:0] function pin function 3 pin function 2 pin function 1 pin function 0 note : the letter x in bit names, etc., denotes a port number from a to c. 0x300c20 pa0Cpa3 port function select register (ppa_cfp0) 0x300c21 pa4 port function select register (ppa_cfp1) 0x300c22 pb0Cpb3 port function select register (ppb_cfp0) 0x300c24 pc0Cpc3 port function select register (ppc_cfp0) 0x300c25 pc4Cpc7 port function select register (ppc_cfp1) these bits select the function of each i/o port pin. (default: 0b00 = pin function 0) the i/o ports concurrently serve as the input/output pins for peripheral circuits or bus signals. whether they are used as i/o ports or for peripheral circuits/bus signals can be selected bit-for-bit using these registers. all pins not used for peripheral circuits/bus signals can be used as general-purpose i/o ports. for details of pin functions, see section i. 3.3, switching over the multiplexed pin functions.
vi peripheral modules 4 (ports): extended general-purpose i/o ports (egpio) vi-2-8 epson s1c33e08 technical manual this page is blank.
i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual vii peripheral m odules 5 ( analog )

vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vii.1 a/d converter (adc) vii.1.1 features and structure of a/d converter the s1c33e08 contains an a/d converter with the following features: ? conversion method: successive comparison ? resolution: 10 bits ? input channels: 5 channels ? a/d converter input clock: maximum of 2 mhz, minimum of 16 khz ? conversion time: minimum of 10 s (when a 2-mhz input clock is selected) maximum of 1250 s (when a 16-khz input clock is selected) ? conversion range: between v ss and av dd ? two conversion modes can be selected: normal mode: conversion is completed in one operation. continuous mode: conversion is continuous and terminated through software control. continuous conversion of multiple channels can be performed in each mode. ? three types of a/d-conversion start triggers can be selected: triggered by the external pin (#adtrg) triggered by the compare match b of the 16-bit timer 0 triggered by the software ? a/d conversion results can be read out from the 10 -bit data register or the conversion result buffer* for each channel. ? an interrupt is generated upon completion of a/d conversion or when the conversion result is out of the specified range (upper and lower-limit values can be specified)*. ? these functions can be used in the advanced mode. the a/d converter of the s 1 c 33 e 08 has two operating modes, standard mode of which functions are compatible with the c 33 std analog block for the existing models and an advanced mode allowing use of the extended functions. figure vii. 1.1.1 shows the structure of the a/d converter. internal data bus av dd analog input decoder control circuit ain0 ain1 ain2 ain3 ain4 #adtrg 16-bit timer 0 cmu prescaler interrupt request a/d conversion clock can be used in advanced mode conversion completed out of range analog block successive approximation block data register interrupt control circuit control registers ch0Cch4 conversion result buffers upper-limit/ lower-limit value registers comparator figure vii. 1.1.1 structure of a/d converter
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-2 epson s1c33e08 technical manual vii.1.2 input pins of a/d converter table vii. 1.2.1 shows the pins used by the a/d converter. table vii. 1.2.1 input pins of a/d converter pin name #adtrg ain0 ain1 ain2 ain3 ain4 av dd i/o i i i i i i C function a/d tr igger a/d con ve r ter input 0 a/d con ve r ter input 1 a/d con ve r ter input 2 a/d con ve r ter input 3 a/d con ve r ter input 4 analog po wer supply v oltage (+) av dd (analog power-supply pin) av dd is the power-supply pin for the analog circuit. note : when the a/d converter is enabled, a current flows between av dd and v ss , and power is consumed, even when a/d operations are not performed. therefore, when the a/d converter is not used, it must be disabled (default 0 setting of ade (d2/0x300544)). ? ade : a/d enable bit in the a/d control/status register (d2/0x300544) ain[4:0] (analog-signal input pins) the analog input pins ain 4 (ch.4 ) through ain0 (ch.0 ) are shared with i/o ports. therefore, when these pins are used for analog input, they must be set for use with the a/d converter in the software. this setting can be made individually for each pin. at initial reset, all these pins are set for i/o ports. the analog input voltage av in can be input in the range of v ss av in av dd . #adtrg (external-trigger input pin) this pin is used to input a trigger signal to start a/d conversion from an external source. since this pin is shared with i/o port, it must be set for use with the a/d converter in the software before an external trigger can be applied to the pin. at initial reset, this pin is set for i/o port. note : the a/d input pins are shared with general-purpose i/o ports or other peripheral circuit inputs/ outputs, so that functionality in the initial state is set to other than the a/d input. before the a/d converter can be used, the function of these pins must be switched for the analog input by setting the corresponding port function select registers. for details of pin functions and how to switch over, see section i.3.3, switching over the multiplexed pin functions.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vii.1.3 a/d converter operating clock the a/d converter use the adc_clk clock (= mclk) generated by the cmu as the operating clock. the conversion clock is generated in the a/d converter module. controlling the supply of the operating clock adc_clk is supplied to the a/d converter with default settings. it can be turned off using adc_cke (d 3/ 0x301b04 ) to reduce the amount of power consumed on the chip if the a/d converter is not used. ? adc_cke : a/d converter clock control bit in the gated clock control register 1 (d3/0x301b04) setting adc_cke (d 3/0x301b04 ) to 0 (1 by default) turns off the clock supply to the a/d converter. when the clock supply is turned off, the a/d converter control registers cannot be accessed. for details on how to set and control the clock, refer to section iii. 1, clock management unit (cmu). note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be removed by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless rewriting said registers. clock state in standby mode the clock supply to the a/d converter stops depending on type of standby mode. halt mode: the operating clock is supplied the same way as in normal mode. sleep mode: the operating clock supply stops. therefore, the a/d converter also stops operating in sleep mode.
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-4 epson s1c33e08 technical manual vii.1.4 setting a/d converter when the a/d converter is used, the following settings must be made before an a/d conversion can be performed: 1 . setting analog input pins ... see sections vii.1.2 and i.3.3. 2 . setting the operating mode (standard mode/advanced mode) 3. setting the input clock 4 . selecting the analog-conversion start and end channels 5 . setting the a/d conversion mode 6. selecting a trigger 7. setting the sampling time 8 . setting the upper-limit and lower-limit values (advanced mode) 9 . setting the interrupt mode (advanced mode) 10 . setting interrupt/idma/hsdma ... see section vii.1.6. note : before making these settings, make sure the a/d converter is disabled (ade (d2/0x300544) = 0). changing the settings while the a/d converter is enabled could cause a malfunction. ? ade : a/d enable bit in the a/d control/status register (d2/0x300544) setting the operating mode (standard mode / advanced mode) the a/d converter of the s 1c33e08 has two operating modes, standard mode of which functions are compatible with the c 33 std analog block for the existing models and an advanced mode allowing use of the extended functions. table vii. 1.4.1 shows differences between the standard mode and the advanced mode. table vii. 1.4.1 differences between standard mode and advanced mode function reading conversion results conversion-complete flag, overwrite error flag comparison with upper/lower-limit values interrupts standar d mode the conversion results are read from the a/d conversion result register common to all channels. when converting for multiple channels, the a/d conversion result register must be read before conversion for the next channel has completed. one bit is assigned for the flag and is commonly used in all channels. not supported. conversion-complete interrupt only can be generated. the interrupts cannot be masked in channel units. ad v anced mode the conversion results can be read from the conversion result buffer provided for each channel. thus the conversion result for the current channel will not be lost even when the conversion for the next channel is completed during a multiple channel conversion. different flags are provided for each channel. an upper-limit value and a lower-limit value can be set and conversion results of the specified channel can be checked whether they are within the specified range or not. conversion-complete interrupts and out-of- range interrupts can be generated. conversion complete interrupts for the specified channels can be masked. to configure the a/d converter in the advanced mode, set adcadv (d 8/0x30055 e) to 1 . the control bits for the extended functions can be accessed after this setting. at initial reset, adcadv is set to 0 and the a/d converter enters the standard mode. ? adcadv : standard/advanced mode select bit in the a/d converter mode select/internal status register (d8/0x30055e) the following descriptions unless otherwise specified are common contents for both modes. the extended functions in the advanced mode are explained assuming that adcadv (d 8/0x30055 e) has been set to 1.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 setting the input clock the a/d converter contains a prescaler and the a/d conversion clock can be selected from among the eight types shown in table vii. 1.4.2 below. use psad[2:0] (d[2:0]/0x300520) for this selection. ? psad[2:0] : a/d converter clock division ratio setup bits in the a/d clock control register (d[2:0]/0x300520) table vii. 1.4.2 input clock selection psad2 1 1 1 1 0 0 0 0 psad1 1 1 0 0 1 1 0 0 psad0 1 0 1 0 1 0 1 0 division ratio mclk/256 mclk/128 mclk/64 mclk/32 mclk/16 mclk/8 mclk/4 mclk/2 (default: 0b000 = mclk/2) the selected clock is output from the prescaler by writing 1 to psonad (d3/0x300520). ? psonad : a/d converter clock control bit in the a/d clock control register (d3/0x300520) notes : ? the recommended input clock frequency is a maximum of 2 mhz and a minimum of 16 khz. ? do not start an a/d conversion when the clock output from the prescaler is turned off, and do not turn off the prescaler's clock output when an a/d conversion is underway. this could cause the a/d converter to operate erratically. selecting analog-conversion start and end channels select the channel in which the a/d conversion is to be performed from among the pins (channels) that have been set for analog input. to enable a/d conversions in multiple channels to be performed successively through one convert operation, specify the conversion start and conversion end channels using cs[ 2:0 ] (d[10:8 ]/ 0x300542) and ce[2:0] (d[13:11]/0x300542 ) respectively. ? cs[2:0] : a/d converter start channel setup bits in the a/d trigger/channel select register (d[10:8]/0x300542) ? ce[2:0] : a/d converter end channel setup bits in the a/d trigger/channel select register (d[13:11]/0x300542) table vii. 1.4.3 relationship between cs/ce and input channel cs2/ce2 1 0 0 0 0 other cs1/ce1 0 1 1 0 0 cs0/ce0 0 1 0 1 0 channel selected ain4 ain3 ain2 ain1 ain0 reser ve d example: operation of one a/d conversion cs[ 2:0] = 0, ce[2:0] = 0 : converted only in ain0 cs[ 2:0] = 0, ce[2:0] = 3 : converted in the following order: ain0 ain1 ain2 ain3 cs[ 2:0] = 3, ce[2:0] = 1 : converted in the following order: ain3 ain4 ain0 ain1 note : only conversion-channel input pins that have been set for use with the a/d converter can be set using cs[2:0] (d[10:8]/0x300542) and ce[2:0] (d[13:11]/0x300542).
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-6 epson s1c33e08 technical manual setting the a/d conversion mode the a/d converter can operate in one of the following two modes. this operation mode is selected using ms (d5/0x300542). ? ms : a/d conversion mode select bit in the a/d trigger/channel select register (d5/0x300542) 1 . normal mode (ms = 0) all inputs in the range of channels set using cs[ 2 : 0 ] (d[ 10 : 8 ]/ 0 x 300542 ) and ce[ 2 : 0 ] (d[ 13 : 11 ]/ 0 x 300542 ) are a/d converted once and then stopped. 2 . continuous mode (ms = 1) a/d conversions in the range of channels set using cs[ 2:0 ] and ce[2:0 ] are executed successively until stopped by the software. at initial reset, the normal mode is selected. selecting a trigger use ts[ 1:0 ] (d[4:3]/0x300542 ) to select a trigger to start a/d conversion from among the three types shown in table vii. 1.4.4. ? ts[1:0] : a/d conversion trigger select bits in the a/d trigger/channel select register (d[4:3]/0x300542) table vii. 1.4.4 trigger selection ts1 1 1 0 0 ts0 1 0 1 0 t rigge r exter nal tr igger (#adtrg) reserv ed 16-bit timer 0 softw are 1 . external trigger the signal input to the #adtrg pin is used as a trigger. when this trigger is used, the #adtrg pin must be set in advance using the port function select register. a/d conversion is started when a low level of the #adtrg signal is detected. 2 . 16-bit timer the comparison match b signal of the 16 -bit timer 0 is used as a trigger. since the cycle can be programmed using the timer, this trigger is effective when cyclic a/d conversions are required. for details on how to set the timer, refer to the explanation of the 16-bit timer in this manual. 3 . software trigger writing 1 to adst (d1/0x300544 ) in the software serves as a trigger to start a/d conversion. ? adst : a/d conversion control/status bit in the a/d control/status register (d1/0x300544) setting the sampling time the a/d converter contains st[ 1:0 ] (d[9:8]/0x300544 ) that allows the analog-signal input sampling time to be set in four steps (3, 5, 7, or 9 times the conversion clock period). however, this register should be used as set by default (st[ 1:0] = 11; x9 clock periods). ? st[1:0] : input signal sampling time setup bits in the a/d control/status register (d[9:8]/0x300544)
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 setting the upper-limit and lower-limit values (advanced mode) the advanced mode allows a range check of the conversion results by setting the upper-limit and lower-limit values. setup the a/d converter according to the procedure shown below to use this function. 1 . selecting the channel select the channel to compare the a/d conversion results and the upper-limit and lower-limit value using adcmp[2:0] (d[14:12]/0x300544). ? adcmp[2:0] : a/d upper/lower-limit comparison channel select bits in the a/d control/status register (d[14:12]/0x300544) table vii. 1.4.5 selecting the channel for checking conversion results adcmp1 0 1 1 0 0 adcmp0 0 1 0 1 0 channel selected ain4 ain3 ain2 ain1 ain0 reser ve d adcmp2 1 0 0 0 0 other 2 . setting upper-limit and lower-limit values set the upper-limit value to adupr[ 9:0 ] (d[9:0 ]/0x300558 ) and the lower-limit value to adlwr[9:0] (d[9:0]/0x30055a). ? adupr[9:0] : a/d upper limit value setup bits in the a/d upper limit value register (d[9:0]/0x300558) ? adlwr[9:0] : a/d lower limit value setup bits in the a/d lower limit value register (d[9:0]/0x30055a) when the conversion result exceeds the upper-limit value set or is lower than the lower-limit value, it is determined as out of range. if the conversion result is the same value as the upper-limit or lower-limit value, it is determined as within the range. 3 . enabling comparison with the upper-limit and lower-limit values set adcmpe (d 15/0x300544) to 1 to enable the range check function. ? adcmpe : a/d upper/lower-limit comparison enable bit in the a/d control/status register (d15/0x300544) setting the interrupt mode (advanced mode) the interrupt functions are extended in the advanced mode, so the following configuration is necessary. 1 . enabling/disabling the conversion-complete interrupt the conversion-complete interrupt can be enabled/disabled using cnvinten (d 4/0x300544 ). set cnvinten to 1 when using the conversion-complete interrupt, or to 0 when it is not used. at initial reset, cnvinten is set to 1 , so the conversion-complete interrupt function is enabled. ? cnvinten : a/d conversion-complete interrupt enable bit in the a/d control/status register (d4/0x300544) 2 . enabling/disabling the out-of-range interrupt the out-of-range interrupt can be enabled/disabled using cmpinten (d 5/0x300544 ). set cmpinten to 1 when using the out-of range interrupt, or to 0 when it is not used. at initial reset, cmpinten is set to 0, so the out-of-range interrupt function is disabled. ? cmpinten : a/d out-of-range interrupt enable bit in the a/d control/status register (d5/0x300544) 3 . setting the interrupt signal mode the s 1 c 33 e 08 a/d converter has two interrupt request outputs for the interrupt sources above and each interrupt can be handled individually. the a/d converter with advanced mode in the c 33 std core model uses one signal line for interrupt requests to the itc. in the initial setting, the out-of-range interrupt signal is ored with the conversion-complete interrupt signal to send to the itc. the s 1 c 33 e 08 a/d converter also supports this interrupt signal mode. so, the cause of conversion-complete interrupt flag in the itc is set when an a/d conversion has completed or when the conversion results are out of range. this signal mode can be canceled using intmode (d 6 / 0 x 300544 ). to handle each interrupt individually, set intmode (d 6 / 0 x 300544 ) to 1 . in this setting, the out-of-range interrupt signal is not ored with the conversion-complete interrupt signal. ? intmode : interrupt signal mode select bit in the a/d control/status register (d6/0x300544)
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-8 epson s1c33e08 technical manual 4 . masking conversion-complete interrupt for the specified channels the a/d conversion-complete interrupt mask register is used to mask the conversion-complete interrupts of the specified channels. when intmask x (d x/0x30055 c) for channel x in the register is set to 0 , channel x does not generate conversion-complete interrupts. for instance, by masking the conversion-complete interrupt of the channel used for range checking, it is possibl e to generate out-of range interrupts only. ? intmask x : ch. x conversion-complete interrupt mask bit in the a/d conversion complete interrupt mask register (d x /0x30055c) at initial reset, intmask x are all set to 1 to enable conversion-complete interrupts.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vii.1.5 control and operation of a/d conversion figure vii. 1.5.1 shows the operation of the a/d converter. ade trigger adst a/d operation add adf conversion-result (add) read owe ad0buf * adf0 * owe0 * ad1buf * adf1 * owe1 * ad2buf * adf2 * owe2 * interrupt request ain0 ain0 sampling conversion ain1 ain1 sampling conversion ain2 ain0 converted data ain1 converted data (when ain0 to ain2 are converted) ain2 converted data add is overwritten ain0 converted data ain1 converted data ain2 converted data ain2 sampling conversion (1 ) normal mode ade trigger adst a/d operation add adf conversion-result (add) read owe ad0buf * adf0 * owe0 * ad1buf * adf1 * owe1 * interrupt request ain0-1 ain0-1 sampling conversion ain1-1 ain1-1 sampling conversion ain0-2 ain0-2 sampling conversion ain1-2 ain0-1 converted data ain1-1 converted data ain0-2 converted data (when ain0 to ain1 are converted) reset in software invalid sampling conversion ain0-1 converted data ain0-2 converted data ain1-1 converted data ad0buf is overwritten (2 ) continuous mode ? extended functions that can be used when adcadv = 1 figure vii. 1.5.1 operation of a/d converter
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-10 epson s1c33e08 technical manual starting up the a/d converter circuit after the settings specified in the preceding section have been made, write 1 to ade (d2/0x300544 ) to enable the a/d converter. the a/d converter is thereby readied to accept a trigger to start a/d conversion. to set the a/d converter again, or if it is not be used, set ade to 0. ? ade : a/d enable bit in the a/d control/status register (d2/0x300544) starting a/d conversion when a trigger is input while ade (d 2/0x300544 ) = 1 , a/d conversion is started. if a software trigger has been selected, a/d conversion is started by writing 1 to adst (d1/0x300544). ? adst : a/d conversion control/status bit in the a/d control/status register (d1/0x300544) only the trigger selected using ts[ 1:0] (d[4:3]/0x300542 ) are valid; no other trigger is accepted. ? ts[1:0] : a/d conversion trigger select bits in the a/d trigger/channel select register (d[4:3]/0x300542) when a trigger is input, the a/d converter samples and a/d-converts the analog input signal, beginning with the conversion start channel selected by cs[ 2:0] (d[10:8]/0x300542). ? cs[2:0] : a/d converter start channel setup bits in the a/d trigger/channel select register (d[10:8]/0x300542) adst (d 1/0x300544 ) used for the software trigger is set to 1 during a/d conversion, even when it is started by some other trigger, so it can be used as an a/d-conversion status bit. the channel in which conversion is underway can be identified by reading ch[ 2:0] (d[2:0]/0x300542). ? ch[2:0] : a/d conversion channel status bits in the a/d trigger/channel select register (d[2:0]/0x300542) reading out a/d conversion results ? standard mode upon completion of the a/d conversion in the start channel, the a/d converter stores the conversion result, in 10 -bit data registers add[9:0 ] (d[9:0]/0x300540 ), and sets the conversion-complete flag adf (d3/0x300544) and cause-of-interrupt flag fade (d 1/0x300287 ). if multiple channels are specified using cs[2:0 ] (d[10:8]/ 0x300542 ) and ce[2:0 ] (d[13:11]/0x300542 ), a/d conversions in the subsequent channels are performed in succession. ? add[9:0] : a/d converted data bits in the a/d conversion result register (d[9:0]/0x300540) ? adf : a/d conversion completion flag in the a/d control/status register (d3/0x300544) ? fade : a/d conversion completion interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d1/0x300287) ? ce[2:0] : a/d converter end channel setup bits in the a/d trigger/channel select register (d[13:11]/0x300542) the results of a/d conversion are stored in add[ 9:0 ] (d[9:0]/0x300540 ) each time conversion in one channel is completed. since an interrupt can be generated simultaneously, this interrupt is normally used to read out the converted data. in addition, be sure to reset the cause-of-interrupt flag (by writing 0 ) to prepare the a/d converter for the next operation. since the cause of interrupt of the a/d converter can also be used to invoke dma, the conversion results can automatically be transferred to a specified memory location. if multiple a/d conversion channels are specified, the conversion results in one channel must be read out prior to completion of conversion in the next channel. if the a/d conversion currently under way is completed before the previous conversion results are read out, add[ 9:0 ] is overwritten with the new conversion results. if add[ 9:0 ] is updated when the conversion-complete flag adf (d3/0x300544 ) = 1 (before the converted data is read out), the overwrite-error flag owe (d 0/0x300544 ) is set to 1 . the conversion-complete flag adf is reset to 0 when the converted data is read out. if add[9:0 ] is updated when adf = 0 , owe remains at 0, indicating that the operation has been completed normally. when reading out data, also read owe to make sure the data is valid. once owe is set, it remains set until it is reset to 0 in the software. note also that if owe is set, adf also is set. in this case, read out the converted data and reset adf. ? owe : overwrite error flag in the a/d control/status register (d0/0x300544)
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ? advanced mode upon completion of the a/d conversion in the start channel (ch. x ), the a/d converter stores the conversion result to the 10 -bit ch. x conversion result buffer ad x buf[ 9:0 ] (d[9:0 ]/0x300548 + 2? x ) and sets the ch. x conversion-complete flag adf x (d x /0x300546 ) and the cause-of-interrupt flag fade (d1/0x300287 ). if multiple channels are specified using cs[ 2:0 ] (d[10:8 ]/0x300542 ) and ce[2:0 ] (d[13:11 ]/0x300542 ), a/d conversions in the subsequent channels are performed in succession. ? ad x buf[9:0] : a/d ch. x converted data bits in the a/d ch. x conversion result buffer register (d[9:0]/0x300548 + 2? x ) ? adf x : a/d ch. x conversion-complete flag in the a/d channel status flag register (d x /0x300546) the results of a/d conversion are stored in the a/d conversion result buffer for each channel each time conversion in one channel is completed. since an interrupt can be generated simultaneously, this interrupt is normally used to read out the converted data. in addition, be sure to reset the cause-of-interrupt flag (by writing 0 ) to prepare the a/d converter for the next operation. since the cause of interrupt of the a/d converter can also be used to invoke dma, the conversion results can automatically be transferred to a specified memory location. in the advanced mode, each channel has a conversion result buffer, so it is not necessary to read the conversion results prior to completion of conversion in the next channel. however, if the next a/d conversion in the same channel is completed before the previous conversion results are read out, the conversion result buffer is overwritten with the new conversion results. if ad x buf[ 9:0 ] (d[9:0 ]/0x300548 + 2? x ) is updated when the conversion-complete flag adf x = 1 (before the converted data is read out), the overwrite-error flag owe x (d x + 8/0x300546 ) is set to 1 . adf x (d x /0x300546 ) is reset to 0 when the converted data is read out. if ad x buf[9:0 ] is updated when adf x = 0 , owe x remains at 0 , indicating that the operation has been completed normally. when reading out data, also read owe x to make sure the data is valid. once owe x is set, it remains set until it is reset to 0 by writing 0 in the software. note also that if owe x is set, adf x is also set. in this case, read out the converted data and reset adf x . ? owe x : a/d ch. x overwrite error flag in the a/d channel status flag register (d x + 8/0x300546) add[ 9:0 ] (d[9:0]/0x300540 ), adf (d3/0x300544 ) and owe (d0/0x300544 ) used in the standard mode are also effective in the advanced mode as well. the functions and actions of the register/bits are the same as those of the standard mode. owe is set during conversion in multiple-channels, but it is not necessary to reset it. range check (comparison with upper-limit/lower-limit values in advanced mode) when the range check function is enabled (adcmpe (d 15/0x300544 ) = 1 ) and an a/d conversion in the channel specified using adcmp[ 2:0] (d[14:12]/0x300544 ) has completed, the conversion results are compared with the contents of adupr[ 9:0] (d[9:0]/0x300558 ) and adlwr[9:0] (d[9:0]/0x30055a). ? adcmpe : a/d upper/lower-limit comparison enable bit in the a/d control/status register (d15/0x300544) ? adcmp[2:0] : a/d upper/lower-limit comparison channel select bits in the a/d control/status register (d[14:12]/0x300544) ? adupr[9:0] : a/d upper limit value setup bits in the a/d upper limit value register (d[9:0]/0x300558) ? adlwr[9:0] : a/d lower limit value setup bits in the a/d lower limit value register (d[9:0]/0x30055a) if the conversion results exceed the upper-limit value, the upper-limit comparison status bit aduprst (d 11/ 0x300544 ) is set to 1 . if the results are less than the lower-limit value, the lower-limit comparison status bit adlwrst (d 10/0x300544 ) is set to 1 . when the out-of range interrupt is enabled, an interrupt occurs if one of the status bits has been set. this interrupt request sets the cause-of-interrupt flag fadc (d 0/0x300287 ). also the same cause-of-interrupt flag fade (d 1/0x300287 ) as the conversion-complete interrupt is set to 1 when intmode (d6/0x300544) has been set to 0. ? aduprst : a/d upper-limit comparison status bit in the a/d control/status register (d11/0x300544) ? adlwrst : a/d lower-limit comparison status bit in the a/d control/status register (d10/0x300544) ? fadc : a/d out-of-range interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d0/0x300287) ? intmode : interrupt signal mode select bit in the a/d control/status register (d6/0x300544) when the conversion results are the same as the upper-limit or lower-limit values, it is assumed within the range and an interrupt is not generated.
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-12 epson s1c33e08 technical manual terminating a/d conversion ? for normal mode (ms = 1) in the normal mode, a/d conversion is performed successively from the conversion start channel specified using cs[ 2 : 0 ] (d[ 10 : 8 ]/ 0 x 300542 ) to the conversion end channel specified using ce[ 2 : 0 ] (d[ 13 : 11 ]/ 0 x 300542 ), and is completed after these conversions are executed in one operation. adst (d 1/0x300544 ) is reset to 0 upon completion of the conversion. ? ms : a/d conversion mode select bit in the a/d trigger/channel select register (d5/0x300542) ? for continuous mode (ms = 0) in the continuous mode, a/d conversion from the conversion-start to the conversion-end channels is executed repeatedly, without being stopped in the hardware. to terminate conversion, therefore, adst (d 1/0x300544) must be reset to 0 in the software. however, the a/d conversion being executed will be completed normally or forcibly stopped depending on the timing of writing 0 to adst. when the a/d conversion has completed normally, adf (d 3/0x300544 ) is set to 1 and the conversion results can be obtained. if it is forcibly stopped, adf maintains its previous status, therefore, conversion results cannot be obtained. ? forced termination a/d conversion is immediately terminated by writing 0 to adst (d1/0x300544 ). the results of the conversion then under-way cannot be obtained.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vii.1.6 a/d converter interrupt and dma upon completion of a/d conversion in each channel, the a/d converter generates an interrupt and invokes the idma if necessary. in the advanced mode, the a/d converter can generate an interrupt when the conversion results are out of the range specified with the upper-limit and lower-limit registers. control registers of the interrupt controller the following shows the interrupt control bits available for the a/d converter: ? fade : a/d conversion completion interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d1/0x300287) ? fadc : a/d out-of-range interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d0/0x300287) ? eade : a/d conversion completion interrupt enable bit in the port input 4C7, rtc, a/d interrupt enable register (d1/0x300277) ? eadc : a/d out-of-range interrupt enable bit in the port input 4C7, rtc, a/d interrupt enable register (d0/0x300277) ? pad[2:0] : a/d interrupt level bits in the serial i/f ch.1, a/d interrupt priority register (d[6:4]/0x30026a) the a/d converter sets the cause-of-interrupt flag fade (d 1/0x300287 ) to 1 when a/d conversion in one channel is completed, and the conversion results are stored in add[ 9:0 ] and ad x buf[9:0 ] (advanced mode). ? ad x buf[9:0] : a/d ch. x converted data bits in the a/d ch. x conversion result buffer register (d[9:0]/0x300548 + 2? x ) ? add[9:0] : a/d converted data bits in the a/d conversion result register (d[9:0]/0x300540) if the out-of-range interrupt is enabled in the advanced mode, the cause-of-interrupt flag fadc (d 0/0x300287) is set to 1 when the conversion results in the specified channel are out of range. also the same cause-of-interrupt flag fade (d 1/0x300287 ) as the conversion-complete interrupt is set to 1 when intmode (d6/0x300544) has been set to 0. at this time, if the interrupt enable register bit has been set to 1 , an interrupt request is generated. interrupts can be disabled by leaving the interrupt enable register bit set to 0 . the cause-of-interrupt flag is set to 1 upon completion of a/d conversion in each channel, regardless of the setting of the interrupt enable register (even when it is set to 0 ). the interrupt priority register sets the priority level (0 to 7 ) of an interrupt. an interrupt request to the cpu is accepted no other interrupt request of a higher priority has been generated. in addition, it is only when the psr's ie bit = 1 (interrupts enabled) and the set value of the il is smaller than the a/ d-converter interrupt level set by the interrupt priority register, that the a/d converter's interrupt request is actually accepted by the cpu. for details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to section iii.2, interrupt controller (itc). intelligent dma the a/d converter can invoke the intelligent dma (idma) through the use of its cause of interrupt when an a/d conversion has completed. this allows the conversion results to be transferred to a specified memory location with no need to execute an interrupt processing routine. the idma channel number assigned to the a/d converter is 0x1b. before idma can be invoked, the idma request bit rade (d 2/0x300293 ) and the idma enable bit deade (d2/0x300297) must be set to 1 . transfer conditions on the idma side must also be set in advance. ? rade : a/d conversion completion idma request bit in the serial i/f ch.1, a/d, port input 4C7 idma request register (d2/0x300293) ? deade : a/d conversion completion idma enable bit in the serial i/f ch.1, a/d, port input 4C7 idma enable register (d2/0x300297) if a cause of interrupt occurs when the idma request and idma enable bits are set to 1 , idma is invoked. no interrupt request is generated at that point. an interrupt request is generated upon completion of the dma transfer. otherwise, the bit can be set so as not to generate an interrupt, with only a dma transfer performed. for details on dma transfers and how to control interrupts upon completion of a dma transfer, refer to section ii.2, intelligent dma (idma).
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-14 epson s1c33e08 technical manual high-speed dma the cause of a/d conversion complete interrupt can also invoke high-speed dma (hsdma). the following shows the hsdma channel number and trigger set-up bit: table vii. 1.6.1 hsdma trigger set-up bits hsdma channel 0 1 2 3 t rigger set-up bits hsd0s[3:0] (d[3:0]) / hsdma ch.0C1 tr igger set-up register (0x300298) hsd1s[3:0] (d[7:4]) / hsdma ch.0C1 tr igger set-up register (0x300298) hsd2s[3:0] (d[3:0]) / hsdma ch.2C3 tr igger set-up register (0x300299) hsd3s[3:0] (d[7:4]) / hsdma ch.2C3 tr igger set-up register (0x300299) for hsdma to be invoked, the trigger set-up bits should be set to 0b1100 in advance. transfer conditions, etc. must also be set on the hsdma side. if the a/d cause of interrupt is selected as the hsdma trigger, the hsdma channel is invoked through generation of the cause of interrupt. for details on hsdma transfer, refer to section ii. 1, high-speed dma (hsdma). trap vector the a/d converter's interrupt trap-vector default address is set to 0xc00100. the base address of the trap table can be changed using the ttbr register.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vii.1.7 details of control registers table vii. 1.7.1 list of a/d converter registers address 0x00300520 0x00300540 0x00300542 0x00300544 0x00300546 0x00300548 0x0030054a 0x0030054c 0x0030054e 0x00300550 0x00300558 0x0030055a 0x0030055c 0x0030055e function controls a/d converter clock and selects division ratio . a/d conversion data sets start/end channels and conversion mode. controls a/d converter and indicates conversion status. overwrite error and conversion complete status a/d ch.0 conversion data a/d ch.1 conversion data a/d ch.2 conversion data a/d ch.3 conversion data a/d ch.4 conversion data specifies a/d conversion upper limit value. specifies a/d conversion lower limit value. masks a/d conversion complete interrupt. selects a/d operating mode and indicates internal status and internal counter value. register name a/d clock control register (pad_clkctl) a/d conversion result register (pad_add) a/d trigger/channel select register (pad_trig_chnl) a/d control/status register (pad_en_smpl_stat) a/d channel status flag register (pad_end) a/d ch.0 conversion result buffer register (pad_ch0_buf) a/d ch.1 conversion result buffer register (pad_ch1_buf) a/d ch.2 conversion result buffer register (pad_ch2_buf) a/d ch.3 conversion result buffer register (pad_ch3_buf) a/d ch.4 conversion result buffer register (pad_ch4_buf) a/d upper limit value register (pad_upper) a/d lower limit value register (pad_lower) a/d conversion complete interrupt mask register (pad_ch04_intmask) a/d converter mode select/internal status register (pad_advmode) siz e 16 16 16 16 16 16 16 16 16 16 16 16 16 16 the following describes each a/d converter control register. the a/d converter control registers are mapped in the 16 -bit device area from 0x300520 to 0x30055 e, and can be accessed in units of half-words and bytes. note : when setting the a/d converter control registers, be sure to write a 0, and not a 1, for all reserved bits.
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-16 epson s1c33e08 technical manual 0x300520: a/d clock control register (pad_clkctl) name address register name bit function setting init. r/w remarks C C psonad psad2 psad1 psad0 d15C4 d3 d2 d1 d0 reserved a/d converter clock control a/d converter clock division ratio selection C 0 0 0 0 C r/w r/w 0 when being read. 00300520 (hw) 1 on 0 off psad[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/256 mclk/128 mclk/64 mclk/32 mclk/16 mclk/8 mclk/4 mclk/2 a/d clock control register (pad_clkctl) d[15:4] reserved d3 psonad: a/d converter clock control bit controls the a/d conversion clock supply to the a/d converter. 1 (r/w): on 0 (r/w): off (default) d[2:0] psad[2:0]: a/d converter clock division ratio setup bits selects a division ratio to generate the a/d converter clock. table vii. 1.7.2 selecting division ratio psad2 1 1 1 1 0 0 0 0 psad1 1 1 0 0 1 1 0 0 psad0 1 0 1 0 1 0 1 0 division ratio mclk/256 mclk/128 mclk/64 mclk/32 mclk/16 mclk/8 mclk/4 mclk/2 (default: 0b000 = mclk/2)
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300540: a/d conversion result register (pad_add) name address register name bit function setting init. r/w remarks C add9 add8 add7 add6 add5 add4 add3 add2 add1 add0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d converted data add9 = msb add0 = lsb C 0x0 to 0x3ff C 0 0 0 0 0 0 0 0 0 0 C r 0 when being read. 00300540 (hw) a/d conversion result register (pad_add) d[15:10] reserved d[9:0] add[9:0]: a/d converted data bits stores the results of a/d conversion. (default: 0x000) the lsb is stored in add 0 , and the msb is stored in add9. this is a read-only register, so writing to this register is ignored.
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-18 epson s1c33e08 technical manual 0x300542: a/d trigger/channel select register (pad_trig_chnl) name address register name bit function setting init. r/w remarks C 0 to 4 0 to 4 0 to 4 C ce2 ce1 ce0 cs2 cs1 cs0 C ms ts1 ts0 ch2 ch1 ch0 d15C14 d13 d12 d11 d10 d9 d8 d7C6 d5 d4 d3 d2 d1 d0 reserved a/d converter end channel selection a/d converter start channel selection reserved a/d conversion mode selection a/d conversion trigger selection a/d conversion channel status C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w r/w C r/w r/w r 0 when being read. 0 when being read. 00300542 (hw) a/d trigger/ channel select register (pad_trig_chnl) 11 10 01 00 ts[1:0] C trigger #adtrg pin reserved 16-bit timer software 1 continuous 0 normal d[15:14] reserved d[13:11] ce[2:0]: a/d converter end channel setup bits sets the conversion end channel by selecting a channel number from 0 to 4 . (default: 0b000 = ain0) analog inputs can be a/d-converted successively from the channel set using cs[ 2:0 ] (d[10:8 ]) to the channel set using these bits in one operation. if only one channel is to be a/d converted, set the same channel number in both cs[2:0] and ce[2:0]. d[10:8] cs[2:0]: a/d converter start channel setup bits sets the conversion start channel by selecting a channel number from 0 to 4 . (default: 0b000 = ain0) analog inputs can be a/d-converted successively from the channel set using these bits to the channel set using ce[ 2:0 ] (d[13:11 ]) in one operation. if only one channel is to be a/d converted, set the same channel number in both cs[2:0] and ce[2:0]. d[7:6] reserved d5 ms: a/d conversion mode select bit selects an a/d conversion mode. 1 (r/w): continuous mode 0 (r/w): normal mode (default) the a/d converter is set for the continuous mode by writing 1 to ms. in this mode, a/d conversions in the range of the channels selected using cs[ 2:0 ] (d[10:8 ]) and ce[2:0 ] (d[13:11 ]) are executed con - tinuously until stopped in the software. when ms = 0 , the a/d converter operates in the normal mode. in this mode, a/d conversion is com - pleted after all inputs in the range of the channels selected by cs[ 2:0 ] and ce[2:0 ] are converted in one operation.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d[4:3] ts[1:0]: a/d conversion trigger select bits selects a trigger to start a/d conversion. table vii. 1.7.3 trigger selection ts1 1 1 0 0 ts0 1 0 1 0 t rigge r exter nal tr igger (#adtrg) reserv ed 16-bit timer 0 softw are (default: 0b00 = software trigger) when an external trigger is used, the #adtrg pin must be set in advance using the port function select register. a/d conversion is started when a low level of the #adtrg signal is detected. when the 16 -bit timer is used, since its comparison match b signal serves as a trigger, set the cycle and other parameters for the timer. d[2:0] ch[2:0]: a/d conversion channel status bits indicates the channel number ( 0 to 4 ) currently being a/d-converted. (default: 0b000 = ain0) when a/d conversion is performed in multiple channels, read this bit to identify the channel in which conversion is underway.
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-20 epson s1c33e08 technical manual 0x300544: a/d control/status register (pad_en_smpl_stat) name address register name bit function setting init. r/w remarks adcmpe adcmp2 adcmp1 adcmp0 aduprst adlwrst st1 st0 C intmode cmpinten cnvinten adf ade adst owe d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 upper/lower-limit comparison enable upper/lower-limit comparison channel selection upper-limit comparison status lower-limit comparison status input signal sampling time setup reserved interrupt signal mode out-of-range int. enable conversion-complete int. enable conversion-complete flag a/d enable a/d conversion control/status overwrite error flag 0 to 4 11 10 01 00 st[1:0] sampling time 9 clocks 7 clocks 5 clocks 3 clocks 0 0 0 0 0 0 1 1 C 0 0 1 0 0 0 0 r/w r/w r r r/w C r/w r/w r/w r r/w r/w r/w can be used when adcadv = "1". use with 9 clocks. 0 when being read. can be used when adcadv = "1". reset when add is read. reset by writing 0. 00300544 (hw) a/d control/ status register (pad_en_smpl _stat) 1 out of range 0 within range 1 enabled 0 disabled 1 out of range 0 within range C 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 complete only 0 or 1 completed 0 run/standby 1 start/run 0 stop 1 error 0 normal d15 adcmpe: a/d upper/lower-limit comparison enable bit (for advanced mode) enables/disables comparison between converted data and upper-/lower-limit values. 1 (r/w): enabled 0 (r/w): disabled (default) adcmpe selects whether the converted data is compared with the upper-/lower-limit values after a/d conversion of the channel specified using adcmp[ 2:0 ] (d[14:12 ]). set adcmpe to 1 when using the comparison function or set to 0 when not used. d[14:12] adcmp[2:0]: a/d upper/lower-limit comparison channel select bits (for advanced mode) set the channel number ( 0 C 4 ) to compare its converted data with the upper-/ lower-limit values. (default: 0b000 = ain0) d11 aduprst: a/d upper-limit comparison status bit (for advanced mode) indicates the results of comparison between the a/d converted data and the upper-limit value. 1 (r): exceeded the upper limit 0 (r): within the range (default) when the upper-/lower-limit comparison function is enabled (adcmpe (d 15 ) = 1 ), the converted data is compared with the upper-/lower-limit values after a/d conversion of the channel specified us - ing adcmp[ 2:0 ] (d[14:12 ]) has completed. if the converted data exceeds the upper-limit value set in adupr[9:0] (d[9:0]/0x300558 ), aduprst is set to 1 . if the converted data is equal to or less than the upper-limit value, aduprst is set to 0 . an interrupt occurs when aduprst is set to 1 if the out-of- range interrupt is enabled. d10 adlwrst: a/d lower-limit comparison status bit (for advanced mode) indicates the results of comparison between the a/d converted data and the lower-limit value. 1 (r): under the lower limit 0 (r): within the range (default) when the upper-/lower-limit comparison function is enabled (adcmpe (d 15 ) = 1 ), the converted data is compared with the upper-/lower-limit values after a/d conversion of the channel specified using adcmp[2:0 ] (d[14:12 ]) has completed. if the converted data is less than the lower-limit value set in adlwr[ 9:0 ] (d[9:0]/0x30055 a), adlwrst is set to 1 . if the converted data is equal to or more than the lower-limit value, adlwrst is set to 0 . an interrupt occurs when adlwrst is set to 1 if the out- of-range interrupt is enabled.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d[9:8] st[1:0]: input signal sampling time setup bits sets the analog input sampling time. table vii. 1.7.4 sampling time st1 1 1 0 0 st0 1 0 1 0 sampling time 9-cloc k per iod 7-cloc k per iod 5-cloc k per iod 3-cloc k per iod (default: 0b11 = 9 -clock period) the a/d converter conversion clock is used for counting. to maintain the conversion accuracy, use st as set by default ( 9-clock period). d7 reserved d6 intmode: interrupt signal mode select bit (for advanced mode) configures the conversion-complete interrupt signal delivered to the itc. 1 (r/w): conversion-complete signal only 0 (r/w): or between conversion-complete and out-of-range signals (default) intmode selects whether the conversion-complete interrupt signal line connected to the itc is used to send the conversion-complete signal only or used to send the signal of which the conversion-com - plete and out-of-range signal are ored. set intmode to 1 when handling the out-of-range interrupt as another interrupt. when using the out- of-range interrupt, set cmpinten (d5) to 1. d5 cmpinten: a/d out-of-range interrupt enable bit (for advanced mode) enables/disables the out-of-range interrupt. 1 (r/w): enabled 0 (r/w): disabled (default) when cmpinten is set to 1 , upper and lower-limit comparison results become a cause of interrupt. when it is set to 0, an out-of-range interrupt is not generated. d4 cnvinten: a/d conversion-complete interrupt enable bit (for advanced mode) enables/disables the conversion-complete interrupt. 1 (r/w): enabled (default) 0 (r/w): disabled when cnvinten is set to 1 , completion of an a/d conversion becomes a cause of interrupt. when it is set to 0 , a conversion-complete interrupt is not generated. d3 adf: a/d conversion completion flag indicates that a/d conversion has been completed. 1 (r): conversion completed 0 (r): being converted or standing by (default) this flag is set to 1 when a/d conversion is completed, and the converted data is stored in the data register and is reset to 0 when the converted data is read out. when a/d conversion is performed in multiple channels, if the next a/d conversion is completed while adf = 1 (before the converted data is read out), the data register is overwritten with the new conversion results, causing an overrun error to occur. therefore, adf must be reset by reading out the converted data before the next a/d conversion is completed.
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-22 epson s1c33e08 technical manual d2 ade: a/d enable bit enables the a/d converter (readied for conversion). 1 (r/w): enabled 0 (r/w): disabled (default) when ade is set to 1 , the a/d converter is enabled, meaning it is ready to start a/d conversion (i.e., ready to accept a trigger). when ade = 0 , the a/d converter is disabled, meaning it is unable to accept a trigger. before setting the conversion mode, start/end channels, etc. for the a/d converter, be sure to reset ade to 0 . this helps to prevent the a/d converter from operating erratically. d1 adst: a/d conversion control/status bit controls a/d conversion. 1 (r/w): software trigger 0 (r/w): a/d conversion is stopped (default) if a/d conversion is to be started by a software trigger, set adst to 1 . if any other trigger is used, adst is automatically set to 1 by the hardware. adst remains set while a/d conversion is underway. in normal mode, upon completion of a/d conversion in selected channels, adst is reset to 0 and the a/d conversion circuit is turned off. to stop a/d conversion during operation in continuous mode, reset adst by writing 0. when ade (d 2) = 0 (a/d conversion disabled), adst is fixed to 0, with no trigger accepted. d0 owe: overwrite error flag indicates that the converted data has been overwritten. 1 (r): overwritten 0 (r): normal (default) 1 (w): has no effect 0 (w): flag is reset during a/d conversion in multiple channels, if the conversion results for the next channel are written to the converted-data register (overwritten) before the converted data is read out to reset the conversion- complete flag adf (d 3 ) that has been set through conversion of the preceding channel, owe is set to 1 . when adf (d 3 ) is reset, because this means that the converted data has been read out, owe is not set. once owe is set to 1, it remains set until it is reset by writing 0 in the software.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300546: a/d channel status flag register (pad_end) name address register name bit function setting init. r/w remarks C owe4 owe3 owe2 owe1 owe0 C adf4 adf3 adf2 adf1 adf0 d15C13 d12 d11 d10 d9 d8 d7C5 d4 d3 d2 d1 d0 reserved ch.4 overwrite error flag ch.3 overwrite error flag ch.2 overwrite error flag ch.1 overwrite error flag ch.0 overwrite error flag reserved ch.4 conversion-complete flag ch.3 conversion-complete flag ch.2 conversion-complete flag ch.1 conversion-complete flag ch.0 conversion-complete flag C 0 0 0 0 0 C 0 0 0 0 0 C r/w r/w r/w r/w r/w C r r r r r 0 when being read. can be used when adcadv = "1". reset by writing 0. 0 when being read. can be used when adcadv = "1". reset when adbufx is read. 00300546 (hw) a/d channel status flag register (pad_end) 1 error 0 normal 1 completed 0 run/standby C C note : the letter x in bit names, etc., denotes a channel number from 0 to 4. d[15:13] reserved d[12:8] owe[4:0]: a/d ch. x overwrite error flags (for advanced mode) these bits indicate that the conversion result buffer for each channel has been overwritten. 1 (r): overwritten 0 (r): normal (default) 1 (w): has no effect 0 (w): flag is reset during a/d conversion in continuous mode, if the new conversion results in the same channel are writ - ten to the conversion result buffer (overwritten) before the converted data is read out to reset the adf x conversion-complete flag that has been set through the previous conversion, owe x is set to 1 . when adf x is reset, because this means that the converted data has been read out, owe x is not set. once owe x is set to 1, it remains set until it is reset by writing 0 in the software. d[7:5] reserved d[4:0] adf[4:0]: a/d ch. x conversion-complete flags (for advanced mode) these bits indicate that a/d conversion in each channel has been completed. 1 (r): conversion completed 0 (r): being converted or standing by (default) this flag is set to 1 when a/d conversion of the corresponding channel is completed, and the converted data is stored in the conversion result buffer and is reset to 0 when the conversion result buffer is read out. when a/d conversion is performed in continuous mode, if the next a/d conversion of the same channel is completed while adf x = 1 (before the conversion result buffer is read out), the buffer is overwritten with the new conversion results, causing an overrun error to occur. therefore, adf x must be reset by reading out the converted data before the next a/d conversion is completed.
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-24 epson s1c33e08 technical manual 0x300548C0x300550: a/d ch. x conversion result buffer registers (pad_ch x _buf) name address register name bit function setting init. r/w remarks 0x0 to 0x3ff C ad x buf9 ad x buf8 ad x buf7 ad x buf6 ad x buf5 ad x buf4 ad x buf3 ad x buf2 ad x buf1 ad x buf0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d ch. x converted data ad x buf9 = msb ad x buf0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r 0 when being read. can be used when adcadv = "1". 00300548 | 00300550 (hw) a/d ch. x conversion result buffer register (pad_ch x _buf) C note : the letter x in bit names, etc., denotes a channel number from 0 to 4. 0x300548 a/d ch.0 conversion result buffer register (pad_ch0_buf) 0x30054a a/d ch.1 conversion result buffer register (pad_ch1_buf) 0x30054c a/d ch.2 conversion result buffer register (pad_ch2_buf) 0x30054e a/d ch.3 conversion result buffer register (pad_ch3_buf) 0x300550 a/d ch.4 conversion result buffer register (pad_ch4_buf) d[15:10] reserved d[9:0] ad x buf[9:0]: a/d ch. x converted data bits (for advanced mode) the conversion results in each channel are stored. (default: 0x000) this is a read-only register, so writing to this register is ignored.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300558: a/d upper limit value register (pad_upper) name address register name bit function setting init. r/w remarks 0x0 to 0x3ff C adupr9 adupr8 adupr7 adupr6 adupr5 adupr4 adupr3 adupr2 adupr1 adupr0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d conversion upper limit value adupr9 = msb adupr0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. can be used when adcadv = "1". 00300558 (hw) a/d upper limit value register (pad_upper) C d[15:10] reserved d[9:0] adupr[9:0]: a/d upper limit value setup bits (for advanced mode) set the upper-limit value to be compared with the a/d conversion results. (default: 0x000) the value set in this register is used for the range check of the a/d conversion results in the channel specified with adcmp[ 2:0 ] (d[14:12]/0x300544 ). if the converted data exceeds the set value, an inter - rupt can be generated.
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-26 epson s1c33e08 technical manual 0x30055a: a/d lower limit value register (pad_lower) name address register name bit function setting init. r/w remarks 0x0 to 0x3ff C adlwr9 adlwr8 adlwr7 adlwr6 adlwr5 adlwr4 adlwr3 adlwr2 adlwr1 adlwr0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d conversion lower limit value adlwr9 = msb adlwr0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. can be used when adcadv = "1". 0030055a (hw) a/d lower limit value register (pad_lower) C d[15:10] reserved d[9:0] adlwr[9:0]: a/d lower limit value setup bits (for advanced mode) set the lower-limit value to be compared with the a/d conversion results. (default: 0x000) the value set in this register is used for the range check of the a/d conversion results in the channel specified with adcmp[ 2:0 ] (d[14:12]/0x300544 ). if the converted data is less than the set value, an interrupt can be generated.
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30055c: a/d conversion complete interrupt mask register (pad_ch04_intmask) name address register name bit function setting init. r/w remarks C intmask4 intmask3 intmask2 intmask1 intmask0 d15C5 d4 d3 d2 d1 d0 reserved ch.4 conversion-complete int. mask ch.3 conversion-complete int. mask ch.2 conversion-complete int. mask ch.1 conversion-complete int. mask ch.0 conversion-complete int. mask C 1 1 1 1 1 C r/w r/w r/w r/w r/w 0 when being read. can be used when adcadv = "1". 0030055c (hw) a/d conversion complete interrupt mask register (pad_ch04 _intmask) C 1 interrupt enabled 0 interrupt mask note : the letter x in bit names, etc., denotes a channel number from 0 to 4. d[15:5] reserved d[4:0] intmask[4:0]: ch. x conversion-complete interrupt mask bits (for advanced mode) these bits mask the a/d conversion-complete interrupt for each channel individually. 1 (r/w): interrupt is enabled (default) 0 (r/w): interrupt is masked when intmask x is set to 0 , the conversion-completed interrupt request of the ch. x is masked and the cause-of-interrupt flag fade (d 1/0x300287 ) will not be set to 1 even if a/d conversion is completed. when intmask x is 1 , the a/d converter can generate an interrupt upon completion of a/d conver - sion in ch. x . ? fade : a/d conversion completion interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d1/0x300287)
vii peripheral modules 5 (analog): a/d converter (adc) vii-1-28 epson s1c33e08 technical manual 0x30055e: a/d converter mode select/internal status register (pad_advmode) name address register name bit function setting init. r/w remarks C adcadv C istate1 istate0 icounter3 icounter2 icounter1 icounter0 d15C9 d8 d7C6 d5 d4 d3 d2 d1 d0 reserved standard/advanced mode selection reserved internal status internal counter value C 0 C 0 0 0 0 0 0 C r/w C r r do not write 1. 0 when being read. 0030055e (hw) a/d converter mode select/ internal status register (pad_advmode) C 0 to 15 C 1 advanced 0 standar d 11 10 01 00 istate[1:0] status converting reserved sampling idle d[15:9] reserved d8 adcadv: standard/advanced mode select bit selects the a/d converter operating mode. 1 (r/w): advanced mode 0 (r/w): standard mode (default) when adcadv is set to 1 , the a/d converter is set in the advanced mode, and the registers/bits for the extended function can be used. when adcadv is set to 0 , only the standard c33 a/d converter functions implemented in c33 std models can be used. in this mode, the extended registers/bits for advanced mode become read only and writing operation is disabled. d[7:6] reserved d[5:4] istate[1:0]: internal status bits indicates the a/d converter internal status. table vii. 1.7.5 internal status is ta te1 1 1 0 0 is ta te0 1 0 1 0 status con ve r ting reser ve d sampling idle (default: 0b00 = idle) d[3:0] icounter[3:0]: internal counter value setup bits indicates the internal counter value. (default: 0b0000)
vii peripheral modules 5 (analog): a/d converter (adc) s1c33e08 technical manual epson vii-1-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vii.1.8 precautions ? before setting the conversion mode, start/end channels, etc. for the a/d converter, be sure to disable ade (d2/ 0x300544 ). a change in settings while the a/d converter is enabled could cause it to operate erratically. ? ade : a/d enable bit in the a/d control/status register (d2/0x300544) ? in consideration of the conversion accuracy, we recommend that the a/d conversion clock be min. 16 khz to max. 2 mhz. ? do not start an a/d conversion when the clock supplied from the prescaler to the a/d converter is turned off, and do not turn off the prescaler's clock output when an a/d conversion is underway, as doing so could cause the a/d converter to operate erratically. ? after an initial reset, fade (d1/0x300287 ) and fadc (d0/0x300287 ) become indeterminate. to prevent generation of an unwanted interrupt or idma request, be sure to reset these flags in a program. ? fade : a/d conversion completion interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d1/0x300287) ? fadc : a/d out-of-range interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d0/0x300287) ? to prevent the regeneration of interrupts due to the same cause of interrupt following the occurrence an interrupt, always be sure to reset the cause-of-interrupt flag before setting the psr again or executing the reti instruction. ? when the a/d converter is set to enabled state, a current flows between av dd and v ss , and power is consumed, even when a/d operations are not performed. therefore, when the a/d converter is not used, it must be set to the disabled state (default 0 setting of ade (d2/0x300544)). ? when the 16 -bit timer 0 compare match b signal is used as a trigger factor, the division ratio of the prescaler in the 16-bit timer module must not be set to mclk/1. ? when using an external trigger to start a/d conversion, the low period of the trigger signal to be applied to the #adtrg pin must be two or more cpu operating clock cycles. furthermore, return the #adtrg input level to high within 20 cycles of the a/d input clock set. otherwise, it will be detected as the trigger for the next a/d conversion. ? software controllable pull-up resistors are provided for the input ports. disable the pull-up resistors of the ports used for analog inputs. ? when in break mode during icd-based debugging, the operating clock for the a/d converter is turned off due to the internal chip design. therefore, the a/d converter stops operating and registers cannot be accessed for write (but can be accessed for read).
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i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual viii peripheral m odules 6 ( lcd )

viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.1 lcd controller (lcdc) viii.1.1 overview the s 1c33e08 has a built-in lcd controller (lcdc) that supports 4/8 -bit monochrome and color lcd panels, and 12 -bit generic hr-tft panels. also the s1c33e08 contains a 12 -k byte vram (ivram) allowing a 320 240 -dot monochrome screen (1 -bpp mode) to be displayed. furthermore, the sdram controller allows the lcdc to access the external sdram as a vram, thus a 320 240 -dot screen with 8 -bpp color depth (typ.) can be dis - played. the lcdc provides support for picture-in-picture plus (a variable size overlay window). the lcdc can use both the ivram and external vram, this makes it possible to manages the main and sub (pip) window display data in different memories. the features of the lcdc are described below. internal bus interface and vram ? the uma (unified memory access) method using the bus arbiter and ivram arbiter is implemented. this method allows the lcdc to access sdram (external vram) while the cpu is accessing an internal circuit, or to access ivram (internal vram) while the cpu is accessing another circuit. ? the lcdc registers are mapped into area 6 and 32-bit accesses are possible. ? the 12 k-byte internal vram (ivram) is mapped at addresses 0x80000 to 0x82 fff. ? the external vram map is configurable (in a 2mb or 64mb sdram area). ? the lcdc interrupt signal is assigned to interrupt vector no. 73 (trap table base address + 0x124 ) in the itc. display support ? 4- or 8 -bit monochrome lcd interface ? 4- or 8 -bit color lcd interface ? single-panel, single-drive passive displays ? 12 -bit generic hr-tft interface 320 240 -dot sharp hr-tft panel, sii liquid tft panel, or some other tft panels ? typical resolutions 320 240 (8 -bpp mode, external vram is required) bpp = bits per pixel 320 240 (1-bpp mode) * note that the panel width must be a multiple of 16 bits per pixel. display modes ? due to frame rate modulation, grayscale display is possible in up to 16 shades of gray when a monochrome passive lcd panel is used. two-shade display in 1-bpp mode four-shade display in 2-bpp mode 16-shade display in 4-bpp mode ? a maximum of 64 k colors can be simultaneously displayed on a color passive lcd panel. 256-color display in 8-bpp mode 4k-color display in 12-bpp mode 64k-color display in 16-bpp mode ? a maximum of 4096 colors can be simultaneously displayed on a tft panel. two-color display in 1-bpp mode four-color display in 2-bpp mode 16-color display in 4-bpp mode 256-color display in 8-bpp mode 4k-color display in 12-bpp mode
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-2 epson s1c33e08 technical manual display features ? picture-in-picture plus displays a variable size window overlaid over background image. clock ? the pclk (pixel clock) is generated in the cmu by dividing the osc3 clock by 1 to 16. ? different clock paths are provided for the ahb bus interface (for accessing the vram), sapb interface (for accessing the control registers), and pclk, and each clock supply can be controlled individually in the cmu. this makes it possible to reduce current consumption by disabling unnecessary clocks. power save ? software power-save mode ? doze mode is supported for ram built-in or self-refresh-type lcd panels ? blank display
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.1.2 block diagram ivram arbiter sdramc (bus arbiter) ivram (12kb) sapb bus interface look-up table (16 6 3) lcdc cache sequence controller registers power save circuit sramc cmu ahb bus interface sdram lcd interface fpdat[11:0] fpframe fpline fpshift fpdrdy tft_ctl[3:0] to lcd panel lcdc clocks lcd controller s1c33e08 cpu_ahb bus lcdc_ahb bus figure viii. 1.2.1 block diagram of the lcd controller sapb bus interface the c 33 pe core accesses the lcdc registers and look-up table though this interface. ahb bus interface the lcdc access the vram through this interface. lcdc cache this consists of two 32-byte fifos used as a display data cache for sending display data to the lcd panel. sequence controller the sequence controller controls data flow from the ahb bus interface to the lcd interface through the look- up table. it also generates display data memory addresses for r efreshing display. look-up table this consists of three 16 6 -bit tables (red, green, and blue) and is used to set up the gray level or color data to be displayed. in monochrome mode, only the green look-up table is used. lcd interface the lcd interface performs frame rate modulation for passive lcd panels. it also formats display data and generates the timing control signals for various lcd panels. power save circuit this circuit controls the power save mode in the lcdc.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-4 epson s1c33e08 technical manual viii.1.3 output pins of the lcd controller table viii. 1.3.1 lists the output pins of the lcd controller. table viii.1.3.2 shows the pin configurations classified by type of lcd panel. table viii. 1.3.1 output pins of the lcd controller pin name fpd a t[11:0] fpframe fpline fpshift fpdrd y tft_ctl[3:0] i/o o o o o o o function lcd displa y data outputs lcd frame cloc k output lcd line cloc k output lcd shift cloc k output lcd drd y/mod signal output tft i/f control signal outputs note : the lcdc output pins are shared with general-purpose i/o ports or other peripheral circuit in - puts/outputs, so that functionality in the initial state is set to other than the lcdc output. before the lcdc output signals assigned to these pins can be used, the function of these pins must be switched for the lcdc output by setting the corresponding port function select registers. for details of pin functions and how to switch over, see section i.3.3, switching over the multi - plexed pin functions. table viii. 1.3.2 pin configurations by type of lcd panel pin name fpframe fpline fpshift fpdrd y fpd at 0 fpd at 1 fpd at 2 fpd at 3 fpd at 4 fpd at 5 fpd at 6 fpd at 7 fpd at 8 fpd at 9 fpd a t10 fpd a t11 tft_ctl0 tft_ctl1 tft_ctl2 tft_ctl3 4 bits monochr ome passive panel (single) dr iv en 0 * dr iv en 0 * dr iv en 0 * dr iv en 0 * dr iv en 0 * dr iv en 0 * dr iv en 0 * dr iv en 0 * color passive panel (single) mod dr iv en 0 * dr iv en 0 * dr iv en 0 * dr iv en 0 * d0 d1 d2 d3 8 bits mod d0 d1 d2 d3 d4 d5 d6 d7 4 bits mod dr iv en 0 * dr iv en 0 * dr iv en 0 * dr iv en 0 * d0 d1 d2 d3 8-bit f ormat 1 fpshift2 d0 d1 d2 d3 d4 d5 d6 d7 8-bit f ormat 2 generic hr-tft panel 12 bits sps lp dclk dr iv en 0 * b0 b1 b2 b3 g0 g1 g2 g3 r0 r1 r2 r3 ps cls rev spl mod d0 d1 d2 d3 d4 d5 d6 d7 fpframe fpline fpshift ? these pins can be used f or other per ipheral functions .
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 fpdat[7:0] fpframe fpline fpshift fpdrdy p xx s1c33e08 d[7:0] fpframe fpline fpshift mod/fpshift2 bias power lcd panel fpdat[7:4] fpframe fpline fpshift fpdrdy p xx s1c33e08 d[3:0] fpframe fpline fpshift mod bias power lcd panel 8-bit passive lcd panel fpdat[11:0] fpframe fpline fpshift tft_ctl0 tft_ctl1 tft_ctl2 tft_ctl3 p xx s1c33e08 d[11:0] sps lp dclk ps cls rev spl bias power lcd panel 12-bit generic hr-tft lcd panel 4-bit passive lcd panel figure viii. 1.3.1 typical lcd-panel connections
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-6 epson s1c33e08 technical manual viii.1.4 system settings viii.1.4.1 configuration of display data memory (vram) the s 1c33e08 has a built-in 12 k-byte display data memory (ivram). this memory allows selection whether it is used as a vram by locating at 0x80000 to 0x82 fff in area 3 or a general-purpose ram by locating in area 0. setting iram (d 0/0x3001a64 ) to 1 configures the ram as a general-purpose ram in area 0 ; setting to 0 config - ures it as a vram in area 3 . at initial reset, this memory is located in area 3 as a vram allowing lcdc to access directly. ? iram : iram assignment bit in the iram select register (d0/0x3001a64) the lcdc can use an external sdram as a vram in addition to ivram (the sdram can store general- purpose data as well as display data). there is no special configuration procedure for use of the external sdram. furthermore, both the external sdram and ivram can be used as vram simultaneously. the lcdc handles two screen data for the main window and the sub-window overlaid over the main window to support picture-in- picture plus. also the lcdc can switch the display by selecting a screen from two or more display data prepared in the vram. since the display start memory address is specified using a register, display data can be stored in any location (but it must be a word boundary address) in the memory. figure viii. 1.4.1.1 shows memory usage examples. ivram sdram window main sub when using picture-in-picture plus ivram sdram window main sub ivram sdram window main sub ivram sdram window main sub not used ex. 1 ivram sdram window screen 1 window screen 2 when switching screens ex. 5 ex. 2 ex. 3 ex. 4 sdram virtual screen actual display window when using virtual screen area ex. 7 ivram sdram window screen 1 window screen 2 ex. 6 not used sdram virtual screen actual display window figure viii. 1.4.1.1 memory usage examples the memory size required for a screen depends on the screen size and bpp mode. it can be expressed by the follow - ing equation: screen data size = h_pixel v_pixel bpp / 32 [words] (the fractional portion of the number must be rounded up.) h_pixel: number of horizontal pixels v_pixel: number of vertical pixels bpp: number of bits per pixel ( 1, 2, 4, 8, 12, 16) for example, a 320 240 -pixel screen displayed in 256 colors (8 -bpp mode) needs a 19,200 words (75 k bytes) of memory area.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.1.4.2 setting the lcdc clock the cmu provides the clock paths with a control bit shown below for the lcdc. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) lcdc ahb bus interface clock (lcdc_ahbif_clk) the lcdc uses this clock (mclk) to access ivram (internal vram) or an sdram (external vram). this clock is required for displaying a screen on the lcd panel. lcdcahbif_cke (d 2/0x301b00 ) is used for clock supply control (default: off). ? lcdcahbif_cke : lcdc ahb bus interface clock control bit in the gated clock control register 0 (d2/0x301b00) (2 ) control register clock (lcdc_sapb_clk) this clock (mclk) is used to control the lcdc registers located in area 6 . this clock is required for accessing the lcdc registers and it can be stopped otherwise. lcdcsapb_cke (d 1/0x301b00 ) is used for clock sup - ply control (default: off). ? lcdcsapb_cke : lcdc sapb bus interface clock control bit in the gated clock control register 0 (d1/0x301b00) (3 ) ivram arbiter clock (ivram_arb_clk) this clock (mclk) is used when the lcdc or cpu accesses ivram. when ivram is configured as a0 ram accessed by the cpu only, the clock supply can be stopped. ivramarb_cke (d19/0x301b04 ) is used for clock supply control (default: on). ? ivramarb_cke : ivram arbiter clock control bit in the gated clock control register 1 (d19/0x301b04) (4 ) lcd interface clock (lcdc_clk) this is the lcd interface clock (lcdc_clk) generated by dividing the osc 3 clock. the frequency divider generates 16 kinds of clocks from osc3?1/1 to osc3?1/16 . select a divided clock according to the frame rate using lcdcdiv[3:0] (d[19:16]/0x301b08). f lcdc frame rate = [hz] ht vt f lcdc : lcdc_clk frequency ht: horizontal total period (including non-display period) [pixels] vt: vertical total period (including non-display period) [pixels] ? lcdcdiv[3:0] : lcdc clock divider select bits in the system clock control register (d[19:16]/0x301b08) table viii. 1.4.2.1 selecting the lcdc clock lcdcdiv3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 lcdcdiv2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 lcdc_clk osc3?1/16 osc3?1/15 osc3?1/14 osc3?1/13 osc3?1/12 osc3?1/11 osc3?1/10 osc3?1/9 osc3?1/8 osc3?1/7 osc3?1/6 osc3?1/5 osc3?1/4 osc3?1/3 osc3?1/2 osc3?1/1 lcdcdiv1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 lcdcdiv0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (default: 0b0111 = osc3?1/8) lcdc_cke (d 0/0x301b00 ) is used for clock supply control (default: off). ? lcdc_cke : lcdc main clock control bit in the gated clock control register 0 (d0/0x301b00)
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-8 epson s1c33e08 technical manual (5 ) lcdc_ahb bus clock (lcdc_ahbbus_clk) the lcdc_ahb bus clock (mclk) is always supplied in normal operation. however, it can be automatically turned off in halt mode (see section iii. 1.9.2 ) by setting lcdcahb_hcke (d28/0x301b04 ) to 0 (default: on). ? lcdcahb_hcke : lcdc_ahb bus clock control (halt) bit in the gated clock control register 1 (d28/0x301b04) notes : ? the lcdc clock supply cannot be stopped while the lcd displays a screen. before the lcdc clock supply can be stopped, the lcdc must enter power save mode. ? the gated clock control registers 0 and 1 (0x301b00, 0x301b04 ) are write-protected. write protection of the cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be removed by writing 0x96 to the clock control protect register (0x301b24 ). since un - necessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register ( 0x301b24 ) is other than 0x96 , unless rewriting said registers.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.1.5 setting the lcd panel viii.1.5.1 types of panels the lcd controller supports the following types of lcd panels. ? 4- or 8 -bit single monochrome passive lcd panels ? 4- or 8 -bit single color passive lcd panels ? 12-bit generic hr-tft lcd panels dual panels are not supported. the type of lcd panel used must be set in the lcd controller i n advance, using the control bits described below. selecting between stn and hr-tft use tftsel (d 31/0x301a60 ) to select the type of lcd panel, either stn or hr-tft. tftsel = 1: generic hr-tft panel selected tftsel = 0 : stn panel selected (default) ? tftsel : hr-tft panel select bit in the lcdc display mode register (d31/0x301a60) selecting between color and monochrome use color (d 30/0x301a60) to select the type of lcd panel, either color or monochrome. color = 1: color panel selected color = 0 : monochrome panel selected (default) ? color : color/mono panel select bit in the lcdc display mode register (d30/0x301a60) selecting the data width use dwd[ 1:0] (d[27:26]/0x301a60) to select the data width and format. ? dwd[1:0] : lcd panel data width select bits in the lcdc display mode register (d[27:26]/0x301a60) table viii. 1.5.1.1 selection of the lcd panel color C 1 0 d wd1 C 1 1 0 0 1 1 0 0 lcd panel 12-bit gener ic hr-tft lcd color single 8-bit passiv e lcd fo r mat 2 reser ve d color single 8-bit passiv e lcd fo r mat 1 color single 4-bit passiv e lcd reser ve d reser ve d mono single 8-bit passiv e lcd mono single 4-bit passiv e lcd d wd0 C 1 0 1 0 1 0 1 0 tftsel 1 0
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-10 epson s1c33e08 technical manual viii.1.5.2 stn panel timing parameters the stn panel timing parameters shown in figures below can be set using the lcdc control registers. ht vt vdp hdp non displa y per iod displa y per iod figure viii. 1.5.2.1 stn panel timing parameters fpframe fpline fpdrdy (mod) fpdat x vdp vndp fpline fpdrdy (mod) fpshift fpdat x line 1 line 2 line 3 line 1 line 2 line 4 line n vt hdp hndp ht figure viii. 1.5.2.2 stn panel timing chart (example) ht: horizontal total period use htcnt[ 6:0] (d[22:16]/0x301a10) to set the horizontal total period. ht = (htcnt[6:0] + 1) 8 [ts] (ts: pixel clock period) ? htcnt[6:0] : horizontal total period (ht) setup bits in the horizontal display register (d[22:16]/0x301a10) htcnt[ 6:0] (d[22:16]/0x301a10 ) must be programmed such that the following condition is met: htcnt[ 6:0] hdpcnt[6:0] + 3 hdp: horizontal display period use hdpcnt[ 6:0] (d[6:0]/0x301a10) to set the horizontal display period (= horizontal panel resolution). hdp = (hdpcnt[6:0] + 1) 8 [ts] ? hdpcnt[6:0] : horizontal display period (hdp) setup bits in the horizontal display register (d[6:0]/0x301a10) hdpcnt[ 6:0] (d[6:0]/0x301a10 ) must be programmed such that the following condition is met: hdp 16 (hdpcnt[6:0] 1)
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 vt: vertical total period use vtcnt[ 9:0] (d[25:16]/0x301a14 ) to set the vertical total period. vt = vtcnt[ 9:0] + 1 [lines] ? vtcnt[9:0] : vertical total period (vt) setup bits in the vertical display register (d[25:16]/0x301a14) vdp: vertical display period use vdpcnt[ 9:0] (d[9:0]/0x301a14 ) to set the vertical display period (= vertical panel resolution). vdp = vdpcnt[ 9:0] + 1 [lines] ? vdpcnt[9:0] : vertical display period (vdp) setup bits in the vertical display register (d[9:0]/0x301a14) vdpcnt[ 9:0] (d[9:0]/0x301a14 ) must be programmed such that the following condition is met: vt vdp + 1 fpshift mask for monochrome lcd panel when color passive panel is selected (color (d 30/0x301a60 ) = 1 ), the fpshift clock is output during the horizontal display period (hdp) and it stops during the horizontal non-display period (hndp) as shown in fig - ure viii. 1.5.2.2. when monochrome passive panel is selected (color (d 30/0x301a60 ) = 0 ), the fpshift clock does not stop even in the horizontal non-display period by the default setting. to stop the fpshift clock during the horizon - tal non-display period, set fpsmask (d29/0x301a60) to 1. ? fpsmask : fpshift mask enable bit in the lcdc display mode register (d29/0x301a60) note : when using an stn panel, the registers for setting the hr-tft timing parameters must be set to 0x0.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-12 epson s1c33e08 technical manual viii.1.5.3 hr-tft panel timing parameters the hr-tft panel timing parameters shown in figures below can be set using the lcdc control registers. fpline (lp) hpw hps hdps ht fpframe (sps) vt vdps vdp hdp vps vpw non displa y per iod displa y per iod figure viii. 1.5.3.1 hr-tft panel timing parameters d1 d2 d319 d320 fpframe (sps) fpline (lp) fpline (lp) fpshift (clk) fpdat[11:0] tft_ctl3 (spl) tft_ctl1 (cls) tft_ctl0 (ps) tft_ctl2 (rev) tft_ctl1 pulse start offset tft_ctl2 delay tft_ctl1 pulse stop offset tft_ctl0 pulse start offset tft_ctl0 pulse stop offset ht hdps hdp hps fpframe pulse start offset vps vpw fpframe pulse stop offset hpw horizontal timing line 1 line 2 line 239 line 240 fpdat[11:0] fpframe (sps) vdps vdp vt vertical timing figure viii. 1.5.3.2 hr-tft panel timing chart
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ht: horizontal total period use htcnt[ 6:0] (d[22:16]/0x301a10) to set the horizontal total period. ht = (htcnt[6:0] + 1) 8 [ts] (ts: pixel clock period) ? htcnt[6:0] : horizontal total period (ht) setup bits in the horizontal display register (d[22:16]/0x301a10) htcnt[ 6:0] (d[22:16]/0x301a10 ) must be programmed such that the following conditions are met: htcnt[ 6:0] hdpcnt[6:0] + 3 ht > hdp + hdps hdp: horizontal display period use hdpcnt[ 6:0] (d[6:0]/0x301a10) to set the horizontal display period (= horizontal panel resolution). hdp = (hdpcnt[6:0] + 1) 8 [ts] ? hdpcnt[6:0] : horizontal display period (hdp) setup bits in the horizontal display register (d[6:0]/0x301a10) hdpcnt[ 6:0] (d[6:0]/0x301a10 ) must be programmed such that the following condition is met: hdp 16 (hdpcnt[6:0] 1) hdps: horizontal display period start position use hdpscnt[ 9:0 ] (d[9:0 ]/0x301a20 ) to set the horizontal display period start position for the hr-tft panel. hdps = hdpcnt[9:0] + 1 [ts] ? hdpcnt[9:0] : horizontal display period start position setup bits in the horizontal display start position register (d[9:0]/0x301a20) hdpscnt[ 9:0] (d[9:0]/0x301a20 ) must be programmed such that the following condition is met: ht > hdp + hdps hps: horizontal sync pulse start position use fplst[ 9:0 ] (d[25:16]/0x301a28 ) to set the horizontal sync pulse (fpline or lp) start position for the hr-tft panel. hps = fplst[9:0] + 1 [ts] ? fplst[9:0] : fpline pulse start position setup bits in the fpline pulse setup register (d[25:16]/0x301a28) hpw: horizontal sync pulse width use fplwd[ 6:0] (d[6:0]/0x301a28) to set the horizontal sync pulse width for the hr-tft panel. hpw = fplwd[ 6:0] + 1 [ts] ? fplwd[6:0] : fpline pulse width setup bits in the fpline pulse setup register (d[6:0]/0x301a28) horizontal sync pulse polarity use fplpol (d 7/0x301a28) to set the horizontal sync pulse polarity for the hr-tft panel. fplpol = 1 : active high fplpol = 0 : active low (default) ? fplpol : fpline pulse polarity setup bit in the fpline pulse setup register (d7/0x301a28) vt: vertical total period use vtcnt[ 9:0] (d[25:16]/0x301a14 ) to set the vertical total period. vt = vtcnt[ 9:0] + 1 [lines] ? vtcnt[9:0] : vertical total period (vt) setup bits in the vertical display register (d[25:16]/0x301a14) vtcnt[ 9:0] (d[25:16]/0x301a14 ) must be programmed such that the following condition is met: vt > vdp + vdps
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-14 epson s1c33e08 technical manual vdp: vertical display period use vdpcnt[ 9:0] (d[9:0]/0x301a14 ) to set the vertical display period (= vertical panel resolution). vdp = vdpcnt[ 9:0] + 1 [lines] ? vdpcnt[9:0] : vertical display period (vdp) setup bits in the vertical display register (d[9:0]/0x301a14) vdpcnt[ 9:0] (d[9:0]/0x301a14 ) must be programmed such that the following condition is met: vt vdp + 1 vdps: vertical display period start position use vdpscnt[ 9:0] (d[9:0]/0x301a24 ) to set the vertical display period start position for the hr-tft panel. vdps = vdpscnt[ 9:0] [lines] ? vdpscnt[9:0] : vertical display period start position setup bits in the vertical display start position register (d[6:0]/0x301a24) vdpscnt[ 9:0] (d[9:0]/0x301a24 ) must be programmed such that the following condition is met: vt > vdp + vdps vps: vertical sync pulse start position use fpfst[ 9:0 ] (d[25:16]/0x301a2 c) to set the vertical sync pulse (fpframe or sps) start position for the hr-tft panel. vps = fpfst[9:0] [lines] = fpfst[9:0] ht [ts] ? fpfst[9:0] : fpframe pulse start position setup bits in the fpframe pulse setup register (d[25:16]/0x301a2c) vpw: vertical sync pulse width use fpfwd[ 2:0] (d[2:0]/0x301a2 c) to set the vertical sync pulse width for the hr-tft panel. vpw = fpfwd[2:0] + 1 [lines] = (fpfwd[2:0] + 1) ht [ts] ? fpfwd[2:0] : fpframe pulse width setup bits in the fpframe pulse setup register (d[2:0]/0x301a2c) vertical sync pulse polarity use fpfpol (d 7/0x301a2 c) to set the vertical sync pulse polarity for the hr-tft panel. fpfpol = 1 : active high fpfpol = 0 : active low (default) ? fpfpol : fpframe pulse polarity setup bit in the fpframe pulse setup register (d7/0x301a2c) vertical sync pulse offset the vertical sync pulse position and width that are basically set in line units can be adjusted in pixel clock units. fpline/lp fpfrme/sps (without offset) fpfrme/sps (with offset) vps vpw vps' (fpline/fpframe pulse polar ity: activ e lo w) vpw' fpframe pulse star t offset fpframe pulse stop offset figure viii. 1.5.3.3 vertical sync pulse offset use fpfsto[ 9:0 ] (d[9:0 ]/0x301a30 ) and fpfstpo[9:0 ] (d[25:16 ]/0x301a30 ) to adjust the vertical sync pulse start and stop positions. vps = fpfst[9:0] ht + fpfsto[9:0] [ts] vpw = (fpfwd[2:0] + 1) ht - fpfsto[9:0] + fpfstpo[9:0] [ts] ? fpfsto[9:0] : fpframe pulse start offset bits in the fpframe pulse offset register (d[9:0]/0x301a30) ? fpfstpo[9:0] : fpframe pulse stop offset bits in the fpframe pulse offset register (d[25:16]/0x301a30)
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 fpshift (clk) signal the fpshift (clk) signal polarity for hr-tft panels can be sele cted using fpspol (d 1/0x301a40). ? fpspol : fpshift polarity select bit in the hr-tft special output register (d1/0x301a40) when hr-tft panel is selected (tftsel (d 31/0x301a60 ) = 1 ), the fpshift (clk) clock does not stop even in the horizontal non-display period by the default setting. to stop the fpshift clock during the horizon - tal non-display period, set fpsmask (d29/0x301a60) to 1. ? fpsmask : fpshift mask enable bit in the lcdc display mode register (d29/0x301a60) fpspol = 0 fpsmask = 0 fpspol = 1 fpsmask = 0 fpspol = 0 fpsmask = 1 fpspol = 1 fpsmask = 1 fpdata[11:0] tft_ctl3 (spl) fpshift (clk) d1 d2 d3 d319 d320 figure viii. 1.5.3.4 fpshift (clk) variations tft_ctl1 (cls) pulse start/stop offset the tft_ctl 1 (cls) pulse position and width can be specified in pixel clock cycles. use ctl1 st[9:0] (d[9:0]/0x301a44) to set the pulse start position and ctl1stp[9:0] (d[25:16]/0x301a44) to set the pulse stop position. these values should be specified an offset from the fpline pulse start position. ? ctl1st[9:0] : tft_ctl1 pulse start offset setup bits in the tft_ctl1 pulse register (d[9:0]/0x301a44) ? ctl1stp[9:0] : tft_ctl1 pulse stop offset setup bits in the tft_ctl1 pulse register (d[25:16]/0x301a44) by setting this register, the tft_ctl 1 pulse width is set to ctl1stp[9:0] - ctl1st[9:0] + 1 [ts]. to program the tft_ctl 1 pulse, ctl1ctl (d3/0x301a40) and preset (d2/0x301a40) must be set to 1. ? ctl1ctl : tft_ctl1 control bit in the hr-tft special output register (d3/0x301a40) ? preset : tft_ctl0C2 preset enable bit in the hr-tft special output register (d2/0x301a40) when ctl 1 ctl (d3/0x301a40 ) is set to 0 (default), the tft_ctl1 pulse is toggled at the fpline pulse start edge. the tft_ctl 1 and tft_ctl0 signals can be swapped using ctlswap (d0/0x301a40). tft_ctl 1 pin: cls output (ctlswap = 0 ), ps output (ctlswap = 1) tft_ctl 0 pin: ps output (ctlswap = 0 ), cls output (ctlswap = 1) ? ctlswap : tft_ctl0/tft_ctl1 swap bit in the hr-tft special output register (d0/0x301a40) tft_ctl 0 (ps) pulse start/stop offset the tft_ctl 0 (ps) pulse position and width can be specified in pixel clock cycles. use ctl0 st[9:0] (d[9:0]/0x301a48) to set the pulse start position and ctl0stp[9:0] (d[25:16]/0x301a48) to set the pulse stop position. these values should be specified an offset from the fpline pulse start position. ? ctl0st[9:0] : tft_ctl0 pulse start offset setup bits in the tft_ctl0 pulse register (d[9:0]/0x301a48) ? ctl0stp[9:0] : tft_ctl0 pulse stop offset setup bits in the tft_ctl0 pulse register (d[25:16]/0x301a48) by setting this register, the tft_ctl 0 pulse width is set to ctl0stp[9:0] - ctl0st[9:0] + 1 [ts]. to program the tft_ctl 0 pulse, preset (d2/0x301a40) must be set to 1. the tft_ctl 1 and tft_ctl0 signals can be swapped using ctlswap (d0/0x301a40).
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-16 epson s1c33e08 technical manual tft_ctl2 (rev) delay use ctl 2 dly[9:0 ] (d[9:0]/0x301a4 c) to set the tft_ctl2 toggle edge delay time from the fpline pulse start edge. ? ctl2dly[9:0] : tft_ctl2 delay setup bits in the tft_ctl2 register (d[9:0]/0x301a4c) to program the tft_ctl 2 delay time, preset (d2/0x301a40) must be set to 1.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.1.5.4 display modes the number of gray levels in grayscale display and the number of colors in color display are determined by the number of bits representing each pixel (bpp = bits per pixel). use bpp[ 2:0] (d[2:0]/0x301a60) to set a display (bpp) mode. ? bpp[2:0] : bit-per-pixel select bits in the lcdc display mode register (d[2:0]/0x301a60) table viii. 1.5.4.1 specification of display modes bpp1 1 0 0 1 1 0 0 monochr ome (color = 0) reser ve d reser ve d reser ve d reser ve d 4 bpp , 16 gra y le v els 2 bpp , 4 gra y le v els 1 bpp , 2 gra y le v els color (color = 1), stn reser ve d 16 bpp , 64k colors 12 bpp , 4k colors 8 bpp , 256 colors reser ve d reser ve d reser ve d displa y mode bpp0 ? 1 0 1 0 1 0 color (color = 1), tft reser ve d reser ve d 12 bpp , 4k colors 8 bpp , 256 colors 4 bpp , 16 colors 2 bpp , 4 colors 1 bpp , 2 colors bpp2 1 1 1 0 0 0 0 (def ault: 0b000) (1) 1-bpp (2 -gray-level/2-color) mode one pixel is represented by 1 bit, displayed in two gray levels (stn) or two colors (tft). for monochrome lcd panels, 2 -gray-level display can be obtained by assigning two gray levels from among the 64 gray levels available, including black and white, to two entries in the green look-up table (described later) (one each for bits = 0 and 1). for color lcd panels, two colors from among the 256 k colors available can be set in advance using two en - tries for pixel data 0 and 1 in each of the red, green, and blue look-up tables. data for eight consecutive pixels is stored as one byte in the display memory. a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 p0 p1 p2 p3 p4 p5 p6 p7 p8 displa y memor y pn = (an) lcd panel byte 0 byte 1 (bit 7) (bit 0) lut figure viii.1.5.4.1 data format in 1-bpp mode the look-up table can be bypassed in this mode, i.e., black-whi te mode, to reduce power consumption. (2) 2-bpp (4 -gray-level/4-color) mode one pixel is represented by 2 bits, displayed in four gray levels (stn) or four colors (tft). for monochrome lcd panels, 4 -gray-level display can be obtained by assigning four gray levels from among the 64 gray levels available, including black and white, to four entries in the green look-up table (one each for bits = 00 to 11). for color lcd panels, four colors from among the 256 k colors available can be set in advance using four en - tries for pixel data 00 to 11 in each of the red, green, and blue look-up tables. data for four consecutive pixels is stored as one byte in the display memory. lut a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 p0 p1 p2 p3 p4 p5 p6 p7 pn = (an, bn) byte 0 byte 1 displa y memor y lcd panel (bit 7) (bit 0) figure viii.1.5.4.2 data format in 2-bpp mode the look-up table can be bypassed in this mode to reduce power consumption.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-18 epson s1c33e08 technical manual (3) 4-bpp (16 -gray-level/16-color) mode one pixel is represented by 4 bits, displayed in 16 gray levels (stn) or 16 colors (tft). for monochrome lcd panels, 16 -gray-level display can be obtained by assigning 16 gray levels from among the 64 gray levels available, including black and white, to 16 entries in the green look-up table (one each for bits = 0000 to 1111). for color lcd panels, 16 colors from among the 256 k colors available can be set in advance using 16 entries for pixel data 0000 to 1111 in each of the red, green, and blue look-up tables. data for two consecutive pixels is stored as one byte in the display memory. lut a0 b0 c0 d0 a1 b1 c1 d1 a2 b2 c2 d2 a3 b3 c3 d3 a4 b4 c4 d4 a5 b5 c5 d5 p0 p1 p2 p3 p4 p5 p6 p7 pn = (an, bn, cn, dn) byte 0 byte 1 byte 2 displa y memor y lcd panel (bit 7) (bit 0) figure viii.1.5.4.3 data format in 4-bpp mode the look-up table can be bypassed in this mode to reduce power consumption. (4) 8-bpp (256-color) mode one pixel is represented by 8 bits, displayed in 256 colors. in this mode, 256 discrete combinations are configured using 8 entries in the red and green look-up tables, and 4 entries in the blue look-up table. data for one pixel is stored as one byte in the display memory. lut a0 b0 c0 d0 e0 f0 g0 h0 p0 p1 p2 p3 p4 p5 p6 p7 pn = (an, bn, cn, dn, en, fn, gn, hn) byte 0 byte 1 byte 2 displa y memor y lcd panel (bit 7) (bit 0) a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 figure viii.1.5.4.4 color data format in 8-bpp mode the look-up tables can be bypassed in this mode. in this case, the display data stored in the display memory di - rectly specifies a color. the following figure shows the correspondence between the memory data and the pixel data to be sent to the lcd panel. b1 b0 b1 b0 b1 b0 g1 g0 g2 g1 g0 g2 r1 r0 r2 r1 r0 r2 r2 r1 r0 g2 g1 g0 b1 b0 msb memor y data color 8-bpp mode displa y data (b lue) displa y data (green) displa y data (red) figure viii. 1.5.4.5 pixel data when lut is bypassed
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 (5) 12-bpp (4k-color) mode one pixel is represented by 12 bits, displayed in 4k colors. in this mode, 4 k discrete combinations are configured using 16 entries in each of the red, green and blue look- up tables. data for two pixels is stored as three bytes in the display memory. lut g0 3 g0 2 g0 1 g0 0 b0 3 b0 2 b0 1 b0 0 b1 3 b1 2 b1 1 b1 0 r0 3 r0 2 r0 1 r0 0 r1 3 r1 2 r1 1 r1 0 g1 3 g1 2 g1 1 g1 0 p0 p1 p2 p3 p4 p5 p6 p7 pn = (rn 3C0 , gn 3C0 , bn 3C0 ) byte 0 byte 1 byte 2 displa y memor y lcd panel (bit 7) (bit 0) figure viii.1.5.4.6 color display data format in 12-bpp mode the look-up tables can be bypassed in this mode. in this case, the display data stored in the display memory di - rectly specifies a color. the following figure shows the correspondence between the memory data and the pixel data to be sent to the lcd panel. r3 r2 r1 r0 r3 r2 r1 r0 g3 g2 g1 g0 b3 b2 b1 b0 msb memor y data color 12-bpp mode r3 r2 displa y data (b lue) displa y data (green) displa y data (red) g3 g2 g1 g0 g3 g2 b3 b2 b1 b0 b3 b2 figure viii. 1.5.4.7 pixel data when lut is bypassed (6) 16-bpp (64k-color) mode one pixel is represented by 16 bits, displayed in 64k colors (stn). data for one pixel is stored as two bytes in the display memory. lut g0 2 g0 1 g0 0 b0 4 b0 3 b0 2 b0 1 b0 0 r0 4 r0 3 r0 2 r0 1 r0 0 g0 5 g0 4 g0 3 g1 2 g1 1 g1 0 b1 4 b1 3 b1 2 b1 1 b1 0 r1 4 r1 3 r1 2 r1 1 r1 0 g1 5 g1 4 g1 3 p0 p1 p2 p3 p4 p5 p6 p7 pn = (rn 4C0 , gn 5C0 , bn 4C0 ) byte 0 byte 1 byte 2 byte 3 displa y memor y lcd panel (bit 7) (bit 0) figure viii.1.5.4.8 color display data format in 16-bpp mode the look-up tables are bypassed in this mode, and the display data stored in the display memory directly speci - fies a color. the following figure shows the correspondence between the memory data and the pixel data to be sent to the lcd panel. r4 r3 r2 r1 r0 r3 r4 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 msb memor y data color 16-bpp mode r4 displa y data (b lue) displa y data (green) displa y data (red) g3 g4 g5 g2 g1 g0 b3 b4 b2 b1 b0 b4 figure viii.1.5.4.9 pixel data when lut is bypassed in addition to the bpp mode selection, set dithen (d 6/0x301a60 ) to 1 to display in 64 k colors. when dithen (d6/0x301a60) is set to 0, the number of colors that can be displayed is limited to 4k colors. ? dithen : dither mode enable bit in the lcdc display mode register (d6/0x301a60) note : 16-bpp mode cannot be set when a hr-tft panel is used.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-20 epson s1c33e08 technical manual viii.1.5.5 look-up tables the lcd controller contains a look-up table consisting of 16 6 -bit entries, one for each of the rgb color elements (red, green, and blue). 6-bit luminance data pix el data the pix el data selects an lut entr y. 6-bit displa y data (r) red look-up tab le 0 1 2 3 : : 14 15 6-bit luminance data pix el data 6-bit displa y data (g or gr ay ) green look-up tab le 0 1 2 3 : : 14 15 6-bit luminance data pix el data 6-bit displa y data (b) blue look-up tab le 0 1 2 3 : : 14 15 figure viii. 1.5.5.1 configuration of the look-up tables the pixel data in the display memory is used as an index to the look-up tables, so that luminance data is generated based on the values in the entries indicated by the pixel data, before being output to the lcd panel. the lcd controller can control reversal of the display. this control is exercised on the output of the look-up tables. the look-up tables can be bypassed in 1-bpp, 2-bpp, 4-bpp, 8 -bpp, and 12 -bpp modes. in this case, the pixel data stored in the display memory directly specifies a gray level or color. to bypass the look-up table, set lutpass (d4/0x301a60) to 1. ? lutpass : lut bypass mode select bit in the lcdc display mode register (d4/0x301a60) the look-up table cannot be used in 1-, 2-, 4-, and 16-bpp color mode.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 grayscale-mode look-up tables in grayscale mode, the lcd controller uses only the green look-up table. for display in grayscale mode, select the data to be written to the look-up table from the 64 gray levels represented by 6 bits. the data 0x0, 0x20, and 0x3 f represent black, 50 % gray, and white, respectively. the differences in configuration between display modes are shown below. (1) 1-bpp (2 -gray-level) mode use the first two entries of the green look-up table. select two pieces of data from the 64 gray levels, and write them to the respective entries. the data in entry 0 is output for pixel data 0 , and the data in entry 1 is output for pixel data 1 . for monochrome display, write 0x0 to entry 0 and 0x3f to entry 1 before using the lcd panel. 1-bit pix el data from displa y b uff er 0 1 6-bit displa y data lutp ass green look-up tab le inde x unused 0 1 2 : 15 6-bit gra yscale data f or pix el data 0 6-bit gra yscale data f or pix el data 1 d[0,0,0,0,0,0] figure viii. 1.5.5.2 look-up table in 1-bpp (2 -gray-level) mode table viii. 1.5.5.1 shows an example of the basic data setting. table viii. 1.5.5.1 example of look-up-table settings in 1-bpp (2 -gray-level) mode inde x 0 1 2C15 r look-up table 0 0 0 g look-up table 0 0xfc 0 b look-up table 0 0 0 the above table shows 8 -bit values. they can be written to the look-up table data registers and only the high-order 6 bits are set into the look-up table (the low-order 2 bits are ignored). (2) 2-bpp (4 -gray-level) mode use the first four entries of the green look-up table. select four pieces of data from the 64 gray levels, and write them to the respective entries. the data in entry 0 is output for pixel data 00 , and the data in entry 3 is output for pixel data 11. 6-bit gra yscale data f or pix el data 00 6-bit gra yscale data f or pix el data 01 6-bit gra yscale data f or pix el data 10 6-bit gra yscale data f or pix el data 11 green look-up tab le inde x unused 0 1 2 3 4 : 15 2-bit pix el data from displa y b uff er 00 01 10 11 6-bit displa y data lutp ass d[1,0,1,0,1,0] figure viii. 1.5.5.3 look-up table in 2-bpp (4 -gray-level) mode table viii. 1.5.5.2 shows an example of the basic data setting. table viii. 1.5.5.2 example of look-up-table settings in 2-bpp (4 -gray-level) mode inde x 0 1 2 3 4C15 r look-up table 0 0 0 0 0 g look-up table 0 0x54 0xa8 0xfc 0 b look-up table 0 0 0 0 0 the above table shows 8 -bit values. they can be written to the look-up table data registers and only the high-order 6 bits are set into the look-up table (the low-order 2 bits are ignored).
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-22 epson s1c33e08 technical manual (3) 4-bpp (16 -gray-level) mode use the 16 entries of the green look-up table. select 16 pieces of data from the 64 gray levels, and write them to the respective entries. the data in entry 0 is output for pixel data 0000 , and the data in entry 15 is output for pixel data 1111. 6-bit gra yscale data f or pix el data 0x0 6-bit gra yscale data f or pix el data 0x1 6-bit gra yscale data f or pix el data 0x2 6-bit gra yscale data f or pix el data 0xf 6-bit gra yscale data f or pix el data 0xe 6-bit gra yscale data f or pix el data 0x3 green look-up tab le inde x 0 1 2 3 14 15 : : 4-bit pix el data from displa y b uff er 0000 0001 0010 0011 : 1110 1111 6-bit displa y data lutp ass d[3,2,1,0,3,2] figure viii. 1.5.5.4 look-up table in 4-bpp (16 -gray-level) mode table viii. 1.5.5.3 shows an example of the basic data setting. table viii. 1.5.5.3 example of look-up-table settings in 4-bpp (16 -gray-level) mode inde x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r look-up table 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g look-up table 0 0x10 0x20 0x30 0x44 0x54 0x64 0x74 0x88 0x98 0xa8 0xb8 0xcc 0xdc 0xec 0xfc b look-up table 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the above table shows 8 -bit values. they can be written to the look-up table data registers and only the high-order 6 bits are set into the look-up table (the low-order 2 bits are ignored).
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 color-mode look-up tables in color mode, the lcd controller uses the red (r), green (g), and blue (b) look-up tables. each color ele - ment is represented by 6 -bit data. rgb = 00?00?00 is black, rgb = 3f?00?00 is red, rgb = 00?20?00 is 50% luminance green, rgb = 3f?00?3 f is magenta, rgb = 3f?3f?3 f is white, and so on. in this way, colors are determined by the proportions of the three color elements. if the luminance of each color element is represented by 6 bits, then we obtain 64 64 64 = 256 k colors. of these, select as many pieces of color data as can be used for the available display mode ( 256 or 4 k colors), and write them to the valid entries of the look-up tables before using the lcd panel. the differences in configurations between display modes are shown below. (1) 8-bpp (256-color) mode one pixel is represented by 8 bits, displayed in 256 colors. in this mode, 256 discrete combinations are config - ured using 8 entries in each of the red and green look-up tables, and 4 entries in the blue look-up table. bits 7 C5 in 8 bits of pixel data are used as an index to the red look-up table, while bits 4C2 and bits 1C0 are used as indices to the green and blue look-up tables, respectively. 6-bit r data f or pix el data 0x0 6-bit r data f or pix el data 0x1 6-bit r data f or pix el data 0x2 6-bit r data f or pix el data 0x7 6-bit r data f or pix el data 0x3 red look-up tab le inde x 0 1 2 3 6-bit r data f or pix el data 0x4 4 6-bit r data f or pix el data 0x5 5 6-bit r data f or pix el data 0x6 6 7 unused 8 : 15 000 001 010 011 100 101 110 111 3-bit r pix el data from displa y b uff er 6-bit r displa y data r[2:0] r[2,1,0,2,1,0] lutp ass 6-bit g data f or pix el data 0x0 6-bit g data f or pix el data 0x1 6-bit g data f or pix el data 0x2 6-bit g data f or pix el data 0x7 6-bit g data f or pix el data 0x3 green look-up tab le inde x 0 1 2 3 6-bit g data f or pix el data 0x4 4 6-bit g data f or pix el data 0x5 5 6-bit g data f or pix el data 0x6 6 7 unused 8 : 15 000 001 010 011 100 101 110 111 3-bit g pix el data from displa y b uff er 6-bit g displa y data g[2:0] g[2,1,0,2,1,0] lutp ass 6-bit b data f or pix el data 0x0 6-bit b data f or pix el data 0x1 6-bit b data f or pix el data 0x2 6-bit b data f or pix el data 0x3 red look-up tab le inde x 12 13 14 15 unused 0 : 11 00 01 10 11 2-bit b pix el data from displa y b uff er 6-bit r displa y data b[1:0] b[1,0,1,0,1,0] lutp ass figure viii. 1.5.5.5 look-up table in 8-bpp (256-color) mode
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-24 epson s1c33e08 technical manual (2) 12-bpp (4k-color) mode one pixel is represented by 12 bits, displayed in 4 k (4,096 ) colors. in this mode, 4 k discrete combinations are configured using 16 entries in each of the red, green, and blue look-up tables. bits 11C8 in 12 bits of pixel data are used as an index to the red look-up table, while bits 7C4 and bits 3C0 are used as indices to the green and blue look-up tables, respectively. 6-bit r data f or pix el data 0x0 6-bit r data f or pix el data 0x1 6-bit r data f or pix el data 0x2 6-bit r data f or pix el data 0xf 6-bit r data f or pix el data 0xe 6-bit r data f or pix el data 0x3 red look-up tab le inde x 0 1 2 3 14 15 : : 6-bit g data f or pix el data 0x0 6-bit g data f or pix el data 0x1 6-bit g data f or pix el data 0x2 6-bit g data f or pix el data 0xf 6-bit g data f or pix el data 0xe 6-bit g data f or pix el data 0x3 green look-up tab le inde x 0 1 2 3 14 15 : : 6-bit b data f or pix el data 0x0 6-bit b data f or pix el data 0x1 6-bit b data f or pix el data 0x2 6-bit b data f or pix el data 0xf 6-bit b data f or pix el data 0xe 6-bit b data f or pix el data 0x3 blue look-up tab le inde x 0 1 2 3 14 15 : : 4-bit b pix el data from displa y b uff er 0000 0001 0010 0011 : 1110 1111 0000 0001 0010 0011 : 1110 1111 4-bit g pix el data from displa y b uff er 4-bit r pix el data from displa y b uff er 0000 0001 0010 0011 : 1110 1111 6-bit r displa y data r[3:0] r[3,2,1,0,3,3] lutp ass 6-bit g displa y data g[3:0] g[3,2,1,0,3,3] lutp ass 6-bit b displa y data b[3:0] b[3,2,1,0,3,3] lutp ass figure viii. 1.5.5.6 look-up table in 12-bpp (4k-color) mode
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 setting data in the look-up tables use the look-up table data registers for writing and reading 6 -bit gray/color data to/from the look-up tables. the look-up table data registers are mapped to addresses 0x301aa0 to 0x301 aac. table viii. 1.5.5.4 look-up table register address address 0x301aa0 0x301aa4 0x301aa8 0x301aa c lut entry 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data bit d[7:0] (d[1:0] are ineff ectiv e) d[15:8] (d[9:8] are ineff ectiv e) d[23:16] (d[17:16] are ineff ectiv e) d[31:24] (d[25:24] are ineff ectiv e) d[7:0] (d[1:0] are ineff ectiv e) d[15:8] (d[9:8] are ineff ectiv e) d[23:16] (d[17:16] are ineff ectiv e) d[31:24] (d[25:24] are ineff ectiv e) d[7:0] (d[1:0] are ineff ectiv e) d[15:8] (d[9:8] are ineff ectiv e) d[23:16] (d[17:16] are ineff ectiv e) d[31:24] (d[25:24] are ineff ectiv e) d[7:0] (d[1:0] are ineff ectiv e) d[15:8] (d[9:8] are ineff ectiv e) d[23:16] (d[17:16] are ineff ectiv e) d[31:24] (d[25:24] are ineff ectiv e) write data to all the entry to be used. although each entry is 6 -bit width, the registers above allow writing with 8 -bit data corresponding to the lcd output (6 high-order bits are effective). write each data with the low-order 2 bits set to 0 . the data written to the register is set to the r, g, and b look-up tables simultaneously. no writ - ing sequence is defined. writing can be started from any entry.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-26 epson s1c33e08 technical manual viii.1.5.6 frame rates the frame rate is calculated from the lcd panel s horizontal and vertical total periods, and pixel clock frequency, as shown below. f lcdc_clk frame rate = ht vt f lcdc_clk : pixel clock frequency f lcdc_clk = osc3/1 to osc3/16 (hz) see section iii.1.9.3, clock supply to the lcdc. ht: horizontal total period ht = (htcnt[ 6:0] + 1) 8 (ts) where ts = pixel clock cycle ? htcnt[6:0] : horizontal total period (ht) setup bits in the horizontal display register (d[22:16]/0x301a10) vt: vertical total period vt = vtcnt[ 9:0] + 1 (lines) ? vtcnt[9:0] : vertical total period (vt) setup bits in the vertical display register (d[25:16]/0x301a14) viii.1.5.7 other settings mod rate the period during which the mod signal is switched can be set using the mod[ 5:0] (d[5:0]/0x301a18). mod = 0x0 : mod signal switched at a period of the fpframe signal (default) mod = other than 0x0 : switched at a period of mod + 1 fpline pulses ? mod[5:0] : lcd mod rate setup bits in the mod rate register (d[5:0]/0x301a18) repeating of the frm pattern this setup item is provided for el panels. whether the frame-rate modulation pattern is to be repeated every 0x40000 frames (counted by the internal frame counter) can be set using frmrpt (d7/0x301a60). frmrpt = 1: frm pattern repeated (for el panel) frmrpt = 0 : frm pattern not repeated (default) ? frmrpt : frame repeat for el panel bit in the lcdc display mode register (d7/0x301a60)
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.1.6 display control viii.1.6.1 controlling lcd power up/down the lcd controller is activated when the lcdc clocks are supplied from the cmu. following initial reset, the lcd controller is set in power-save mode. supplying the clocks does not immediately cause the lcd panel to ini - tiate a power-up sequence and start displaying data. the lcd panel is placed in power-save mode, with all lcd signal output pins fixed low. to change the lcd controller from power-save mode back into normal mode, set the psave[ 1:0 ] (d[1:0 ]/ 0x301a04 ) to 0b11 . the lcd controller starts a power-up sequence from that point, and outputs lcd signals. conversely, to change from normal mode to power-save mode, set psave[ 1:0 ] (d[1:0]/0x301a04 ) to 0b00 . the lcd controller starts a power-down sequence from that point, and drives the lcd signals low. the lcd control registers and look-up tables can be accessed even in power-save mode. ? psave[1:0] : power save mode enable bits in the status and power save configuration register (d[1:0]/0x301a04) if the power to the lcd panel is turned on or off while lcd signals are not being correctly output, the panel may be damaged. therefore, the power to the lcd panel must be turned on only after the lcd controller starts control - ling lcd signals. use an i/o port to control the power to the lcd panel for this purpose. when lcd signals have no effect, disable the lcd power supply by controlling the port output; when lcd signals become effective, enable the lcd power supply using the port. the procedure for initializing the lcd at power-on is summarized below. 1 . configure the clocks, pins, and display memory area (refer to viii.1.4 system settings). 2 . set the lcd-panel parameters, display mode, and look-up tables (refer to viii.1.5 setting the lcd panel). 3 . enable the lcdc interrupt. 4 . write display data to the display memory. 5 . set the display start address (refer to viii.1.6.2 setting the display start address and line address offset). 6 . place the lcd controller in normal mode (psave = 0b11). 7 . the lcd controller starts outputting the lcd signals. 8 . wait time should be inserted depending on the lcd panel power source. 9 . control the port to turn the lcd panel power on. the following is the power-down procedure. 1 . control the port to turn the lcd panel power off. 2 . wait time should be inserted depending on the lcd panel power source. 3 . place the lcd controller in power-save mode (psave = 0b00). 4 . the lcd controller pulls lcd signals down to low.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-28 epson s1c33e08 technical manual viii.1.6.2 setting the display start address and line address offset display start address the display memory address from which to start display for the main window can be changed as desired using the main window display start address register ( 0x301a70 ). the start address set in the main window dis - play start address register ( 0x301a70 ) corresponds to the upper left edge of the lcd panel. note that a word boundary address (a[1:0] = 0b00 ) in ivram or the external sdram must be specified to this register. line address offset the s 1c33e08 lcdc manipulates display data in units of words. therefore, the image width (number of pix - els) must be a multiple of ( 32 bits bpp). the line address offset is the number of words corresponding to the image width and it should be specified in the following cases: 1 . when the picture-in-picture plus function is used (when a sub-window is displayed) 2 . when the lcd panel horizontal resolution is not a multiple of (32 bits bpp) the line address offset is calculated as follows: main window line address offset = main window width in pixels bpp / 32 set this value to mwladr[ 9:0] (d[9:0]/0x301a74). ? mwladr[9:0] : main window line address offset bits in the main window line address offset register (d[9:0]/0x301a74) ( 1 ) when the lcd panel horizontal resolution is a multiple of (32 bits bpp) example 1 ) lcd panel width = 320 pixels, 1-bpp mode main window line address offset = 320 1 / 32 = 10 [words] example 2 ) lcd panel width = 160 pixels, 8-bpp mode main window line address offset = 160 8 / 32 = 40 [words] when using the picture-in-picture plus function, set the calculated value to mwladr[ 9:0 ] (d[9:0 ]/ 0x301a74). when the picture-in-picture plus function is not used, it is not necessary to set mwladr[ 9:0 ] (d[9:0]/ 0x301a74 ). leave it unaltered from 0 or set the calculated value to mwladr[9:0 ] (d[9:0]/0x301a74 ) to display normally. be sure to avoid setting another value. ( 2 ) when the lcd panel horizontal resolution is not a multiple of (32 bits bpp) example 3 ) lcd panel width = 240 pixels, 1-bpp mode main window line address offset = 240 1 / 32 = 7.5 [words] 8 [words] in this case, the calculated results have a decimal fraction. it must be rounded up. mwladr[ 9:0] (d[9:0]/0x301a74) must be set to 8. furthermore, the image area with 256 (8 32 ) pixels wide must be prepared in the display memory. image data should be left justified in the area. the 0.5 word data (16 pixels) at the end of each line will not be displayed. 240 pix els lcd panel displa y memor y a a: main windo w star t address b: main windo w line address offset dumm y data main windo w data main windo w 256 pix els b (8 words) figure viii. 1.6.2.1 data layout in image area with offset when the lcd panel horizontal resolution is not a multiple of ( 32 bits bpp), a main window line address offset must be set to mwladr[ 9:0 ] (d[9:0]/0x301a74 ) regardless of whether the picture-in-picture plus function is used or not.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 the main window line address offset corresponds to one display line in the display memory. by adding/sub - tracting this value or a multiple to/from the main window display start address register ( 0x301a70 ), the im - age can be scrolled vertically. viii.1.6.3 writing display data the lcd controller may generate an interrupt at the beginning with the vertical non-display period after finishing each frame refresh sequence. furthermore, vndpf (d 7/0x301a04 ) is provided and is set to 1 if the display is in a vertical non-display period. ? vndpf : vertical display status flag in the status and power save configuration register (d7/0x301a04) to eliminate screen flicker, display data, lut data and the display buffer should be changed in a vertical non- display period by using this interrupt or vndpf (d 7/0x301a04). for more information on the lcdc interrupt, see section viii. 1.7, lcdc interrupt and dma. viii.1.6.4 inverting and blanking the display the display can be blanked (the entire screen turned black or white) without rewriting the contents of the display memory. setting blank (d 24/0x301a60 ) to 1 causes the fpdat signal to go low or high, blanking the display. setting it to 0 turns the display back on. whether the screen turns black or white is determined by swinv (d25/ 0x301a60 ) described below. ? blank : display blank enable bit in the lcdc display mode register (d24/0x301a60) ? swinv : software video invert bit in the lcdc display mode register (d25/0x301a60) furthermore, the display can be inverted simply by manipulating a control bit. setting swinv (d 25/0x301a60 ) to 1 inverts the display, and setting it to 0 returns the display to normal. (this function is effective only for stn panels and it does not support hr-tft panels.) this is accomplished by inverting the display data output from the look-up tables, rather than by inverting the pixel data in the display memory. the screen can be made to blink using these operations. make sure switching takes place within the vertical non- display period (vndpf (d7/0x301a04) = 1). viii.1.6.5 picture-in-picture plus picture-in-picture plus enables a sub-window to be displayed within the main window. the sub-window may be positioned anywhere within the main window and is controlled through the sub-window control registers. the sub- window retains the same color depth as the main window. the following diagram shows the sub-window configuration parameters. main windo w sub-windo w b c d e a a: p anel's or igin = main windo w star t address b: sub-windo w x star t position c: sub-windo w y star t position d: sub-windo w x end position e: sub-windo w y end position figure viii. 1.6.5.1 sub-window configuration parameters note : when using the picture-in-picture plus function, the main window line address offset must be set to mwladr[9:0] (d[9:0]/0x301a74). see section viii.1.6.2.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-30 epson s1c33e08 technical manual display memory for the sub-window the display data for the sub-window can be stored in ivram or the external sdram. if the same memory as the main window is used, make sure that the display data areas for the main window and sub-window do not overlap. the sub-window start address is specified by the sub-window display start address register ( 0x301a80 ) in the same manner as the main window. the start address set in the sub-window display start address register (0x301a80 ) corresponds to the upper left corner of the sub-window. note that a word boundary address (a[ 1:0 ] = 0b00 ) in ivram or the external sdram must be specified to this register. the sub-window width must be a multiple of ( 32 bits bpp). sub-window coordinates the display position and size of the sub-window are configured with the x and y coordinates of the start posi - tion (upper left corner) and end position (lower right corner). specify the sub-window start position using pipxst[ 9:0 ] (d[9:0 ]/0x301a88 ) for the x coordinate and pipyst[9:0 ] (d[25:16]/0x301a88 ) for the y coordinate. use pipxend[9:0 ] (d[9:0]/0x301a8 c) for specify - ing the x coordinate of the end position and pipyend[9:0] (d[25:16]/0x301a8 c) for the y coordinate. ? pipxst[9:0] : sub-window horizontal (x) start position bits in the sub-window start position register (d[9:0]/0x301a88) ? pipyst[9:0] : sub-window vertical (y) start position bits in the sub-window start position register (d[25:16]/0x301a88) ? pipxend[9:0] : sub-window horizontal (x) end position bits in the sub-window end position register (d[9:0]/0x301a8c) ? pipyend[9:0] : sub-window vertical (y) end position bits in the sub-window end position register (d[25:16]/0x301a8c) the x coordinate should be specified with the number of data words converted from the number of pixels from the lcd panel origin point according to the bpp mode. therefore, it can be specified in ( 32 bits bpp) pixel increments. 1-bpp mode: 1 -word = 32 -pixel units 2-bpp mode: 1 -word = 16 -pixel units 4-bpp mode: 1 -word = 8 -pixel units 8-bpp mode: 1 -word = 4 -pixel units 12-bpp mode: 3 -word = 8 -pixel units (because the value must be an integer) 16-bpp mode: 1 -word = 2 -pixel units for example, to specify the sub-window horizontal start position as 80 pixels in 8 -bpp mode, set pipxst[9:0] (d[9:0]/0x301a88) to 20. the y coordinate is specified with the number of lines from the lcd panel origin point in line units. for ex - ample, to specify the sub-window vertical start position as 60 lines, set pipyst[9:0 ] (d[25:16]/0x301a88 ) to 60. sub-window display control the picture-in-picture plus function is enabled and the sub-window is displayed by setting pipen (d 31/ 0x301a88) to 1 . this bit must be set after the sub-window configuration parameters are set up. ? pipen : pip sub-window enable bit in the sub-window start position register (d31/0x301a88) at initial reset, pipen (d 31/0x301a88) is set to 0 and sub-window is disabled for display.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 sub-window configuration example the following shows an example to configure main and sub-windows. [conditions] ? lcd panel resolution: 320 240 pixels ? bpp mode: 4 bpp (16 shades of gray/16 colors) ? memory used: external sdram (area 19, 0x10000000C) ? virtual screen size: 320 240 pixels ? sub-window size: 160 120 pixels ? sub-window start position: x = 80 pixels, y = 60 pixels main windo w exter nal sdram 160 80 120 60 180 240 0x10000000 0x100095ff 0x10009600 0x1000bb7f 320 240 (unit: pix el) sub-windo w main windo w displa y data sub-windo w displa y data figure viii. 1.6.5.2 sub-window configuration example 1 . main window start address this example assumes that the display data for the main window is located at the beginning of the external sdram (area 19). main window display start address register ( 0x301a70) = 0x10000000 2 . main window line address offset convert the screen width ( 320 pixels) into the number of words in 4 -bpp mode and set it to mwladr[9:0] (d[9:0]/0x301a74). mwladr[ 9:0] (d[9:0]/0x301a74) = 320 pixels 4 bpp 32 bits = 40 words main window line address offset register ( 0x301a74) = 40 (= 0x28) 3 . sub-window start address this example assumes that the sub-window data is located immediately following the main window data area. main window data size = 320 pixels 240 pixels 4 bpp 8 bits = 0x9600 bytes sub-window display start address register ( 0x301a80) = 0x10000000 + 0x9600 = 0x10009600 4 . sub-window start and end positions the x coordinates should be converted into the number of words in 4 -bpp mode to set them to the registers. the y coordinates can be set to the registers in the line numbers. sub-window start position pipxst[ 9:0] (d[9:0]/0x301a88) = 80 pixels 4 bpp 32 bits = 10 words (= 0x0a) pipyst[ 9:0] (d[25:16]/0x301a88) = 60 lines (= 0x3c) sub-window start position register ( 0x301a88) = 0x003c000a sub-window end position pipxend[ 9:0] (d[9:0]/0x301a8c) = (80 + 160 ) pixels 4 bpp 32 bits -1 = 29 words (= 0x1d) pipyend[ 9:0] (d[25:16]/0x301a8c) = 60 + 120 lines -1 = 180 lines (= 0xb3) sub-window end position register ( 0x301a8c) = 0x00b3001d after the settings above are completed, write 0x803c000 a to the sub-window start position register (0x301a88 ) to enable display of the sub-window.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-32 epson s1c33e08 technical manual viii.1.7 lcdc interrupt and dma frame interrupt when a frame refresh cycle (vertical display period) has finished, a vertical non-display period begins and the frame interrupt flag intf (d 31/0x301a04 ) is set to 1 . at the same time, the lcd controller outputs an inter - rupt signal to the itc when the frame interrupt has been enabled by setting inten (d 0/0x301a00 ) to 1 . if the interrupt conditions set using the itc registers are met, an interrupt to the cpu is generated. occurrence of this interrupt source indicates that the display data can be written to the display memory. this interrupt can also be used to invoke idma, enabling data to be written to the display memory by means of a dma transfer. ? intf : frame interrupt flag in the status and power save configuration register (d31/0x301a04) ? inten : frame interrupt enable bit in the frame interrupt register (d0/0x301a00) fpframe fpline intf vndpf vdp vndp (e .g. 3 lines) interr upt is generated reset by wr iting 1 figure viii. 1.7.1 frame interrupt timing once the intf flag is set to 1 , it is not reset until the software writes 1 to it. therefore, when enabling the frame interrupt, write 1 to intf before inten is set to 1 in order to avoid an unnecessary interrupt. when not using the lcdc interrupt, set inten to 0. note : the lcdc does not support the frame interrupt when the tft interface is selected (tftsel (d31/0x301a60) = 1). ? tftsel : hr-tft panel select bit in the lcdc display mode register (d31/0x301a60) control registers of the interrupt controller table viii. 1.7.1 shows the itc's control registers for the lcdc interrupts. table viii. 1.7.1 control registers of interrupt controller cause-of-interrupt fla g flcdc (d1/0x300288) interrupt priority register plcdc[2:0] (d[2:0]/0x300269) interrupt enable register elcdc (d1/0x300278) when the cause of interrupt occurs, the cause-of-interrupt flag is set to 1 . if the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated. interrupts due to a cause of interrupt can be disabled by leaving the interrupt enable register bit for that cause of interrupt set to 0 . the cause-of-interrupt flag is set to 1 whenever interrupt generation conditions are met, re - gardless of the setting of the interrupt enable register. the interrupt priority register sets the interrupt priority level for each interrupt system. an interrupt request to the cpu is accepted only when no other interrupt request of a higher priority has been generated. in addition, only when the psr's ie bit = 1 (interrupts enabled) and the set value of the il is smaller than the input interrupt level set using the interrupt priority register will the input interrupt request actually be accepted by the cpu. for details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to section iii.2, interrupt controller (itc).
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 intelligent dma the cause of lcdc interrupt can be used to invoke intelligent dma (idma). this enables display data trans - fer from the data memory to the display memory to be performe d by means of a dma transfer. the idma channel number set for the lcdc interrupt is 33. the idma request and enable bits shown in table viii. 1.7.2 must be set to 1 for idma to be invoked. transfer conditions, etc. on the idma side must also be set in advance. table viii. 1.7.2 control bits for idma transfer idma request bit rlcdc (d1/0x30029b) idma enable bit delcdc (d1/0x30029c) if a cause of interrupt factor occurs when the idma request and enable bits are set to 1 , idma is invoked. no interrupt request is generated at that point. an interrupt request is generated upon completion of the dma transfer. the bits can also be set so as not to generate an interrupt, with only a dma transfer performed. for details on dma transfer and how to control interrupts upon completion of a dma transfer, refer to section ii.2, intelligent dma (idma). trap vectors the trap-vector address for the lcdc interrupt is set to 0x0c00124 by default. the base address of the trap table can be changed using the ttbr register.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-34 epson s1c33e08 technical manual viii.1.8 power save the lcd controller has two types of power-save modes. use psave[ 1:0 ] (d[1:0]/0x301a04 ) to set power-save modes. ? psave[1:0] : power save mode select bits in the status and power save configuration register (d[1:0]/0x301a04) table viii. 1.8.1 settings of power-save modes psa ve1 1 1 0 0 psa ve0 1 0 1 0 mode nor mal operation doz e mode reser ve d po wer-sa ve mode power-save mode when the lcd controller enters this mode, all lcd signal output pins are dropped low, with the lcd panel placed in power-down mode. all operations of the lcd controller, other than accessing of its control registers and look-up tables are disabled. the lcd controller is placed in power-save mode by setting psave (d[ 1:0]/0x301a04) to 0b00. the lcd controller is taken out of power-save mode by setting psave (d[ 1:0]/0x301a04) to 0b11. doze mode doze mode is a power-save mode designed for use with built-in ram type or self-refresh type lcd panels. these panels do no need to send data constantly in order to refresh the display of the same image. the lcd controller can be set in doze mode during this period. in doze mode, the fpdat and fpshift signals are fixed low so that no access to the display memory occurs. although the power-saving effects are not as significant as in power-save mode, this mode helps reduce the current consumption in the lcd panel while keeping the dis - play on. comparison of power-save modes the differences between power-save modes are summarized in table viii. 1.8.2. table viii. 1.8.2 differences between power-save modes item accessing i/o registers accessing look-up tab le accessing vram displa y (stn panels) displa y (hr-tft panels) lcdc displa y-data-f etch operation fpd a t[11:0] signals (stn, hr-tft panels) fpshift signal (stn panels) fpline, fpframe, fpdrd y signals (stn panels) fpshift signal (hr-tft panels) when fpspol (d1/0x301a40) = 0 fpshift signal (hr-tft panels) when fpspol (d1/0x301a40) = 1 fpframe signal (hr-tft panels) when fpfpol (d7/0x301a2c) = 0 fpframe signal (hr-tft panels) when fpfpol (d7/0x301a2c) = 1 fpline signal (hr-tft panels) when fplpol (d7/0x301a28) = 0 fpline signal (hr-tft panels) when fplpol (d7/0x301a28) = 1 tft_ctl1 signal * (hr-tft panels) when ctl1st[9:0] (d[9:0]/0x301a44) = 0 tft_ctl1 signal * (hr-tft panels) when ctl1st[9:0] (d[9:0]/0x301a44) 0 tft_ctl0, tft_ctl2, tft_ctl3 signals (hr-tft panels) normal enab led enab led enab led activ e activ e activ e activ e activ e activ e activ e activ e activ e activ e activ e activ e activ e activ e activ e po wer -sa ve mode enab led enab led enab led inactiv e inactiv e inactiv e lo w lo w lo w high lo w high lo w high lo w high lo w lo w lcdc disabled disab led disab led enab led inactiv e inactiv e inactiv e lo w lo w lo w lo w lo w lo w lo w lo w lo w lo w lo w lo w doze mode enab led enab led enab led activ e inactiv e inactiv e lo w lo w activ e high lo w activ e activ e activ e activ e activ e activ e activ e ? the tft_ctl1 signal is configured with ctl1ctl (d3/0x301a40) = 1, preset (d2/0x301a40) = 1, and ctlsw ap (d0/0x301a40) = 0.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.1.9 details of control registers table viii. 1.9.1 list of lcdc registers address 0x00301a00 0x00301a04 0x00301a10 0x00301a14 0x00301a18 0x00301a20 0x00301a24 0x00301a28 0x00301a2c 0x00301a30 0x00301a40 0x00301a44 0x00301a48 0x00301a4c 0x00301a60 0x00301a64 0x00301a70 0x00301a74 0x00301a80 0x00301a88 0x00301a8c 0x00301aa0 0x00301aa4 0x00301aa8 0x00301aac function enables lcdc interrupts. controls power-save mode and indicates interrupt status. sets horizontal total and display periods. sets vertical total and display periods. sets mod rate. sets horizontal display period start position for hr-tft. sets vertical display period start position for hr-tft. sets fpline pulse for hr-tft. sets fpframe pulse for hr-tft. sets fpframe pulse offset for hr-tft. controls hr-tft signals. sets tft_ctl1 pulse. sets tft_ctl0 pulse. sets tft_ctl2 signal. sets display mode and controls display. selects iram allocation. sets main window display start address. sets main window line address offset. sets sub-window display start address. sets sub-window start position. sets sub-window end position. look-up table data (entries 0 to 3) look-up table data (entries 4 to 7) look-up table data (entries 8 to 11) look-up table data (entries 12 to 15) register name frame interrupt register (plcdc_int) status and power save configuration register (plcdc_ps ) horizontal display register (plcdc_hd) vertical display register (plcdc_vd) mod rate register (plcdc_mr) horizontal display start position register (plcdc_hdps) vertical display start position register (plcdc_vdps) fpline pulse setup register (plcdc_l) fpframe pulse setup register (plcdc_f) fpframe pulse offset register (plcdc_fo) hr-tft special output register (plcdc_tso) tft_ctl1 pulse register (plcdc_tc1) tft_ctl0 pulse register (plcdc_tc0) tft_ctl2 register (plcdc_tc2) lcdc display mode register (plcdc_dmd) iram select register (plcdc_iram) main window display start address register (plcdc_madd) main window line address offset register (plcdc_mladd) sub-window display start address register (plcdc_sadd) sub-window start position register (plcdc_ssp) sub-window end position register (plcdc_sep) look-up table data register 0 (plcdc_lut_03) look-up table data register 1 (plcdc_lut_47) look-up table data register 2 (plcdc_lut_8b) look-up table data register 3 (plcdc_lut_cf) siz e 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 the following describes each lcdc control register. the lcdc control registers are mapped in the 32 -bit device area from 0x301a00 to 0x301 aac, and can be ac - cessed only in units of words. note : when setting the lcdc control registers, be sure to write a 0, and not a 1, for all reserved bits.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-36 epson s1c33e08 technical manual 0x301a00: frame interrupt register (plcdc_int) name address register name bit function setting init. r/w remarks C inten d31C1 d0 reserved frame interrupt enable C 0 C r/w 0 when being read. 00301a00 (w) 1 enabled 0 disabled frame interrupt register (plcdc_int) C d[31:1] reserved d0 inten: frame interrupt enable bit enables the lcdc frame interrupt request. 1 (r/w): enable 0 (r/w): disable (default) when using the frame interrupt, set inten to 1 . the output of the interrupt signal to the itc is en - abled. when this bit is set to 0, the lcdc interrupt will not be generated. note : the lcdc does not support the frame interrupt when the tft interface is selected (tftsel (d31/0x301a60) = 1).
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a04: status and power save configuration register (plcdc_ps) name address register name bit function setting init. r/w remarks C C intf C vndpf C psave1 psave0 d31 d30C8 d7 d6C2 d1 d0 frame interrupt flag reserved vertical display status reserved power save mode 0 C 1 C 0 0 r/w C r C r/w reset by writing 1. 0 when being read. 0 when being read. 00301a04 (w) 1 generated 0 not generated status and power save configuration register (plcdc_ps) 1 1 0 0 1 0 1 0 psave[1:0] mode normal operation doze mode reserved power save mode 1 vndp 0 vdp d31 intf: frame interrupt flag indicates the frame interrupt status. 1 (r): interrupt is generated 0 (r): interrupt is not generated (default) 1 (w): flag is reset 0 (w): invalid intf is set to 1 when a vertical non-display period begins. if inten (d0/0x301a00 ) is set to 1 to en - able the frame interrupt, the interrupt signal is asserted and the lcdc interrupt cause flag in the itc is set to 1 . this flag can only be reset by writing 1 to it. note : the lcdc does not support the frame interrupt when the tft interface is selected (tftsel (d31/0x301a60) = 1). d[30:8] reserved d7 vndpf: vertical display status flag indicates whether the lcd panel is in a vertical non-display period or not. 1 (r): vertical non-display period (default) 0 (r): vertical display period vndpf is set to 1 during a vertical non-display period, and set to 0 during a vertical display period. when images must be switched without causing the screen to flicker, it is possible to switch within a vertical non-display period by reading this bit. note : when a tft lcd panel is used with the s1c33e08 tft lcd interface selected (tftsel (d31/0x301a60) = 1), this flag may be fixed at 1 in some rare cases depending on the timing. refer to section viii.1.10, precautions, for how to solve this problem. d[6:2] reserved d[1:0] psave[1:0]: power save mode select bits selects power-save mode. table viii. 1.9.2 settings of power-save modes psa ve1 1 1 0 0 psa ve0 1 0 1 0 mode nor mal operation doz e mode reser ve d po wer-sa ve mode (default: 0b00 = power-save mode) the lcd controller is placed in power-save mode by setting psave to 0b00 . in this mode, all lcd signal output pins are dropped low and all operations of the lcd controller, other than accessing of its control registers and look-up tables are disabled. the lcd controller is taken out of power-save mode by setting psave to 0b11. doze mode is a power-save mode designed for use with built-in ram type or self-refresh type lcd panels. in doze mode, the fpdat and fpshift signals are fixed low so that no access to the display memory occurs. although the power-saving effects are not as significant as in power-save mode, this mode helps reduce the current consumption in the lcd panel whil e keeping the display on.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-38 epson s1c33e08 technical manual 0x301a10: horizontal display register (plcdc_hd) name address register name bit function setting init. r/w remarks C htcnt6 htcnt5 htcnt4 htcnt3 htcnt2 htcnt1 htcnt0 C hdpcnt6 hdpcnt5 hdpcnt4 hdpcnt3 hdpcnt2 hdpcnt1 hdpcnt0 d31C23 d22 d21 d20 d19 d18 d17 d16 d15C7 d6 d5 d4 d3 d2 d1 d0 reserved horizontal total period (ht) setup ht = hdp + hndp ht > hdps + hdp (for hr-tft) reserved horizontal display period (hdp) setup C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. 0 when being read. 00301a10 (w) horizontal display register (plcdc_hd) C ht = (htcnt + 1) 8 [ts] hndp = (htcnt - hdpcnt) 8 [ts] C hdp = (hdpcnt + 1) 8 [ts] d[31:23] reserved d[22:16] htcnt[6:0]: horizontal total period (ht) setup bits sets the horizontal total period (ht) in 8 -pixel increments. (default: 0x0) ht = (htcnt[6:0] + 1) 8 [ts] (ts: pixel clock period) the horizontal total period contains horizontal display period and horizontal non-display period and the maximum value that can be set is 1,024 -pixel period. the following conditions must be satisfied when setting htcnt[ 6:0]: htcnt[ 6:0] hdpcnt[6:0] + 3 ht > hdp + hdps d[15:7] reserved d[6:0] hdpcnt[6:0]: horizontal display period (hdp) setup bits sets the horizontal display period (hdp, panel horizontal resolution) in 8 -pixel increments. (default: 0x0) hdp = (hdpcnt[6:0] + 1) 8 [ts] the following condition must be satisfied when setting hdpcnt[ 6:0]: hdp 16 (hdpcnt[6:0] 1)
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a14: vertical display register (plcdc_vd) name address register name bit function setting init. r/w remarks C vtcnt9 vtcnt8 vtcnt7 vtcnt6 vtcnt5 vtcnt4 vtcnt3 vtcnt2 vtcnt1 vtcnt0 C vdpcnt9 vdpcnt8 vdpcnt7 vdpcnt6 vdpcnt5 vdpcnt4 vdpcnt3 vdpcnt2 vdpcnt1 vdpcnt0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved vertical total period (vt) setup vt = vdp + vndp vt > vdps + vdp (for hr-tft) reserved vertical display period (vdp) setup C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. 0 when being read. 00301a14 (w) vertical display register (plcdc_vd) C vt = vtcnt + 1 [lines] vndp = htcnt - hdpcnt [lines] C vdp = vdpcnt + 1 [lines] d[31:26] reserved d[25:16] vtcnt[9:0]: vertical total period (vt) setup bits sets the vertical total period (vt) in line units. (default: 0x0) vt = vtcnt[ 9:0] + 1 [lines] the vertical total period contains vertical display period and vertical non-display period and the maxi - mum value that can be set is 1,024 lines. the following condition must be satisfied when setting vtcnt[ 9:0]: vt > vdp + vdps d[15:10] reserved d[9:0] vdpcnt[9:0]: vertical display period (vdp) setup bits sets the vertical display period (vdp, panel vertical resolution) in line units. (default: 0x0) vdp = vdpcnt[ 9:0] + 1 [lines] the following condition must be satisfied when setting vdpcnt[ 9:0]: vt vdp + 1
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-40 epson s1c33e08 technical manual 0x301a18: mod rate register (plcdc_mr) name address register name bit function setting init. r/w remarks C mod5 mod4 mod3 mod2 mod1 mod0 d31C6 d5 d4 d3 d2 d1 d0 reserved lcd mod rate mod5 = msb mod0 = lsb C 0 0 0 0 0 0 C r/w 0 when being read. 00301a18 (w) mod rate register (plcdc_mr) C 0x0 to 0x3f d[31:6] reserved d[5:0] mod: lcd mod rate setup bits sets the cycle time at which to switch the mod signal. (default: 0x0) when this register is 0x0 , the mod signal switches at the cycle time of the fpframe signal. if an - other period is desired, set the fpline pulse-count value.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a20: horizontal display start position register (plcdc_hdps) name address register name bit function setting init. r/w remarks C hdpscnt9 hdpscnt8 hdpscnt7 hdpscnt6 hdpscnt5 hdpscnt4 hdpscnt3 hdpscnt2 hdpscnt1 hdpscnt0 d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved horizontal display period start position for hr-tft ht > hdps + hdp C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. 0x0 must be set for stn panels. 00301a20 (w) horizontal display start position register (plcdc_hdps) C hdps = hdpscnt + 1 [pixels] note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:10] reserved d[9:0] hdpscnt[9:0]: horizontal display period start position setup bits sets the horizontal display period start position (hdps) for hr-tft panels in pixel clock units. (default: 0x0) hdps = hdpscnt[9:0] + 1 [ts] (ts: pixel clock period) the following condition must be satisfied when setting hdpscnt[ 9:0]: ht > hdp + hdps
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-42 epson s1c33e08 technical manual 0x301a24: vertical display start position register (plcdc_vdps) name address register name bit function setting init. r/w remarks C vdpscnt9 vdpscnt8 vdpscnt7 vdpscnt6 vdpscnt5 vdpscnt4 vdpscnt3 vdpscnt2 vdpscnt1 vdpscnt0 d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved vertical display period start position for hr-tft vt > vdps + vdp C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. 0x0 must be set for stn panels. 00301a24 (w) vertical display start position register (plcdc_vdps) C vdps = vdpscnt [lines] note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:10] reserved d[9:0] vdpscnt[9:0]: vertical display period start position setup bits sets the vertical display period start position (vdps) for hr-tft panels in line units. (default: 0x0) vdps = vdpscnt[ 9:0] [line] the following condition must be satisfied when setting vdpscnt[ 9:0]: vt > vdp + vdps
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-43 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a28: fpline pulse setup register (plcdc_l) name address register name bit function setting init. r/w remarks C fplst9 fplst8 fplst7 fplst6 fplst5 fplst4 fplst3 fplst2 fplst1 fplst0 C fplpol fplwd6 fplwd5 fplwd4 fplwd3 fplwd2 fplwd1 fplwd0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved fpline pulse start position reserved fpline pulse polarity fpline pulse width C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 C r/w C r/w r/w 0 when being read. ? 1: for hr-tft 0x0 must be set for stn panels. 0 when being read. ( ? 1) 00301a28 (w) fpline pulse setup register (plcdc_l) C start position = fplst + 1 [pixels] C pulse width = fplwd + 1 [pixels] 0 1 active high active low note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:26] reserved d[25:16] fplst[9:0]: fpline pulse start position setup bits sets the horizontal sync pulse (fpline or lp) start position (hps) for hr-tft panels in pixel clock units. (default: 0x0) hps = fplst[9:0] + 1 [ts] (ts: pixel clock period) d[15:8] reserved d7 fplpol: fpline pulse polarity setup bit sets the horizontal sync pulse polarity for hr-tft panels. 1 (r/w): active high 0 (r/w): active low (default) d[6:0] fplwd[6:0]: fpline pulse width setup bits sets the horizontal sync pulse width (hpw) for hr-tft panels i n pixel clock units. (default: 0x0) hpw = fplwd[ 6:0] + 1 [ts] (ts: pixel clock period)
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-44 epson s1c33e08 technical manual 0x301a2c: fpframe pulse setup register (plcdc_f) name address register name bit function setting init. r/w remarks C fpfst9 fpfst8 fpfst7 fpfst6 fpfst5 fpfst4 fpfst3 fpfst2 fpfst1 fpfst0 C fpfpol C fpfwd2 fpfwd1 fpfwd0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C8 d7 d6C3 d2 d1 d0 reserved fpframe pulse start position reserved fpframe pulse polarity reserved fpframe pulse width C 0 0 0 0 0 0 0 0 0 0 C 0 C 0 0 0 C r/w C r/w C r/w 0 when being read. ? 1: for hr-tft 0x0 must be set for stn panels. 0 when being read. ( ? 1) 0 when being read. ( ? 1) 00301a2c (w) fpframe pulse setup register (plcdc_f) C start position = fpfst ht [pixels] C C pulse width = (fpfwd+1) ht [pixels] 0 1 active high active low note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:26] reserved d[25:16] fpfst[9:0]: fpframe pulse start position setup bits sets the vertical sync pulse (fpframe or sps) start position (vps) for hr-tft panels. (default: 0 x 0 ) vps = fpfst[9:0] [lines] = fpfst[9:0] ht [ts] (ts: pixel clock period) d[15:8] reserved d7 fpfpol: fpframe pulse polarity setup bit sets the vertical sync pulse polarity for hr-tft panels. 1 (r/w): active high 0 (r/w): active low (default) d[6:3] reserved d[2:0] fpfwd[2:0]: fpframe pulse width setup bits sets the vertical sync pulse width (vpw) for hr-tft panels. (default: 0x0) vpw = fpfwd[2:0] + 1 [lines] = (fpfwd[2:0] + 1) ht [ts] (ts: pixel clock period)
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-45 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a30: fpframe pulse offset register (plcdc_fo) name address register name bit function setting init. r/w remarks C fpfstpo9 fpfstpo8 fpfstpo7 fpfstpo6 fpfstpo5 fpfstpo4 fpfstpo3 fpfstpo2 fpfstpo1 fpfstpo0 C fpfsto9 fpfsto8 fpfsto7 fpfsto6 fpfsto5 fpfsto4 fpfsto3 fpfsto2 fpfsto1 fpfsto0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved fpframe pulse stop offset reserved fpframe pulse start offset C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. ? 1: for hr-tft 0x0 must be set for stn panels. 0 when being read. ( ? 1) 00301a30 (w) fpframe pulse offset register (plcdc_fo) C stop offset = fpfstpo [pixels] C start offset = fpfsto [pixels] note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:26] reserved d[25:16] fpfstpo[9:0]: fpframe pulse stop offset bits adjusts the vertical sync pulse end position (pulse width), which has been set in line units, in pixel clock units. (default: 0x0) vpw = (fpfwd[2:0] + 1) ht - fpfsto[9:0] + fpfstpo[9:0] [ts] (ts: pixel clock period) d[15:10] reserved d[9:0] fpfsto[9:0]: fpframe pulse start offset bits adjusts the vertical sync pulse start position, which has been set in line units, in pixel clock units. (default: 0x0) vps = fpfst[9:0] ht + fpfsto[9:0 ] [ts] (ts: pixel clock period)
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-46 epson s1c33e08 technical manual 0x301a40: hr-tft special output register (plcdc_tso) name address register name bit function setting init. r/w remarks C ctl1ctl preset fpspol ctlswap d31C4 d3 d2 d1 d0 reserved tft_ctl1 control tft_ctl0C2 preset enable fpshift polarity tft_ctl0/tft_ctl1 swap C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. for hr-tft 0x0 must be set for stn panels. 00301a40 (w) hr-tft special output register (plcdc_tso) C 0 1 program toggle/line 0 1 program preset 0 1 falling rising 0 1 swap not swap note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:4] reserved d3 ctl1ctl: tft_ctl1 control bit selects the behavior of the tft_ctl 1 (cls) signal. 1 (r/w): toggle at the programmed timing 0 (r/w): toggle every line (default) set ctl 1 ctl to 1 when using the tft_ctl1 (cls) signal that has been programmed using the tft_ctl1 pulse register (0x301a44 ) or preset with standard conditions. ctl1 ctl is set to 0 by de - fault, in this case the tft_ctl 1 (cls) signal toggles between high and low every time the fpline (lp) pulse is output. d2 preset: tft_ctl0C2 preset enable bit enables use of the programmed tft_ctl 0 (ps), tft_ctl1 (cls), and tft_ctl2 (rev) signals. 1 (r/w): programmed signals 0 (r/w): preset signal (default) by setting preset to 1 , the signal timing conditions may be programmed using the registers shown below. tft_ctl 0 (ps): tft_ctl0 pulse register (0x301a48) tft_ctl 1 (cls): tft_ctl1 pulse register (0x301a44) tft_ctl 2 (rev): tft_ctl2 register (0x301a4c) when preset = 0 , the tft_ctl0 , tft_ctl1 , and tft_ctl2 signals are fixed at low. d1 fpspol: fpshift polarity select bit selects the polarity of the fpshift (clk) signal for hr-tft pa nels. 1 (r/w): falling edge 0 (r/w): rising edge (default) when fpspol is set to 1 , the fpdat[11:0 ] output signal toggles at the rising edge (sampled at the falling edge) of the fpshift (clk) signal. when fpspol is set to 0 , the fpdat[11:0 ] output signal toggles at the falling edge (sampled at the rising edge) of the fpshift (clk) signal. d0 ctlswap: tft_ctl0/tft_ctl1 swap bit swaps the signal between tft_ctl 1 and tft_ctl0. 1 (r/w): swapped (tft_ctl0 = cls, tft_ctl1 = ps) 0 (r/w): not swapped (tft_ctl0 = ps, tft_ctl1 = cls) (default)
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-47 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a44: tft_ctl1 pulse register (plcdc_tc1) name address register name bit function setting init. r/w remarks C ctl1stp9 ctl1stp8 ctl1stp7 ctl1stp6 ctl1stp5 ctl1stp4 ctl1stp3 ctl1stp2 ctl1stp1 ctl1stp0 C ctl1st9 ctl1st8 ctl1st7 ctl1st6 ctl1st5 ctl1st4 ctl1st3 ctl1st2 ctl1st1 ctl1st0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved tft_ctl1 pulse stop offset tft_ctl1 pulse width = (ctl1stp - ctl1st +1) ts reserved tft_ctl1 pulse start offset C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. ? 2: for hr-tft this register is enabled when preset = 1. 0 when being read. ( ? 2) 00301a44 (w) tft_ctl1 pulse register (plcdc_tc1) C stop offset = ctl1stp + 1 [pixels] C start offset = ctl1st [pixels] note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:26] reserved d[25:16] ctl1stp[9:0]: tft_ctl1 pulse stop offset setup bits specifies the tft_ctl 1 (cls) pulse end position with an offset value (in pixel clock units) from the fpline pulse start position. (default: 0x0) d[15:10] reserved d[9:0] ctl1st[9:0]: tft_ctl1 pulse start offset setup bits specifies the tft_ctl 1 (cls) pulse start position with an offset value (in pixel clock units) from the fpline pulse start position. (default: 0x0) setting this register configures the tft_ctl 1 pulse width to ctl 1 stp[ 9 : 0 ] - ctl 1 st[ 9 : 0 ] + 1 [ts]. to enable this register, set ctl 1ctl (d3/0x301a40) and preset (d2/0x301a40) to 1.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-48 epson s1c33e08 technical manual 0x301a48: tft_ctl0 pulse register (plcdc_tc0) name address register name bit function setting init. r/w remarks C ctl0stp9 ctl0stp8 ctl0stp7 ctl0stp6 ctl0stp5 ctl0stp4 ctl0stp3 ctl0stp2 ctl0stp1 ctl0stp0 C ctl0st9 ctl0st8 ctl0st7 ctl0st6 ctl0st5 ctl0st4 ctl0st3 ctl0st2 ctl0st1 ctl0st0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved tft_ctl0 pulse stop offset tft_ctl0 pulse width = (ctl0stp - ctl0st +1) ts reserved tft_ctl0 pulse start offset C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. ? 2: for hr-tft this register is enabled when preset = 1. 0 when being read. ( ? 2) 00301a48 (w) tft_ctl0 pulse register (plcdc_tc0) C stop offset = ctl0stp + 1 [pixels] C start offset = ctl0st [pixels] note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:26] reserved d[25:16] ctl0stp[9:0]: tft_ctl0 pulse stop offset setup bits specifies the tft_ctl 0 (ps) pulse end position with an offset value (in pixel clock units) from the fpline pulse start position. (default: 0x0) d[15:10] reserved d[9:0] ctl0st[9:0]: tft_ctl0 pulse start offset setup bits specifies the tft_ctl 0 (ps) pulse start position with an offset value (in pixel clock units) from the fpline pulse start position. (default: 0x0) setting this register configures the tft_ctl 0 pulse width to ctl 0 stp[ 9 : 0 ] - ctl 0 st[ 9 : 0 ] + 1 [ts]. to enable this register, set preset (d 2/0x301a40) to 1.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-49 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a4c: tft_ctl2 register (plcdc_tc2) name address register name bit function setting init. r/w remarks C ctl2dly9 ctl2dly8 ctl2dly7 ctl2dly6 ctl2dly5 ctl2dly4 ctl2dly3 ctl2dly2 ctl2dly1 ctl2dly0 d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved tft_ctl2 delay C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. for hr-tft this register is enabled when preset = 1. 00301a4c (w) tft_ctl2 register (plcdc_tc2) C delay = ctl2dly [pixels] note : this register is used only for setting hr-tft panel parameters. when using an stn panel, leave this register unaltered as 0x0. d[31:10] reserved d[9:0] ctl2dly[9:0]: tft_ctl2 delay setup bits sets the delay time (in pixel clock units) from the fpline pulse start position until the tft_ctl 2 sig - nal toggles. (default: 0x0) to enable this register, set preset (d 2/0x301a40) to 1.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-50 epson s1c33e08 technical manual 0x301a60: lcdc display mode register (plcdc_dmd) name address register name bit function setting init. r/w remarks C C C C tftsel color fpsmask C dwd1 dwd0 swinv blank C frmrpt dithen C lutpass C bpp2 bpp1 bpp0 d31 d30 d29 d28 d27 d26 d25 d24 d23C8 d7 d6 d5 d4 d3 d2C0 hr-tft panel selection color/mono selection fpshift mask enable reserved lcd panel data width software video invert display blank enable reserved frame repeat for el panel dither mode enable reserved lut bypass mode reserved bit-per-pixel select 0 0 0 C 0 0 0 0 C 0 0 C 0 C 0 0 0 r/w r/w r/w C r/w r/w r/w C r/w r/w C r/w C r/w 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301a60 (w) 1 blank 0 normal lcdc display mode register (plcdc_dmd) 1 inverted 0 normal 1 color 0 mono 1 hr-tft 0 stn dwd[1:0] 11 10 01 00 data format 8-bit (format2) reserved 8-bit (format1) 4-bit 1 enabled 0 disabled 1 repeated 0 not repeated bpp[2:0] 101 100 011 010 001 000 other bpp (color/gray) 16 bpp (64kc) 12 bpp (4kc) 8 bpp (256c) 4 bpp (16c/16gr) 2 bpp (4c/4gr) 1 bpp (2c/2gr) reserved 1 enabled 0 disabled 1 bypassed 0 used d31 tftsel: hr-tft panel select bit selects the type of connected lcd panel (stn or hr-tft). 1 (r/w): generic hr-tft panel 0 (r/w): stn panel (default) when generic hr-tft panel is selected, color (d 30 ) and dwd[1:0 ] (d[27:26 ]) settings are dis - abled. d30 color: color/mono panel select bit selects the type of connected lcd panel (color or monochrome). 1 (r/w): color panel 0 (r/w): monochrome panel (default) d29 fpsmask: fpshift mask enable bit enables the fpshift mask (effective only for stn monochrome lcd panels and hr-tft panels). 1 (r/w): enable 0 (r/w): disable (default) when fpsmask is set to 1 , the fpshift signal is masked and is not output during the non-display period. when fpsmask is set to 0 , the fpshift signal is output even during the non-display period. this setting is effective only for stn monochrome lcd panels (color = 0 ) and hr-tft panels. when an stn color lcd panel is used, the fpshift signal is always masked regardless of the setting of this bit. d28 reserved
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-51 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 d[27:26] dwd[1:0]: lcd panel data width select bits selects the lcd panel s data width and format. table viii. 1.9.3 selection of lcd panels color C 1 0 d wd1 C 1 1 0 0 1 1 0 0 lcd panel 12-bit gener ic hr-tft lcd color single 8-bit passiv e lcd fo r mat 2 reser ve d color single 8-bit passiv e lcd fo r mat 1 color single 4-bit passiv e lcd reser ve d reser ve d mono single 8-bit passiv e lcd mono single 4-bit passiv e lcd d wd0 C 1 0 1 0 1 0 1 0 tftsel 1 0 d25 swinv: software video invert bit inverts the display. 1 (r/w): invert 0 (r/w): normal display (default) when swinv is set to 1 , the display on the lcd panel is inverted (displayed in inverse video). when swinv is set to 0 , normal display is maintained. inverse operation is applied to output of the look-up tables, and does not affect the display memory. the software video invert function is effective only for stn panels and it does not support hr-tft panels. d24 blank: display blank enable bit clears the display (entire screen turned blank). 1 (r/w): blank 0 (r/w): normal display (default) when blank is set to 0 , data in the display memory is displayed on the lcd panel. when blank is set to 1 , all fpdat signals are dropped low (when swinv = 0 ) or high (when swinv = 1 ) to clear the display. this setting does not affect the display memory. this function is effective for both stn and hr-tft panels. d[23:8] reserved d7 frmrpt: frame repeat for el panel bit selects whether to repeat the frame-rate modulation pattern (effective only for el panels). 1 (r/w): repeated 0 (r/w): not repeated (default) when frmrpt is set to 1 , the internal 19 -bit frame counter is enabled and starts counting the number of frames. each time this counter overflows ( 0x40000 0 ), the frame-rate modulation pattern is re - peated. when frmrpt is set to 0 , the counter is disabled and the frame-rate modulation pattern is not repeated. d6 dithen: dither mode enable bit enables or disables dither mode. 1 (r/w): dither mode 0 (r/w): normal mode (default) when dithen is set to 1 , a maximum of 64 k colors in 16 bpp mode will be generated. setting dithen to 0 allows use of a maximum of 4k colors. d5 reserved
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-52 epson s1c33e08 technical manual d4 lutpass: lut bypass mode select bit selects whether the look-up table is bypassed. 1 (r/w): bypassed 0 (r/w): used (default) when lutpass is set to 1 , the look-up table is bypassed and the pixel data in the display memory represents the display data to be sent to the lcd panel. when lutpass is set to 0 , the look-up table is used to convert pixel data in the display memory into lcd interface data. in 1-, 2-, 4-, and 16-bpp color mode, this bit must be set to 1 as the look-up table is not used. d3 reserved d[2:0] bpp[2:0]: bit-per-pixel select bits selects display mode (bpp mode). the contents of selection, including that of color (d 30 ), are listed in table viii. 1.9.4. table viii. 1.9.4 specification of display modes bpp1 1 0 0 1 1 0 0 monochr ome (color = 0) reser ve d reser ve d reser ve d reser ve d 4 bpp , 16 gra y le v els 2 bpp , 4 gra y le v els 1 bpp , 2 gra y le v els color (color = 1), stn reser ve d 16 bpp , 64k colors 12 bpp , 4k colors 8 bpp , 256 colors reser ve d reser ve d reser ve d displa y mode bpp0 ? 1 0 1 0 1 0 color (color = 1), tft reser ve d reser ve d 12 bpp , 4k colors 8 bpp , 256 colors 4 bpp , 16 colors 2 bpp , 4 colors 1 bpp , 2 colors bpp2 1 1 1 0 0 0 0 (def ault: 0b000)
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-53 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a64: iram select register (plcdc_iram) name address register name bit function setting init. r/w remarks C C iram d31C1 d0 reserved iram assignment C 0 C r/w 0 when being read. 00301a64 (w) iram select register (plcdc_iram) 1 a0ram 0 ivram d[31:1] reserved d0 iram: iram assignment bit selects whether the 12 k-byte ivram is used as a vram or a general-purpose ram. 1 (r/w): a0ram 0 (r/w): ivram (default) the ivram is located at 0x80000 to 0x82 fff in area 3 by default and it can be used as a vram. when the ivram is not used as a vram, it can be located in area 0 as a general-purpose ram by set - ting iram to 1.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-54 epson s1c33e08 technical manual 0x301a70: main window display start address register (plcdc_madd) name address register name bit function setting init. r/w remarks 0x0 to 0xfffffffc mwadr31 mwadr30 | mwadr1 mwadr0 d31 d30 | d1 d0 main window start address mwadr31 = msb mwadr0 = lsb 0x0 r/w 00301a70 (w) main window display start address register (plcdc_madd) d[31:0] mwadr[31:0]: main window start address sets the main window display start address. (default: 0x0) note that a word boundary address (a[ 1:0 ] = 0b00 ) in the ivram or external sdram must be speci - fied to this register.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-55 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a74: main window line address offset register (plcdc_mladd) name address register name bit function setting init. r/w remarks C mwladr9 mwladr8 mwladr7 mwladr6 mwladr5 mwladr4 mwladr3 mwladr2 mwladr1 mwladr0 d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved main window line address offset C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. 00301a74 (w) main window line address offset register (plcdc_mladd) C main window width (pixels) bpp/32 d[31:10] reserved d[9:0] mwladr[9:0]: main window line address offset bits sets the line address offset for displaying the main window. (default: 0x0) the s 1c33e08 lcdc manipulates display data in units of words. therefore, the image width (number of pixels) must be a multiple of ( 32 bits bpp). the line address offset is the number of words corre - sponding to the image width and it should be specified in the following cases: 1 . when the picture-in-picture plus function is used (when a sub-window is displayed) 2 . when the lcd panel horizontal resolution is not a multiple of (32 bits bpp) the line address offset is calculated as follows: main window line address offset = main window width in pixels bpp / 32 for example, to realize the virtual screen with a 640 -pixel width, set mwladr[9:0 ] as follows: example 1) mwladr[9:0] = 640 8 / 32 = 160 [words] (in 8-bpp mode) example 2) mwladr[9:0] = 640 1 / 32 = 20 [words] (in 1-bpp mode) if the calculated value has a decimal fraction it must be rounded up. for example, if the lcd width and image width are 240 pixels in 1-bpp mode, example 3) mwladr[9:0] = 240 1 / 32 = 7.5 [words] in this case, mwladr[ 9:0 ] must be set to 8 . furthermore, the image must be prepared in 256 (8 32) pixels wide. for details, see section viii. 1.6.2, setting the display start address and line address offset.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-56 epson s1c33e08 technical manual 0x301a80: sub-window display start address register (plcdc_sadd) name address register name bit function setting init. r/w remarks 0x0 to 0xfffffffc swadr31 swadr30 | swadr1 swadr0 d31 d30 | d1 d0 sub-window start address swadr31 = msb swadr0 = lsb 0x0 r/w 00301a80 (w) sub-window display start address register (plcdc_sadd) d[31:0] swadr[31:0]: sub-window start address sets the sub-window display start address. (default: 0x0) note that a word boundary address (a[ 1:0 ] = 0b00 ) in the ivram or external sdram must be speci - fied to this register.
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-57 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301a88: sub-window start position register (plcdc_ssp) name address register name bit function setting init. r/w remarks pipen C pipyst9 pipyst8 pipyst7 pipyst6 pipyst5 pipyst4 pipyst3 pipyst2 pipyst1 pipyst0 C pipxst9 pipxst8 pipxst7 pipxst6 pipxst5 pipxst4 pipxst3 pipxst2 pipxst1 pipxst0 d31 d30C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pip sub-window enable reserved sub-window vertical (y) start position reserved sub-window horizontal (x) start position 0 C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 r/w C r/w C r/w 0 when being read. ? 3: this register is enabled when pipen = 1. 0 when being read. ( ? 3) 00301a88 (w) sub-window start position register (plcdc_ssp) C y start position = pipyst (lines) from the origin C x start position = pipxst (pixels) from the origin (word units) 0 1 enabled disabled d31 pipen: pip sub-window enable bit enables the picture-in-picture plus function to display the s ub-window in the main window. 1 (r/w): enable 0 (r/w): disable (default) configure the sub-window using the registers at 0x301a80 to 0x301a8c before setting pipen to 1. d[30:26] reserved d[25:16] pipyst[9:0]: sub-window vertical (y) start position bits sets the sub-window vertical display start position. (default: 0x0) specify the number of lines from the lcd panel origin point to the upper left corner of the sub-window in 1-line increments. pipyst[ 9:0 ] = y start [lines] for example, to specify the sub-window vertical start position as 60 lines, set pipyst[9:0] to 60. d[15:10] reserved d[9:0] pipxst[9:0]: sub-window horizontal (x) start position bits sets the sub-window horizontal display start position. (default: 0x0) convert the number of pixels from the lcd panel origin point to the upper left corner of the sub-win - dow into the number of data words according to the bpp mode and set it to these bits. pipxst[ 9:0] = x start pixels bpp 32 [words] it can be specified in ( 32 bits bpp) pixel increments. 1-bpp mode: 1 -word = 32 -pixel units 2-bpp mode: 1 -word = 16 -pixel units 4-bpp mode: 1 -word = 8 -pixel units 8-bpp mode: 1 -word = 4 -pixel units 12-bpp mode: 3 -word = 8 -pixel units (because the value must be an integer) 16-bpp mode: 1 -word = 2 -pixel units for example, to specify the sub-window horizontal start position as 80 pixels in 8 -bpp mode, set pipxst[9:0] to 20.
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-58 epson s1c33e08 technical manual 0x301a8c: sub-window end position register (plcdc_sep) name address register name bit function setting init. r/w remarks C pipyend9 pipyend8 pipyend7 pipyend6 pipyend5 pipyend4 pipyend3 pipyend2 pipyend1 pipyend0 C pipxend9 pipxend8 pipxend7 pipxend6 pipxend5 pipxend4 pipxend3 pipxend2 pipxend1 pipxend0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved sub-window vertical (y) end position reserved sub-window horizontal (x) end position C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. ? 3: this register is enabled when pipen = 1. 0 when being read. ( ? 3) 00301a8c (w) sub-window end position register (plcdc_sep) C y end position = pipyend (lines) from the origin C x end position = pipxend (pixels) from the origin (word units) d[31:26] reserved d[25:16] pipyend[9:0]: sub-window vertical (y) end position bits sets the sub-window vertical display end position. (default: 0x0) specify the number of lines from the lcd panel origin point to the lower right corner of the sub-win - dow in 1-line increments. pipyend[ 9:0 ] = y end - 1 [lines] d[15:10] reserved d[9:0] pipxend[9:0]: sub-window horizontal (x) end position bits sets the sub-window horizontal display end position. (default: 0x0) convert the number of pixels from the lcd panel origin point to the lower right corner of the sub- window into the number of data words according to the bpp mode and set it to these bits. pipxend[ 9:0] = x end pixels bpp 32 - 1 [words]
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-59 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301aa0: look-up table data register 0 (plcdc_lut_03) name address register name bit function setting init. r/w remarks lut35 lut34 lut33 lut32 lut31 lut30 C lut25 lut24 lut23 lut22 lut21 lut20 C lut15 lut14 lut13 lut12 lut11 lut10 C lut05 lut04 lut03 lut02 lut01 lut00 C d31 d30 d29 d28 d27 d26 d25C24 d23 d22 d21 d20 d19 d18 d17C16 d15 d14 d13 d12 d11 d10 d9C8 d7 d6 d5 d4 d3 d2 d1C0 look-up table entry 3 data reserved look-up table entry 2 data reserved look-up table entry 1 data reserved look-up table entry 0 data reserved 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w C r/w C r/w C r/w C 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301aa0 (w) look-up table data register 0 (plcdc_lut_03) 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C this register is used to set data to the look-up table entries 3 to 0. data written to this register is set to the entries 3 to 0 in the red, green, and blue look-up tables simultaneously. also this register allows reading of the currently set look-up table data. d[31:26] lut3[5:0]: look-up table entry 3 data set the 6-bit data for the look-up table entry 3 . (default: 0x0) d[25:24] reserved d[23:18] lut2[5:0]: look-up table entry 2 data set the 6-bit data for the look-up table entry 2 . (default: 0x0) d[17:16] reserved d[15:10] lut1[5:0]: look-up table entry 1 data set the 6-bit data for the look-up table entry 1 . (default: 0x0) d[9:8] reserved d[7:2] lut0[5:0]: look-up table entry 0 data set the 6-bit data for the look-up table entry 0 . (default: 0x0) d[1:0] reserved
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-60 epson s1c33e08 technical manual 0x301aa4: look-up table data register 1 (plcdc_lut_47) name address register name bit function setting init. r/w remarks lut75 lut74 lut73 lut72 lut71 lut70 C lut65 lut64 lut63 lut62 lut61 lut60 C lut55 lut54 lut53 lut52 lut51 lut50 C lut45 lut44 lut43 lut42 lut41 lut40 C d31 d30 d29 d28 d27 d26 d25C24 d23 d22 d21 d20 d19 d18 d17C16 d15 d14 d13 d12 d11 d10 d9C8 d7 d6 d5 d4 d3 d2 d1C0 look-up table entry 7 data reserved look-up table entry 6 data reserved look-up table entry 5 data reserved look-up table entry 4 data reserved 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w C r/w C r/w C r/w C 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301aa4 (w) look-up table data register 1 (plcdc_lut_47) 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C this register is used to set data to the look-up table entries 7 to 4. data written to this register is set to the entries 7 to 4 in the red, green, and blue look-up tables simultaneously. also this register allows reading of the currently set look-up table data. d[31:26] lut7[5:0]: look-up table entry 7 data set the 6-bit data for the look-up table entry 7 . (default: 0x0) d[25:24] reserved d[23:18] lut6[5:0]: look-up table entry 6 data set the 6-bit data for the look-up table entry 6 . (default: 0x0) d[17:16] reserved d[15:10] lut5[5:0]: look-up table entry 5 data set the 6-bit data for the look-up table entry 5 . (default: 0x0) d[9:8] reserved d[7:2] lut4[5:0]: look-up table entry 4 data set the 6-bit data for the look-up table entry 4 . (default: 0x0) d[1:0] reserved
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-61 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x301aa8: look-up table data register 2 (plcdc_lut_8b) name address register name bit function setting init. r/w remarks lutb5 lutb4 lutb3 lutb2 lutb1 lutb0 C luta5 luta4 luta3 luta2 luta1 luta0 C lut95 lut94 lut93 lut92 lut91 lut90 C lut85 lut84 lut83 lut82 lut81 lut80 C d31 d30 d29 d28 d27 d26 d25C24 d23 d22 d21 d20 d19 d18 d17C16 d15 d14 d13 d12 d11 d10 d9C8 d7 d6 d5 d4 d3 d2 d1C0 look-up table entry 11 data reserved look-up table entry 10 data reserved look-up table entry 9 data reserved look-up table entry 8 data reserved 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w C r/w C r/w C r/w C 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301aa8 (w) look-up table data register 2 (plcdc_lut_8b) 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C this register is used to set data to the look-up table entries 11 to 8. data written to this register is set to the entries 11 to 8 in the red, green, and blue look-up tables simultaneously. also this register allows reading of the currently set look-up table data. d[31:26] lutb[5:0]: look-up table entry 11 data set the 6-bit data for the look-up table entry 11 . (default: 0x0) d[25:24] reserved d[23:18] luta[5:0]: look-up table entry 10 data set the 6-bit data for the look-up table entry 10 . (default: 0x0) d[17:16] reserved d[15:10] lut9[5:0]: look-up table entry 9 data set the 6-bit data for the look-up table entry 9 . (default: 0x0) d[9:8] reserved d[7:2] lut8[5:0]: look-up table entry 8 data set the 6-bit data for the look-up table entry 8 . (default: 0x0) d[1:0] reserved
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-62 epson s1c33e08 technical manual 0x301aac: look-up table data register 3 (plcdc_lut_cf) name address register name bit function setting init. r/w remarks lutf5 lutf4 lutf3 lutf2 lutf1 lutf0 C lute5 lute4 lute3 lute2 lute1 lute0 C lutd5 lutd4 lutd3 lutd2 lutd1 lutd0 C lutc5 lutc4 lutc3 lutc2 lutc1 lutc0 C d31 d30 d29 d28 d27 d26 d25C24 d23 d22 d21 d20 d19 d18 d17C16 d15 d14 d13 d12 d11 d10 d9C8 d7 d6 d5 d4 d3 d2 d1C0 look-up table entry 15 data reserved look-up table entry 14 data reserved look-up table entry 13 data reserved look-up table entry 12 data reserved 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w C r/w C r/w C r/w C 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301aac (w) look-up table data register 3 (plcdc_lut_cf) 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C this register is used to set data to the look-up table entries 15 to 12. data written to this register is set to the entries 15 to 12 in the red, green, and blue look-up tables simultaneously. also this register allows reading of the currently set look-up table data. d[31:26] lutf[5:0]: look-up table entry 15 data set the 6-bit data for the look-up table entry 15 . (default: 0x0) d[25:24] reserved d[23:18] lute[5:0]: look-up table entry 14 data set the 6-bit data for the look-up table entry 14 . (default: 0x0) d[17:16] reserved d[15:10] lutd[5:0]: look-up table entry 13 data set the 6-bit data for the look-up table entry 13 . (default: 0x0) d[9:8] reserved d[7:2] lutc[5:0]: look-up table entry 12 data set the 6-bit data for the look-up table entry 12 . (default: 0x0) d[1:0] reserved
viii peripheral modules 6 (lcd): lcd controller (lcdc) s1c33e08 technical manual epson viii-1-63 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.1.10 precautions ? the lcdc clock supply cannot be stopped while the lcd displays a screen. before the lcdc clock supply can be stopped, the lcdc must enter power save mode. ? when using an stn panel, the registers for setting the hr-tft timing parameters must be set to 0x0. ? display addresses and positions are specified with a word boundary address or in word units, therefore the main window line address offset register (d[ 9:0]/0x301a74 ) must be set to a multiple of (32 bits bpp). depend - ing on the lcd horizontal resolution and the bpp mode selected, it may be necessary to reserve a larger image area than the lcd panel resolution and set the appropriate line address offset even if the application does not need a lager image than the lcd panel to be displayed. for example, if the lcd width and image width are 240 pixels in 1-bpp mode, line address offset = 240 1 / 32 = 7.5 [words] in this case, mwladr[ 9:0 ] (d[9:0]/0x301a74 ) must be set to 8 . furthermore, the image must be prepared in 256 (8 32 ) pixels wide. ? mwladr[9:0] : main window line address offset bits in the main window line address offset register (d[9:0]/0x301a74) ? when a tft lcd panel is used with the s 1 c 33 e 08 tft lcd interface selected (tftsel (d 31 / 0 x 301 a 60 ) = 1 ), the vndpf flag (d 7/0x301a04 ) may be fixed at 1 (vertical non-display period) in some rare cases depending on the timing. this means that the flag cannot normally indicate the vertical display and vertical non-display periods in the tft interface. ? tftsel : hr-tft panel select bit in the lcdc display mode register (d31/0x301a60) ? vndpf : vertical display status flag in the status and power save configuration register (d7/0x301a04) how to solve this problem for example, when the application needs to know a vertical non-display period to perform the following process - ing (switching the system clock in a vertical non-display period): (1 ) the system clock is 60 mhz (using the pll) and the tft lcd is displaying. (2 ) the program detects a vertical non-display period and switches the system clock to 12 mhz while keeping the tft lcd displayed. (3 ) the program sets the cpu to enter halt mode. to realize the above processing, use the following procedure to detect a vertical non-display period: (1 ) the system clock is 60 mhz (using the pll) and the tft lcd is displaying. (2 ) set the clock control register of a 16 -bit timer. (3 ) set the comparison data b setup register of the 16 -bit timer. (4 ) clear the 16-bit timer compare-match b interrupt flag. (5 ) detect the fpframe signal by reading the data register of the i/o port that has been configured for the fpframe output and run the 16 -bit timer when the fpframe signal is asserted (high level is detected when fpframe is configured to high active, or low level is detected when it is configured to low active). (6 ) detect that the 16 -bit timer compare-match b interrupt flag is set (it means that a vertical non-display pe - riod is detected). (7 ) switch the system clock to 12 mhz. (8 ) enter halt mode. use the following equation to calculate the comparison data b to be set to the 16-bit timer: 1 comparison data b = ((vdps + vdp) ht - vps) f t16 f fpshift f fpshift : lcdc fpshift clock frequency [hz] vdps: vertical display period start position (vdps = vdpscnt[ 9:0 ] [lines]) vdpscnt[9:0 ]: d[9:0]/0x301a24 vdp: vertical display period (vdp = vdpcnt[ 9:0] +1 [lines]) vdpcnt[9:0 ]: d[9:0]/0x301a14 ht: horizontal total period (ht = (htcnt[ 6:0] +1) 8 [ts]) htcnt[6:0 ]: d[22:16]/0x301a10 vps : vertical sync pulse start position (vps = fpfst[9:0] ht + fpfsto[9:0] [ts]) fpfst[9:0 ]: d[25:16]/0x301a2c fpfsto[ 9:0 ]: d[9:0]/0x301a30 f t16 : 16-bit timer x clock frequency [hz]
viii peripheral modules 6 (lcd): lcd controller (lcdc) viii-1-64 epson s1c33e08 technical manual ? the lcdc does not support the frame interrupt (inten (d0/0x301a00 ), intf (d31/0x301a04 )) when tft interface is selected (tftsel (d 31/0x301a60) = 1). ? intf : frame interrupt flag in the status and power save configuration register (d31/0x301a04) ? inten : frame interrupt enable bit in the frame interrupt register (d0/0x301a00)
viii peripheral modules 6 (lcd): ivram and ivram arbiter s1c33e08 technical manual epson viii-2-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.2 ivram and ivram arbiter viii.2.1 ivram the s 1c33e08 has a built-in 12 k-byte ram (ivram) to be used as a video ram for the lcdc, which is located at 0x80000 to 0x82 fff in area 3 by default. when the lcdc is not used or when an external sdram is used as a video ram, ivram can be moved to area 0 to use as a general-purpose high-speed ram. the lcdc provides the control bit iram (d 0/0x301a64 ) for this switch over. setting iram (d0/0x3001a64 ) to 1 configures the ram as a general-purpose ram in area 0; setting to 0 configures it as a vram in area 3. ? iram : iram assignment bit in the iram select register (d0/0x301a64) table viii. 2.1.1 lists the differences in the ivram function depending on the allocated areas. table viii. 2.1.1 ivram function in different areas item location accessing from the lcdc accessing from the cpu accessing by dma use f or vram program ex ecution stor ing general-pur pose data w ait cycle iram = 0 (ivram) area 3, 0x80000C0x82fff enab led (via ivram arbiter) 32-bit read only enab led (via ivram arbiter) 8, 16, 32-bit read/wr ite enab led (via ivram arbiter) enab led disab led enab led 2 cycles min. iram = 1 (general-purpose ram) area 0, 0x2000C0x4fff * disab led enab led (direct) 8, 16, 32-bit read/wr ite disab led disab led enab led enab led 0 cycles min. ? can be used as a 20kb ram with a0ram when using ivram as a display memory, the memory size required for a screen depends on the screen size and bpp mode (shades of gray/colors). it can be expressed by the following equation: screen data size = h_pixel v_pixel bpp / 32 [words] (the fractional portion of the number must be rounded up.) h_pixel: number of horizontal pixels v_pixel: number of vertical pixels bpp: number of bits per pixel ( 1, 2, 4, 8, 12, 16) table viii. 2.1.2 ivram usage samples panel size 320 240 240 180 160 160 color depth 1 bpp 1 bpp 2 bpp 1 bpp 2 bpp data size 2400 words (9600 b ytes) 1440 words (5760 b ytes) ? 2 2700 words (10800 b ytes) 800 words (3200 b ytes) 1600 words (6400 b ytes) used ivram range ? 1 0x80000C0x8257f 0x80000C0x8167f 0x80000C0x82a2f 0x80000C0x80c7f 0x80000C0x818ff ? 1 ? 2 these e xamples assume that ivram is used from the beginning. the displa y star t address can be changed using an lcdc register , note , ho we ve r, that a word boundar y address must be specified. the image width must be set in word units (= multiple of 32/bpp pix els). a 240-pix el of image width in 1-bpp mode cannot be specified in word units . in this case , the image area must be allocated to a 256-pix el width (the lcd can displa y images with a 240-pix el width).
viii peripheral modules 6 (lcd): ivram and ivram arbiter viii-2-2 epson s1c33e08 technical manual viii.2.2 ivram arbiter the ivram arbiter circuit arbitrates between the vram data read request from the lcdc and the access request from the cpu. lcdc lcdc cache ivram arbiter ivram (12 kb) lcdc_ahb c33 pe core dma cpu_ahb < figure viii. 2.2.1 ivram arbiter when the cpu (or dma) and lcdc request to access ivram at the same time or the cpu (or dma) requests to access ivram that is being accessed by the lcdc, the ivram arbiter gives high priority to the lcdc. the ivram arbiter obtains display data requested from the lcdc in burst reading. therefore, the cpu is placed in a wait state until the lcdc cache becomes full upon completion of burst reading.
viii peripheral modules 6 (lcd): ivram and ivram arbiter s1c33e08 technical manual epson viii-2-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 viii.2.3 ivram arbiter operating clock the ivram arbiter use the ivram_arb_clk clock (= mclk) generated by the cmu as the operating clock. controlling the supply of the operating clock ivram_arb_clk is supplied to the ivram arbiter with default settings. it can be turned off using ivramarb_cke (d 19/0x301b04 ) to reduce the amount of power consumed on the chip if the ivram arbi - ter is not used. ? ivramarb_cke : ivram arbiter clock control bit in the gated clock control register 1 (d19/0x301b04) setting ivramarb_cke (d 19/0x301b04 ) to 0 (1 by default) turns off the clock supply to the ivram arbi - ter. for details on how to set and control the clock, refer to section iii. 1, clock management unit (cmu). note : the gated clock control register 1 (0x301b04) is write-protected. write protection of this and other cmu control registers at addresses 0x301b00 to 0x301b14 to be rewritten must be re - moved by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 could cause the system to operate erratically, make sure the data set in the clock control protect register (0x301b24) is other than 0x96, unless re - writing said registers. clock state in standby mode the clock supply to the ivram arbiter stops depending on type of standby mode. halt mode: the operating clock is supplied the same way as in normal mode. sleep mode: the operating clock supply stops. therefore, the ivram arbiter also stops operating in sleep mode .
viii peripheral modules 6 (lcd): ivram and ivram arbiter viii-2-4 epson s1c33e08 technical manual viii.2.4 details of the control register the following describes the iram select register. the iram select register is mapped in the 32 -bit device area, and can be accessed only in units of words. note : when setting the iram select register, be sure to write a 0, and not a 1, for all reserved bits. 0x301a64: iram select register (plcdc_iram) name address register name bit function setting init. r/w remarks C C iram d31C1 d0 reserved iram assignment C 0 C r/w 0 when being read. 00301a64 (w) iram select register (plcdc_iram) 1 a0ram 0 ivram d[31:1] reserved d0 iram: iram assignment bit selects whether the 12 k-byte ivram is used as a vram or a general-purpose ram. 1 (r/w): a0ram 0 (r/w): ivram (default) the ivram is located at 0x80000 to 0x82 fff in area 3 by default and it can be used as a vram. when the ivram is not used as a vram, it can be located in area 0 as a general-purpose ram by set - ting iram to 1.
i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 s1c33e08 technical manual ix peripheral m odules 7 ( usb )

ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ix.1 usb function controller (usb) ix.1.1 outline of the usb function controller the s 1c33e08 has a built-in usb function controller that supports the full-speed mode defined in the usb2.0 specification. the features are shown below. ? supports transfer at fs (12 mbps). ? supports control, bulk, isochronous and interrupt transfers. ? supports four general-purpose endpoints and endpoint 0. ? incorporate 1kb programmable fifo for endpoints. ? equipped with a general-purpose dma port. ? supports asynchronous procedures. supports a slave configuration. can be used with a bus width of 8 bits. ? inputs 48 mhz clock. ? supports snooze mode. figure ix.1.1.1 shows the block diagram of the usb function controller. usbdm usbdp bridge usb part to port 9 input interrupt circuit pdreq pdack pdwr pdrd ? 1 ? 1 ? 1 ? 1 snooze reset atpgen usbvbus fifo (1kb) decoder fifo controller sie port interface controller cpu interface controller test mux usbio ? 1 the pdreq, pdack, pdwr and pdrd signals level must be configured as "active high". add[5:0] #ce6 #rd #wrl int_usb #int figure ix.1.1.1 usb function controller block diagram
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-2 epson s1c33e08 technical manual serial interface engine (sie) the sie manages transactions and generates packets. it also controls bus events such as suspend, resume and reset operations. fifo this is a 1 kb buffer for endpoints. fifo controller this controller performs fifo sram address management (user-programmable), timing generation, arbitration and more. port interface controller this controller performs asynchronous handshakes. cpu interface controller this controller controls timings of the cpu interface and enables register access. test mux switches the operational mode (test mode) using the input signa l. ix.1.2 pins for the usb interface table ix. 1.2.1 list the pins used for the usb interface. table ix. 1.2.1 usb interface pins i/o i/o i/o i function usb d+ pin usb d- pin usb vbus pin. allo ws input of 5 v. pin name usbdp usbdm usbvbus
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ix.1.3 usb operating clocks and dma registers ix.1.3.1 controlling the usb clocks the cmu provides the clock paths with a control bit shown below for the usb module. the clock supply turns on when the control bit is set to 1 and it turns off when the control bit is set to 0. (1 ) usb clock (usb_clk) this clock (osc 3 = 48 mhz) is used for the usb interface module. usb_cke (d8/0x301b00 ) is used for clock supply control (default: off). (2 ) control register clock (usbsapb_clk) this clock (mclk) is used to control the usb registers located in area 6 . this clock is required for accessing the usb registers and the dma area, and it can be stopped otherwise. usbsapb_cke (d 9 / 0 x 301 b 00 ) is used for clock supply control (default: off). note : the gated clock control register 0 (0x301b00) is write-protected. to rewrite this register and other cmu control registers at addresses 0x301b00 to 0x301b14, write protection must be removed by writing 0x96 to the clock control protect register (0x301b24). since unnecessary rewrites to addresses 0x301b00 to 0x301b14 may cause the system to operate erratically, make sure that data set in the clock control protect register (0x301b24) is other than 0x96 unless rewriting said registers. ix.1.3.2 setting the misc register 1 . usbwt[2:0] (d[2:0 ])/usb wait control register (0x300012) usbwt[ 2:0 ] (d[2:0]/0x300012 ) used to set the number of wait cycles to be inserted when accessing the usb registers. table ix. 1.3.2.1 number of wait cycles during usb access usbwt2 1 1 1 1 0 0 0 0 usbwt1 1 1 0 0 1 1 0 0 usbwt0 1 0 1 0 1 0 1 0 number of wait cyc les (in units of mclk cyc les) 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles 1 cycle 0 cycles mclk c loc k frequenc y less than 60 mhz less than 56 mhz less than 45 mhz less than 36 mhz less than 24 mhz less than 16 mhz less than 8 mhz less than 8 mhz (default: 0b111 = 7 cycles) the number of wait cycles should be set according to the mclk clock frequency. 2 . usbsnz (d5 )/usb wait control register (0x300012) = 0 this disables the usb snooze control. the osc 3 oscillator circuit must be turned on before the usb function controller can be used. refer to iii.1 clock management unit (cmu) and iii.4 misc registers for details of the clock control.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-4 epson s1c33e08 technical manual ix.1.3.3 setting the itc and hsdma controllers the usb function controller supports data transfer using the hsdma (high-speed dma) function. therefore, the itc and the hsdma (ch. 1 ) must be set up before starting usb data transfer. this section describes how the itc and the hsdma control registers are set up. refer to iii.2 interrupt controller (itc) and ii.1 high-speed dma (hsdma) for details of the itc and the hsdma, respectively. 1 . setting the signals used for dma transfer the usb controller has the following pads used for dma data transfer and they are connected to the corresponding sramc/itc/hsdma. pdreq * (dma request interrupt signal) pdack (dma acknowledge signal) pdrd (data read signal) pdwr (data write signal) ? the pdreq signal is inverted before it is input to the itc. the active level of these signals can be selected using the usb register. set the respective control bits as follows. pdreq: pdreq_level (d 3/0x300994) = 0 (active high) pdack: pdack_level (d 2/0x300994) = 0 (active high) pdrd, pdwr: pdrdwr_level (d 1/0x300994) = 0 (active high) 2 . setting the itc dma request (pdreq) the pdreq signal used for a dma request is input to the port 9 input interrupt (fpt9 ) system. the port 9 input interrupt circuit is configured by selecting a port (signal) to be used for generating an interrupt from p 91, pdreq, p 81 , and p71 . when using the dma request/interrupt by pdreq, set spt9[1:0 ] (d[3:2]/0x3003c4) to 10 to select pdreq. this setting enables the pdreq signal to be sent to the itc as the port 9 input interrupt signal and it will be used as a trigger for hsdma ch. 1 . furthermore, sppt9 (d1/0x3003c6 ) for selecting a polarity of the fpt 9 input signal should be set to 0 (low level or falling edge) since the pdreq signal is inverted before input to the itc. the interrupt control bits (cause-of-interrupt flag, interrupt enable register, idma request register, interrupt priority register) do not affect this invocation. usb interrupt (int_usb) the usb interrupt signal (int_usb) is input to the port 10 input interrupt (fpt10 ) system. the port 10 input interrupt circuit is configured by selecting a port (signal) to be used for generating an interrupt from p92 , int_usb, p82 , and p72 . when using the dma request/interrupt by int_usb, set spta[1:0 ] (d[5:4]/ 0x3003c4 ) to 10 to select int_usb. this setting enables the int_usb signal to be sent to the itc as the port 10 input interrupt signal for requesting an interrupt. set septa (d 2 / 0 x 3003 c 7 ) = 0 and sppta (d 2 / 0 x 3003 c 6 ) = 1 to select the detection mode and polarity of the fpt10 input signal to high level.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 3 . setting the hsdma setting the address mode the hsdma circuit provides two data transfer mode: dual-address transfer and single-address transfer modes. the usb function controller supports only the dual-address mode. in this mode, a source address and a destination address for dma transfer can be specified and a dma transfer is performed in two phases. the first phase reads data at the source address into the on-chip temporary register. the second phase writes the temporary register data to the destination address. to configure hsdma ch. 1 in this mode, set dualm1 (d15/0x301132) to 1. note : do not set the hsdma ch.1 to single-address mode when using it for usb data transfer. setting the transfer mode the usb function controller supports two transfer modes, asynchronous multi-word dma transfer (slave) mode and asynchronous single-word dma transfer (slave) mode. the asynchronous multi-word dma transfer (slave) mode asserts the pdreq signal while the usb fifo contains data. the cpu cannot determine the amount of data in the fifo to be transferred in a dma transfer while the usb is sending/receiving data dynamically (since data in the fifo is increased/decreased dynamically according to the circumstances of the usb data transfer). therefore, set the usb function controller to asynchronous single-word dma transfer (slave) mode and the hsdma to single transfer mode with one byte transfer per trigger, and manage the dma transfer count with the total amount of usb transfer data. to set the hsdma into single transfer mode, set d 1 mod[1:0 ] (d[15:14 ]/0x30113 a) to 00 . in this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by datsize 1 . if data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. setting the transfer data size datsize 1 (d14/0x301136) is used to set the unit size of data to be transferred. set this bit to 0 (8 bits). setting the transfer counter in the single transfer mode, up to 24 bits of transfer count can be specified using the registers below. set the desired transfer count to these registers. blklen 1[7:0 ]: ch.1 transfer counter [7:0] (d[7:0])/hsdma ch.1 transfer counter register (0x301130) tc 1_l[7:0 ]: ch.1 transfer counter [15:8] (d[15:8])/hsdma ch.1 transfer counter register (0x301130) tc 1_h[7:0 ]: ch.1 transfer counter [23:16] (d[7:0])/hsdma ch.1 control register (0x301132) note : the transfer count thus set is decremented according to the transfers performed. if the transfer count is set to 0, it is decremented to all fs by the first transfer performed. this means that you have set the maximum value that is determined by the number of bits available. setting the source and destination addresses in dual-address mode, a source address and a destination address for dma transfer can be specified using the registers below. s1adrl[15:0 ]: ch.1 source address [15:0 ] (d[15:0 ])/hsdma ch.1 low-order source address set-up register ( 0x301134) s1adrh[11:0 ]: ch.1 source address [27:16 ] (d[11:0 ])/hsdma ch.1 high-order source address set-up register ( 0x301136) d1adrl[15:0 ]: ch.1 destination address [15:0 ] (d[15:0 ])/hsdma ch.1 low-order destination address set- up register ( 0x301138) d1adrh[11:0 ]: ch.1 destination address [27:16 ] (d[11:0 ])/hsdma ch.1 high-order destination address set-up register ( 0x30113a) note : the dma transfer address for the usb function controller must be located in area 6 (0x300a00 to 0x300aff, 256 bytes). make sure that the transfer address does not exceed the address range from 0x300a00 to 0x300aff by the address increment/decrement operation during dma transfer.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-6 epson s1c33e08 technical manual setting the address increment/decrement conditions the source and/or destination addresses can be incremented or decremented when one data transfer is completed. s 1 in[ 1 : 0 ] (d[ 13 : 12 ] 0 x 301136 ) for source address and d 1 in[ 1 : 0 ] (d[ 13 : 12 ]/ 0 x 30113 a) for destination address are used to set this condition. s1in/d1in = 00 : address fixed (default) the address is not changed by a data transfer performed. even when transferring multiple data, the transfer data is always read/write from/to the same address. s1in/d1in = 01 : address decremented the address is decremented by an amount equal to the data size set by datsize 1 when one data transfer is completed. the address that has been decremented during transfer does not return to the initial value. s1in/d1in = 10 or 11 : address incremented the address is incremented by an amount equal to the data size set by datsize 1 when one data transfer is completed. the address that has been incremented during transfer does not return to the initial value. in the single transfer mode, 10 and 11 set the same condition. selecting the dma trigger factor the hsdma trigger factor for the usb function controller is port 9 input (fpt9 ). hsd1 s[3:0 ] (d[7:4 ]/ 0x300289) must be set to 1101. by selecting a cause of interrupt with the hsdma trigger set-up register, the hsdma channel is invoked when the selected cause of interrupt occurs. the interrupt control bits (cause-of-interrupt flag, interrupt enable register, idma request register, interrupt priority register) do not affect this invocation. the cause of interrupt that invokes hsdma sets the cause-of-interrupt flag and hsdma does not reset the flag. consequently, when the dma transfer is completed (even if the transfer counter is not 0 ), an interrupt request to the cpu will be generated if the interrupt has been enabled. to generate an interrupt only when the transfer counter reaches 0, disable the interrupt by the cause of interrupt that invokes hsdma and use the hsdma transfer completion interrupt. when the selected trigger factor occurs, the trigger flag is set to 1 to invoke the hsdma channel. the hsdma starts a dma transfer if it has been enabled and the trigger flag is cleared by the hardware at the same time. this makes it possible to queue the hsdma triggers that have been generated. the trigger flag can be read and cleared using hs 3 _tf (d0/0x30113 e). by writing 1 to this bit, the set trigger flag can be cleared if the dma transfer has not been started. when this bit is read, 1 indicates that the flag is set and 0 indicates that the flag is cleared. enabling/disabling dma transfer the hsdma transfer is enabled by writing 1 to hs1 _en (d0/0x30113 c). however, the control information must always be set correctly before enabling a dma transfer. note that the control information cannot be set when hs1_en = 1 . when hs1_en is set to 0 , hsdma requests are no longer accepted. when a dma transfer is completed (transfer counter = 0), hs1_en is reset to 0 to disable the following trigger inputs.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ix.1.4 functional description this section describes the functionality of the usb function c ontroller. in the subsequent sections, the register names follow the notational convention below: * when a register for one address is referred to: register name + register. example: mainint register * when a discrete bit is referred to: register name. bit name + bit, or bit name + bit. example: mainintstat.rcvep0setup bit, or forcenak bit of the ep0 controlout register * when a register present for a specific end-point is referred to: ep x { x=0 ,a,b,c,d}register name + register, ep x { x =a,b,c,d}register name + register, and so forth. example: ep x { x=0 ,a,b,c,d}intstat register, ep x { x =a,b,c,d}control register
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-8 epson s1c33e08 technical manual ix.1.4.1 usb control end points this macro has an endpoint (ep 0 ) for control transfer and four general purpose-endpoints (epa, epb, epc, epd). endpoints, epa, epb, epc and epd can be used as endpoints for bulk- or interrupt- or isochronous-type transfer, respectively. there is no difference between bulk and interrupt transfers in terns of hardware. the macro hardware provides endpoints and manages transactions. however, it does not provide a management function in the interface defined for the usb (hereinafter referred to as usb-defined interface). the usb- defined interface should be implemented in your firmware. according to the device-specific descriptor definition, set endpoints as required and configure the usb-defined interface using an appropriate endpoint combination. besides variable control items and statuses that are controlled for each transfer operation, each endpoint has fixed basic setting items determined by the usb-defined interface. the basic setting items should be set up when initializing the chip or when the usb-defined interface is switched in response to a setinterface() request. table ix. 1.4.1.1 lists the basic setting items for the ep0 endpoint (default control pipe). the ep 0 endpoint shares the register set and fifo region between the in and out directions. for data and status stages at the ep 0 endpoint, set the data transaction direction in your firmware before executing such stages. table ix. 1.4.1.1 basic setting items for endpoint ep0 register/bit ep0maxsiz e description sets the maximum pa ck et siz e to 8, 16, 32 or 64 f or the fs-mode operation. the ep0 endpoint is assigned a region of the siz e that is set in the ep0maxsiz e register , star ting with fifo address 0. item max. pa ck et siz e table ix. 1.4.1.2 lists the basic setting items for the general-purpose endpoints (epa, epb, epc, and epd). the epa, epb, epc, and epd endpoints allow optional settings for the transaction directions and the endpoint numbers, which allows up to four discrete endpoints to be used. set up and/or enable these endpoints as appropriate according to the definitions for the usb-defined interface. table ix. 1.4.1.2 setting items for endpoints epa, epb, epc and epd register/bit ep x { x =a,b ,c ,d}config.inxout ep x { x =a,b ,c ,d}maxsiz e_h, ep x { x =a,b ,c ,d}maxsiz e_l ep x { x =a, b, c,d}config.endp ointnumber ep x { x =a,b ,c ,d}config.t ogglemode ep x { x =a,b ,c ,d}config.enendp oint ep x { x =a,b ,c ,d}star tadrs_h, ep x { x =a,b ,c ,d}star tadrs_l description sets the transf er direction f or each endpoint. sets the maximum pa ck et siz e of each endpoint to an y desired v alue between 1 and 1024 b ytes . f or endpoints that perf or m b ulk transf ers , set them to 8, 16, 32 or 64 b ytes in fs mode . sets each endpoint number to an y desired v alue between 0x1 and 0xf . sets a mode f or a toggle sequence . set it to 0 f or an endpoint that perf or ms b ulk transf er . 0: t oggles only in successful transactions . 1: t oggles f or ev er y transaction. enab les each endpoint. set it up when the usb-defined interf ace that uses the rele v ant endpoint is enab led. sets a region to be assigned to each endpoint using fifo addresses . f or a fifo region, assign a region equiv alent to the maximum pa ck et siz e set f or the rele v ant endpoint or greater . note that the siz e of the fifo region aff ects data transf er throughput. f or details of fifo region assignment, see the "fifo management" section. item tr ansaction direction max. pa ck et siz e endpoint number t oggle mode enab le endpoint fifo region
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 transaction this macro hardware executes transactions while its interface provides the firmware with utilities for executing transactions. the interface to the firmware is implemented through control and status registers as well as the interrupt signal which is asserted depending on the status. for settings that enable asserting interruption according to the status, see the section on register description. the macro issues a status to the firmware for each transaction. however, the firmware does not always have to control respective transactions. the macro references the fifo when responding to a transaction and determines if data transfer is possible based on the number of data or vacancies to automatically handle the transaction. for example, for an out endpoint, the firmware can smoothly and sequentially process out transactions by reading data from the fifo region via either the port interface (epa, epb, epc, epd) or the cpu interface (ep 0 , epa, epb, epc, epd) to create a space in the fifo region. on the other hand, for an in endpoint, the firmware can smoothly and sequentially process in transactions by writing data in the fifo region via either the port interface (epa, epb, epc, epd) or the cpu interface (ep 0 , epa, epb, epc, epd) to create valid data. table ix. 1.4.1.3 lists control items and statuses related to transaction control on the ep0 endpoint. table ix. 1.4.1.3 control items and statuses for endpoint ep0 register/bit ep0control.inxout ep0control.replydescr iptor ep0controlin.enshor tpkt ep0controlin.t ogglestat, ep0controlout .t ogglestat ep0controlin.t oggleset, ep0controlout .t oggleset ep0controlin.t oggleclr , ep0controlout .t oggleclr ep0controlin.f orcenak, ep0controlout .f orcenak ep0controlin.f orcest all, ep0controlout .f orcest all ep0controlout .a utof orcenak mainintstat.rcvep0setup ep0intstat.in_t rana ck, ep0intstat.out_t rana ck, ep0intstat.in_t rannak, ep0intstat.out_t rannak, ep0intstat.in_t ranerr , ep0intstat.out_t ranerr description sets the transf er direction at the data and status stages . activ ates automatic descr iptor retur n. enab les transmission of shor t pa ck ets that are under the maximum pa ck et si ze. this setting is cleared after the in transaction that has transmitted a shor t pa ck et is completed. indicates the state of the toggle sequence bit. this setting is automatically initializ ed by the setup stage . sets the toggle sequence bit. clears the toggle sequence bit. retur ns a nak response to in or out transactions regardless of the number of data or v acancies in the fifo region. retur ns a st all response to in or out transactions . sets the ep0control.f orcenak bit whene v er an out transaction is completed. indicates that a setup transaction is ex ecuted. indicates the result of the transaction. item tr ansaction direction enab le descr iptor retur n enab le shor t pa ck et transmission t oggle sequence bit set toggle clear toggle f orced nak response st all response set automatic f orcenak setup reception status tr ansaction status
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-10 epson s1c33e08 technical manual table ix. 1 . 4 . 1 . 4 lists control items and statuses related to transaction processing on the epa, epb, epc, and epd endpoints. table ix. 1.4.1.4 control items and statuses for endpoints epa, epb, epc, and epd register/bit ep x { x =a,b ,c ,d}control.a utof orcenak ep x { x =a,b ,c ,d}control.enshor tpkt ep x { x =a,b ,c ,d}control. disaf_nak_shor t ep x { x =a,b ,c ,d}control.t ogglestat ep x { x =a,b ,c ,d}control.t oggleset ep x { x =a,b ,c ,d}control.t oggleclr ep x { x =a,b ,c ,d}control.f orcenak ep x { x =a,b ,c ,d}control.f orcest all ep x { x =a,b ,c ,d}intstat.out_shor ta ck, ep x { x =a,b ,c ,d}intstat.in_t rana ck, ep x { x =a,b ,c ,d}intstat.out_t rana ck, ep x { x =a,b ,c ,d}intstat.in_t rannak, ep x { x =a,b ,c ,d}intstat.out_ tr annak, ep x { x =a,b ,c ,d}intstat.in_t ranerr , ep x { x =a,b ,c ,d}intstat.out_t ranerr description sets the endpoint's ep x { x =a,b ,c,d}control.f orcenak bit whene v er an out transaction is completed. enab les transmission of shor t pa ck ets that are under the maximum pa ck et siz e f or in transactions . this setting is cleared after the in transaction that has transmitted a shor t pa ck et is completed. in out transactions , reception of a shor t pa ck et automatically disab les the function that sets the endpoint's ep x { x =a,b ,c,d}control.f orcenak bit. indicates the state of the toggle sequence bit. sets the toggle sequence bit. clears the toggle sequence bit. retur ns a nak response to a transaction regardless of the number of data or v acancies in the fifo region. retur ns a st all response to the transaction. indicates the result of the transaction. item set automatic f orcenak enab le shor t pa ck et transmission disab le automatic f orcenak setting upon shor t pa ck et reception t oggle sequence bit set toggle clear toggle f orced nak response st all response tr ansaction status setup transaction the setup transaction addressed to the ep 0 endpoint of the macro's own node is automatically executed. (the usb function must be enabled for this to happen.) when a setup transaction is issued, all the contents of the data packet ( 8 bytes) are stored in the registers ep0setup_0 through ep0setup_7 , followed by an ack response. meanwhile, a rcvep0 setup status is issued to the firmware. if an error occurs during a setup transaction, no response or s tatus is issued. when the setup transaction is completed, the forcenak bit of the ep 0 controlin and ep0 controlout registers are set and the forcestall bit is cleared. the togglestat bit is also set. after the firmware completes setting the ep0 endpoint and becomes ready to proceed to the next stage, clear the forcenak bit of the relevant direction in the ep0controlin or ep0 controlout register. figure ix. 1.4.1.1 illustrates how the setup transaction is executed. (a) the host issues a setup token addressed to the ep 0 endpoint of this node. (b) next, the host sends an 8 -byte long data packet. the macro writes these data in the ep0setup_0 through ep0setup_7 registers. (c) the macro automatically returns an ack response. in addition, it sets registers to be automatically set up and issues a status to the firmware. setup a ac k c d ata b host to de vice de vice to host figure ix.1.4.1.1 setup transaction
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 out transaction in out transactions, data reception is started regardless of the available space in the fifo. thus, this product provides satisfactory throughput by assigning a fifo region about twice as large as the maximum packet size since it can read the fifo data via the port interface, for example, and receive data while creating an available space concurrently. after all data are successfully received in an out transaction, the transaction is closed and an ack response is returned. in addition, the firmware receives an out_tranack status of the relevant endpoint (ep x { x =0 ,a,b,c,d}intstat.out_tranack bit). furthermore, the fifo is updated to acknowledge the data reception and to secure a space for the data. in out transactions on the epa, epb, epc, and epd endpoints, reception of all short-packet data causes an out_shortack status (ep x { x =a,b,c,d}intstat.out_shortack bit) to be issued, in addition to executing the above closing process. if the ep x { x =a,b,c,d}control.disaf_nak_short bit is cleared, the relevant endpoint's ep x { x =a,b,c,d}forcenak bit is set. if a toggle miss-match has occurred in an out transaction, an ack response is returned to the transaction but no status is issued. accordingly, the fifo is not updated. in the event of an error in an out transaction, no response is returned to the transaction. and an out_tranerr status (ep x { x=0 ,a,b,c,d}intstat.out_tranerr bit) is issued. accordingly, the fifo is not updated. if not all data are received in an out transaction, a nak response is returned to the transaction and the out_trannak status (ep x { x =a,b,c,d}intstat.out_trannak bit) is issued. accordingly, the fifo is not updated. figure ix. 1.4.1.2 illustrates how a successful out transaction is executed and closed. (a) the host issues an out token addressed to an out endpoint present on this node. (b) next, the host sends a data packet under the maximum packet size. the macro writes these data in the relevant endpoint's fifo. (c) upon data reception, the macro automatically returns an ack response. in addition, it sets registers to be automatically set up and issues a status to the firmware. out a ac k c d ata b host to de vice de vice to host figure ix.1.4.1.2 out transaction
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-12 epson s1c33e08 technical manual in transaction on an in endpoint, if maximum packet size data exist in the fifo or if the firmware has granted permission for short-packet transmission, the macro responds to the in transaction, returning the data packet. a permission for short-packet data transmission (including zero-length packets) is granted by setting the ep0 controlin.enshortpkt bit and the ep x { x =a,b,c,d}control.enshortpkt bit. when transmitting a short-packet data, make sure that no attempt is made to write any new data into the endpoint's fifo after the transmission permission is granted and until the transaction is closed. on the ep 0 endpoint, the ep0 controlin.forcenak bit is set after the in transaction that transmits the short- packet data is closed. after an ack response is received in the in transaction that has returned the data, the transaction is closed, followed by issuance of an in_tranack status (ep x { x=0 ,a,b,c,d}intstat.in_tranack bit). also, the fifo is updated to acknowledge completion of the data transmission and to free the space. if an ack response is not received in the in transaction that has returned the data, the transaction is considered as a failure, followed by issuance of an in_tranerr status (ep x { x =0 ,a,b,c,d}intstat.in_tranerr bit). accordingly, the fifo is not updated, or no space is freed. in on an in endpoint, if no maximum packet size data exist in the fifo and no permission is granted for short-packet transmission, the in transaction receives a nak response and an in_trannak status (ep x { x=0 ,a,b,c,d}intstat.in_trannak bit) is issued to the firmware. accordingly, the fifo is not updated, or no space is freed. figure ix. 1.4.1.3 illustrates how a successful in transaction is executed and closed. (a) the host issues an in token addressed to an in endpoint present on this node. (b) if response is possible for this in transaction, the macro transmits a data packet under the maximum packet size. (c) the host returns an ack response. after receiving an ack response, the macro sets registers to be automatically set up and issues a status to the firmware. in a ac k c d ata b host to de vice de vice to host figure ix.1.4.1.3 in transaction
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 control transfer control transfer on the ep 0 endpoint is controlled as a combination of a number of discrete transactions. figure ix.1.4.1.4 illustrates how control transfer is executed for an out data stage. (a) the host starts control transfer in a setup transaction. the device's firmware analyzes the request contents to prepare for responding to a data stage. (b) the host issues an out transaction and executes a data stage, and the device receives data. (c) the host issues an in transaction and executes a status stage, and the device returns a zero-length data packet. control transfer without a data stage is executed as in this example but without the data stage. transition to a status stage is triggered by an issuance of a transaction by the host whose direction is opposite to that of the data stage. have your firmware monitor an in_trannak status (ep 0 intstat.in_trannak bit) as a trigger to transit to a status stage from a data stage. a b b c host to de vice de vice to host figure ix.1.4.1.4 control transfer having an out data stage figure ix. 1.4.1.5 illustrates how control transfer is executed for an in data stage. (a) the host starts control transfer in a setup transaction. the device's firmware analyzes the request contents to prepare for responding to a data stage. (b) the host issues an in transaction and executes a data stage, and the device transmits data. (c) the host issues an out transaction and executes a status stage, and the device returns an ack response. transition to a status stage is triggered by an issuance of a transaction by the host whose direction is opposite to that of the data stage. have your firmware monitor an out_trannak status (ep 0 intstat.out_trannak bit) as a trigger to transit to a status stage from a data stage. a b b c host to de vice de vice to host figure ix.1.4.1.5 control transfer having an in data stage since status and data stages in control transfer execute ordinary out and in transactions, flow control using nak responses works effectively. the device is allowed to prepare for returning responses within a specified time frame.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-14 epson s1c33e08 technical manual setup stage the macro automatically executes a setup transaction upon reception of a setup token addressed to its own node. have your firmware monitor a rcvep 0setup status and analyze the request referring to the ep0setup_0 through ep0setup_7 registers to control control transfer. if the host has received a request that involves an out data stage, clear the inxout bit of the ep 0control register to set the ep 0 endpoint direction to out. if the host has received a request that involves an in data stage, set the inxout bit of the ep 0 control register to set the ep0 endpoint direction to in. if the host has received a request that involves no data stage, set the inxout bit of the ep 0 control register to set the ep0 endpoint direction to in in order to transit to a status stage. data stage/status stage transit to the next stage according to the result of request analysis executed by reading the ep 0setup_0 through ep0setup_7 registers. if it is an out stage, clear the inxout of the ep 0 control register to set the direction to out and control the stage by setting the ep 0 controlout accordingly. when the setup stage is completed, the forcenak bit is set. if it is an in stage, set the inxout of the ep 0 control register to set the direction to in and control the stage by setting the ep0 controlin accordingly. when the setup stage is completed, the forcenak bit is set. automatic address setting function this macro provides an automatic address setting function when processing a setaddress() request in a control transfer at the ep0 endpoint. this function is available for the firmware when the ep 0setup_0 through ep0setup_7 registers are checked to confirm the contents and it is proven to be a valid setaddress() request. if it is determined to be a valid setaddress() request, clear or set the ep 0 controlin.forcenak and ep0 controlin.enshortpkt bits accordingly and set the usb_address.autosetaddress bit before responding to the status stage. after this function is enabled and the in transaction at the ep 0 endpoint is completed, the macro extracts the address from the data in the setaddress() request and sets it on the usb_address.usb_address bit. meanwhile, a setaddresscmp status (sie_intstat.setaddresscmp bi t) is issued to the firmware. after this function is enabled, if any other transaction is invoked at the ep 0 endpoint before an in transaction is executed, this function is cancelled and the usb_address.autosetaddress bit is cleared. accordingly, a setaddresscmp status is not issued to the firmware. descriptor return function this macro provides a descriptor return function that is useful for an request that requires data and is issued more than once during control transfer at the ep0 endpoint (for example, during a getdescriptor() request). the firmware can use this function for a request that involves an in data stage. clear the ep 0 controlin.forcenak bit, and before starting responding to the data stage, set the top address of the data to be returned that is within the fifo's descriptor region on the descadrs_h, l register as well as the total number of bytes in the return data on the descsize_h, l register and set the ep 0control.replydescriptor bit. the descriptor return function executes in transactions by returning data packets in response to in transactions until it finishes sending all of a specified number of data. if a fractional number of data exist against the maximum packet size, the descriptor return function sets ep 0 controlin.enshortpkt, enabling response to in transactions until the entire data return is completed. after returning all the specified number of data, the macro clears the ep 0 control.replydescriptor bit and issues a descriptorcmp status (fifo_intstat.descriptorcmp bit) to the firmware. for details of the descriptor region, see the section on the fifo in the functional description.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 bulk transfer/interrupt transfer bulk and interrupt transfers at the general-purpose endpoints, epa, epb, epc, and epd, can be controlled either as a data flow or as a series of discrete transactions (see the transaction section). data flow control this section describes controlling standard data flows in out and in transfers. out transfer data received from an out transfer are placed on the fifo region at the respective endpoints. the fifo data can be read via either the cpu interface (ep 0 , epa, epb, epc, epd) or the port interface (epa, epb, epc, epd). to read the fifo data via the cpu interface, select one and only one endpoint using the cpu_joinrd register. the fifo data of the selected endpoint can be read sequentially with the epnfifoforcpu, according to the order of reception. also, you can refer to the epnrdremain_h and epnrdremain_l registers to check the number of remaining data. reading from an blank fifo causes dummy reading to be performed. to read the fifo data via the port interface, select one and only one out endpoint using the dma_join register. perform the port interface procedure to read the fifo data of the selected endpoint; they are read sequentially in the order of reception. also, you can refer to the dma_remain_h and dma_remain_l registers to check the number of remaining data. after the fifo is emptied, the port interface automatically pauses to perform flow control. do not set the cpu and port interfaces with the cpu_joinrd and dma_join registers for reading from the same endpoint. additionally, be sure to start reading data after ensuring that no data return responses are returned to in transactions by setting the forcenak bit, for example, if you want to set an in endpoint for data reading using the cpu_joinrd register. data cannot be read from the in endpoint via the port interface. if the fifo has available space for receiving data packets, the macro automatically responds to out transactions to receive data. this enables the firmware to perform out transfer without individual transaction control. note, however, that the ep x { x =a,b,c,d}control.forcenak bit of the endpoint is set if short packets are received (including zero-length data packet) when the ep x { x =a,b,c,d}control.disaf_nak_short bit is cleared. clear this bit when the next data transfer is ready. figure ix. 1.4.1.6 illustrates the data flow in out transfer. the fifo region for an out endpoint is connected to the port interface. also, the fifo region assigned to this endpoint is assumed to be twice as large as the maximum packet size. f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 u2 u1 usb po rt reading po rt reading po rt fifo figure ix.1.4.1.6 example of data flow in out transfer
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-16 epson s1c33e08 technical manual (u1 ) data transfer of the maximum packet size is performed in the first out transaction. (u2 ) data transfer of the maximum packet size is performed in the second out transaction. (f1 ) the fifo is blank. although the port interface is invoked, no transfer is performed since the fifo is blank. (the pdreq signal is negated.) (f2 ) an out transaction is developing, and data reception has started in the fifo. at this point, the fifo data is not considered to be valid since the transaction is not closed. (f3 ) although data packet reception is completed from the out transaction, the fifo data is not considered to be valid since the transaction is not closed. (f4 ) the out transaction is closed and the received data are considered to be valid. (f5 ) the presence of valid data in the fifo triggers data transfer via the port interface. (the pdreq signal is asserted.) (f6 ) as port transfer develops, the amount of the remaining valid data in the fifo is reduced. (f7 ) starting the next transaction starts writing data. port transfer continues as long as any valid data remains. (f8 ) port transfer has stopped as there is no valid data left. the second out transaction is not closed yet. (f9 ) the second out transaction is closed, causing the fifo data t o become valid. (f10 ) the presence of valid data in the fifo restarts port transfer. in transfer place data transmitted thorough in transfer on each endpoint's fifo. the fifo data can be written via either the cpu interface (ep 0 , epa, epb, epc, epd) or the port interface (epa, epb, epc, epd). to write data into the fifo via the cpu interface, select one and only one endpoint using the cpu_joinwr register. data can be written in the selected endpoint's fifo by using the epnfifoforcpu register, which are transmitted in data packets in the order of writing. also, you can refer to the epnwrremain_h and epnwrremain_l registers to check the available space in the fifo. an attempt to write in a full fifo causes dummy writing to be performed. to write data into the fifo via the port interface, select one and only one in endpoint using the dma_join register. perform the port interface procedure to write data into the selected endpoint's fifo. these data are transmitted in data packets in the order of writing. after the fifo becomes full, the port interface automatically pauses to perform flow control. do not set the cpu and port interfaces with the cpu_joinwr and dma_join registers for writing data into the same endpoint. additionally, be sure to start writing data after ensuring that no data are received from the out transactions by setting the forcenak bit, for example, if you want to set an out endpoint for data writing using the cpu_joinwr register. data cannot be written into an out endpoint via the port interface. if the fifo contains data exceeding the maximum packet size, the macro automatically responds to in transactions to perform data transmission. this enables the firmware to perform in transfer without individual transaction control. note, however, that you should set the enshortpkt bit if you need to transmit a short packet at the end of the data transfer. since this bit is cleared when the in transaction which has transmitted the short packet is closed, you can set it after data is completely written into the fifo. when the dma_fifo_control.autoenshort bit is set, the ep x { x =a,b,c,d}control.enshortpkt bit of the relevant endpoint is automatically set if the fifo still contains any fractional amount of data under the maximum packet size after writing via the port interface is completed. using this function provides automatic control to the end that only a non-zero-length short packet is returned, eliminating return of a zero-length data packet.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 figure ix. 1.4.1.7 illustrates the data flow in in transfer. the fifo region for an in endpoint is connected to the port interface. also, the fifo region assigned to this endpoint is assumed to be twice as large as the maximum packet size. f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 u3 u2 u1 usb po rt wr iting po rt wr iting po rt fifo figure ix.1.4.1.7 example of data flow in in transfer (u1 ) in the first in transaction, an nak response is returned since the fifo has no valid maximum packet size data. (u2 ) data transfer of the maximum packet size is performed in the second in transaction. (u3 ) data transfer of the maximum packet size is performed in the third in transaction. (f1 ) the fifo is blank. (f2 ) port transfer is started and valid data is written into the fifo. (the pdreq signal is asserted.) (f3 ) as the fifo still has an available space, port transfer is continuing. (f4 ) since the fifo contains valid maximum packet size data, the macro responds to the in transaction with data packet transmission. as the transaction is not closed yet, the region from which data are transmitted is not freed. the fifo is full, causing port transfer to stop. (the pdreq signal is negated.) (f5 ) although data packet transmission in the in transaction has been completed, the fifo region is not freed since the transaction is not closed. port transfer remains discontinued. (f6 ) the fifo region is freed as the transaction is closed upon reception of an ack handshake packet. (f7 ) as the fifo now has some available space, port transfer is resumed. (the pdreq signal is asserted.) (f8 ) the macro responds to an in transaction and transmits a data packet. since the fifo has some available space, port transfer continues. (f9 ) although data packet transmission in the in transaction has been completed, the fifo region is not freed since the transaction is not closed. since the fifo has some available space, port transfer continues. (f10 ) the fifo region is freed when the transaction is closed upon reception of an ack handshake packet. although port transfer pauses as all the available space has been consumed, it is resumed upon closing of the in transaction that creates available space.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-18 epson s1c33e08 technical manual auto-negotiation function this function automatically performs suspend detection, reset detection and resume detection, checking the state of the usb bus for each operation. you can check each interruption (detectreset and detectsuspend) to confirm what has been actually performed. disable ena utonego != 1 irq_detectsuspend insuspend != 0 irq_detectreset irq_nonj == 1 normal state reset state suspend state resume state normal irq_detectreset == 0 and irq_detectsuspend == 0 ena utonego == 0 insuspend == 0 ena utonego == 1 endetectreset = 1 endetectsuspend = 1 disbusdetect = 0 detectseq = star t detectseq = stop detectseq = star t detectseq = stop set_insuspend = 1 in_suspend linestate == k w ait_se0 w ait_se0end linestate == se0 linestate == j linestate == se0 linestate == se0 linestate == k e vt_detectreset chk_event figure ix.1.4.1.8 auto-negotiator
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ( 1 ) disable the macro enters this state when the usb_control.enautonego bit is cleared. to enable the auto-negotiation function, set interruptions for reset detection (sie_intenb.endetectreset) and suspend detection (sie_intenb.endetectsuspend) before setting the usb_control.enautonego bit and give permission to event detection interruption. enabling the auto-negotiation function automatically clears the usb_control.disbusdetect bit and enables the event detection function. while the auto-negotiation function is enabled, never set the usb_control. disbusdetect bit. ( 2 ) normal this is a state of waiting for reset or suspend detection. the state is determined to be reset if se 0 of 2.5 s or greater, and it is determined to be suspend if no activities are detected beyond 3 ms. concurrently with judgment as described above, an interruption for reset detection or suspend detection is generated, and the sie_intstat.detectreset bit and the sie_intstat. detectsuspend bit are set. if the state is determined to be suspend, suspend the event detection function once and enter the in_suspend state. ( 3 ) in_suspend when the state is determined to be suspended, h/w automatically sets the usb_control.insuspend bit and the macro enters the in_suspend state. this usb_control.insuspend bit enables the function of detecting changes of buses from fs-j, only enabling detection of resume or reset from the host. the ability to reduce current consumption during suspend depends on the application. this macro provides snooze function for reducing current consumption. to use the function of reducing current consumption when the auto-negotiation function is enabled, be sure to check that the usb_control.insuspend bit is set before staring the current consumption reducing function. at this time, in order to detect resume (fs-k) that indicates the end of suspend, set the sie_intenb. ennonj bit in the firmware when the macro enters this state to give permission to nonj interruption. when nonj interruption status (sie_intstat.nonj) is set, it is interpreted as an indication of return from suspend, and the macro enters the chk_event state after the usb_control.insuspend bit is cleared in the firmware. in an application with a remote wake-up function enabled, if it is determined that the macro must return from suspend, set the usb_control.sendwakeup bit in this state and output fs-k at least for 1 ms but do not exceed 15 ms. ( 4 ) chk_event in this state, the macro checks the usb cable and determines that the state is resume if fs-k is detected, and that it is reset if se0 is detected. when determined to be reset, set the sie_intstat.detectreset bit. note that you should terminate this auto-negotiation function as soon as the usb cable is unplugged; in none of the above states, the macro does not consider the implication of usb cable disconnection.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-20 epson s1c33e08 technical manual description by negotiation function suspend detection when the usb_control.disbusdetect bit is set to 0 , the macro hardware automatically performs the following suspend detection sequence. (1 ) the internal timer checks that there is no data transmission/reception (continues to detect j in usb_status.linestate[1:0]) for 3 ms or longer (t 1 ). (2 ) at t 2 , if j is detected in usb_status.linestate[1:0], set the sie_intstat.detectsuspend bit. (3 ) if the sie_intenb.endetectsuspend and mainintenb.ensie_intstat bits are set, the macro asserts the #int signal. if the sie_intstat.detectsuspend bit is set, on the firmware that controls this macro, set the usb_control. disbusdetect bit to 1 and usbsnz (d5/0x300012 ) to 1 to start processing snooze before reaching t 4 . as for self-powered products, however, the firmware does not have to perform snooze. (figure ix. 1.4.1.9 shows the operation when snooze is performed.) time detectsuspend snooz e disbusdetect linestate[1:0] usbdp/usbdm inter nal cloc k t 0 t 1 t 2 t 3 t 4 t 5 last activity "j" state "j" state fully meet usb2.0 required frequency figure ix.1.4.1.9 suspend timing (fs mode)
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 reset detection when the usb_control.disbusdetect bit is set to 0 , the macro hardware automatically performs the following reset detection sequence. (1 ) the internal timer checks that it has continued to detect se0 in usb_status.linestate[1:0 ]) for 2.5 s or longer (t 1 ). (2 ) at t 2 , if se0 is detected in usb_status.linestate[1:0], the macro sets the sie_intstat.detectreset bit. (3 ) if the sie_intenb.endetectreset and mainintenb.ensie_intstat bits are set, the macro asserts the #int signal. if the sie_intstat.detectreset bit is set, on the firmware that controls this macro, set the usb_control. disbusdetect bit to 1. time detectreset disbusdetect linestate[1:0] usbdp/usbdm t -1 t 0 t 1 t 2 last activity "j" state "j" state dr iv en se0 se0 figure ix.1.4.1.10 reset timing (fs mode)
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-22 epson s1c33e08 technical manual issuing resume this section describes how to enable automatic resume to be triggered by some cause when remote wake-up is supported and the remote wakeup function is enabled from the host. remote wakeup can only be enabled 5 ms after the bus enters the idle state. furthermore, the current used before the usb suspend state cannot be pulled from the vbus until 10 ms has elapsed after the resume signal output. the s 1c33e08 supports snooze state. this section describes the operation for issuing resume when the oscillation circuit is in operation (usb_cke (d 8/0x301b00 ) = 1 , not in sleep). steps (3 ), (4 ), (8 ) and (9) below are handled by the macro hardware automatically. perform steps ( 1 ), (2 ), (6 ), (6 a) and (10 ) on the firmware that controls this macro. (1 ) clear the sie_intenb.ennonj and usbsnz (d5/0x300012 ) bits. this is to cause this macro return from snooze for automatic wakeup. (2 ) set the usb_control.sendwakeup bit and send out the resume signal. (3 ) the macro sets xcvrcontrol.opmode[1:0 ] to disable bit stuffing and nrzi encoding and prepares for transmission of all 0 data. (4 ) the macro starts data transmission and sends out fs k (the resume signal) to a downstream port. (5 ) the downstream port detects this resume signal and returns fs k (the resume signal) onto the bus. (6 ) clear the usb_control.sendwakeup bit and suspend resume signal send-out. after that, clear the usb_control.insuspend bit. (7 ) the downstream port suspends resume signal send-out. here, note that the resume signal from downstream port (host) has eop of ls at the end. to detect the resume signal sent from downstream port, the following procedure is needed after step ( 6 ) is performed. (6 a) set the usb_control.startdetectj bit. (7 ) the downstream port suspends resume signal send-out. here, note that the resume signal from downstream port (host) has eop of ls at the end. (8 ) the sie_intstat.detectj bit is set. (9 ) if the sie_intenb.endectectj bit is set, the macro asserts the #int signal. (10 ) clear the usb_control.startdetectj bit. however, steps ( 6 a)C(10 ) is not necessary when the auto-negotiation function is used, so just wait another event. this section describes the operation of the oscillation circuit by assuming that it is in operation (usb_cke (d8/0x301b00 ) = 1 , not in sleep). if the oscillation circuit is in the sleep state (deactivated), osc power-up time is needed before returning from the snooze state (with usbsnz (d5/0x300012) reset from 1 to 0).
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 detecting resume when the usb is suspended, j is observed on the bus (usb_status.linestate[1:0 ] is j ). if k is observed on the bus, it means the instruction for wakeup (resume) is received from the downstream port. this section describes the operation when resume is detected, assuming that this macro is in the snooze state when the usb is suspended. use the firmware that controls this macro to perform steps ( 4 ), (5 ), (5 a) and (9 ). the other steps are handled by the macro hardware automatically. (1 ) the bus transits from j to k. (2 ) the macro sets the sie_intstat.nonj bit. (3 ) if the sie_intenb.ennonj and mainintenb.ensie_intstat bits are set, the macro asserts the #int signal. (4 ) clear usbsnz (d5/0x300012). (5 ) clear the usb_control.sendwakeup bit and suspend resume signal send-out. after that, clear the usb_control.insuspend bit. (6 ) the downstream port suspends k send-out. to detect the resume signal sent from downstream port, the following procedure is needed after step ( 5 ) is performed. (5 a) set the usb_control.startdetectj bit. (6 ) the downstream port suspends k send-out. (7 ) the sie_intstat.detectj bit is set. (8 ) if the sie_intenb.endectectj bit is set, the macro asserts the #int signal. (9 ) clear the usb_control.startdetectj bit. however, steps ( 5a)C(9 ) is not necessary when the auto-negotiation function is used, so just wait another event. this section describes the operation of the oscillation circuit by assuming that it is in operation (usb_cke (d8/0x301b00 ) = 1 , not in sleep). if the oscillation circuit is in the sleep state (deactivated), osc power-up time is needed before returning from the snooze state (with usbsnz (d5/0x300012) reset from 1 to 0).
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-24 epson s1c33e08 technical manual cable plug-in this section describes the operation that is carried out when the macro is connected to the hub or the host (via cable plug-in). use the firmware that controls this macro to perform steps ( 3 ) and (4 ). steps (1 ) and (2 ) are handled by the macro hardware automatically. (1 ) when the cable is connected, vbus turns to high and the macro sets the usb_status.vbus and sie_intstat.vbus_changed bits (t 0 ). (2 ) if the sie_intenb.envbus_changed and mainintenb.ensie_intstat bits are set, the macro asserts the #int signal. (3 ) set usb_cke (d8/0x301b00) to start supplying the usb clock (t 1 ). (4 ) clear usbsnz (d5/0x300012) (t 2 ). (5 ) the downstream port sends out reset (t 4 ). usb_cke usbsnz activ eusb disbusdetect opmode[1:0] linestate[1:0] usbdp/usbdm inter nal cloc k time (vbus) upstream po rt actions de vice actions t 0 t 4 t 1 t 2 t 3 "00" (nor mal mode) fully meet usb2.0 required frequency "j" state fs idle ("j" state) se1 se0 se0 se0 clk po wer up time figure ix.1.4.1.11 device attach timing table ix. 1.4.1.5 device attach timing values description vbus is enab led. set usb_cke to 1 (on the fir mw are). the cloc k input star ts . clear usbsnz to 0 (on the fir mw are). set activ eusb to 1. set opmode[1:0] to 00 (on the fir mw are). the do wnstream por t sends out reset. set disbusdetect to 1 (on the fir mw are). v alue 0 (ref erence) t 1 t 1 + 250 ms < t 2 t 0 + 100 ms < t 3 t 3 + 100 ms < t 4 timing parameter t 0 t 1 t 2 t 3 t 4
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ix.1.4.2 fifo management fifo memory map this section describes the memory map for the fifo region. epc area epd area epb area ep a area descr iptor area ep0 area (single buff er) 0x000 (ep0maxsiz e) ep astar tadrs epbstar tadrs == ep aendadrs epcstar tadrs == epbendadrs epdstar tadrs == epcendadrs figure ix.1.4.2.1 fifo memory map the fifo memory is roughly divided into six areas: ep 0 area, descriptor area, epa area, epb area, epc area, and epd area, and each of these areas can be divided according to the settings for the ep 0 maxsize register, epastartadrs register, epbstartadrs register, epcstartadrs register, and epdstartadrs register. the ep 0 area is used for the required usb endpoint 0 , and can be used both for in and out directions. this area is uniquely determined to be the maximum packet size of endpoint 0 that is set up in the ep0maxsize register. this means that it can only receive/transmit one packet (single buffer) at a time. epa, epb, epc, and epd areas are for the general-purpose endpoint that can take an endpoint number and an in/ out setting. the epa area extends from the address set in the epastartadrs register up to the point before the address set in the epbstartadrs register. the epb area extends from the address set in the epbstartadrs register up to the point before the address set in the epcstartadrs register. the epd area extends from the address set in the epdstartadrs register up to the end of fifo ram. the addresses available in the area setup registers must be written in the unit of four bytes (meaning that the lowest two bits cannot be written). additionally, a space exceeding the maximum packet size must be assigned to these areas. although there should be no problem as far a value larger than the maximum packet size is assigned, we recommend that you use its integral multiple to set them up. the descriptor area extends from the address set in the ep 0 maxsize register up to the point before the address set in the epastartadrs. (actually, the entire fifo region can be used as the descriptor area. we recommend, however, that the area described here be used in order to avoid operational contentions.) the practical use is described later. set the epncontrol.allfifo_clr bit for the initial setting or re-setting of an area set-up register. once the initial setting for an area is established, the epncontrol.allfifo_clr bit is cleared. this bit will never cause the ram data to be cleared. therefore, unless you have changed the descriptor area, there is no need to re-set the information recorded within the area since will never be cleared otherwise.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-26 epson s1c33e08 technical manual using the descriptor area the descriptor area provides high-speed, straightforward execution of part of operations for packets received/ transmitted via ep0 , or a standard request. among contents of standard requests, write those in this area that are uniquely determined by the device during the initial setup stage following power-on to automatically execute the data stage included in the request simply by setting the top address and the data size in response to a request from the host. accordingly, this technique eliminates the need of writing data in the ep 0 area, enabling very quick response to a request. writing data in the descriptor area to write data in the descriptor area, first set the write start address in the descadrs_h and descadrs_l registers, and then write data in the descdoor register (regwindowsel == 0x2 ). after completing writing data, the descadrs_h and descadrs_l registers are automatically incremented by one, enabling sequential writing in the descdoor register (regwindowsel == 0x2 ) when writing data at a series of adjacent addresses. note that this incrementing function does not mean that written data can be read when writing and reading are executed sequentially; it only increments by one for both writing and reading. reading data from descriptor area to read data from the descriptor area, first set the read start address in the descadrs_h and descadrs_l registers, and then read data from the descdoor register (regwindowsel == 0x2 ). after completing reading data, the descadrs_h and descadrs_l registers are automatically incremented by one, enabling sequential reading in the descdoor register (regwindowsel == 0x2 ) when reading data from a series of adjacent addresses. note that this incrementing function does not mean that written data can be read when writing and reading are executed sequentially; it only increments by one for both writing and reading. executing data stage (in) in the descriptor area to use written data in response to a request from ep 0 , set the top address of the data to be transmitted to the data stage, set the data size specified in the request in the descsize_h and descsize_l registers, and then set the ep0control.replydescriptor bit to 1. after receiving the in token from the host, the macro start transmitting data to the host, automatically splitting them into the maximum packet size (set in the ep 0 maxsize). in addition, if the value in the descsize_h or descsize_l register is under the maximum packet size, or if the remaining number of data after splitting, the macro automatically transmits such data as short packets. when the specified number of data are completely transmitted, the ep 0 control.replydescriptor is cleared and the fifo_intstat.descriptorcmp is set. at this stage, the fifo_intenb.endescriptorcmp bit is set and the mainintenb.eneprintstat bit is set as well, the #int signal is asserted at the same time. if the process enters a status stage before the transmitted amount reaches the specified number of data (that is, if an out token is received), the ep 0control.replydescriptor is automatically cleared to suspend this function. at the same time, the ep 0 intstat.out_trannak status and the fifo_intstat.descriptorcmp status are set. if either of the following sets of bits are set, the #int signal is asserted at the same time: (1 ) the ep0 intenb.enout_trannak, mainintenb.enep0 intstat and mainintenb.eneprintstat bits, or (2 ) the fifo_intenb.endescriptorcmp and mainintenb.eneprintstat bits.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 accessing to fifo by cpu to enable the cpu to access the fifo, set the bit of the relevant endpoint of the cpu_joinrd and cpu_joinwr registers to 1 and execute reading and writing via the epnfifoforcpu register. for each of the cpu_joinrd and cpu_joinwr registers, you can only set one bit out of the four bits. if you attempt to set more than one bit at a time, only the highest bit is set. the epnrdremain_h and epnrdremain_l registers indicate the remaining number of data that can be read at the endpoint set in the cpu_joinrd register. the epnwrremain_h and epnwrremain_l registers indicate the remaining area space available for writing at the endpoint set in the cpu_joinwr register. note that, if the cpu_joinrd register is set when register dumping is planned for debugging of a cpu using ice, data will be read from the fifo upon dumping the register. limiting access to fifo the fifo of this macro allows concurrent execution of data reception/transmission between the macro and the usb and/or the port and writing/reading to and from the cpu. because of this, there are two limitations for accessing the fifo (for writing and reading) from the cpu (the firmware): (1 ) from the cpu, no writing is allowed to the same endpoint while the usb or the port is writing data to the fifo. (2 ) no reading from the cpu is allowed from the same endpoint while the usb or the port is reading from the fifo. never execute these operations; they may destroy data continuity.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-28 epson s1c33e08 technical manual ix.1.4.3 port interface functional description the port interface is a dma interface designed for fast data transfer between this macro and the fifo for its built-in endpoints. it provides asynchronous dma transfer mode for transfer triggered by the read/write- strobe signal. basic operations this section describes the basic operations of the port interface. register setting table ix. 1.4.3.1 lists the registers used for setting basic items of the port interface. set desired values for the respective registers. to enable the dma to write, set the dma_join register to connect the port interface to the endpoint set to the in direction of the usb. to enable the dma to read, connect to the endpoint set to the out direction. do not modify the basic setting registers while the dma is transferring data (when dma_control. dma_running is set to 1 ). we do not guarantee normal operations if the basic setting registers are modified while the dma in transferring data. table ix. 1.4.3.1 port interface's registers for basic setting items register/bit dma_join.joinepr{r=a,b ,c ,d}dma dma_count_r{r=hh,hl,lh,ll} dma_config_0.activ ep or t dma_config_0.pdreq_le ve l dma_config_0.pd a ck_le ve l dma_config_0.pdrd wr_le ve l dma_config_1.rcvlimitmode dma_config_1.singlew ord dma_config_1.countmode description connects the po rt interf ace to the endpoint of the bit set to 1. wr iting/reading is enab led to/from the connected endpoint. sets the number of b ytes to be do wn-counted in countdo wn mode . enab les the por t f or the po rt interf ace . sets the activ e le v el of the po rt interf ace signal. 0: high-activ e. 1: lo w-activ e. only enab led while wr iting in asynchronous transf er mode . if this bit is set to 1, up to 16 b ytes of data can be receiv ed ev en after negating pdreq. sets the transf er mode f or operation in asynchronous transf er mode . 0: multi-word transf er . 1: single-word transf er . sets countdo wn/f ree-r un mode . 0: f ree-r un mode . 1: countdo wn mode . item endpoint connection counter settin g activ e por t activ e le ve l rcvlimit mode single-/multi-word count mod e dma transfer after setting the basic setting registers, write 1 to the dma_control.dma_go bit to cause the port interface to start running the dma. after the dma starts running, the dma_control.dma_running bit is set to 1, indicating that the dma is running. if the dma is set to the countdown mode with dma_config_ 1 .countmode = 1 , the dma completes data transfer when the dma_count_hh, hl, lh and ll registers reach 0000_0000 h. to force the dma to terminate data transfer, provide 1 to the dma_control.dma_stop bit. after the dma completes data transfer, the dma_control.dma_running bit attains 0 and the dma_intstat.dma_cmp bit 1 . at this time, if the dma_intenb.endma_cmp bit is set, the #int signal is asserted to the cpu.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 asynchronous dma transfer this macro provides an 8 -bit asynchronous dma transfer function that outputs/inputs data, triggered by the data transfer request signal pdreq, data transfer permit signal pdack and read-strobe pdrd/write- strobe pdwr. this mode only supports the slave functionality, and enables data transfer either in multi-word or single-word mode. asynchronous multi-word dma transfer mode - slave 1) writing operation the port interface starts writing operation in asynchronous multi-word dma transfer mode when the following register settings are established: ? dma_config_1 .singleword bit = 0 ? direction of the target endpoint = in the port interface starts data transfer on the dma when 1 is written on the dma_control.dma_go bit. after data transfer starts on the dma, it requests data transfer by asserting pdreq to the hsdma (master) if any available space is found at the connected endpoint. the dma loads the data and writes them to the endpoint when pdwr is rising (when the dma_config_ 0 .pdrdwr_level bit is set to 1 ). when available space is entirely consumed at the endpoint, the interface negates pdreq to the hsdma (master) to reject data transfer. if any data is set to the dma_latency.dma_latency[ 3:0 ] bit other than 0 h, this mode negates pdreq once after completing transfer of 4 -byte data, and does not assert pdreq as long as 130 ns n (n = dma_ latency.dma_latency[ 3:0]). if the dma is set to the countdown mode with dma_config_ 1 .countmode = 1 , the dma completes data transfer when the dma_count_hh, hl, lh and ll registers reach 0000_0000 h. to force the dma to terminate data transfer, set the dma_control.dma_stop bit to 1 . note that forced termination of dma transfer by writing to this bit may cause loss of data from those being transferred. to avoid it, first terminate the hsdma (master) and then terminate the macro's dma transfer. pdreq (o) #pdreq (o) pd a ck (i) pdwr (i) data (i) data sampling d0 d1 dn-1 dn in ve r ted figure ix.1.4.3.1 transfer waveforms in asynchronous multi-word dma transfer mode - writing providing 1 to the dma_config_1 .dma_rcvlimitmode bit enables the rcvlimit mode. the rcvlimit mode is not available in countdown mode. when the dma is writing asynchronously in rcvlimit mode, up to 16 bytes of data can be received even after this macro negates pdreq. in this mode, pdreq is negated when the available space is less than 32 bytes at the relevant endpoint as a result of the dma's writing operation. however, when pdreq is negated, 16 bytes of data that have not been written to the endpoint may exist within the internal circuit. therefore, up to 16 bytes of data can be received after pdreq is negated. in this mode, pdreq is negated before the endpoint becomes completely full. if the region set with the ep{a,b,c,d}startadrs register is the same as that set with the ep{a,b,c,d}maxsize register (single buffer), the endpoint never becomes full, and data cannot be transmitted through usb in transfer.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-30 epson s1c33e08 technical manual therefore, you should set up an area exceeding the ep{a,b,c,d}maxsize value + 32 bytes to use the rcvlimit mode, using the ep{a,b,c,d}startadrs register. pdreq (o) #pdreq (o) pd a ck (i) pdwr (i) data (i) data sampling in ve r ted d0 d1 dn-1 dn d2 figure ix.1.4.3.2 waveforms in asynchronous multi-word dma transfer mode - writing (rcvlimit mode) 2) reading operation the port interface starts reading operation in the asynchronous multi-word dma transfer mode when the following register settings are established: ? dma_config_1 .singleword bit = 0 ? direction of the target endpoint = out the port interface starts data transfer on the dma when 1 is written on the dma_control.dma_go bit. after data transfer starts on the dma, it requests data transfer by asserting pdreq to the hsdma (master) if any data exist at the connected endpoint. turning pdack to active starts outputting transferred data to the data bus. have the hsdma (master) load the data while pdrd is rising (when the dma_config_ 0 .pdrdwr_level bit is set to 1 ). when no data remains at the endpoint, the interface negates pdreq to the hsdma (master) to reject data transfer. if any data is set to the dma_latency.dma_latency[ 3:0 ] bit other than 0 h, this mode negates pdreq once after completing transfer of 4 -byte data, and does not assert pdreq as long as 130 ns n (n = dma_ latency.dma_latency[ 3:0]). if the dma is set to the countdown mode with dma_config_ 1 .countmode = 1 , the dma completes data transfer when the dma_count_hh, hl, lh and ll registers reach 0000_0000 h. to force the dma to terminate data transfer, set the dma_control.dma_stop bit to 1 . note that forced termination of dma transfer by writing to this bit may cause loss of data from those being transferred. to avoid it, first terminate the hsdma (master) and then terminate the macro's dma transfer. pdreq (o) #pdreq (o) pd a ck (i) pdrd (i) data (o) data sampling in ve r ted d0 d1 dn-1 dn figure ix.1.4.3.3 transfer waveforms in asynchronous multi-word dma transfer mode - reading
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 asynchronous single-word dma transfer mode - slave 1) writing operation the port interface starts writing operation in asynchronous single-word dma transfer mode when the following register settings are established: ? dma_config_1 .singleword bit = 1 ? direction of the target endpoint = in the port interface starts data transfer on the dma when 1 is written on the dma_control.dma_go bit. after data transfer starts on the dma, it requests data transfer by asserting pdreq to the hsdma (master) if any available space is found at the connected endpoint. the dma loads the data and writes them to the endpoint when pdwr is rising (when the dma_config_ 0 .pdrdwr_level bit is set to 1 ). this mode negates pdreq after transferring 1 -byte data (pdwr becomes active). at this point, if any space is still available at the endpoint, it requests data transfer by asserting pdreq to the hsdma (master). if there is no available space left at the endpoint, pdreq is not asserted and data transfer is rejected. if any data is set to the dma_latency.dma_latency[ 3:0 ] bit other than 0 h, this mode negates pdreq once after completing transfer of 4-byte data, and does not assert pdreq as long as 130 ns n (n = dma_latency. dma_latency[ 3:0]). if the dma is set to the countdown mode with dma_config_ 1 .countmode = 1 , the dma completes data transfer when the dma_count_hh, hl, lh and ll registers reach 0000_0000 h. to force the dma to terminate data transfer, set the dma_control.dma_stop bit to 1 . note that forced termination of dma transfer by writing to this bit may cause loss of data from those being transferred. to avoid it, first terminate the hsdma (master) and then terminate the macro's dma transfer. pdreq (o) #pdreq (o) pd a ck (i) pdwr (i) data (i) data sampling in ve r ted d0 d1 dn-1 dn figure ix.1.4.3.4 transfer waveforms in asynchronous single-word dma transfer mode - writing 2) reading operation the port interface starts reading operation in the asynchronous single-word dma transfer mode when the following register settings are established: ? dma_config_1 .singleword bit = 1 ? direction of the target endpoint = out the port interface starts data transfer on the dma when 1 is written on the dma_control.dma_go bit. after data transfer starts on the dma, it requests data transfer by asserting pdreq to the hsdma (master) if any data exist at the connected endpoint. turning pdack to active starts outputting transferred data to the data bus. have the hsdma (master) load the data while pdrd is rising (when the dma_config_ 0 .pdrdwr_level bit is set to 1 ). this mode negates pdreq after transferring 1 -byte data (pdrd becomes active). at this point, if any data still remain at the endpoint, it requests data transfer by asserting pdreq to the hsdma (master). if there are no data left at the endpoint, pdreq is not asserted and data transfer is rejected. if any data is set to the dma_latency.dma_latency[ 3:0 ] bit other than 0 h, this mode negates pdreq once after completing transfer of 4-byte data, and does not assert pdreq as long as 130 ns n (n = dma_latency. dma_latency[ 3:0]).
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-32 epson s1c33e08 technical manual if the dma is set to the countdown mode with dma_config_ 1 .countmode = 1 , the dma completes data transfer when the dma_count_hh, hl, lh and ll registers reach 0000_0000 h. to force the dma to terminate data transfer, set the dma_control.dma_stop bit to 1 . note that forced termination of dma transfer by writing to this bit may cause loss of data from those being transferred. to avoid it, first terminate the hsdma (master) and then terminate the macro's dma transfer. pdreq (o) #pdreq (o) pd a ck (i) pdrd (i) data (o) data sampling in ve r ted d0 d1 dn-1 dn figure ix.1.4.3.5 transfer waveforms in asynchronous single-word dma transfer mode - reading
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ix.1.4.4 snooze this macro has snooze function which enables very low power operation when usb is not active. when the snooze signal is asserted by writing 1 to usbsnz (d5/0x300012 ), the following procedure will be performed and allows to stop feeding 48 mhz clock after 5 clocks inputs. ? disable usb differential comparator ? allow asynchronous access for vbus_changed and nonj bits of the sie_intstat register. (monitor the usb interface input pins) ? mask read/write for synchronous registers ? mask synchronous interrupt this macro will resume after 5 clocks (oscillation must be stable) when the snooze signal is negated. 48 mhz cloc k snooze 5 cloc k 5 cloc k figure ix.1.4.4.1 snooze sequence snooze mode should be set or canceled by the following procedure: setting snooze mode (1 ) write 0x96 to the misc protect register (0x300020 ) to disable write protection for the misc registers. (2 ) set usbsnz (d5/0x300012 ) in the usb wait control register to 1 to enable the snooze control. (3 ) write a value other than 0x96 to the misc protect register (0x300020 ) to enable write protection for the misc registers. (4 ) write 0x96 to the clock control protect register (0x301b24 ) to disable write protection for the cmu registers. (5 ) set usb_cke (d 8 / 0 x 301 b 00 ) in the gated clock control register 0 to 0 to stop supplying the usb clock. (6 ) write a value other than 0x96 to the clock control protect register (0x301b24 ) to enable write protection for the cmu registers. canceling snooze mode (1 ) write 0x96 to the clock control protect register (0x301b24 ) to disable write protection for the cmu registers. (2 ) set usb_cke (d 8 / 0 x 301 b 00 ) in the gated clock control register 0 to 1 to start supplying the usb clock. (3 ) write a value other than 0x96 to the clock control protect register (0x301b24 ) to enable write protection for the cmu registers. (4 ) write 0x96 to the misc protect register (0x300020 ) to disable write protection for the misc registers. (5 ) set usbsnz (d5/0x300012 ) in the usb wait control register to 0 to disable the snooze control. (6 ) write a value other than 0x96 to the misc protect register (0x300020 ) to enable write protection for the misc registers.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-34 epson s1c33e08 technical manual ix.1.5 registers ix.1.5.1 list of registers ? italic & bold represents readable/writable registers in snooze/sleep mode. address 300900 300901 300902 300903 300904 300905 300906 300907 300908 300909 30090a 30090b 30090c 30090d 30090e 30090f r/w r/(w) r/(w) r r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) init 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 d7 sie_intstat vbus_changed descr iptorcmp d6 eprintstat nonj out_shor ta ck out_shor ta ck out_shor ta ck out_shor ta ck d5 dma_intstat detectreset in_t rana ck in_t rana ck in_t rana ck in_t rana ck in_t rana ck d4 fifo_intstat detectsuspend out_t rana ck out_t rana ck out_t rana ck out_t rana ck out_t rana ck d3 rcvsof epdintstat in_t rannak in_t rannak in_t rannak in_t rannak in_t rannak d2 detectj epcintstat out_t rannak out_t rannak out_t rannak out_t rannak out_t rannak d1 ep0intstat epbintstat dma_countup fifo_in_cmp in_t ranerr in_t ranerr in_t ranerr in_t ranerr in_t ranerr d0 rcvep0setup setaddresscmp ep aintstat dma_cmp fifo_out_cmp out_t ranerr out_t ranerr out_t ranerr out_t ranerr out_t ranerr register name mainintstat sie_intstat eprintstat dma_intstat fifo_intstat ep0intstat ep aintstat epbintstat epcintstat epdintstat address 300910 300911 300912 300913 300914 300915 300916 300917 300918 300919 30091a 30091b 30091c 30091d 30091e 30091f r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w init 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 d7 ensie_intstat envbus_changed endescr iptorcmp d6 eneprintstat ennonj enout_shor ta ck enout_shor ta ck enout_shor ta ck enout_shor ta ck d5 endma_intstat endetectreset enin_t rana ck enin_t rana ck enin_t rana ck enin_t rana ck enin_t rana ck d4 enfifo_intstat endetectsuspend enout_t rana ck enout_t rana ck enout_t rana ck enout_t rana ck enout_t rana ck d3 enrcvsof enepdintstat enin_t rannak enin_t rannak enin_t rannak enin_t rannak enin_t rannak d2 endetectj enepcintstat enout_t rannak enout_t rannak enout_t rannak enout_t rannak enout_t rannak d1 enep0intstat enepbintstat endma_countup enfifo_in_cmp enin_t ranerr enin_t ranerr enin_t ranerr enin_t ranerr enin_t ranerr d0 enrcvep0setup ensetaddresscmp enep aintstat endma_cmp enfifo_out_cmp enout_t ranerr enout_t ranerr enout_t ranerr enout_t ranerr enout_t ranerr register name mainintenb sie_intenb eprintenb dma_intenb fifo_intenb ep0intenb ep aintenb epbintenb epcintenb epdintenb address 300920 300921 300922 300923 300924 300925 300926 300927 300928 300929 30092a 30092b 30092c 30092d 30092e 30092f r/w r r/w r r/w r/w w w r r init 0x12 0x00 0xxx 0x01 0x00 0x00 0x00 0x80 0x00 d7 disbusdetect vbus rpuenb enusb_t est allf orcenak fnin v alid d6 ena utonego 1(fs) eprf orcest all d5 insuspend allfifo_clr d4 star tdetectj d3 sendw ak eup t est_se0_nak epdfifo_clr d2 t est_j epcfifo_clr d1 t est_k epbfifo_clr d0 activ eusb t est_p a cke t ep0fifo_clr ep afifo_clr register name re visionnum usb_control usb_status xcvrcontrol usb_t est epncontrol eprfifo_clr fr amenumber_h fr amenumber_l linestate[1:0] opmode[1:0] fr amenumber[10:8] re vision number[7:0] fr amenumber[7:0]
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 address 300930 300931 300932 300933 300934 300935 300936 300937 300938 300939 30093a 30093b 30093c 30093d 30093e 30093f r/w r r r r r r r r r/w r/w r/w r/w r/w init 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 d7 a utosetaddress inxout a utof orcenak d6 enshor tpkt d5 d4 t ogglestat t ogglestat d3 t oggleset t oggleset d2 t oggleclr t oggleclr d1 f orcenak f orcenak d0 replydescr iptor f orcest all f orcest all register name ep0setup_0 ep0setup_1 ep0setup_2 ep0setup_3 ep0setup_4 ep0setup_5 ep0setup_6 ep0setup_7 usb_address ep0control ep0controlin ep0controlout ep0maxsiz e usb_address[6:0] ep0maxsiz e[6:3] address 300940 300941 300942 300943 300944 300945 300946 300947 300948 300949 30094a 30094b 30094c 30094d 30094e 30094f r/w r/w r/w r/w r/w init 0x00 0x00 0x00 0x00 d7 a utof orcenak a utof orcenak a utof orcenak a utof orcenak d6 enshor tpkt enshor tpkt enshor tpkt enshor tpkt d5 disaf_nak_shor t disaf_nak_shor t disaf_nak_shor t disaf_nak_shor t d4 t ogglestat t ogglestat t ogglestat t ogglestat d3 t oggleset t oggleset t oggleset t oggleset d2 t oggleclr t oggleclr t oggleclr t oggleclr d1 f orcenak f orcenak f orcenak f orcenak d0 f orcest all f orcest all f orcest all f orcest all register name ep acontrol epbcontrol epccontrol epdcontrol address 300950 300951 300952 300953 300954 300955 300956 300957 300958 300959 30095a 30095b 30095c 30095d 30095e 30095f r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w init 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 d7 inxout iso inxout iso inxout iso inxout iso d6 t ogglemode iso_crcmode t ogglemode iso_crcmode t ogglemode iso_crcmode t ogglemode iso_crcmode d5 enendp oint enendp oint enendp oint enendp oint d4 d3 d2 d1 d0 register name ep amaxsiz e_h ep amaxsiz e_l ep aconfig_0 ep aconfig_1 epbmaxsiz e_h epbmaxsiz e_l epbconfig_0 epbconfig_1 epcmaxsiz e_h epcmaxsiz e_l epcconfig_0 epcconfig_1 epdmaxsiz e_h epdmaxsiz e_l epdconfig_0 epdconfig_1 ep amaxsiz e[9:8] endp ointnumber[3:0] ep amaxsiz e[7:0] epbmaxsiz e[9:8] endp ointnumber[3:0] epbmaxsiz e[7:0] epcmaxsiz e[9:8] epdmaxsiz e[9:8] endp ointnumber[3:0] epcmaxsiz e[7:0] endp ointnumber[3:0] epdmaxsiz e[7:0] address 300970 300971 300972 300973 300974 300975 300976 300977 300978 300979 30097a 30097b 30097c 30097d 30097e 30097f r/w r/w r/w r/w r/w r/w r/w r/w r/w init 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 d7 d6 d5 d4 d3 d2 d1 d0 register name ep astar tadrs_h ep astar tadrs_l epbstar tadrs_h epbstar tadrs_l epcstar tadrs_h epcstar tadrs_l epdstar tadrs_h epdstar tadrs_l ep astar tadrs[11:8] ep astar tadrs[7:2] epbstar tadrs[11:8] epbstar tadrs[7:2] epcstar tadrs[11:8] epcstar tadrs[7:2] epdstar tadrs[11:8] epdstar tadrs[7:2]
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-36 epson s1c33e08 technical manual address 300980 300981 300982 300983 300984 300985 300986 300987 300988 300989 30098a 30098b 30098c 30098d 30098e 30098f r/w r/w r/w r/w r/w r r r r r/w r/w r/w r/w r/w init 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 d7 d6 d5 d4 d3 joinepdrd joinepdwr d2 joinepcrd joinepcwr d1 joinepbrd joinepbwr enepnfifo_w r d0 joinep ard joinep aw r enepnfifo_rd register name cpu_joinrd cpu_joinwr enepnfifo_access epnfifof orcpu epnrdremain_h epnrdremain_l epnwrremain_h epnwrremain_l descadrs_h descadrs_l descsiz e_h descsiz e_l descdoor epnrdremain[11:8] epnrdremain[7:0] epnfifodata[7:0] epnwrremain[11:8] epnwrremain[7:0] descadrs[11:8] descadrs[7:0] descsiz e[9:8] descsiz e[7:0] descmode[7:0] address 300990 300991 300992 300993 300994 300995 300996 300997 300998 300999 30099a 30099b 30099c 30099d 30099e 30099f r/w r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w init 0x00 0x00 0xx0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 d7 fifo_running dma_running activ ep or t rcvlimitmode d6 a utoenshor t pdreq d5 pd ac k d4 d3 joinepddma counterclr pdreq_le ve l singlew ord d2 joinepcdma pd a ck_le ve l d1 joinepbdma dma_stop pdrd wr_le ve l d0 joinep adma dma_go countmode register name dma_fifo_control dma_join dma_control dma_config_0 dma_config_1 dma_latency dma_remain_h dma_remain_l dma_count_hh dma_count_hl dma_count_lh dma_count_ll dma_count[31:24] dma_latency[3:0] dma_count[15:8] dma_remain[11:8] dma_remain[7:0] dma_count[23:16] dma_count[7:0]
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 ix.1.5.2 detailed description of registers 0x300900: mainintstat (main interrupt status) name address register name bit setting init. r/w remarks sie_intstat eprintstat dma_intstat fifo_intstat C ep0intstat rcvep0setup d7 d6 d5 d4 d3C2 d1 d0 0 0 0 0 C 0 0 r r r r C r r(w) 0 when being read. 00300900 (b) 1 sie interrupts 0 none 1 epr interrupts 0 none 1 dma interrupts 0 none 1 fifo interrupts 0 none C 1 ep0 interrupts 0 none 1 receive ep0 setup 0 none mainintstat (main interrupt status) this register displays causes of interrupt having occurred in the usb function controller. this register has the bit indirectly showing causes of interrupt and the bit directly showing causes of interrupt. the bit indirectly showing causes of interrupt can be traced to the bit directly showing causes of interrupt by reading the relevant status registers. the bit showing causes of interrupt is read-only, and is automatically cleared by clearing the bit directly showing causes of interrupt at the main source. the bits showing causes of interrupt are writable, and the causes of interrupt can be cleared by setting the relevant bits to 1 . when the corresponding bits are enabled by the mainintenb register, setting the cause of interrupt to 1 asserts the #int signal, and causes an interruption of the cpu. clearing all relevant causes of interrupt negates the #int signal. d7 sie_intstat shows a cause of interrupt indirectly. when the sie_intstat register has a cause of interrupt and the sie_intenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1 . reading this bit is valid during snooze as well. d6 eprintstat shows a cause of interrupt indirectly. when the eprintstat register has a cause of interrupt and the eprintenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1. d5 dma_intstat shows a cause of interrupt indirectly. when the dma_intstat register has a cause of interrupt and the dma_intenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1. d4 fifo_intstat shows a cause of interrupt indirectly. when the fifo_intstat register has a cause of interrupt and the fifo_intenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1. d[3:2] reserved d1 ep0intstat shows a cause of interrupt indirectly. when the ep 0 intstat register has a cause of interrupt and the ep0 intenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1. d0 rcvep0setup shows a cause of interrupt directly. set to 1 when the received data are set to the ep0setup_0 to ep0setup_7 after the set up stage has been completed. at the same time, the forcestall bit, the forcenak bit and the togglestat bit of the ep0controlin and ep0 controlout registers are automatically set to 0, 1 and 1 , respectively.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-38 epson s1c33e08 technical manual 0x300901: sie_intstat (sie interrupt status) name address register name bit setting init. r/w remarks vbus_changed nonj detectreset detectsuspend rcvsof detectj C setaddresscmp d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 C 0 r(w) r(w) r(w) r(w) r(w) r(w) C r(w) 0 when being read. 00300901 (b) 1 vbus is changed 0 none 1 detect non j state 0 none 1 detect usb reset 0 none 1 detect usb suspend 0 none 1 receive sof token 0 none 1 detect j state 0 none C 1 autosetaddress complete 0 none sie_intstat (sie interrupt status) this register displays the interrupts related to sie. d7 vbus_changed shows a cause of interrupt directly. when the condition of the vbus terminal changes, this bit is set to 1. check the condition of the vbus by the vbus bit in the usb_status register. if the vbus is 0 , it shows that the cable is pulled off. this bit is valid during snooze as well. d6 nonj shows a cause of interrupt directly. set to 1 when the status other than the j state is detected in the usb bus. this bit is valid when the insuspend bit of the usb_control register is set to 1. d5 detectreset shows a cause of interrupt directly. set to 1 when the reset state of the usb is detected. this reset detection is valid when the activeusb bit of the usb_control register is set to 1. when the autonegotiation function is not used, if this bit is set to 1 , set to the disbusdetect bit of the usb_control register to 1 , not to detect the succeeding reset wrongly by disabling detection of the reset/suspend state. set the disbusdetect bit to 0 (to be cleared) after completing the process for reset, to enable the reset/suspend state detection. refer to the item on the enautonego bit of the usb_control register, for the autonegotiation function. d4 detectsuspend shows a cause of interrupt directly. set to 1 when the suspend state of the usb is detected. after detecting the usb suspend state, setting the usbsnz bit of the usb wait control register (0x300012) to 1 enables the ic to enter the snooze mode (to stop the built-in pll oscillation). d3 rcvsof shows a cause of interrupt directly. set to 1 when the sof token is received. d2 detectj shows a cause of interrupt directly. set to 1 when the j-state is detected. d1 reserved d0 setaddresscmp shows a cause of interrupt directly. when the autosetaddress function (refer to the usb_address register) ends normally, this bit is set to 1 . the case when autosetaddress function ends normally is that when ack is received during in transaction.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300902: eprintstat (epr interrupt status) name address register name bit setting init. r/w remarks C epdintstat epcintstat epbintstat epaintstat d7C4 d3 d2 d1 d0 C 0 0 0 0 C r r r r 0 when being read. 00300902 (b) C 1 epc interrupt 0 none 1 epb interrupt 0 none 1 epa interrupt 0 none eprintstat (epr interrupt status) 1 epd interrupt 0 none d[7:4] reserved d3 epdintstat shows a cause of interrupt indirectly. when the epdintstat register has a cause of interrupt and the epdintenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1. d2 epcintstat shows a cause of interrupt indirectly. when the epcintstat register has a cause of interrupt and the epcintenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1. d1 epbintstat shows a cause of interrupt indirectly. when the epbintstat register has a cause of interrupt and the epbintenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1. d0 epaintstat shows a cause of interrupt indirectly. when the epaintstat register has a cause of interrupt and the epaintenb register bit corresponding to the cause of interrupt is enabled, this bit is set to 1.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-40 epson s1c33e08 technical manual 0x300903: dma_intstat (dma interrupt status) name address register name bit setting init. r/w remarks C dma_countup dma_cmp d7C2 d1 d0 C 0 0 C r(w) r(w) 0 when being read. 00300903 (b) C 1 dma complete 0 none dma_intstat (dma interrupt status) 1 dma counter overflow 0 none this register displays the interrupt status of the dma. d[7:2] reserved d1 dma_countup shows a cause of interrupt directly. set to 1 when values of dma_count_hh, hl, lh and ll overflow while the dma operates in the free run mode. then values of dma_count_hh, hl, lh and ll return to 0 , and the dma operation continues. d0 dma_cmp shows a cause of interrupt directly. set to 1 when the dma is stopped or completes the specified number of transfer operations and the end processing.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300904: fifo_intstat (fifo interrupt status) name address register name bit setting init. r/w remarks descriptorcmp C fifo_in_cmp fifo_out_cmp d7 d6C2 d1 d0 0 C 0 0 r(w) C r(w) r(w) 0 when being read. 00300904 (b) C 1 out fifo complete 0 none 1 descriptor complete 0 none fifo_intstat (fifo interrupt status) 1 in fifo complete 0 none this register displays the interrupt status of the fifo. d7 descriptorcmp shows a cause of interrupt directly. set to 1 when as many data as specified in the descsize register have been replied in the description reply function. and the out_trannak bit of the ep 0 intstat register is set to 1 as well as this bit, when changing to the status stage takes place (the out token is received) before sending data up to the quantity specified in the descsize register. d[6:2] reserved d1 fifo_in_cmp shows a cause of interrupt directly. if the transfer direction of the endpoint bound to dma (refer to the dma_join register) is the in direction, this bit is set to 1 when the fifo becomes empty after completion of the dma transf er. d0 fifo_out_cmp shows a cause of interrupt directly. if the transfer direction of the endpoint bound to dma (refer to the dma_join register) is the out direction, this bit is set to 1 when the dma transfer is completed.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-42 epson s1c33e08 technical manual 0x300907: ep0intstat (ep0 interrupt status) name address register name bit setting init. r/w remarks C in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7C6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 00300907 (b) 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none ep0intstat (ep0 interrupt status) C this register displays the interrupt status of the endpoint ep 0. d[7:6] reserved d5 in_tranack shows a cause of interrupt directly. set to 1 when ack is received in the in transaction. d4 out_tranack shows a cause of interrupt directly. set to 1 when ack is replied in the out transaction. d3 in_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the in transaction. d2 out_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the out transaction. d1 in_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the in transaction, when an error occurred in the packet or when the handshake is failed in time-out. d0 out_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the out transaction or when an error occurred in the packet.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-43 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300908: epaintstat (epa interrupt status) name address register name bit setting init. r/w remarks C out_shortack in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 00300908 (b) 1 out short packet ack 0 none 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none epaintstat (epa interrupt status) C this register displays the interrupt status of the endpoint epa. d7 reserved d6 out_shortack shows a cause of interrupt directly. set to 1 when a short packet is received and ack is replied in the out transaction, out_tranack and this bits are set to 1 at the same time. d5 in_tranack shows a cause of interrupt directly. set to 1 when ack is received in the in transaction. d4 out_tranack shows a cause of interrupt directly. set to 1 when ack is replied in the out transaction. d3 in_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the in transaction. d2 out_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the out transaction. d1 in_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the in transaction, when an error occurred in the packet or when the handshake is failed in time-out. d0 out_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the out transaction or when an error occurred in the packet.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-44 epson s1c33e08 technical manual 0x300909: epbintstat (epb interrupt status) name address register name bit setting init. r/w remarks C out_shortack in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 00300909 (b) 1 out short packet ack 0 none 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none epbintstat (epb interrupt status) C this register displays the interrupt status of the endpoint epb. d7 reserved d6 out_shortack shows a cause of interrupt directly. set to 1 when a short packet is received and ack is replied in the out transaction, out_tranack and this bits are set to 1 at the same time. d5 in_tranack shows a cause of interrupt directly. set to 1 when ack is received in the in transaction. d4 out_tranack shows a cause of interrupt directly. set to 1 when ack is replied in the out transaction. d3 in_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the in transaction. d2 out_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the out transaction. d1 in_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the in transaction, when an error occurred in the packet or when the handshake is failed in time-out. d0 out_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the out transaction or when an error occurred in the packet.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-45 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30090a: epcintstat (epc interrupt status) name address register name bit setting init. r/w remarks C out_shortack in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 0030090a (b) 1 out short packet ack 0 none 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none epcintstat (epc interrupt status) C this register displays the interrupt status of the endpoint epc. d7 reserved d6 out_shortack shows a cause of interrupt directly. set to 1 when a short packet is received and ack is replied in the out transaction, out_tranack and this bits are set to 1 at the same time. d5 in_tranack shows a cause of interrupt directly. set to 1 when ack is received in the in transaction. d4 out_tranack shows a cause of interrupt directly. set to 1 when ack is replied in the out transaction. d3 in_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the in transaction. d2 out_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the out transaction. d1 in_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the in transaction, when an error occurred in the packet or when the handshake is failed in time-out. d0 out_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the out transaction or when an error occurred in the packet.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-46 epson s1c33e08 technical manual 0x30090b: epdintstat (epd interrupt status) name address register name bit setting init. r/w remarks C out_shortack in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 0030090b (b) 1 out short packet ack 0 none 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none epdintstat (epd interrupt status) C this register displays the interrupt status of the endpoint epd. d7 reserved d6 out_shortack shows a cause of interrupt directly. set to 1 when a short packet is received and ack is replied in the out transaction, out_tranack and this bits are set to 1 at the same time. d5 in_tranack shows a cause of interrupt directly. set to 1 when ack is received in the in transaction. d4 out_tranack shows a cause of interrupt directly. set to 1 when ack is replied in the out transaction. d3 in_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the in transaction. d2 out_trannak shows a cause of interrupt directly. set to 1 when nak is replied in the out transaction. d1 in_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the in transaction, when an error occurred in the packet or when the handshake is failed in time-out. d0 out_tranerr shows a cause of interrupt directly. set to 1 when stall is replied in the out transaction or when an error occurred in the packet.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-47 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300910: mainintenb (main interrupt enable) name address register name bit setting init. r/w remarks en sie_intstat en eprintstat endma_intstat enfifo_intstat C en ep0intstat en rcvep0setup d7 d6 d5 d4 d3C2 d1 d0 0 0 0 0 C 0 0 r/w r/w r/w r/w C r/w r/w 0 when being read. 00300910 (b) C 1 enabled 0 disabled 1 enabled 0 disabled mainintenb ( main interrupt enable ) this register enables/disables assertion of the interrupt signal (#int) with the cause of interrupt of the mainintstat register. setting the corresponding bit to 1 enables interrupt. ensie_intstat bit is valid during snooze as well.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-48 epson s1c33e08 technical manual 0x300911: sie_intenb (sie interrupt enable) name address register name bit setting init. r/w remarks envbus_changed ennonj endetectreset endetectsuspend enrcvsof endetectj C ensetaddresscmp d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 C 0 r/w r/w r/w r/w r/w r/w C r/w 0 when being read. 00300911 (b) C 1 enabled 0 disabled sie_intenb (sie interrupt enable ) 1 enabled 0 disabled this register enables/disables assertion of the sie_intstat bit of the mainintstat register with the cause of interrupt of the sie_intstat register. envbus_changed and ennonj bits are valid during snooze as well.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-49 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300912: eprintenb (epr interrupt enable) name address register name bit setting init. r/w remarks C enepdintstat enepcintstat enepbintstat enepaintstat d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300912 (b) C eprintenb (epr interrupt enable ) 1 enabled 0 disabled this register enables/disables assertion of the eprintstat bit of the mainintstat register with the cause of interrupt of the eprintstat register.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-50 epson s1c33e08 technical manual 0x300913: dma_intenb (dma interrupt enable) name address register name bit setting init. r/w remarks C endma_countup endma_cmp d7C2 d1 d0 C 0 0 C r/w r/w 0 when being read. 00300913 (b) C dma_intenb (dma interrupt enable) 1 enabled 0 disabled this register enables/disables assertion of the dma_intstat bit of the mainintstat register with the cause of interrupt of the dma_intstat register.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-51 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300914: fifo_intenb (fifo interrupt enable) name address register name bit setting init. r/w remarks endescriptorcmp C enfifo_in_cmp enfifo_out_cmp d7 d6C2 d1 d0 0 C 0 0 r/w C r/w r/w 0 when being read. 00300914 (b) C 1 enabled 0 disabled fifo_intenb (fifo interrupt enable) 1 enabled 0 disabled this register enables/disables assertion of the fifo_intstat bit of the mainintstat register with the cause of interrupt of the fifo_intstat register.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-52 epson s1c33e08 technical manual 0x300917: ep0intenb (ep0 interrupt enable) name address register name bit setting init. r/w remarks C enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7C6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300917 (b) ep0intenb (ep0 interrupt enable) C 1 enabled 0 disabled this register enables/disables assertion of the ep 0 intstat bit of the mainintstat register with the cause of interrupt of the ep0 intstat register.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-53 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300918: epaintenb (epa interrupt enable) name address register name bit setting init. r/w remarks C enout_shortack enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300918 (b) epaintenb (epa interrupt enable) C 1 enabled 0 disabled this register enables/disables assertion of the epaintstat bit of the eprintstat register with the cause of interrupt of the epaintstat register.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-54 epson s1c33e08 technical manual 0x300919: epbintenb (epb interrupt enable) name address register name bit setting init. r/w remarks C enout_shortack enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300919 (b) epbintenb (epb interrupt enable) C 1 enabled 0 disabled this register enables/disables assertion of the epbintstat bit of the eprintstat register with the cause of interrupt of the epbintstat register.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-55 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30091a: epcintenb (epc interrupt enable) name address register name bit setting init. r/w remarks C enout_shortack enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0030091a (b) epcintenb (epc interrupt enable) C 1 enabled 0 disabled this register enables/disables assertion of the epcintstat bit of the eprintstat register with the cause of interrupt of the epcintstat register.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-56 epson s1c33e08 technical manual 0x30091b: epdintenb (epd interrupt enable) name address register name bit setting init. r/w remarks C enout_shortack enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0030091b (b) epdintenb (epd interrupt enable) C 1 enabled 0 disabled this register enables/disables assertion of the epdintstat bit of the eprintstat register with the cause of interrupt of the epdintstat register.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-57 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300920: revisionnum (revision number) name address register name bit setting init. r/w remarks revisionnum[7] revisionnum[6] revisionnum[5] revisionnum[4] revisionnum[3] revisionnum[2] revisionnum[1] revisionnum[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 0 1 0 r 00300920 (b) revisionnum (revision number) revision number (0x12) this register shows the revision number of the usb function controller. this register is valid during snooze as well.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-58 epson s1c33e08 technical manual 0x300921: usb_control (usb control) name address register name bit setting init. r/w remarks disbusdetect enautonego insuspend startdetectj sendwakeup C activeusb d7 d6 d5 d4 d3 d2C1 d0 0 0 0 0 0 C 0 r/w r/w r/w r/w r/w C r/w 0 when being read. 00300921 (b) 1 disable bus detect 0 enable bus detect 1 enable auto negotiation 0 disable auto negotiation 1 monitor nonj C 0 do nothing 1 send remote wakeup signal 0 do nothing 1 start j-state detection 0 do nothing 1 activate usb 0 disactivate usb usb_control (usb control register) the operation setting is done for the usb. d7 disbusdetect setting this bit to 1 disables the automatic detection of the usb reset/suspend state. when this bit is set to 0 (to be cleared), activities on the usb bus is monitored to detect the reset/ suspend state. if the bus activities cannot be detected within 3 ms, the usb is determined to be suspend state. and if se0 longer than 2.5 microseconds is detected, the usb is determined to be reset state, and then the relevant cause of interrupt (detectreset, detectsuspend) is set. if the detectreset or the detectsuspend bit is set to 1 , set the disbusdetect bit to 1 to disable detection when the reset/suspend state is continued. when using the auto negotiation function, do not set this bit to 1. d6 enautonego this bit enables the auto negotiation function. the auto negotiation function automates the work sequence to be done after detecting the reset, from the end of the speed negotiation to determination of the speed mode. refer to the section describing operations for details of the auto negotiation. d5 insuspend this bit enables the detection of the nonj state. if the usb suspend state is detected and f/w is prepared. set this bit to 1 . to return from the suspended state, set this bit to 0 (to be cleared). the nonj state can be detected only when this bit is set. if the snooze function is not be used when the usb goes into the suspend state, set this bit. refer to description on operations for how to use the auto negotiation function. d4 startdetectj this bit enables the detection of the j state. after setting this bit and j-state is coming, detectj interrupt is set when endetectj is set. d3 sendwakeup setting this bit to 1 outputs the remotewakeup signal (k) to the usb port. within the time between 1 ms and 15 ms after starting to send the remotewakeup signal, set this bit to 0 (to be cleared) to stop sending the signals. d[2:1] reserved d0 activeusb since this bit is set to 0 (to be cleared) after hardware reset, all usb functions are stopped. the operation as a usb will be enabled by setting this bit to 1 after completing the setting of this ic.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-59 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300922: usb_status (usb status) name address register name bit setting init. r/w remarks vbus fs C linestate[1] linestate[0] d7 d6 d5C2 d1 d0 x 1 C x x r r C r 0 when being read. 00300922 (b) 1 fs mode (fix ed) 0 C 1 vbus=high 0 vbus=low C linestate[1:0] dp/dm 1 1 0 0 1 0 1 0 se1 k j se0 usb_status (usb status register) this register displays the status related to the usb. this register is valid during snooze as well. d7 vbus this bit displays the status of the usbvbus pin. d6 fs returns always 1 (fs mode). d[5:2] reserved d[1:0] linestate[1:0] shows the signal status on the usb cable. shows the value received by the fs receiver of the dp/dm. linestate linestate[1] 1 1 0 0 linestate[0] 1 0 1 0 dp/dm se1 k j se0
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-60 epson s1c33e08 technical manual 0x300923: xcvrcontrol (xcvr control) name address register name bit setting init. r/w remarks rpuenb C opmode[1] opmode[0] d7 d6C2 d1 d0 0 C 0 1 r/w C r/w 0 when being read. 00300923 (b) 1 enable pull-up 0 disable pull-up C opmode[1:0] operation mode 1 1 0 0 1 0 1 0 reserved disable bitstuffing and nrzi encoding non-driving normal operation xcvrcontrol (xcvr control register) the operation setting is done for the transceiver macro. d7 rpuenb this bit enables the d+ pull-up resistor. d[6:2] reserved d[1:0] opmode this bit sets the operation mode of the transceiver macro. this bit needs not be set up normally, excluding when the usb cable is pulled off (*) and during the test mode. opmode opmode[1] 1 1 0 0 opmode[0] 1 0 1 0 operation mode reserved disable bitstuffing and nrzi encoding non-driving normal operation * when the usb cable is pulled off, it is recommended to set this register to 0x01.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-61 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300924: usb_test (usb test) name address register name bit setting init. r/w remarks enusb_test C test_se0_nak test_j test_k test_packet d7 d6C4 d3 d2 d1 d0 0 C 0 0 0 0 r/w C r/w r/w r/w r/w 0 when being read. 00300924 (b) 1 enable usb test 0 do nothing C 1 test_se0_nak 0 do nothing 1 test_j 0 do nothing 1 test_k 0 do nothing 1 test_packet 0 do nothing usb_test (usb test) the operation setting is done in this register for the usb test mode. set the bit corresponding to the test mode specified by the setfeature request, and after completing the status stage, set the enusb_test bit to 1 and perform the test mode operation defined by the usb standard. d7 enusb_test when this bit is set to 1 , if one of the lower order 4 bits in the usb_test register is set to 1 , the ic will go into the test mode corresponding to the bit. when performing the test mode, the disbusdetect bit of the usb_control register must be set to 1 not to detect the usb suspend and the reset before performing the test. in addition, set the enautonego bit of the usb_control register to 0 (to be cleared) to disable the auto negotiation. note that the change to the test mode must be done after completing the status stage for the setfeature request. d[6:4] reserved d3 test_se0_nak by setting this bit to 1 and the enusb_test bit to 1 , the test_se0 _nak test mode can start. d2 test_j by setting this bit to 1 and the enusb_test bit to 1 , the test_j test mode can start. in this test mode, before enusb_test bit is set to 1, set opmode to 10 (disable bitstuffing and nrzi encoding). d1 test_k by setting this bit to 1 and the enusb_test bit to 1 , the test_k test mode can start. in this test mode, before enusb_test bit is set to 1, set opmode to 10 (disable bitstuffing and nrzi encoding). d0 test_packet by setting this bit to 1 , the test_packet test mode can start. since this test mode uses the endpoint epc, set the followings. ( 1 ) set the maxpacketsize of the endpoint epc to 64 or more, the direction of transfer to in and the endpointnumber to 0 xf to make the endpoint be ready to use. and allocate the fifo of the endpoint epc for 64 bytes or more. ( 2 ) do not overlap the above setting with the settings of the endpoints epa and epb. or clear the epaconfig_ 0 .enendpoint bit and epbconfig_0.enendpoint bit. ( 3 ) clear the fifo of the epc and write data for the following test packet into this fifo. ( 4 ) set the enin_tranerr of the epcintenb register to 0 (clear this bit). in_tranerr status is set to 1 at every time the test packet transmission completes. the data to write into the fifo in the packet transmission test mode are the following 53 bytes. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e since the sie adds the pid and crc to the test packet when sending it, the data to write into the fifo are from the data after the data 0 pid to the data before the crc 16 that are described as the test packet data in the usb standard rev. 2 . 0 . (note that test packet is defined only hs mode in usb specification.)
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-62 epson s1c33e08 technical manual 0x300925: epncontrol (endpoint control) name address register name bit setting init. r/w remarks allforcenak eprforcestall allfifo_clr C ep0fifo_clr d7 d6 d5 d4C1 d0 0 0 0 C 0 w w w C w 0 when being read. 00300925 (b) 1 set all forcenak 0 do nothing 1 set ep's forcestall 0 do nothing 1 clear all fifo C 0 do nothing 1 clear ep0 fifo 0 do nothing epncontrol (endpoint control ) this register sets operations of entire endpoints, and display them. d7 allforcenak set the forcenak bit of all endpoints to 1. d6 eprforcestall set the forcestall bit of epa, epb, epc and epd endpoints to 1. d5 allfifo_clr clear the fifos of all endpoints. after setting the area of the respective endpoints, be sure to set this bit to 1 to clear the fifos of all endpoints. this bit is automatically set 0 (to be cleared) after completing the fifo clear operation. do not set this bit to 1 during start operation of the general port (when the dma_running bit of the dma_control register is 1 ). otherwise, a malfunction may occur. d[4:1] reserved d0 ep0fifo_clr clear the fifo of the endpoint ep 0 . this bit is automatically set 0 (to be cleared) after completing the fifo clear operation.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-63 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300926: eprfifo_clr (epr fifo clear) name address register name bit setting init. r/w remarks C epdfifo_clr epcfifo_clr epbfifo_clr epafifo_clr d7C4 d3 d2 d1 d0 C 0 0 0 0 C w w w w 0 when being read. 00300926 (b) C 1 clear epc fifo 0 do nothing 1 clear epb fifo 0 do nothing 1 clear epa fifo 0 do nothing eprfifo_clr (epr fifo clear) 1 clear epd fifo 0 do nothing this register clears the fifo of the endpoints. d[7:4] reserved d3 epdfifo_clr clear the fifo of the endpoint epd. this bit is automatically set 0 (to be cleared) after completing the fifo clear operation. do not set this bit to 1 when the endpoint epd is connected to the general port (the joinepddma bit of the dma_join register is set to 1 ) and the start operation of the general port is being done (when the dma_running bit of the dma_control register is 1 ). otherwise, a malfunction may occur. d2 epcfifo_clr clear the fifo of the endpoint epc. this bit is automatically set 0 (to be cleared) after completing the fifo clear operation. do not set this bit to 1 when the endpoint epc is connected to the general port (the joinepcdma bit of the dma_join register is set to 1 ) and the start operation of the general port is being done (when the dma_running bit of the dma_control register is 1 ). otherwise, a malfunction may occur. d1 epbfifo_clr clear the fifo of the endpoint epb. this bit is automatically set 0 (to be cleared) after completing the fifo clear operation. do not set this bit to 1 when the endpoint epb is connected to the general port (the joinepbdma bit of the dma_join register is set to 1 ) and the start operation of the general port is being done (when the dma_running bit of the dma_control register is 1 ). otherwise, a malfunction may occur. d0 epafifo_clr clear the fifo of the endpoint epa. this bit is automatically set 0 (to be cleared) after completing the fifo clear operation. do not set this bit to 1 when the endpoint epa is connected to the general port (the joinepadma bit of the dma_join register is set to 1 ) and the start operation of the general port is being done (when the dma_running bit of the dma_control register is 1 ). otherwise, a malfunction may occur.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-64 epson s1c33e08 technical manual 0x30092e: framenumber_h (frame number high) name address register name bit setting init. r/w remarks fninvalid C framenumber[10] framenumber[9] framenumber[8] d7 d6C3 d2 d1 d0 1 C 0 0 0 r C r 0 when being read. 0030092e (b) 1 invalid frame number 0 valid frame number C frame number high framenumber_h (frame number high) this register displays the usb frame number that is updated every time the sof token is received. when frame numbers are acquired, the framenumber_h and the framenumber_l registers must be accessed as a pair. when accessing them, access the framenumber_h register first. d7 fninvalid when an error occurs in the received sof packet, this bit is set to 1. d[6:3] reserved d[2:0] framenumber[10:8] the upper order 3 bits in the framenumber field of the received sof packet are stored in these bits.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-65 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30092f: framenumber_l (frame number low) name address register name bit setting init. r/w remarks framenumber[7] framenumber[6] framenumber[5] framenumber[4] framenumber[3] framenumber[2] framenumber[1] framenumber[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 0030092f (b) framenumber_l (frame number low) frame number low d[7:0] framenumber[7:0] the lower order 8 bits in the framenumber field of the received sof packet are stored in these bits.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-66 epson s1c33e08 technical manual 0x300930C0x300937: ep0setup_0 (ep0 setup 0)Cep0setup_7 (ep0 setup 7) name address register name bit setting init. r/w remarks ep0setup_n[7] ep0setup_n[6] ep0setup_n[5] ep0setup_n[4] ep0setup_n[3] ep0setup_n[2] ep0setup_n[1] ep0setup_n[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300930 | 00300937 (b) ep0setup_0 (ep0 set-up 0) | ep0setup_7 (ep0 set-up 7) endpoint 0 set-up data 0 | endpoint 0 set-up data 7 eight-byte data received at the endpoint ep 0 setup stage are stored from the ep0setup_0 sequentially. 0x300930: ep0setup_0 bmrequesttype is set. 0x300931: ep0setup_1 brequest is set. 0x300932: ep0setup_2 the lower order 8 bits in wvalue are set. 0x300933: ep0setup_3 the upper order 8 bits in wvalue are set. 0x300934: ep0setup_4 the lower order 8 bits in windex are set. 0x300935: ep0setup_5 the upper order 8 bits in windex are set. 0x300936: ep0setup_6 the lower order 8 bits in wlength are set. 0x300937: ep0setup_7 the upper order 8 bits in wlength are set.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-67 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300938: usb_address (usb address) name address register name bit setting init. r/w remarks autosetaddress usb_address[6] usb_address[5] usb_address[4] usb_address[3] usb_address[2] usb_address[1] usb_address[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w 00300938 (b) usb_address (usb address) usb address 1 auto set address 0 do nothing this register sets up the usb address. d7 autosetaddress sets up the usb address automatically. if this bit is set to 1 after receiving the setaddress request and before implementing the status stage, the address received by the setaddress request will be written into the usb_address register when the status stage completes. the processing procedure of the setaddress request using this f unction is as follows. ( 1 ) the setup transaction of the setaddress request completes. the rcvep 0 setup bit of the mainintstat register is set to 1 . read the ep0setup_0C7 registers and interpret the request. ( 2 ) set the autosetaddress bit. ( 3 ) set the inxout bit of the ep0 control register. ( 4 ) clear the forcenak bit of the ep0 controlin register, and set the enshortpkt bit. ( 5 ) wait for the end of the status stage. the setaddresscmp bit of the sie_intstat register is set to 1. d[6:0] usb_address these bits set up the usb address. the usb address is written automatically by the autosetaddress function. or it can be written.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-68 epson s1c33e08 technical manual 0x300939: ep0control (ep0 control) name address register name bit setting init. r/w remarks inxout C replydescriptor d7 d6C1 d0 0 C 0 r/w C w 0 when being read. 00300939 (b) 1 in 0 out 1 reply descriptor 0 do nothing C ep0control (ep0 control) this register sets up the endpoint ep 0. d7 inxout set the transfer direction of the endpoint ep 0. judging from the request received at the setup stage, set a value in this bit. if the data stage exists, set the transfer direction at the data stage into this bit. as the setup of the forcenak bits of the ep 0 controlin and ep0 controlout registers completes when the setup stage completes, clear them during execution of the data stage or the status stage. after the data stage is completed, set this bit again conforming to the direction of the status stage. when the transfer direction of the data stage is in, the transfer direction of the status stage is out. therefore, set this bit to 0 . when the transfer direction of the data stage is out, or there is no data stage, the transfer direction of the status stage is in. therefore, clear the fifo of the endpoint ep 0 , and set this bit to 1. for the in or out transactions which have a transfer direction different from that of this bit, nak response is done. however, if the forcestall bit of the ep 0 controlin or ep0 controlout register with the transaction direction corresponding to the above one, is set, the stall response will be done. d[6:1] reserved d0 replydescriptor executes the descriptor reply function. if this bit is set to 1 , this bit replies as much descriptor data as specified as maxpacketsize from the fifo, responding to the in transaction of the endpoint ep 0 . the descriptor data start from the address specified in the descadrs_h, l register, and its data size is specified in the descsize_h, l register. since these setting values are updated during execution of the descriptor reply function, set these setting values every time setting the replydescriptor bit. in every transaction, the descadrs_h, l register is incremented as many as the number of data that were sent, while the descsize_h, l register is decremented as many as the number of data that were sent. when the data transmission ends after sending as many data as specified in the descsize_h, l or when a transaction other than the in transaction is done, the descriptor reply function ends, the replydescriptor bit is set to 0 (to be cleared) and the in_tranack bit of the epnintstat register is set to 1. refer to the section describing operations, for details.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-69 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30093a: ep0controlin (ep0 control in) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 C 0 C 0 0 0 0 0 C r/w C r r/w r/w r/w r/w 0 when being read. 0 when being read. 0030093a (b) 1 enable short packet 0 do nothing C C toggle sequence bit ep0controlin (ep0 control in) 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing C enshortpkt C togglestat toggleset toggleclr forcenak forcestall this register sets the operations related to the in transaction of the endpoint ep 0 and displays their status. d7 reserved d6 enshortpkt setting this bit to 1 enables to send the data within the fifo that is less than the quantity specified for the maxpacketsize, as a short packet for the in transaction of the endpoint ep 0 . when the in transaction that transmitted short packets completes, this bit is automatically set to 0 (to be cleared). when a packet of the max packet size is transmitted, this bit is not cleared. if this bit is set to 1 when the fifo has no data, a zero-length packet can be transmitted for the in token from the host. if the data is written into the fifo that is in the transmission process with the packet to which this bit is set, that data may be included in transmission. therefore, do not write into the fifo until the packet transmission completes and this bit is cleared. d5 reserved d4 togglestat shows the status of the toggle sequence bit in the in transaction of the endpoint ep 0. d3 toggleset sets the toggle sequence bit in the in transaction of the e ndpoint ep 0, to 1. d2 toggleclr sets the toggle sequence bit in the in transaction of the e ndpoint ep 0, to 0 (clear). d1 forcenak if this bit is set to 1 , the nak response is done for the in transaction of the endpoint ep0 , regardless of the fifo data quantity. when the rcvep 0 setup bit of the mainintstat register is set to 1 after completion of the setup stage, this bit is set to 1 , and this bit cannot be set to 0 (to be cleared) as long as the rcvep0 setup bit is 1. when the in transaction that transmitted short packets completes, this bit is set to 1. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction. d0 forcestall if this bit is set to 1 , the stall response is done for the in transaction of the endpoint ep0 . this bit has a priority over the setting of the forcenak bit. when the rcvep 0 setup bit of the mainintstat register is set to 1 after completion of the setup stage, this bit is set to 0 (to be cleared), and this bit cannot be set to 1 as long as the rcvep0setup bit is 1. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-70 epson s1c33e08 technical manual 0x30093b: ep0controlout (ep0 control out) name address register name bit setting init. r/w remarks d7 d6C5 d4 d3 d2 d1 d0 0 C 0 0 0 0 0 r/w C r w w r/w r/w 0 when being read. 0 when being read. 0030093b (b) 1 auto force nak 0 do nothing C toggle sequence bit ep0controlout (ep0 control out ) autoforcenak C togglestat toggleset toggleclr forcenak forcestall 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing this register sets the operations related to the out transaction of the endpoint ep 0 and displays their status. d7 autoforcenak sets the forcenak bit of this register to 1 when the out transaction of the endpoint ep0 completes normally. d[6:5] reserved d4 togglestat shows the status of the toggle sequence bit in the out transaction of the endpoint ep 0. d3 toggleset sets the toggle sequence bit in the out transaction of the e ndpoint ep 0, to 1. d2 toggleclr sets the toggle sequence bit in the out transaction of the e ndpoint ep 0, to 0 (clear). d1 forcenak if this bit is set to 1 , the nak response is done for the out transaction of the endpoint ep0 , regardless of the fifo space capacity. when the rcvep 0 setup bit of the mainintstat register is set to 1 after completion of the setup stage, this bit is set to 1 , and this bit cannot be set to 0 (to be cleared) as long as the rcvep0 setup bit is 1 . when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction. d0 forcestall if this bit is set to 1 , the stall response is done for the out transaction of the endpoint ep0 . this bit has a priority over the setting of the forcenak bit. when the rcvep 0 setup bit of the mainintstat register is set to 1 after completion of the setup stage, this bit is set to 0 (to be cleared), and this bit cannot be set to 1 as long as the rcvep0setup bit is 1. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-71 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30093f: ep0maxsize (ep0 max packet size) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2C0 C 0 0 0 1 C C r/w C 0 when being read. 0 when being read. 0030093f (b) C C endpoint ep0 max pa ck et siz e ep0maxsiz e (ep0 max pac ket size) C ep0maxsize[6] ep0maxsize[5] ep0maxsize[4] ep0maxsize[3] C d7 reserved d[6:3] ep0maxsize[6:3] this register sets the maxpacketsize of the endpoint ep 0. the size of this endpoint can be set to 8, 16, 32 or 64 bytes. d[2:0] reserved
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-72 epson s1c33e08 technical manual 0x300940: epacontrol (epa control) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w r/w r w w r/w r/w 0 when being read. 00300940 (b) epacontrol (epa control) autoforcenak enshortpkt disaf_nak_short togglestat toggleset toggleclr forcenak forcestall toggle sequence bit 1 auto force nak 0 do nothing 1 enable short packet 0 do nothing 1 disable auto force 0 auto force nak short 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing this register sets operations of the endpoint epa. d7 autoforcenak sets the forcenak bit of this register to 1 when the transaction of the endpoint epa completes normally. d6 enshortpkt setting this bit to 1 enables to send the data within the fifo that is less than the quantity specified for the maxpacketsize, as a short packet for the in transaction of the endpoint epa. when the in transaction that transmitted short packets completes, this bit is automatically set to 0 (to be cleared). when a packet of the max packet size is transmitted, this bit is not cleared. if this bit is set to 1 when the fifo has no data, a zero-length packet can be transmitted for the in token from the host. if the data is written into the fifo that is in the transmission process with the packet to which this bit is set, that data may be included in transmission. therefore, do not write into the fifo until the packet transmission completes and this bit is cleared. d5 disaf_nak_short when this bit is set to 0 (default setting) and the packet that was received at normal completion time of the out transaction is a short packet, the forcenak bit is automatically set to 1 . when this bit is set to 1, this function is disabled. when the autoforcenak bit is set to 1 , the autoforcenak bit has a priority. d4 togglestat shows the status of the toggle sequence bit of the endpoint epa. d3 toggleset set the toggle sequence bit of the endpoint epa to 1. d2 toggleclr set the toggle sequence bit of the endpoint epa to 0 (to be cleared). d1 forcenak if this bit is set to 1 , the nak response is done for the transaction of the endpoint epa regardless of the fifo data quantity and space capacity. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction. d0 forcestall if this bit is set to 1 , the stall response is done for the transaction of the endpoint epa. this bit has a priority over the setting of the forcenak bit. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-73 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300941: epbcontrol (epb control) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w r/w r w w r/w r/w 0 when being read. 00300941 (b) epbcontrol (epb control) autoforcenak enshortpkt disaf_nak_short togglestat toggleset toggleclr forcenak forcestall toggle sequence bit 1 auto force nak 0 do nothing 1 enable short packet 0 do nothing 1 disable auto force 0 auto force nak short 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing this register sets operations of the endpoint epb. d7 autoforcenak sets the forcenak bit of this register to 1 when the transaction of the endpoint epb completes normally. d6 enshortpkt setting this bit to 1 enables to send the data within the fifo that is less than the quantity specified for the maxpacketsize, as a short packet for the in transaction of the endpoint epb. when the in transaction that transmitted short packets completes, this bit is automatically set to 0 (to be cleared). when a packet of the max packet size is transmitted, this bit is not cleared. if this bit is set to 1 when the fifo has no data, a zero-length packet can be transmitted for the in token from the host. if the data is written into the fifo that is in the transmission process with the packet to which this bit is set, that data may be included in transmission. therefore, do not write into the fifo until the packet transmission completes and this bit is cleared. d5 disaf_nak_short when this bit is set to 0 (default setting) and the packet that was received at normal completion time of the out transaction is a short packet, the forcenak bit is automatically set to 1 . when this bit is set to 1, this function is disabled. when the autoforcenak bit is set to 1 , the autoforcenak bit has a priority. d4 togglestat shows the status of the toggle sequence bit of the endpoint epb. d3 toggleset set the toggle sequence bit of the endpoint epb to 1. d2 toggleclr set the toggle sequence bit of the endpoint epb to 0 (to be cleared). d1 forcenak if this bit is set to 1 , the nak response is done for the transaction of the endpoint epb regardless of the fifo data quantity and space capacity. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction. d0 forcestall if this bit is set to 1 , the stall response is done for the transaction of the endpoint epb. this bit has a priority over the setting of the forcenak bit. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-74 epson s1c33e08 technical manual 0x300942: epccontrol (epc control) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w r/w r w w r/w r/w 0 when being read. 00300942 (b) epccontrol (epc control) autoforcenak enshortpkt disaf_nak_short togglestat toggleset toggleclr forcenak forcestall toggle sequence bit 1 auto force nak 0 do nothing 1 enable short packet 0 do nothing 1 disable auto force 0 auto force nak short 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing this register sets operations of the endpoint epc. d7 autoforcenak sets the forcenak bit of this register to 1 when the transaction of the endpoint epc completes normally. d6 enshortpkt setting this bit to 1 enables to send the data within the fifo that is less than the quantity specified for the maxpacketsize, as a short packet for the in transaction of the endpoint epc. when the in transaction that transmitted short packets completes, this bit is automatically set to 0 (to be cleared). when a packet of the max packet size is transmitted, this bit is not cleared. if this bit is set to 1 when the fifo has no data, a zero-length packet can be transmitted for the in token from the host. if the data is written into the fifo that is in the transmission process with the packet to which this bit is set, that data may be included in transmission. therefore, do not write into the fifo until the packet transmission completes and this bit is cleared. d5 disaf_nak_short when this bit is set to 0 (default setting) and the packet that was received at normal completion time of the out transaction is a short packet, the forcenak bit is automatically set to 1 . when this bit is set to 1, this function is disabled. when the autoforcenak bit is set to 1 , the autoforcenak bit has a priority. d4 togglestat shows the status of the toggle sequence bit of the endpoint epc. d3 toggleset set the toggle sequence bit of the endpoint epc to 1. d2 toggleclr set the toggle sequence bit of the endpoint epc to 0 (to be cleared). d1 forcenak if this bit is set to 1 , the nak response is done for the transaction of the endpoint epc regardless of the fifo data quantity and space capacity. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction. d0 forcestall if this bit is set to 1 , the stall response is done for the transaction of the endpoint epc. this bit has a priority over the setting of the forcenak bit. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-75 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300943: epdcontrol (epd control) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w r/w r w w r/w r/w 0 when being read. 00300943 (b) epdcontrol (epd control) autoforcenak enshortpkt disaf_nak_short togglestat toggleset toggleclr forcenak forcestall toggle sequence bit 1 auto force nak 0 do nothing 1 enable short packet 0 do nothing 1 disable auto force 0 auto force nak short 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing this register sets operations of the endpoint epd. d7 autoforcenak sets the forcenak bit of this register to 1 when the transaction of the endpoint epd completes normally. d6 enshortpkt setting this bit to 1 enables to send the data within the fifo that is less than the quantity specified for the maxpacketsize, as a short packet for the in transaction of the endpoint epd. when the in transaction that transmitted short packets completes, this bit is automatically set to 0 (to be cleared). when a packet of the max packet size is transmitted, this bit is not cleared. if this bit is set to 1 when the fifo has no data, a zero-length packet can be transmitted for the in token from the host. if the data is written into the fifo that is in the transmission process with the packet to which this bit is set, that data may be included in transmission. therefore, do not write into the fifo until the packet transmission completes and this bit is cleared. d5 disaf_nak_short when this bit is set to 0 (default setting) and the packet that was received at normal completion time of the out transaction is a short packet, the forcenak bit is automatically set to 1 . when this bit is set to 1, this function is disabled. when the autoforcenak bit is set to 1 , the autoforcenak bit has a priority. d4 togglestat shows the status of the toggle sequence bit of the endpoint epd. d3 toggleset set the toggle sequence bit of the endpoint epd to 1. d2 toggleclr set the toggle sequence bit of the endpoint epd to 0 (to be cleared). d1 forcenak if this bit is set to 1 , the nak response is done for the transaction of the endpoint epd regardless of the fifo data quantity and space capacity. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction. d0 forcestall if this bit is set to 1 , the stall response is done for the transaction of the endpoint epd. this bit has a priority over the setting of the forcenak bit. when a transaction has been being done for a certain period of time, the setting of this bit will be enabled from the next transaction.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-76 epson s1c33e08 technical manual 0x300950: epamaxsize_h (epa max packet size high) 0x300951: epamaxsize_l (epa max packet size low) name address register name bit setting init. r/w remarks C epamaxsize[9] epamaxsize[8] d7C2 d1 d0 C 0 0 C r/w 0 when being read. 00300950 (b) C endpoint epa max packet size epamaxsize_h (epa max packet size high) epamaxsize[7] epamaxsize[6] epamaxsize[5] epamaxsize[4] epamaxsize[3] epamaxsize[2] epamaxsize[1] epamaxsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 00300951 (b) epamaxsize_l (epa max packet size low) endpoint epa max packet size epamaxsize[9:0] this register sets the maxpacketsize of the endpoint epa. when using this endpoint for the bulk transfer, 8, 16, 32, or 64 bytes should be set. when using this endpoint for the interrupt transfer, up to 64 bytes can be set. if the area of the endpoint epa is smaller than specified here, the macro does not operate normally.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-77 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300952: epaconfig_0 (epa configuration 0) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 C 0 0 0 0 r/w r/w r/w C r/w 0 when being read. 00300952 (b) C endpoint number (0x1 to 0xf) epaconfig_0 (epa configuration 0 ) inxout togglemode enendpoint C endpointnumber[3] endpointnumber[2] endpointnumber[1] endpointnumber[0] 1 in 0 out 1 enable endpoint 0 disable endpoint 1 always toggle 0 normal toggle this register sets up the endpoint epa. perform the setup so that combination of the endpointnumber and the inxout does not overlap with those of other endpoints. d7 inxout set the transfer direction of the endpoint. d6 togglemode set the operation mode of the toggle sequence bit. (only for t he in transaction) normal toggle - perform the toggle only when the transaction ends normally. always toggle - always perform the toggle for every transaction. d5 enendpoint setting this bit to 1 enables this endpoint. when this bit is 0 , access to an endpoint is neglected. perform the setup according to the setconfiguration request from the host. d4 reserved d[3:0] endpointnumber set an endpoint number between 0x1 and 0 xf.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-78 epson s1c33e08 technical manual 0x300953: epaconfig_1 (epa configuration 1) name address register name bit setting init. r/w remarks d7 d6 d5C0 0 0 C r/w r/w C 0 when being read. 00300953 (b) C epaconfig_1 (epa configuration 1 ) iso iso_crcmode C 1 iso 0 non-iso 1 crc mode 0 normal iso this register sets up the endpoint epa. perform the setup so that combination of the endpointnumber and the inxout does not overlap with those of other endpoints. d7 iso set the isochronous mode. d6 iso_crcmode according to usb spec, a packet must be discarded when crc error occurs in isochronous transaction. when this bit is set, a packet with crc error is not discarded. this bit is valid when iso bit (d 7) is set. d[5:0] reserved
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-79 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300954: epbmaxsize_h (epb max packet size high) 0x300955: epbmaxsize_l (epb max packet size low) name address register name bit setting init. r/w remarks C epbmaxsize[9] epbmaxsize[8] d7C2 d1 d0 C 0 0 C r/w 0 when being read. 00300954 (b) C endpoint epb max packet size epbmaxsize_h (epb max packet size high) epbmaxsize[7] epbmaxsize[6] epbmaxsize[5] epbmaxsize[4] epbmaxsize[3] epbmaxsize[2] epbmaxsize[1] epbmaxsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 00300955 (b) epbmaxsize_l (epb max packet size low) endpoint epb max packet size epbmaxsize[9:0] this register sets the maxpacketsize of the endpoint epb. when using this endpoint for the bulk transfer, 8, 16, 32, or 64 bytes should be set. when using this endpoint for the interrupt transfer, up to 64 bytes can be set. if the area of the endpoint epb is smaller than specified here, the macro does not operate normally.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-80 epson s1c33e08 technical manual 0x300956: epbconfig_0 (epb configuration 0) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 C 0 0 0 0 r/w r/w r/w C r/w 0 when being read. 00300956 (b) C endpoint number (0x1 to 0xf) epbconfig_0 (epb configuration 0 ) inxout togglemode enendpoint C endpointnumber[3] endpointnumber[2] endpointnumber[1] endpointnumber[0] 1 in 0 out 1 enable endpoint 0 disable endpoint 1 always toggle 0 normal toggle this register sets up the endpoint epb. perform the setup so that combination of the endpointnumber and the inxout does not overlap with those of other endpoints. d7 inxout set the transfer direction of the endpoint. d6 togglemode set the operation mode of the toggle sequence bit. (only for t he in transaction) normal toggle - perform the toggle only when the transaction ends normally. always toggle - always perform the toggle for every transaction. d5 enendpoint setting this bit to 1 enables this endpoint. when this bit is 0 , access to an endpoint is neglected. perform the setup according to the setconfiguration request from the host. d4 reserved d[3:0] endpointnumber set an endpoint number between 0x1 and 0 xf.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-81 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300957: epbconfig_1 (epb configuration 1) name address register name bit setting init. r/w remarks d7 d6 d5C0 0 0 C r/w r/w C 0 when being read. 00300957 (b) C epbconfig_1 (epb configuration 1 ) iso iso_crcmode C 1 iso 0 non-iso 1 crc mode 0 normal iso this register sets up the endpoint epb. perform the setup so that combination of the endpointnumber and the inxout does not overlap with those of other endpoints. d7 iso set the isochronous mode. d6 iso_crcmode according to usb spec, a packet must be discarded when crc error occurs in isochronous transaction. when this bit is set, a packet with crc error is not discarded. this bit is valid when iso bit (d 7) is set. d[5:0] reserved
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-82 epson s1c33e08 technical manual 0x300958: epcmaxsize_h (epc max packet size high) 0x300959: epcmaxsize_l (epc max packet size low) name address register name bit setting init. r/w remarks C epcmaxsize[9] epcmaxsize[8] d7C2 d1 d0 C 0 0 C r/w 0 when being read. 00300958 (b) C endpoint epc max packet size epcmaxsize_h (epc max packet size high) epcmaxsize[7] epcmaxsize[6] epcmaxsize[5] epcmaxsize[4] epcmaxsize[3] epcmaxsize[2] epcmaxsize[1] epcmaxsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 00300959 (b) epcmaxsize_l (epc max packet size low) endpoint epc max packet size epcmaxsize[9:0] this register sets the maxpacketsize of the endpoint epc. when using this endpoint for the bulk transfer, 8, 16, 32, or 64 bytes should be set. when using this endpoint for the interrupt transfer, up to 64 bytes can be set. if the area of the endpoint epc is smaller than specified here, the macro does not operate normally.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-83 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30095a: epcconfig_0 (epc configuration 0) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 C 0 0 0 0 r/w r/w r/w C r/w 0 when being read. 0030095a (b) C endpoint number (0x1 to 0xf) epcconfig_0 (epc configuration 0 ) inxout togglemode enendpoint C endpointnumber[3] endpointnumber[2] endpointnumber[1] endpointnumber[0] 1 in 0 out 1 enable endpoint 0 disable endpoint 1 always toggle 0 normal toggle this register sets up the endpoint epc. perform the setup so that combination of the endpointnumber and the inxout does not overlap with those of other endpoints. d7 inxout set the transfer direction of the endpoint. d6 togglemode set the operation mode of the toggle sequence bit. (only for t he in transaction) normal toggle - perform the toggle only when the transaction ends normally. always toggle - always perform the toggle for every transaction. d5 enendpoint setting this bit to 1 enables this endpoint. when this bit is 0 , access to an endpoint is neglected. perform the setup according to the setconfiguration request from the host. d4 reserved d[3:0] endpointnumber set an endpoint number between 0x1 and 0 xf.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-84 epson s1c33e08 technical manual 0x30095b: epcconfig_1 (epc configuration 1) name address register name bit setting init. r/w remarks d7 d6 d5C0 0 0 C r/w r/w C 0 when being read. 0030095b (b) C epcconfig_1 (epc configuration 1 ) iso iso_crcmode C 1 iso 0 non-iso 1 crc mode 0 normal iso this register sets up the endpoint epc. perform the setup so that combination of the endpointnumber and the inxout does not overlap with those of other endpoints. d7 iso set the isochronous mode. d6 iso_crcmode according to usb spec, a packet must be discarded when crc error occurs in isochronous transaction. when this bit is set, a packet with crc error is not discarded. this bit is valid when iso bit (d 7) is set. d[5:0] reserved
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-85 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30095c: epdmaxsize_h (epd max packet size high) 0x30095d: epdmaxsize_l (epd max packet size low) name address register name bit setting init. r/w remarks C epdmaxsize[9] epdmaxsize[8] d7C2 d1 d0 C 0 0 C r/w 0 when being read. 0030095c (b) C endpoint epd max packet size epdmaxsize_h (epd max packet size high) epdmaxsize[7] epdmaxsize[6] epdmaxsize[5] epdmaxsize[4] epdmaxsize[3] epdmaxsize[2] epdmaxsize[1] epdmaxsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030095d (b) epdmaxsize_l (epd max packet size low) endpoint epd max packet size epdmaxsize[9:0] this register sets the maxpacketsize of the endpoint epd. when using this endpoint for the bulk transfer, 8, 16, 32, or 64 bytes should be set. when using this endpoint for the interrupt transfer, up to 64 bytes can be set. if the area of the endpoint epd is smaller than specified here, the macro does not operate normally.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-86 epson s1c33e08 technical manual 0x30095e: epdconfig_0 (epd configuration 0) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 C 0 0 0 0 r/w r/w r/w C r/w 0 when being read. 0030095e (b) C endpoint number (0x1 to 0xf) epdconfig_0 (epd configuration 0 ) inxout togglemode enendpoint C endpointnumber[3] endpointnumber[2] endpointnumber[1] endpointnumber[0] 1 in 0 out 1 enable endpoint 0 disable endpoint 1 always toggle 0 normal toggle this register sets up the endpoint epd. perform the setup so that combination of the endpointnumber and the inxout does not overlap with those of other endpoints. d7 inxout set the transfer direction of the endpoint. d6 togglemode set the operation mode of the toggle sequence bit. (only for t he in transaction) normal toggle - perform the toggle only when the transaction ends normally. always toggle - always perform the toggle for every transaction. d5 enendpoint setting this bit to 1 enables this endpoint. when this bit is 0 , access to an endpoint is neglected. perform the setup according to the setconfiguration request from the host. d4 reserved d[3:0] endpointnumber set an endpoint number between 0x1 and 0 xf.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-87 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30095f: epdconfig_1 (epd configuration 1) name address register name bit setting init. r/w remarks d7 d6 d5C0 0 0 C r/w r/w C 0 when being read. 0030095f (b) C epdconfig_1 (epd configuration 1 ) iso iso_crcmode C 1 iso 0 non-iso 1 crc mode 0 normal iso this register sets up the endpoint epd. perform the setup so that combination of the endpointnumber and the inxout does not overlap with those of other endpoints. d7 iso set the isochronous mode. d6 iso_crcmode according to usb spec, a packet must be discarded when crc error occurs in isochronous transaction. when this bit is set, a packet with crc error is not discarded. this bit is valid when iso bit (d 7) is set. d[5:0] reserved
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-88 epson s1c33e08 technical manual 0x300970: epastartadrs_h (epa fifo start address high) 0x300971: epastartadrs_l (epa fifo start address low) name address register name bit setting init. r/w remarks C epastartadrs[11] epastartadrs[10] epastartadrs[9] epastartadrs[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300970 (b) C endpoint epa start address epastartadrs_h (epa fifo start address high) epastartadrs[7] epastartadrs[6] epastartadrs[5] epastartadrs[4] epastartadrs[3] epastartadrs[2] C d7 d6 d5 d4 d3 d2 d1C0 0 0 0 0 0 0 C r/w C 0 when being read. 00300971 (b) C endpoint epa start address epastartadrs_l (epa fifo start address low) epastartadrs[11:2] sets the start address of the fifo area allocated to the endpoi nt epa. the area that is allocated to the endpoint epa is from the address set by the epastartadrs and to the address one byte before the one set by the epbstartadrs. after setting the startadrs of all endpoints, be sure to set the allfifo_clr bit of the epncontrol register to 1 to clear all fifos. if the epamaxsize of the endpoint epa is larger than the area specified in here, the macro does not operate normally. set the total of the fifo area secured for all endpoints does not exceed the total capacity of the built-in ram. allocate the fifo area to the endpoints in the order from the lower order address to higher order address like ep 0 , epa, epb, epc, epd. the fifo of the endpoint ep 0 is allocated from the address 0 to up to the size specified as the maxpacketsize of the endpoint ep 0 set in the ep0 maxsize register. allocate the succeeding area for other endpoints. since the fifo capacity is 1 k bytes, do not let the epd end address exceed 0x3 ff. and do not let the epastartadrs exceed the setting value of the epbstartadrs.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-89 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300972: epbstartadrs_h (epb fifo start address high) 0x300973: epbstartadrs_l (epb fifo start address low) name address register name bit setting init. r/w remarks C epbstartadrs[11] epbstartadrs[10] epbstartadrs[9] epbstartadrs[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300972 (b) C endpoint epb start address epbstartadrs_h (epb fifo start address high) epbstartadrs[7] epbstartadrs[6] epbstartadrs[5] epbstartadrs[4] epbstartadrs[3] epbstartadrs[2] C d7 d6 d5 d4 d3 d2 d1C0 0 0 0 0 0 0 C r/w C 0 when being read. 00300973 (b) C endpoint epb start address epbstartadrs_l (epb fifo start address low) epbstartadrs[11:2] sets the start address of the fifo area allocated to the endpoi nt epb. the area that is allocated to the endpoint epb is from the address set by the epbstartadrs and to the address one byte before the one set by the epcstartadrs. after setting the startadrs of all endpoints, be sure to set the allfifo_clr bit of the epncontrol register to 1 to clear all fifos. if the epbmaxsize of the endpoint epb is larger than the area specified in here, the macro does not operate normally. set the total of the fifo area secured for all endpoints does not exceed the total capacity of the built-in ram. allocate the fifo area to the endpoints in the order from the lower order address to higher order address like ep 0 , epa, epb, epc, epd. the fifo of the endpoint ep 0 is allocated from the address 0 to up to the size specified as the maxpacketsize of the endpoint ep 0 set in the ep0 maxsize register. allocate the succeeding area for other endpoints. since the fifo capacity is 1 k bytes, do not let the epd end address exceed 0x3 ff. and do not let the epbstartadrs exceed the setting value of the epcstartadrs.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-90 epson s1c33e08 technical manual 0x300974: epcstartadrs_h (epc fifo start address high) 0x300975: epcstartadrs_l (epc fifo start address low) name address register name bit setting init. r/w remarks C epcstartadrs[11] epcstartadrs[10] epcstartadrs[9] epcstartadrs[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300974 (b) C endpoint epc start address epcstartadrs_h (epc fifo start address high) epcstartadrs[7] epcstartadrs[6] epcstartadrs[5] epcstartadrs[4] epcstartadrs[3] epcstartadrs[2] C d7 d6 d5 d4 d3 d2 d1C0 0 0 0 0 0 0 C r/w C 0 when being read. 00300975 (b) C endpoint epc start address epcstartadrs_l (epc fifo start address low) epcstartadrs[11:2] sets the start address of the fifo area allocated to the endpoi nt epc. the area that is allocated to the endpoint epc is from the address set by the epcstartadrs and to the address one byte before the one set by the epdstartadrs. after setting the startadrs of all endpoints, be sure to set the allfifo_clr bit of the epncontrol register to 1 to clear all fifos. if the epcmaxsize of the endpoint epc is larger than the area specified in here, the macro does not operate normally. set the total of the fifo area secured for all endpoints does not exceed the total capacity of the built-in ram. allocate the fifo area to the endpoints in the order from the lower order address to higher order address like ep 0 , epa, epb, epc, epd. the fifo of the endpoint ep 0 is allocated from the address 0 to up to the size specified as the maxpacketsize of the endpoint ep 0 set in the ep0 maxsize register. allocate the succeeding area for other endpoints. since the fifo capacity is 1 k bytes, do not let the epd end address exceed 0x3 ff. and do not let the epcstartadrs exceed the setting value of the epdstartadrs.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-91 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300976: epdstartadrs_h (epd fifo start address high) 0x300977: epdstartadrs_l (epd fifo start address low) name address register name bit setting init. r/w remarks C epdstartadrs[11] epdstartadrs[10] epdstartadrs[9] epdstartadrs[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300976 (b) C endpoint epd start address epdstartadrs_h (epd fifo start address high) epdstartadrs[7] epdstartadrs[6] epdstartadrs[5] epdstartadrs[4] epdstartadrs[3] epdstartadrs[2] C d7 d6 d5 d4 d3 d2 d1C0 0 0 0 0 0 0 C r/w C 0 when being read. 00300977 (b) C endpoint epd start address epdstartadrs_l (epd fifo start address low) epdstartadrs[11:2] sets the start address of the fifo area allocated to the endpoi nt epd. the area that is allocated to the endpoint epd is from the address set by the epdstartadrs and to the end address of the fifo. after setting the startadrs of all endpoints, be sure to set the allfifo_clr bit of the epncontrol register to 1 to clear all fifos. if the epdmaxsize of the endpoint epd is larger than the area specified in here, the macro does not operate normally. set the total of the fifo area secured for all endpoints does not exceed the total capacity of the built-in ram. allocate the fifo area to the endpoints in the order from the lower order address to higher order address like ep 0 , epa, epb, epc, epd. the fifo of the endpoint ep 0 is allocated from the address 0 to up to the size specified as the maxpacketsize of the endpoint ep 0 set in the ep0 maxsize register. allocate the succeeding area for other endpoints. since the fifo capacity is 1 k bytes, do not let the epd end address exceed 0x3 ff.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-92 epson s1c33e08 technical manual 0x300980: cpu_joinrd (cpu join fifo read) name address register name bit setting init. r/w remarks C joinepdrd joinepcrd joinepbrd joinepard d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300980 (b) C 1 join epc fifo read 0 do nothing 1 join epb fifo read 0 do nothing 1 join epa fifo read 0 do nothing cpu_joinrd (cpu join fifo read) 1 join epd fifo read 0 do nothing this register can be set up to read the fifo data of the endpoint through the cpu interface. when the epnfifoforcpu register is read after the setup of this register is completed, the fifo data of the relevant endpoint can be read. the remained data quantity of the fifo can be referred by the epnrdremain_h, l register. this register can set only one bit to 1 at the same time. when 1 is written into multiple bits at the same time, writing in higher order bit is regarded as valid. when all bits are set to 0, ep0 will be joined. the reading data from cpu i/f through the endpoint use d by usb i/f or dma i/f is not allowed. if cpu i/f needs to read from the in direction endpoint, use t he forcenak bit to avoid reading data from usb i/f. if cpu i/f needs to read from the out direction endpoint, check the dma_running bit of the dma_control register to avoid reading data from dma i/f at the same time. this register is valid when enepnfifo_access.enepnfifo_rd bit is set. d[7:4] reserved d3 joinepdrd if this bit is set to 1 , the fifo data of the endpoint epd can be read from the epnfifoforcpu register. in addition, reference to the data quantity in the fifo of the endpoint epd by the epnrdremain_h, l register is enabled. d2 joinepcrd if this bit is set to 1 , the fifo data of the endpoint epc can be read from the epnfifoforcpu register. in addition, reference to the data quantity in the fifo of the endpoint epc by the epnrdremain_h, l register is enabled. d1 joinepbrd if this bit is set to 1 , the fifo data of the endpoint epb can be read from the epnfifoforcpu register. in addition, reference to the data quantity in the fifo of the endpoint epb by the epnrdremain_h, l register is enabled. d0 joinepard if this bit is set to 1 , the fifo data of the endpoint epa can be read from the epnfifoforcpu register. in addition, reference to the data quantity in the fifo of the endpoint epa by the epnrdremain_h, l register is enabled.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-93 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300981: cpu_joinwr (cpu join fifo write) name address register name bit setting init. r/w remarks C joinepdwr joinepcwr joinepbwr joinepawr d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300981 (b) C 1 join epc fifo write 0 do nothing 1 join epb fifo write 0 do nothing 1 join epa fifo write 0 do nothing cpu_joinwr (cpu join fifo write) 1 join epd fifo write 0 do nothing this register can be set up to write the fifo data of the endpoint through the cpu interface. when the epnfifoforcpu register is written after the setup of this register is completed, the fifo data of the relevant endpoint can be written. the space capacity of the fifo can be referred by the epnwrremain_h, l register. this register can set only one bit to 1 at the same time. when 1 is written into multiple bits at the same time, writing in higher order bit is regarded as valid. when all bits are set to 0, ep0 will be joined. the writing data from cpu i/f through the endpoint use d by usb i/f or dma i/f is not allowed. if cpu i/f needs to write to the out direction endpoint, use t he forcenak bit to avoid writing data from usb i/f. if cpu i/f needs to write to the in direction endpoint, check the dma_running bit of the dma_control register to avoid writing data from dma i/f at the same time. this register is valid when enepnfifo_access.enepnfifo_wr bit is set. d[7:4] reserved d3 joinepdwr if this bit is set to 1 , the fifo data of the endpoint epd can be written into the epnfifoforcpu register. in addition, reference to the space capacity in the fifo of the endpoint epd by the epnwrremain_h, l register is enabled. d2 joinepcwr if this bit is set to 1 , the fifo data of the endpoint epc can be written into the epnfifoforcpu register. in addition, reference to the space capacity in the fifo of the endpoint epc by the epnwrremain_h, l register is enabled. d1 joinepbwr if this bit is set to 1 , the fifo data of the endpoint epb can be written into the epnfifoforcpu register. in addition, reference to the space capacity in the fifo of the endpoint epb by the epnwrremain_h, l register is enabled. d0 joinepawr if this bit is set to 1 , the fifo data of the endpoint epa can be written into the epnfifoforcpu register. in addition, reference to the space capacity in the fifo of the endpoint epa by the epnwrremain_h, l register is enabled.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-94 epson s1c33e08 technical manual 0x300982: enepnfifo_access (enable epn fifo access) name address register name bit setting init. r/w remarks C enepnfifo_wr enepnfifo_rd d7C2 d1 d0 C 0 0 C r/w r/w 0 when being read. 00300982 (b) C 1 enable join epn fifo read 0 do nothing enepnfifo _access (enable epn fifo access) 1 enable join epn fifo write 0 do nothing this register enables the cpu_joinrd and cpu_joinwr registers so that the cpu can access the epn fifo. d[7:2] reserved d1 enepnfifo_wr if this bit is set to 1 , the cpu_joinwr register is enabled and the cpu can write data to the epn fifo selected by the cpu_joinwr register. d0 enepnfifo_rd if this bit is set to 1 , the cpu_joinrd register is enabled and the cpu can read data from the epn fifo selected by the cpu_joinrd register.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-95 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300983: epnfifoforcpu (epn fifo for cpu) name address register name bit setting init. r/w remarks epnfifodata[7] epnfifodata[6] epnfifodata[5] epnfifodata[4] epnfifodata[3] epnfifodata[2] epnfifodata[1] epnfifodata[0] d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x r/w 00300983 (b) epnfifoforcpu (epn fifo for cpu) endpoint ep0 fifo access from cpu d[7:0] epnfifodata[7:0] this register is used for accessing the fifo of the endpoint from the cpu interface. when a bit of the cpu_joinrd register is set to 1 , the data can be read from the fifo by reading values from this register. when a bit of the cpu_joinwr register is set to 1 , the data can be written into the fifo by writing values into this register. if values are read from this register without setting the enepnfifo_rd bit of the enepnfifo_access register, a dummy data will be output. if writing is done into this register without setting the enepnfifo_wr bit of the enepnfifo_access register, writing into the fifo is not done. if this register is read when the fifo of the relevant endpoint is empty, a dummy data will be read. if writing is done into this register when the fifo of the relevant endpoint has no space, writing into the fifo is not done.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-96 epson s1c33e08 technical manual 0x300984: epnrdremain_h (epn fifo read remain high) 0x300985: epnrdremain_l (epn fifo read remain low) name address register name bit setting init. r/w remarks d7C4 d3 d2 d1 d0 C 0 0 0 0 C r 0 when being read. 00300984 (b) epnrdremain_h (epn fifo read remain high) C endpoint n fifo read remain high C epnrdremain[11] epnrdremain[10] epnrdremain[9] epnrdremain[8] epnrdremain[7] epnrdremain[6] epnrdremain[5] epnrdremain[4] epnrdremain[3] epnrdremain[2] epnrdremain[1] epnrdremain[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300985 (b) epnrdremain_l (epn fifo read remain low) endpoint n fifo read remain low epnrdremain[11:0] this register shows the remained data quantity in the fifo of the endpoint connected to the cpu interface by the cpu_joinrd register. when the remained data quantity in the fifo is acquired, the epnrdremain_h and the epnrdremain_l registers must be accessed as a pair. when accessing them, access the epnrdremain_h register first.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-97 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300986: epnwrremain_h (epn fifo write remain high) 0x300987: epnwrremain_l (epn fifo write remain low) name address register name bit setting init. r/w remarks d7C4 d3 d2 d1 d0 C 0 0 0 0 C r 0 when being read. 00300986 (b) epnwrremain_h (epn fifo write remain high) C endpoint n fifo write remain high C epnwrremain[11] epnwrremain[10] epnwrremain[9] epnwrremain[8] epnwrremain[7] epnwrremain[6] epnwrremain[5] epnwrremain[4] epnwrremain[3] epnwrremain[2] epnwrremain[1] epnwrremain[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300987 (b) epnwrremain_l (epn fifo write remain low) endpoint n fifo write remain low epnwrremain[11:0] this register shows the space capacity in the fifo of the endpoint connected to the cpu interface by the cpu_joinwr register. when the space capacity in the fifo is acquired, the epnwrremain_h and the epnwrremain_l registers must be accessed as a pair. when accessing them, access the epnwrremain_h register first.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-98 epson s1c33e08 technical manual 0x300988: descadrs_h (descriptor address high) 0x300989: descadrs_l (descriptor address low) name address register name bit setting init. r/w remarks d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300988 (b) descadrs_h (descriptor address high) C descriptor address C descadrs[11] descadrs[10] descadrs[9] descadrs[8] descadrs[7] descadrs[6] descadrs[5] descadrs[4] descadrs[3] descadrs[2] descadrs[1] descadrs[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 00300989 (b) descadrs_l (descriptor address low) descriptor address descadrs[11:0] specify the start address of the fifo used at the start of descriptor reply operation, descriptor write operation and descriptor read operation in the descriptor reply function. the descriptor address does not have the function to allocate the fifo area for the descriptor reply function. the entire fifo area ranging from 0x0000 to 0x03 ff (1 k bytes) can be specified for the descriptor address, regardless of the fifo area setting. in the description reply, descadrs is updated every time the in transaction completes at the endpoint ep0 , as many times as the number of data transmitted. refer to the item on the replydescriptor of the ep0 control register, for the descriptor reply function. every time data is written into or read from the descriptor, the descadrs is incremented by 1 . refer to the item on the descdoor register, for the descriptor write and read functions. the fifo area for the descriptor reply function is not allocated explicitly. therefore, specify the descadrs_h, l register and the descsize_h, l register to avoid overlapping with fifos of other endpoints. appropriate area is the area ranging from the end address of the area reserved by the endpoint ep0 (0x0040 ) to the start address of the endpoint epa (epastartadrs_h, l). when referring to the descriptor address, read from the descadrs_h to the descadrs_l.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-99 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x30098a: descsize_h (descriptor size high) 0x30098b: descsize_l (descriptor size low) name address register name bit setting init. r/w remarks d7C2 d1 d0 C 0 0 C r/w 0 when being read. 0030098a (b) descsize_h (descriptor size high) C descriptor size C descsize[9] descsize[8] descsize[7] descsize[6] descsize[5] descsize[4] descsize[3] descsize[2] descsize[1] descsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030098b (b) descsize_l (descriptor size low) descriptor size descsize[9:0] specify the total number of the data to reply in descriptor reply function, for the descriptor size. refer to the item on the replydescriptor bit of the ep0 control register, for the descriptor reply function. the area ranging from 0x0000 to 0x03 ff can be specified for the descriptor size regardless of the fifo area setting. in the description reply, descadrs is updated every time the in transaction completes at the endpoint ep0 , as many times as the number of data transmitted. the fifo area for the descriptor reply function is not allocated explicitly. therefore, specify the descadrs_h, l register and the descsize_h, l register to avoid overlapping with fifos of other endpoints. use the area ranging from the end address of the area reserved by the endpoint ep 0 ( 0 x 0040 ) to the start address of the endpoint epa (epastartadrs_h, l). when referring to the descriptor size, read from the descsize _h to the descsize_l.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-100 epson s1c33e08 technical manual 0x30098f: descdoor (descriptor door) name address register name bit setting init. r/w remarks descmode[7] descmode[6] descmode[5] descmode[4] descmode[3] descmode[2] descmode[1] descmode[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030098f (b) descdoor (descriptor door) descriptor door d[7:0] descmode[7:0] this register is the access register that is used for read and write for the descriptor. before starting the write operation, set the start address of the area where the fifo descriptor is written, into the descadrs_h, l register. and then performing writing one byte by one byte into this register automatically increments the descadrs_h, l register one byte by one byte to write data sequentially. the data written by the descdoor register can be used by the replydescriptor function repeatedly. thus the descriptor reply function protects these data from deletion and overwriting. however, if the area where the descriptor data is written into, is overlapped with the area secured by other endpoints, the data will be overwritten. reading this register allows the fifo data being read from the address specified in the descadrs_h, l register, sequentially. at this time, the address of the descadrs_h, l register is also incremented every time when the data is read. therefore, note that even if you write and read the descdoor register, the values written just before reading cannot be read.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-101 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300990: dma_fifo_control (dma fifo control) name address register name bit setting init. r/w remarks d7 d6 d5C0 0 when being read. 00300990 (b) dma_fifo_control (dma fifo control) 0 0 C r r/w C C 1 fifo is running 0 fifo is not running 1 auto enable short packet 0 do nothing fifo_running autoenshort C d7 fifo_running shows that the fifo of the endpoint connected to the dma is operating. if the dma is started, this bit is set to 1 . after completing the dma operation, this bit is set to 0 (to be cleared) when the fifo becomes empty. d6 autoenshort when the dma operation ends and the data smaller than the maxpacketsize remains in the fifo, the enshortpkt bit of that endpoint is set to 1. this function is valid when the direction of the endpoint connected to the dma is the in direction. d[5:0] reserved
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-102 epson s1c33e08 technical manual 0x300991: dma_join (dma join fifo) name address register name bit setting init. r/w remarks C joinepddma joinepcdma joinepbdma joinepadma d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300991 (b) C 1 join epc to dma 0 do nothing 1 join epb to dma 0 do nothing 1 join epa to dma 0 do nothing dma_join (dma join fifo) 1 join epd to dma 0 do nothing the endpoint to perform the dma transfer can be specified by setting the joinepdCadma bits. after setting these bits, the remained data quantity for the endpoint of the out direction or the space capacity for endpoint of the in direction can be referred by the dma_remain_h, l register. this register can set only one bit to 1 at the same time. when 1 is written into multiple bits at the same time, writing in higher order bit is regarded as valid. d[7:4] reserved d[3:0] joinepddma, joinepcdma, joinepbdma, joinepadma when this bit is set to 1 , the dma transfer is enabled through the endpoint ep x ( x =a,b,c,d). in addition, reference to the space capacity (for the in direction) or the data quantity (for the out direction) in the fifo of the endpoint ep x ( x =a,b,c,d) by the dma_remain h, l register, is enabled.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-103 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300992: dma_control (dma control) name address register name bit setting init. r/w remarks d7 d6 d5 d4 d3 d2 d1 d0 0 when being read. 00300992 (b) dma_control (dma control) 0 0 0 C 0 C 0 0 r r r C w C w w C pdack signal logic pdreq signal logic C 1 dma is running 0 dma is not running 1 clear dma counter 0 do nothing 1 finish dma 0 do nothing 1 start dma 0 do nothing dma_running pdreq pdack C counterclr C dma_stop dma_go this register controls the dma transfer and shows the status of the interface. d7 dma_running this bit is automatically set 1 during the dma transfer. the dma_join register cannot be written when this bit is 1. d6 pdreq shows the logic level of the pdreq signal for monitoring. d5 pdack shows the logic level of the pdack signal for monitoring. d4 reserved d3 counterclr when this bit is set to 1 , the dma_count_hh, hl, lh and ll registers are set to 0x00 (to be cleared). when the dma_running bit is 1 , writing into this bit is neglected. d2 reserved d1 dma_stop setting this bit to 1 ends the dma transfer. when the dma transfer stops, the dma_running bit is set to 0 (to be cleared) and the dma_cmp bit of the dma_intstat register is set to 1 . when restarting the dma transfer, check the dma_running bit or the dma_cmp bit, and wait until the dma operation ends. if this bit is set and the dma transfer starts during the async hronous dma transfer, the data defect may occur. in such a case, stop the operation on the master side first, and then set this bit. d0 dma_go setting this bit to 1 starts the dma transfer.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-104 epson s1c33e08 technical manual 0x300994: dma_config_0 (dma configuration 0) name address register name bit setting init. r/w remarks d7 d6C4 d3 d2 d1 d0 0 when being read. 0 when being read. 00300994 (b) dma_config_0 (dma configuration 0 ) 0 C 0 0 0 C r/w C r/w r/w r/w C C C 1 activate dma port 0 disactivate dma port 1 active-low 0 active-high 1 active-low 0 active-high 1 active-low 0 active-high activeport C pdreq_level pdack_level pdrdwr_level C this register sets fields on the bus of the dma interface. d7 activeport set the dma interface to active. when this bit is set to 0 , the dma interface signals become hi-z/don't care state. d[6:4] reserved d3 pdreq_level set the pdreq logic level. set to 0 (active-high). d2 pdack_level set the pdack logic level. set to 0 (active-high). d1 pdrdwr_level set the logic levels of the pdrd and pdwr signals. set to 0 (active-high). d0 reserved
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-105 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300995: dma_config_1 (dma configuration 1) name address register name bit setting init. r/w remarks d7 d6C4 d3 d2C1 d0 0 C 0 C 0 r/w C r/w C r/w 0 when being read. 0 when being read. 00300995 (b) dma_config_1 (dma configuration 1 ) rcvlimitmode C singleword C countmode C C 1 receive limit mode 0 normal 1 single word 0 multi word 1 count-down mode 0 free-run mode this register sets fields on the operation mode of the dma interface. d7 rcvlimitmode setting this bit to 1 realizes the rcvlimit mode. this function is available only during write operation for the asynchronous multi-word dma transfer, and not available in the count down mode. during the asynchronous dma write operation in the rcvlimit mode, data up to 16 bytes can be received even after this macro negates the pdreq signal. in this mode, the pdreq signal is negated when the space of the endpoint becomes less than 32 bytes by the dma write operation. however, when the pdreq signal is negated, 16 -byte data that are not written into the endpoint may exist in the internal circuit. therefore, the data that can be received after the pdreq signal is negated, is 16 bytes or less. in this mode, the pdreq signal is negated before the endpoint becomes completely full. when the area of the endpoint set by the ep{a,b,c,d}startadrs registers is the same as the value set by the ep{a,b,c,d}maxsize register (single buffer), the endpoint never becomes full. therefore, the data cannot be transmitted by the in transfer of the usb. to avoid this limitation, when using the rcvlimit mode, be sure to enter the value of the ep{a,b,c,d}maxsize register + 32 -byte or larger area, into the ep{a,b,c,d}startadrs register. d[6:4] reserved d3 singleword sets the handshake mode in the asynchronous (handshake) mode. in the single word mode, the pdreq signal is negated every time when one word is transferred. in the multi-word mode, the pdreq signal is not negated if the next data communication is possible when one word is transferred. d[2:1] reserved d0 countmode sets the mode to control the number of the dma transmissions. in the free-run mode, the dma transfer operation is continued until the dma_stop is enabled. the transfer byte counter (dma_count_hh, hl, lh, ll) shows the number of transmissions for reference. in the count-down mode, the dma transfer is continued up to the number of bytes set in the transfer byte counter (dma_count_hh, hl, lh, ll) or until the dma_stop is enabled to stop it. the transfer byte counter shows the remained transmission quantity, for reference.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-106 epson s1c33e08 technical manual 0x300997: dma_latency (dma latency) name address register name bit setting init. r/w remarks d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300997 (b) dma_latency (dma latency) C latency C dma_latency[3] dma_latency[2] dma_latency[1] dma_latency[0] this register sets the data transfer latency for the transfer in the asynchronous (handshake) mode. the unit time of the latency is approximately 130 ns. d[7:4] reserved d[3:0] dma_latency[3:0] if a value between 0x1 and 0 xf is written, the pdreq signal is negated every time when the 4 -word is transmitted either in the single word mode or in the multi-word mode, and the pdreq signal is not be asserted for (130 n) ns period.
ix peripheral modules 7 (usb): usb function controller (usb) s1c33e08 technical manual epson ix-1-107 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i2s vi gpio egpio vii adc viii lcdc ivram ix usb ap i/omap differ gnu33 0x300998: dma_remain_h (dma fifo remain high) 0x300999: dma_remain_l (dma fifo remain low) name address register name bit setting init. r/w remarks C dma_remain[11] dma_remain[10] dma_remain[9] dma_remain[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r 0 when being read. 00300998 (b) dma_remain_h (dma fifo remain high) dma fifo remain high C dma_remain[7] dma_remain[6] dma_remain[5] dma_remain[4] dma_remain[3] dma_remain[2] dma_remain[1] dma_remain[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300999 (b) dma_remain_l (dma fifo remain low) dma fifo remain low dma_remain[11:0] when the direction of the endpoint connected to the dma by the dma_join register is the out direction, this register shows the remained data quantity in the fifo of the endpoint. when the direction of the endpoint connected to the dma by the dma_join register is the in direction, this register shows the space capacity in the fifo of the endpoint. the dma_remain_h register and the dma_remain_l register must be accessed as a pair. when accessing them, access the dma_remain_h register first.
ix peripheral modules 7 (usb): usb function controller (usb) ix-1-108 epson s1c33e08 technical manual 0x30099c: dma_count_hh (dma transfer byte counter high/high) 0x30099d: dma_count_hl (dma transfer byte counter high/low) 0x30099e: dma_count_lh (dma transfer byte counter low/high) 0x30099f: dma_count_ll (dma transfer byte counter low/low) name address register name bit setting init. r/w remarks dma_count[31] dma_count[30] dma_count[29] dma_count[28] dma_count[27] dma_count[26] dma_count[25] dma_count[24] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030099c (b) dma_count_hh (dma transfer byte counter high/high) dma transfer byte counter dma_count[23] dma_count[22] dma_count[21] dma_count[20] dma_count[19] dma_count[18] dma_count[17] dma_count[16] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030099d (b) dma_count_hl (dma transfer byte counter high/low) dma transfer byte counter dma_count[15] dma_count[14] dma_count[13] dma_count[12] dma_count[11] dma_count[10] dma_count[9] dma_count[8] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030099e (b) dma_count_lh (dma transfer byte counter low/high) dma transfer byte counter dma_count[7] dma_count[6] dma_count[5] dma_count[4] dma_count[3] dma_count[2] dma_count[1] dma_count[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030099f (b) dma_count_ll (dma transfer byte counter low/low) dma transfer byte counter dma_count[31:0] these registers specify the data length in the dma transfer in units of byte, and displays it. its setting can be done as large as up to 0xffffffff bytes. when the dma is set to be in the free run mode by the setting of the countmode bit of the dma_config_ 1 register (countmode = 0 ), values transmitted by the dma can be referred at any time. in this mode, when the dma transfer byte counter exceeds 0 xffffffff, it returns to 0x00000000 and the dma_countup bit of the dma_intstat register is set to 1. when the dma is set to be in the countdown mode by the setting of the countmode bit of the dma_config_ 1 register (countmode = 1 ), specify the total number of transmissions in the dma transfer byte counter, set the dma_go bit of the dma_control register to 1 , and then start the dma transfer. in this mode, the dma transfer byte counter is decreased as much as the data quantity transferred by the dma. when it reaches 0x00000000 , the dma ends. in this mode, the remained quantity of the data to transfer can be referred. writing into these registers during the dma transfer is neglected. for reading these registers, access the dma_count_hh, hl, lh and ll registers in this order.
i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap is/omap c33pe dev boot notes clock s1c33e08 technical manual x peripheral m odules 8 ( mp3 )

x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1 mp3 decoder (mp3) x.1.1 overview the s 1c33e08 incorporates an mp3 decoder module for decoding mp3 data and playback of the decoded data through the i 2 s module. the mp 3 decoder module consists of a hardware mp3 accelerator and an mp3 decoder bios located in the specific rom (area 1 ). the mp3 decoder bios provides high-level mp3 api functions to realize an mp 3 player and low-level mp3 api functions to realizes an mp3 decoder using the hardware mp3 accel - erator. the high-level mp 3 api functions include codes for decoding mp3 data using the low-level mp3 api func - tions and for playback using the i 2 s module allowing the programmer to implement an mp 3 player easily by creat - ing mp 3 data input and event processing functions. when creating a user-specific mp 3 decoder/player program, the low-level mp 3 api functions may be directly used to calculate equations for decoding mp3 data. note : the epson s1c33e08 incorporates mp3 technology of which thomson sa in france holds the patent. manufacturers using the epson s1c33e08 to develop mp3 products must pay royalties to thomson sa in order to procure the license for the mp3 technology. the following shows the mp 3 and i 2 s specifications supported in the mp 3 decoder bios: mp3 data format supported sampling frequency: 32, 44.1, and 48 khz (mpeg1 audio layer-iii) 16, 22.05, and 24 khz (mpeg2 audio layer-iii lsf) ? the mp3 decoder bios does not support mpeg2.5 (8, 11.025 , and 12 khz) data with the fraunhofer- gesellschaft expanded. the higher the sampling frequency, the more the cpu occupancy rate during playback increases. the cpu clock frequency should be set as high as possible to perform parallel processing using the rtos, etc. bit-rate: 32 to 320 kbps (mpeg1 audio layer-iii, cbr/vbr/abr) 8 to 160 kbps (mpeg2 audio layer-iii lsf, cbr/vbr/abr) channel mode: stereo (joint stereo and dual channel) and monaural i 2 s output specifications quality mode: three quality modes (high, middle, and low) available ? the output sound quality depends on the quality mode selected, note, however, that higher quality modes increase the cpu occupancy rate. pcm data sampling frequency: automatically switched according to the mp 3 data for playback.
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-2 epson s1c33e08 technical manual mp3 decoder api functions high-level mp 3 api functions the following control functions are provided: ? open mp3 decoder (open) ? close mp3 decoder (close) ? start playback (start) ? stop playback (stop) ? pause playback (pause) ? resume playback (resume) for playback from pause ? synchronize and playback (resync) for forward and rewind low-level mp 3 api functions the following calculation functions are provided: ? anti alias processing (antialias) ? inverse discrete cosine transform (idctlong, idctshort) ? window function for inverse-mdct (idctwindow) ? stereo processing (stereoprocess, stereoprocesslsf) ? fast-dct for sub-band synthesis (subbandsynthesisfdct) ? window function for sub-band synthesis (subbandsynthesiswindow/2/4/8)
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.2 composition of mp3 decoder system the s 1c33e08 provides a hardware mp3 accelerator and an mp3 decoder bios to implement an mp3 decoder/ player with an i 2 s interface and hsdma for controlling data stream. mp3 decoder module (high-le vel functions) ? open mp3 decoder ? resume pla ybac k ? close mp3 decoder (f or pla ybac k from pause) ? star t pla ybac k ? synchroniz e and pla ybac k ? stop pla ybac k (f or f orw arding and re winding) ? p ause pla ybac k mp3 player module ? control key entr y ? control data flo w file manager ? fs33, etc. data buffers ? input b uff er (min. 4kb) ? output b uff er mp3 file audio dac mp3 calculation module (lo w-le vel functions) ? anti alias processing ? in v erse discrete cosine transf or m ? windo w function f or in v erse-mdct ? stereo processing ? f ast-dct f or sub-band synthesis ? windo w function f or sub-band synthesis hardware mp3 accelerator hsdma (ch.0, ch.1) i 2 s i 2 s control module ? control audio output (i 2 s, hsdma) mp3 decoder bios s1c33e08 peripheral modules user application api function call callbac k (data request, ev ent handling) interrupts, no. 22/23 mp3 data pcm data pcm data figure x.1.2.1 structure of mp3 decoding system 1 (when mp3 decoder module is used)
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-4 epson s1c33e08 technical manual mp3 decoder/player module ? control key entr y ? control data flo w ? decode mp3 data ? control audio output file manager ? fs33, etc. data buffers ? input b uff er ? output b uff er mp3 file audio dac mp3 calculation module (lo w-le vel functions) ? anti alias processing ? in v erse discrete cosine transf or m ? windo w function f or in v erse-mdct ? stereo processing ? f ast-dct f or sub-band synthesis ? windo w function f or sub-band synthesis hardware mp3 accelerator hsdma (ch.0, ch.1) i 2 s mp3 decoder bios s1c33e08 peripheral modules user application api function call mp3 data pcm data pcm data figure x.1.2.2 structure of mp3 decoding system 2 (when mp3 calculation module only is used) x.1.2.1 mp3 decoder bios the s 1c33e08 contains an mp3 decoder bios that provides apis to realize an mp3 decoder system. the bios is consists of three modules shown below and located in area 1. (1 ) mp3 decoder module this module provides high-level mp 3 api functions that allow the user to implement an mp3 player easily. the module decodes mp 3 data using the mp3 calculation module (2 ) and sends the decoded data to an external audio dac via the i 2 s module using the i 2 s control module (3). (2 ) mp3 calculation module this module provides low-level mp 3 api functions used for calculations to decode mp3 data. when using the mp3 decoder module (1 ) to implement an mp3 player, the user program does not need to call the low-level functions because they are called from the mp 3 decoder module (1 ). when implementing an mp3 player with a user original control program, call the low-level functions directly from the user program to decode mp 3 data. (3 ) i 2 s control module this module is positioned under the mp 3 decoder module (1 ) and it controls the i 2 s module and hsdma to send the decoded data to the external audio dac connected via the i 2 s interface. the module will not be used when the mp3 decoder module (1) is not used.
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.2.2 hardware resource requirements table x. 1.2.2.1 lists the memory and internal peripheral modules required for an mp3 decoding system. table x. 1.2.2.1 hardware resource requirements resource when mp3 decoder module is used when mp3 calculation module only is used a0ram 7kb (0x0400C0x1fff) ? 1 C ivram 12kb (0x2000C0x4fff) ? 1 C external ram 20 kb min. ? 2 C stack area 40 bytes ? 3 40 bytes ? 3 i 2 s module used C hsdma module ch.0 and ch.1 ? 4 C itc module vector no. 22, 23 and 94 ? 4 C ?1 : the mp 3 decoder module (high-level mp 3 api functions) occupies 19 k bytes of the internal ram ( 0 x 0400 C 0x4fff) in area 0 including the ivram. the remaining 1 k bytes of internal ram (0x0000C0x03 ff) is available for the user program. note that an external sdram must be used as the vram for the lcd controller. ?2 : a 16 k-byte work area and at least 4 k bytes of mp3 input data buffer are required for the mp3 decoder module (high-level mp 3 api functions) in addition to the internal ram. the 16 k-byte work area can be located in an exter - nal ram from any given address in word alignment. the input data buffer can be located anywhere independently of the work area, note, however, that the buffer size must be a multiple of eight bytes and the start address must be aligned on a word boundary. ?3 : the mp3 calculation module uses 40 bytes in the stack configured in the user application. ?4 : the mp3 decoder module (i 2 s control module) uses hsdma ch. 0 and ch.1 to fill the i 2 s fifo with the pcm data to be output and their interrupts to control data transfer. note : rstonly (d0/0x30029f), which is used to select a cause-of-interrupt flag reset method, must be set to 1 (reset-only method) when the mp3 decoder function is used. ? rstonly : cause-of-interrupt flag reset method select bit in the flag set/reset method select register (d0/0x30029f) figure x.1.2.2.1 shows the memory maps according to the mp3 module used. area 2 0x0007 ffff 0x0006 0000 reserved for debugging area 0 0x0001 ffff 0x0000 8000 0x0000 4fff 0x0000 0400 0x0000 03ff 0x0000 0000 mp3 work area (19kb) (ivram+a0ram) a0ram (1kb) (reserved) area 3 0x000f ffff 0x0008 4800 0x0008 47ff 0x0008 4000 0x0008 3fff 0x0008 3000 0x0008 2fff 0x0008 0000 dst ram (2kb) (reserved) (reserved) area 1 0x0005 ffff 0x0003 0000 0x0002 ffff 0x0002 0000 specific rom (reserved for firmware) (reserved) area 6 0x003f ffff 0x0030 2000 0x0030 1fff 0x0030 0000 ip and peripherals (reserved) internal areas workareaaddr + 0x3fff workareaaddr mp3 work area (16kb) inputbufferaddr + ( 0xfff ) inputbufferaddr mp3 input buffer (4kb min.) external ram area 6 0x003f ffff 0x0030 2000 0x0030 1fff 0x0030 0000 ip and peripherals (reserved) internal areas external ram depends on the user application. area 2 0x0007 ffff 0x0006 0000 reserved for debugging area 0 0x0001 ffff 0x0000 8000 0x0000 4fff 0x0000 2000 0x0000 1fff 0x0000 0000 a0ram (12kb) a0ram (8kb) (reserved) area 3 0x000f ffff 0x0008 4800 0x0008 47ff 0x0008 4000 0x0008 3fff 0x0008 3000 0x0008 2fff 0x0008 0000 ivram (12kb) dst ram (2kb) (reserved) (reserved) area 1 0x0005 ffff 0x0003 0000 0x0002 ffff 0x0002 0000 specific rom (reserved for firmware) (reserved) selectable can be accessed from the user program cannot be accessed from the user program (1) when mp3 decoder module is used (2) when mp3 calculation module only is used figure x.1.2.2.1 memory map refer to section x.1.6, performance, for the cpu sharing time.
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-6 epson s1c33e08 technical manual x.1.3 usage of mp3 api functions the mp 3 decoder bios provides the api functions that can be called from the user program to realize an mp3 de - coder/player. the api functions are divided into two categories, high-level mp 3 api functions and low-level mp3 api functions. use the high-level mp 3 api functions to realize an mp3 player easily as well as the mp3 decoder. the low-level mp3 api functions provide an mp3 decoding feature only, so use them when creating a user's mp3 player module. x.1.3.1 high-level mp3 api functions the high-level mp 3 api functions allow the user to implement an mp3 player easily. list of high-level mp 3 api functions table x. 1.3.1.1 lists the high-level mp3 api functions and their start address. table x. 1.3.1.1 list of high-level mp3 api functions address api function description 0x0002_3000 c33mp3decopen( ) opens mp3 decoder. 0x0002_3004 c33mp3decclose( ) closes mp3 decoder. 0x0002_3008 c33mp3 decstart( ) starts playback of mp 3 data. 0x0002_300c c33mp3decstop( ) stops playback of mp 3 data. 0x0002_3010 c33mp3 decpause( ) pauses playback of mp 3 data. 0x0002_3014 c33mp3decresume( ) resumes playback of paused mp 3 data. 0x0002_3018 c33mp3decresync( ) resynchronizes mp 3 data for forwarding or rewinding. notes : ? the addresses may be changed in a bios update in the future. ? includes the mp3.h header file, which contains the prototype declarations for the functions, into the user application source file. control procedure the following shows an mp 3 decoder initialization and control procedure: (1 ) enable the clock supply to the required peripheral modules. table x. 1.3.1.2 lists the clocks that must be enabled. table x. 1.3.1.2 clock control clock peripheral control bit sdramc cpu app clock (halt mode) ? 1 sdramc sdapcpu_hcke (d 7/0x301b00) sdramc cpu app clock ? 1 sdramc sdapcpu_cke (d 6/0x301b00) sdramc lcdc app clock ? 1 sdramc sdaplcdc_cke (d 5/0x301b00) sdramc sapb bus interface clock ? 1 sdramc sdsapb_cke (d4/0x301b00) dst ram clock ? 2 on-chip debugger dstram_cke (d3/0x301b00) lcdc sapb bus interface clock lcdc lcdcsapb_cke (d1/0x301b00) i 2 s clock i 2 s i2s_cke (d11/0x301b04) gpio clock gpio gpio_cke (d8/0x301b04) itc clock itc itc_cke (d2/0x301b04) dma clock hsdma dma_cke (d1/0x301b04) ?1 : these clocks must be enabled when the mp3 work area/input buffer is located in an sdram. ?2 : this clock must be enabled when debugging the program.
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock (2 ) define a t_mp3dec_param type variable and set the members. the t_mp3dec_param structure is used as the argument of the c33mp3decopen() function to initial - ize the mp3 decoder. the t_mp3dec_param structure is defined in the mp3.h header file. include this file in the user pro - gram source file. definition of the t_mp3dec_param structure typedef struct { unsigned long workareaaddr; unsigned long inputbufferaddr; unsigned long inputbuffersize; unsigned long systemclock; unsigned long quality; unsigned long i2sconfig; unsigned long (*transferdata)(void*, unsigned long); void (*event)(long); } t_mp3dec_param; workareaaddr set the top address of the work area used by the mp 3 decoder. the work area needs a 16 k-byte area in an external ram. the address must be aligned on a word boundary. inputbufferaddr set the top address of the mp 3 input data buffer. the mp3 decoder bios gets mp3 data from this buf - fer. the buffer needs an external ram area of the size designated with inputbuffersize . the address must be aligned on a word boundary. inputbuffersize set the size of the mp 3 input data buffer. the size should be 4k bytes or more in eight-byte increments. systemclock set the frequency [hz] of the mclk clock that is supplied from the cmu to the i 2 s module. the practical i 2 s output clock is decided by this parameter. i 2 s output clock = system clock system clock sampling frequency 64 64 round sampling frequency is determined by the setting in the mp3 file to be decoded. table x. 1.3.1.3 lists examples of the i 2 s output clock frequencies. table x. 1.3.1.3 examples of i 2 s output clock frequencies cpu clock sampling frequency 48 khz 44.1 khz 32 khz 24 khz 22.05 khz 16 khz 60 mhz 46.875 (+2.3%) 44.642 (-1.2%) 32.327 (-1.0%) 24.038 (-0.2%) 21.802 (+1.1%) 15.889 (+0.7%) 48 mhz 46.875 (+2.3%) 44.117 (-0.0%) 32.608 (-1.9%) 24.193 (-0.8%) 22.058 (-0.0%) 15.957 (+0.3%) 30 mhz 46.875 (+2.3%) 42.613 (+3.4%) 31.250 (+2.3%) 23.437 (+2.6%) 22.321 (-1.2%) 16.163 (-1.0%) 24 mhz 46.875 (+2.3%) 41.666 (+5.5%) 31.250 (+2.3%) 23.437 (+2.4%) 22.058 (-0.0%) 16.304 (-1.9%) 12 mhz 46.875 (+2.3%) 46.875 (-6.3%) 31.250 (+2.3%) 23.437 (+2.6%) 20.833 (+5.5%) 15.625 (+2.3%) 8 mhz 41.666 (+13.2%) 41.666 (+5.5%) 31.250 (+2.3%) 25.000 (-4.2%) 20.833 (+5.5%) 15.625 (+2.3%) values mean practical sampling frequency [khz] (error[%]) quality specify the quality mode for playing back mp 3 data using a constant shown below. mp 3 dec_mode_h (0 ) high quality mode using high cpu power mp 3 dec_mode_m (1 ) middle quality mode using middle cpu power mp 3 dec_mode_l (2 ) low quality mode using low cpu power
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-8 epson s1c33e08 technical manual i2sconfig set the i 2 s output configuration value to be written to the i 2 s control register ( 0x301c00). use the constants shown below. two or more constants can be specified by separating each of them with an operator |. mp 3 dec_wclkmd_l_high (0x8 ) left = high level mp 3 dec_bclkpol_negative (0x4 ) trigger = negative edge mp 3 dec_dttmg_not_delayed (0x2 ) not delay mp 3 dec_dtform_lsb (0x1 ) lsb first refer to the i 2 s interface section for details of the i 2 s control register ( 0x301c00). transferdata set the pointer to the user function to transfer mp 3 data to the mp3 decoder. refer to callback functions below or section x.1.5.9, transferdata (callback function), for de - tails. event set the pointer to the user function to handle events issued from the mp 3 decoder bios. when set to 0 , no event will be issued. refer to callback functions below or section x.1.5.10, event (callback function), for details. (3 ) call the c33mp3decopen() function. example: #include "mp3.h" t_mp3dec_param param; param.workareaaddr = 0x10040000; param.inputbufferaddr = 0x10046000; param.inputbuffersize = 0x1000; // 4[kb] param.systemclock = 48000000; // 48 [mhz] param.quality = mp3dec_mode_m; param.i2sconfig = mp3dec_bclkpol_negative | mp3dec_dttmg_not_delayed; param.transferdata = usertransferfunc; // unsigned long usertransferfunc(void*, // unsigned long) param.event = usereventfunc; // void usereventfunc(long) c33mp3decopen(¶m); the c33mp3decopen() function must be called to initialize the mp 3 decoder and peripheral module set - tings before other api functions can be used. do not call the c33mp3decopen() function twice or more before the mp3 decoder has been closed. (4 ) to start playback of mp3 data, call the c33mp3decstart() function. the c33mp3decstart() function is used to start playback from the beginning of the mp3 data. this function gets mp 3 data into the input data buffer by calling the users data transfer function and de - codes it using the mp 3 calculate module, then outputs the decoded data via the i 2 s module. the playback sequence continues until the end of the mp3 data or a control function is called. (5 ) to stop playback, call the c33mp3decstop() function. this function stops data transfer to the mp 3 decoder and clears buffer conditions. therefore, a play - back cannot be resumed from the stopped position after it is stopped with this function. use the c33mp3decpause() function to stop playback temporarily. (6 ) to pause playback, call the c33mp3decpause() function. this function stops data transfer to the mp 3 decoder similar to the c33mp3decstop() function. how - ever, this function holds the buffer conditions allowing the program to resume playback from the paused position. to resume playback, call the c33mp3decresume() function. the c33mp3decstart() function can - not be used for resuming.
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock (7 ) to playback mp3 data from a desired position (or to restart playback after forwarding or rewinding the au - dio data), call the c33mp3decresync() function. this function synchronizes the decoder with the playback data using the sync word located in the mp 3 frame header before starting playback. therefore, the audio data in the buffer before the resynchronization has completed is not played back. (8 ) to finish mp3 decoding, call the c33mp3decclose() function. this function releases the resources used for the mp 3 decoder. figure x. 1.3.1.1 shows the mp3 decoder state transition diagram. close stop play pause c33mp3decopen c33mp3decplay or c33mp3decresync c33mp3decresume or c33mp3decresync c33mp3decplay or c33mp3decresync c33mp3decstop c33mp3decstop c33mp3decpause c33mp3decpause c33mp3decclose decoder is active. figure x.1.3.1.1 mp3 decoder state transition diagram callback functions when using the high-level mp 3 api functions to implement an mp3 player, the functions shown below must be created in the user program. data transfer function the mp 3 decoder bios gets mp3 data through the input data buffer of which the location and size are designated in the initial parameters ( t_mp3dec_param structure). during playback, the mp 3 decoder bios calls a data transfer function to fill the buffer with the mp 3 data to be decoded when the input buffer becomes empty. create a data transfer function and set its pointer to the transferdata parameter in the t_mp3dec _param structure. example: unsigned long usertransferfunc(void*, unsigned long); . . . param.transferdata = usertransferfunc; // set initial parameter . . . unsigned long usertransferfunc(void *dstaddr, unsigned long size){ return fread(dstaddr, 1, size, fin); // fill the input buffer } this function should fill the input buffer located from the address ( dstaddr ) with the specified size ( size ) or less of mp 3 data and return the size actually transferred. the pointer to the mp3 data to be transferred must be managed in the user program.
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-10 epson s1c33e08 technical manual event handler function the mp 3 decoder bios calls an event handler function when an error occurs during decoding if the pointer to the event handler function is set to the event parameter in the t_mp3dec_param structure. create an event handler function as necessary. if event handling is not necessary, set the event parameter to 0 . in this case, the mp3 decoder bios will not call an event handler function even if an error occurs during decoding. the following shows the values that will be sent to the event handler function. dec_file_end (10 ) the mp3 data being decoded reached end of the file. dec_err_cant_find_sync (-1 ) no sync-word can be found. dec_err_invalid_header (-2 ) the header contains invalid information. dec_err_bad_layer (-3 ) the header contains information other than layer iii. example: void usereventfunc(long); . . . param.event = usereventfunc; . . . void usereventfunc(long eventflag){ switch (eventflag){ case mp3dec_file_end: // go to next track. . . . break; case dec_err_cant_find_sync: case dec_err_invalid_header: case dec_err_bad_layer: // show error message "this is not mp3 format." . . . break; default: // undefined event break; } }
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.3.2 low-level mp3 api functions the low-level mp 3 api functions provide an mp3 decoding feature. when creating an mp3 player module in the user program, use these functions for decoding mp3 data. it is not necessary to call these functions when using the hi gh-level mp3 api functions. list of low-level mp 3 api functions table x. 1.3.2.1 lists the low-level mp3 api functions and their start addresses. table x. 1.3.2.1 list of low-level mp3 api functions address api function description 0x0002_3080 c33mp3calcantialias( ) performs butterfly calculation processing. 0x0002_3084 c33mp3calcidctlong( ) performs inverse mdct calculation processing for long block. 0x0002_3088 c33mp3 calcidctwindow( ) performs window calculation processing. 0x0002_308c c33mp3 calcidctshort( ) performs inverse mdct calculation processing for short block. 0x0002_3090 c33mp3calcstereoprocess( ) performs stereo processing for mpeg 1 layer iii data. 0x0002_3094 c33mp3calcstereoprocesslsf( ) performs stereo processing for mpeg 2 layer iii lsf data. 0x0002_3098 c33mp3 calcsubbandsynthesisfdct( ) performs fast-dct calculation processing. 0x0002_309c c33mp3 calcsubbandsynthesiswindow( ) performs window calculation for sub-band synthesis. 0x0002_30a0 c33mp3 calcsubbandsynthesiswindow2( ) performs window calculation for sub-band synthesis. 0x0002_30a4 c33mp3 calcsubbandsynthesiswindow4( ) performs window calculation for sub-band synthesis. 0x0002_30a8 c33mp3 calcsubbandsynthesiswindow8( ) performs window calculation for sub-band synthesis. these functions may be used without any initial processing. note : the addresses may be changed in bios update in the future. mp3 decoding flowchart figure x. 1.3.2.1 shows an mp3 decoding flowchart. refer to the sample program supplied for how to use the low-level mp 3 api functions. mp3 data pcm data bit stream analysis/ decomposition huffman decoding side information decoding dequantization stereo processing anti aliasing inverse mdct sun-band synthesis filter bank fdct window function scale factor decoding figure x.1.3.2.1 mp3 decoding flowchart
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-12 epson s1c33e08 technical manual x.1.4 mp3 format x.1.4.1 mp3 file format the mp 3 decoder bios can treat only the fundamental mp3 format (hereafter, called mp3 bit stream ) that was standardized with iso/iec. however, extended formats that include mp 3 bit stream are widely diffused, because general mp3 players require various information in addition to mp 3 bit stream. when the mp3 decoder bios is used, you should skip the ex - tended part and send only the mp3 bit stream part to the mp3 decoder bios. the following shows the mp 3 file formats that are generally used: mp3 file (file extension: .mp3 ) the most popular formats in various mp 3 files are shown below. format a header mp3 bit stream the mp 3 decoder bios can skip the header after finding the sync-word (continuous 12 bits of 1 ). format b id3v2 id3 header mp3 bit stream id3v1 id 3v2 3 bytes id3 id3v1 3 bytes tag 1 byte version 30 bytes title 1 byte revision 30 bytes artist 1 byte flag 30 bytes album 4 bytes size of id3 header 4 bytes release year 30 bytes comment 1 byte genre the mp 3 decoder bios cannot skip the id3-tag, because the id3 -tag may have the sync-word. figure x.1.4.1.1 mp3 file format (.mp3) riff wave file (file extension: .wav ) this is an mp 3 file that is supported by windows. a data chunk in this windows riff format has either format a or format b that are mentioned above. riff mp3 file (file extension: .rmp ) this is an mp 3 file that is supported by windows. a data chunk in this windows riff format has format a that is mentioned above.
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.4.2 mp3 bit stream format the composition of an mp3 bit stream is shown below. frame 0 frame header side information granule 0 channel 0 scale factor huffman code channel 1 scale factor huffman code granule 1 channel 0 scale factor huffman code channel 1 scale factor huffman code main data 0 main data 1 frame 1 frame header side information main data 1 main data 2 frame 2 frame header side information main data 2 main data 3 frame header side information main data 0 main data 1 main data 2 main data 3 + figure x.1.4.2.1 mp3 bit stream format one frame data in an mp 3 bit stream is composed of a frame header, side information and main data. the main data is variable length data compressed as huffman code. one frame is composed of two granules in mpeg 1 layer iii or one granule in mpeg2 layer iii. one granule is composed of 576 samples for two channels (l and r). table x. 1.4.2.1 construction of frame and granule on mpeg layer iii content mpeg2 layer iii mpeg1 layer iii sampling frequency [khz] 16 22.05 24 32 44.1 48 number of granule / frame 1 [granule] 2 [granules] number of sample / granule 576 [samples] number of channel / granule 2 [channels]
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-14 epson s1c33e08 technical manual x.1.5 details of mp3 decoder bios api x.1.5.1 return values and event values table x. 1.5.1.1 lists the return and event values sent from the high-level mp3 api functions. table x. 1.5.1.1 return values and event values constant (return/event value) description mp3dec_success (0) process was terminated successfully. mp3dec_file_end (10) decoding process reached end of the mp3 file. mp3dec_err_cant_find_sync (-1) no sync word can be found in the mp 3 data. the mp3 data may be invalid. mp3 dec_err_invalid_header (-2) the frame header contains an invalid parameter. the mp 3 data may be invalid. mp3 dec_err_bad_layer (-3) the mp3 data is for the unsupported layer. mp3 dec_err_not_open (-10) the decoder module cannot be opened. check to see if the vector table is located in the ram. mp3 dec_err_invalid_param (-11) the decoder found invalid parameter. check to see if any invalid parameter is designated. mp3 dec_err_invalid_command (-12) invalid command. this command cannot be executed.
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.2 c33mp3decopen open mp3 decoder [category] high-level function [declaration] long c33mp3decopen(t_mp3dec_param *parameter) [argument] parameter pointer to the initial parameter structure (see the descripti on below.) [return value] mp3dec_success (0 ) success mp3dec_err_not_open (-10 ) failure (the mp3 decoder cannot be opened.) mp3dec_err_invalid_param (-11 ) failure (an invalid parameter was designated.) [description] opens the mp 3 decoder module. this function initializes the various parameters and hardware resources to activate the mp 3 decoder. after that, the user program will be able to use the high-level api functions in the mp 3 decoder bios. processing by this function is as follows: 1 . relocates ivram to area 0. 2 . overwrites the vector table to change the hsdma ch.0 and ch.1 vectors to the interrupt handler functions in the mp3 decoder bios. 3 . connects the p04Cp07 ports to the i 2 s signals. 4 . enables the interrupt of hsdam ch.0 , and set its priority level to seven. 5 . configures the i 2 s l and r channels to trigger hsdma ch.0 and ch.1 for requesting output data. 6 . initializes the decoder resources. if any configuration in steps 1 to 5 fails, the decoder returns to closed status. note : be sure not to call the c33mp3decopen() function twice before calling the c33mp3decclose() function. c33mp3decopen process succeeded check parameter modify vector no. 22 (hsdma ch.0) return mp3dec_err_invalid_param save ivram state relocate ivram to area 0 initialize resources configure i 2 s, hsdma, ports and itc set module state to open process failed return mp3dec_err_not_open return mp3dec_success process failed invalid parameter found check ivram ivram located in area 3 ivram located in area 0 check configuration results configuration failed configuration succeeded figure x.1.5.2.1 open process flow
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-16 epson s1c33e08 technical manual t_mp3dec_param parameter the argument parameter is the pointer to a t_mp3dec_param type variable used to initialize the mp3 decoder. the t_mp3dec_param structure is defined in the mp3 .h header file. include this file in the user pro - gram source file to create a t_mp3dec_param type variable and set the members before calling the c33mp3decopen() function. definition of the t_mp3dec_param structure typedef struct { unsigned long workareaaddr; unsigned long inputbufferaddr; unsigned long inputbuffersize; unsigned long systemclock; unsigned long quality; unsigned long i2sconfig; unsigned long (*transferdata)(void*, unsigned long); void (*event)(long); } t_mp3dec_param; workareaaddr set the top address of the work area used by the mp 3 decoder. the work area needs a 16 k-byte area in an external ram. the address must be aligned on a word bound - ary. inputbufferaddr set the top address of the mp 3 input data buffer. the mp3 decoder bios gets mp3 data from this buffer. the buffer needs an external ram area of the size designated with inputbuffersize . the address must be aligned on a word boundary. inputbuffersize set the size of the mp 3 input data buffer. the size should be 4k bytes or more in eight-byte increments. systemclock set the frequency [hz] of the mclk clock that is supplied from the cmu to the i 2 s module. the practical i 2 s output clock is decided by this parameter. i 2 s output clock = system clock system clock sampling frequency 64 64 round sampling frequency is determined by the setting in the mp3 file to be decoded. table x. 1.5.2.1 lists examples of the i 2 s output clock frequencies. table x. 1.5.2.1 examples of i 2 s output clock frequencies cpu clock sampling frequency 48 khz 44.1 khz 32 khz 24 khz 22.05 khz 16 khz 60 mhz 46.875 (+2.3%) 44.642 (-1.2%) 32.327 (-1.0%) 24.038 (-0.2%) 21.802 (+1.1%) 15.889 (+0.7%) 48 mhz 46.875 (+2.3%) 44.117 (-0.0%) 32.608 (-1.9%) 24.193 (-0.8%) 22.058 (-0.0%) 15.957 (+0.3%) 30 mhz 46.875 (+2.3%) 42.613 (+3.4%) 31.250 (+2.3%) 23.437 (+2.6%) 22.321 (-1.2%) 16.163 (-1.0%) 24 mhz 46.875 (+2.3%) 41.666 (+5.5%) 31.250 (+2.3%) 23.437 (+2.4%) 22.058 (-0.0%) 16.304 (-1.9%) 12 mhz 46.875 (+2.3%) 46.875 (-6.3%) 31.250 (+2.3%) 23.437 (+2.6%) 20.833 (+5.5%) 15.625 (+2.3%) 8 mhz 41.666 (+13.2%) 41.666 (+5.5%) 31.250 (+2.3%) 25.000 (-4.2%) 20.833 (+5.5%) 15.625 (+2.3%) values mean practical sampling frequency [khz] (error[%]) quality specify the quality mode for playing back mp 3 data using a constant shown below. mp 3 dec_mode_h (0 ) high quality mode using high cpu power mp 3 dec_mode_m (1 ) middle quality mode using middle cpu power mp 3 dec_mode_l (2 ) low quality mode using low cpu power
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock i2sconfig set the i 2 s output configuration value to be written to the i 2 s control register ( 0x301c00). use the constants shown below. two or more constants can be specified by separating each of them with an operator |. mp 3 dec_wclkmd_l_high (0x8 ) left = high level mp 3 dec_bclkpol_negative (0x4 ) trigger = negative edge mp 3 dec_dttmg_not_delayed (0x2 ) not delay mp 3dec_dtform_lsb (0x1 ) lsb first refer to the i 2 s interface section for details of the i 2 s control register ( 0x301c00). transferdata set the pointer to the user function to transfer mp 3 data to the mp3 decoder. refer to section x. 1.5.9, transferdata (callback function), for details. event set the pointer to the user function to handle events issued from the mp 3 decoder bios. when set to 0 , no event will be issued. refer to section x. 1.5.10, event (callback function), for details. [reference] x. 1.5.3 c33mp3decclose(), x.1.5.9 transferdata(), x.1.5.10 event()
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-18 epson s1c33e08 technical manual x.1.5.3 c33mp3decclose close mp3 decoder [category] high-level function [declaration] void c33mp3decclose(void) [argument] (none) [return value] (none) [description] closes the mp 3 decoder module. this function deactivates the mp 3 decoder and it releases all resources used for the mp3 decoder to restore the conditions to those before the mp3 decoder opened. be sure to call this function before terminating the mp 3 application. processing by this function is as follows: 1 . stops playback if the decoder is in playback. 2 . disables the i 2 s module and hsdma ch.0 and ch.1. 3 . restores the hsdma ch.0 interrupt vector. 4 . restores ivram to area 3 if ivram was located in area 3 before the mp3 decoder opened. call the c33mp3decopen() function to use the mp3 decoder once again after it is closed. c33mp3decclose process succeeded stop playback and disable i 2 s/hsdma restore vector no. 22 and ivram location release resources set module state to close process succeeded check ivram ivram located in area 3 (the close process is not needed because the mp3 decoder has not been active.) (the close process is not needed because the mp3 decoder has not been active.) ivram located in area 0 process succeeded check work area work area address is null work area address is not null figure x.1.5.3.1 close process flow [reference] x. 1.5.2 c33mp3decopen()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.4 c33mp3 decstart start playback [category] high-level function [declaration] long c33mp3decstart(void) [argument] (none) [return value] mp3dec_success (0 ) success mp3dec_file_end (10 ) end of file mp3dec_err_cant_find_sync (-1 ) failure (no sync word can be found in an audio frame.) mp3dec_err_invalid_header (-2 ) failure (data has an invalid header.) mp3dec_err_bad_layer (-3 ) failure (data is a bad layer.) [description] starts decoding and playback. processing by this function is as follows: 1 . stops playback if the decoder is in playback. 2 . initializes the software and hardware resources. 3 . reads mp3 data to fill the input buffer. 4 . decodes the mp3 data until the output buffer is filled up. 5 . enables the i 2 s and hsdma to activate and starts playback. this function does not skip id3 tag, because it may contain a sync word. when decoding mp3 data with an id3 tag, the id3 tag should be removed before sending mp3 data to the decoder.
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-20 epson s1c33e08 technical manual c33mp3decstart end start i 2 s/hsdma set module state to play stop process (see c33mp3decstop ) initialize decoder decode two frames disable hsdma interrupts enable hsdma interrupts change stack area change stack area clear pcm buffer initialize resources and reset i 2 s/hsdma return mp3dec_success or error information check module state not in stop state in stop state set error information check initialization failed initialization succeeded set error information check decoding failed decoding succeeded start process figure x.1.5.4.1 start process flow [reference] x. 1.5.5 c33mp3decstop(), x.1.5.6 c33mp3decpause()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.5 c33mp3decstop stop playback [category] high-level function [declaration] long c33mp3decstop(void) [argument] (none) [return value] mp3dec_success (0 ) success mp3dec_err_invalid_command (-12 ) invalid command. this command cannot be executed. [description] stops playback. this function stops hardware operations and clears the interrupt flag. the difference between c33mp3decstop() and c33mp3decpause() is as follows: ? the c33mp3decstop() function flushes the condition of the input and output buffers. ? the c33mp3decpause() function holds the condition of the input and output buffers. c33mp3decstop process succeeded stop i 2 s output and disable hsdma disable hsdma interrupts enable hsdma interrupts change stack area clear hsdma interrupt flag set module state to stop change stack area check module state not in stop state in stop state stop process figure x.1.5.5.1 stop process flow [reference] x. 1.5.4 c33mp3decstart(), x.1.5.6 c33mp3decpause()
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-22 epson s1c33e08 technical manual x.1.5.6 c33mp3 decpause pause playback [category] high-level function [declaration] long c33mp3decpause(void) [argument] (none) [return value] mp3dec_success (0 ) success mp3dec_err_invalid_command (-12 ) invalid command. this command cannot be executed. [description] pauses playback. this pause function allows resuming of playback from the stopped position. call the c33mp3decresume() function to release pause status. the difference between c33mp3decpause() and c33mp3decstop() is as follows: ? the c33mp3decpause() function holds the condition of the input and output buffers. ? the c33mp3decstop() function flushes the condition of the input and output buffers. c33mp3decpause process succeeded stop i 2 s output and disable hsdma disable hsdma interrupts enable hsdma interrupts change stack area clear hsdma interrupt flag set module state to pause change stack area check module state in play state not in play state pause process figure x.1.5.6.1 pause process flow [reference] x. 1.5.7 c33mp3decresume(), x.1.5.5 c33mp3decstop()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.7 c33mp3decresume resume playback [category] high-level function [declaration] long c33mp3decresume(void) [argument] (none) [return value] mp3dec_success (0 ) success mp3dec_err_invalid_command (-12 ) invalid command. this command cannot be executed. [description] releases pause status to resume playback. this function starts clock output from the i 2 s module to restart playback. c33mp3decresume process succeeded start i 2 s output and enable hsdma disable hsdma interrupts enable hsdma interrupts change stack area set module state to play change stack area check module state in pause state not in pause state resume process figure x.1.5.7.1 resume process flow [reference] x. 1.5.6 c33mp3decpause()
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-24 epson s1c33e08 technical manual x.1.5.8 c33mp3decresync resynchronization [category] high-level function [declaration] long c33mp3decresync(void) [argument] (none) [return value] mp3dec_success (0 ) success mp3dec_file_end (10 ) end of file mp3dec_err_cant_find_sync (-1 ) failure (no sync word can be found in an audio frame.) mp3dec_err_invalid_header (-2 ) failure (data has an invalid header.) mp3dec_err_bad_layer (-3 ) failure (data is a bad layer.) [description] synchronizes with the data stored in the input buffer to start playback from a new position. use this function for forwarding or rewinding playback. this function skips data until a first sync-word appears and it starts playback from the data that follows the sync-word. processing by this function is as follows: 1 . stops playback if the decoder is in playback. 2 . initializes the software and hardware resources. 3 . reads and decodes mp3 data. the decoder regards that the re-sync process has succeeded when an audio frame can be continuously decoded three times. 4 . enables the i 2 s and hsdma to activate and starts playback. the difference between c33mp3decstart() and c33mp3decresync() is as follows: ? the c33mp3decstart() function treats mp3 data assuming that the data is in sync. ? the c33mp3decresync() function treats mp3 data assuming that the data is out of sync.
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock c33mp3decresync end start i 2 s/hsdma set module state to play stop process (see c33mp3decstop ) initialize decoder decode one frame three times disable hsdma interrupts enable hsdma interrupts change stack area change stack area clear pcm buffer initialize resources and reset i 2 s/hsdma return mp3dec_success or error information check module state not in stop state in stop state set error information check initialization failed initialization succeeded set error information check decoding failed decoding succeeded retry nine times no yes resync process figure x.1.5.8.1 resync process flow [reference] x. 1.5.4 c33mp3decstart()
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-26 epson s1c33e08 technical manual x.1.5.9 transferdata (callback function) set mp3 data [category] high-level function (user function called from the mp 3 decoder bios) [declaration] unsigned long transferdata(void *dstaddr, unsigned long size) [argument] dstaddr destination address size transfer size [byte] [return value] transquant data size actually transferred [byte] [description] transfers mp 3 data to the mp3 input buffer. this function is called from the mp 3 decoder bios every time the mp3 input buffer becomes empty. the user must create this function in accordance with the speci fication below. ? write mp3 data of the size ( size) to the address ( dstaddr). ? return the actual data size transferred as its return value. the mp 3 decoder bios does not save registers (r10Cr15 ). it is necessary to write a wrapper code that saves registers. (refer to the example below.) set the pointer to this function as the initial parameter ( transferdata member of the t_mp3dec_param structure). the following is an example of the function to transfer data from a file: example of transferdata() // prototype definition extern void _transferdata(void); extern unsigned long transferdata(void *dstaddr, unsigned long size); // initialize decoder i/f api : : param.workareaaddr = workaddress; param.inputbufferaddr = mp3buffaddress; param.inputbuffersize = mp3buffsize; param.systemclock = audioclock; param.quality = mode; param.i2sconfig = audiodacconfigure; param.transferdata = (unsigned long(*)(void*, unsigned long))_transferdata; param.event = audioeventsproc; if(c33mp3decopen(¶m) != mp3dec_success){ return audiosetevent(audio_err_dec_not_open); } : : // wrapper for saving r10-r15 (it is necessary.) void _transferdata(void) { asm("push %r10"); asm("push %r11"); asm("push %r12"); asm("push %r13"); asm("push %r14"); asm("push %r15"); asm("xcall transferdata"); asm("pop %r15");
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock asm("pop %r14"); asm("pop %r13"); asm("pop %r12"); asm("pop %r11"); asm("pop %r10"); } // main process that transfers data unsigned long transferdata(void *dstaddr, unsigned long size) { return fread(dstaddr, 1, size, fin); } [reference] x. 1.5.2 c33mp3decopen()
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-28 epson s1c33e08 technical manual x.1.5.10 event (callback function) event handler [category] high-level function (user function called from the mp 3 decoder bios) [declaration] void event(long eventflag) [argument] eventflag event flag dec_file_end (10 ) the mp3 data being decoded reached end of the file. dec_err_cant_find_sync (-1 ) no sync-word can be found. dec_err_invalid_header (-2 ) the header contains invalid information. (the decoder cannot decode data.) dec_err_bad_layer (-3 ) the header contains information other than layer-iii. (the decoder cannot decode data.) [return value] (none) [description] handles an event that has occurred during decoding. this function is called from the mp 3 decoder bios when an error causes the mp3 decoder to stop processing. at this time the mp3 decoder bios pass an argument eventflag to notify the user that an event occurred. the user can create an event() function when the application needs an event handler. to use the event() function, set its pointer as the initial parameter ( event member of the t_mp3dec_param structure). when not using an event() function, set the event parameter to 0 . setting the event parameter 0 disables the mp3 decoder bios to call the event() function even when an event occurs. note : be sure to avoid calling mp3 api functions from this function. the following is an example of the function: example of event() void usereventfunc(long eventflag){ switch (eventflag){ case mp3dec_file_end: // go to next track. . . . break; case dec_err_cant_find_sync: case dec_err_invalid_header: case dec_err_bad_layer: // show error message "this is not mp3 format." . . . break; default: // undefined event break; } } [reference] x. 1.5.2 c33mp3decopen()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.11 c33mp3 calcstereoprocess stereo process [category] low-level function [declaration] void c33mp3calcstereoprocess(long *out_data, long *in_data, short *is_pos, int sblimit, int ms_stereo) [argument] out_data output block data ( out_data[2][sblimit][18] ) in_data input block data ( in_data[2][sblimit][18] ) is_pos intensity stereo position ( is_pos[sblimit][18] ) sblimit sub-band limit ( sblimit = 1C32) ms_stereo ms-stereo flag 0 : ms-stereo other: lr-stereo [return value] (none) [data structure] the input block data ( in_data ) must have an array structure with [ 2 ][32 ][18 ] elements regardless of the sblimit value. if the sblimit is smaller than 32, no redundant area is used. [0][0][0] [0][0][1] [0][0][16] [0][0][17] [0][1][0] [0][1][1] [0][1][16] [0][1][17] [0][31][0] [0][31][1] [0][31][16] [0][31][17] [1][0][0] [1][0][1] [1][0][16] [1][0][17] [1][1][0] [1][1][1] [1][1][16] [1][1][17] [0][sblimit-1][0] [0][sblimit-1][1] [0][sblimit-1][16] [0][sblimit-1][17] [1][sblimit-1][0] [1][sblimit-1][1] [1][sblimit-1][16] [1][sblimit-1][17] [1][31][0] [1][31][1] [1][31][16] [1][31][17] in_data sblimit 32 18 sblimit 32 [0][0][0] [0][0][1] [0][0][16] [0][0][17] [0][1][0] [0][1][1] [0][1][16] [0][1][17] [0][31][0] [0][31][1] [0][31][16] [0][31][17] [1][0][0] [1][0][1] [1][0][16] [1][0][17] [1][1][0] [1][1][1] [1][1][16] [1][1][17] [0][sblimit-1][0] [0][sblimit-1][1] [0][sblimit-1][16] [0][sblimit-1][17] [1][sblimit-1][0] [1][sblimit-1][1] [1][sblimit-1][16] [1][sblimit-1][17] [1][31][0] [1][31][1] [1][31][16] [1][31][17] out_data sblimit 32 18 sblimit 32 [0][0] [0][1] [0][16] [0][17] [1][0] [1][1] [1][16] [1][17] [sblimit-1][0] [sblimit-1][1] [sblimit-1][16] [sblimit-1][17] is_pos sblimit 18 figure x.1.5.11.1 data structure supported by the c33mp3calcstereoprocess() function [restriction] the operation of this function cannot be guaranteed if the sblimit is out of the valid range.
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-30 epson s1c33e08 technical manual [description] performs stereo processing for one block of mpeg 1 layer iii data that has been dequantized by the previous process. this function transforms the block data to l and r stereo bloc k data. outline of this function is shown below. c33mp3calcstereoprocess end ms stereo process intensity stereo process loop i = 0 to ( sblimit 18 - 1) loop i = 0 to ( sblimit 18 - 1) ms stereo flag off on is_pos[i] < 7 7 lr stereo process intensity stereo process is_pos[i] < 7 7 figure x.1.5.11.2 flowchart of stereo process lr stereo process l = l , r = r ms stereo process l = , r = ( l + r ) 2 ( l C r ) 2 intensity stereo process l = m , r = m is_ratio 1 + is_ratio 1 1 + is_ratio is_ratio = tan ( is_pos ) 12 resource requirements stack size: 24 [bytes] register: %r4 , %r5 , %alr work register %r6 argument out_data %r7 argument in_data %r8 argument is_pos %r9 argument sblimit [%sp+1] argument ms_stereo [reference] x. 1.5.12 c33mp3calcstereoprocesslsf()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.12 c33mp3 calcstereoprocesslsf stereo process for lsf [category] low-level function [declaration] void c33mp3calcstereoprocesslsf(long *out_data0, long *in_data0, long *out_data1, long *in_data1, short *is_pos, int sblimit, int ms_stereo, int io) [argument] out_data0 ch.0 output block data ( out_data0[sblimit][18] ) in_data0 ch.0 input block data ( in_data0[sblimit][18] ) out_data1 ch.1 output block data ( out_data1[sblimit][18] ) in_data1 ch.1 input block data ( in_data1[sblimit][18] ) is_pos intensity stereo position ( is_pos[sblimit][18] ) sblimit sub-band limit ( sblimit = 1C32) ms_stereo ms-stereo flag 0 : ms-stereo other: lr-stereo io table number (0 or 1) [return value] (none) [data structure] [0][0][0] [0][0][1] [0][0][16] [0][0][17] [0][1][0] [0][1][1] [0][1][16] [0][1][17] [1][0][0] [1][0][1] [1][0][16] [1][0][17] [1][1][0] [1][1][1] [1][1][16] [1][1][17] [0][sblimit-1][0] [0][sblimit-1][1] [0][sblimit-1][16] [0][sblimit-1][17] [1][sblimit-1][0] [1][sblimit-1][1] [1][sblimit-1][16] [1][sblimit-1][17] in_data0 sblimit 18 sblimit [0][0][0] [0][0][1] [0][0][16] [0][0][17] [0][1][0] [0][1][1] [0][1][16] [0][1][17] [1][0][0] [1][0][1] [1][0][16] [1][0][17] [1][1][0] [1][1][1] [1][1][16] [1][1][17] [0][sblimit-1][0] [0][sblimit-1][1] [0][sblimit-1][16] [0][sblimit-1][17] [1][sblimit-1][0] [1][sblimit-1][1] [1][sblimit-1][16] [1][sblimit-1][17] out_data0 in_data1 out_data1 sblimit 18 sblimit [0][0] [0][1] [0][16] [0][17] [1][0] [1][1] [1][16] [1][17] [sblimit-1][0] [sblimit-1][1] [sblimit-1][16] [sblimit-1][17] is_pos sblimit 18 figure x.1.5.12.1 data structure supported by the c33mp3calcstereoprocesslsf() function [restriction] the operation of this function cannot be guaranteed if the sblimit is out of the valid range.
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-32 epson s1c33e08 technical manual [description] performs stereo processing for one block of mpeg 2 layer iii lsf data that has been dequantized by the previ - ous process. this function transforms the block data to l and r stereo bloc k data. outline of this function is shown below. c33mp3calcstereoprocesslsf end ms stereo process intensity stereo process loop i = 0 to ( sblimit 18 - 1) loop i = 0 to ( sblimit 18 - 1) ms stereo flag off on is_pos[i] lr stereo process intensity stereo process is_pos[i] < 7 7 < 7 7 figure x.1.5.12.2 flowchart of stereo process (lsf) lr stereo process l = l , r = r ms stereo process l = , r = ( l + r ) 2 ( l C r ) 2 intensity stereo process (for lsf data) table x. 1.5.12.1 equations of intensity stereo process (lsf) is_pos in case of scalefac_compress = 0 in case of scalefac_compress = 1 l-ch. r-ch. l-ch. r-ch. 0 l = m r = m l = m r = m 1 l = m 2 (-1/2) r = m l = m 2 (-1/4) r = m 2 l = m r = m 2 (-1/2) l = m r = m 2 (-1/4) 3 l = m 2 (-2/2) r = m l = m 2 (-2/4) r = m 4 l = m r = m 2 (-2/2) l = m r = m 2 (-2/4) 5 l = m 2 (-3/2) r = m l = m 2 (-3/4) r = m 6 l = m r = m 2 (-3/2) l = m r = m 2 (-3/4) resource requirements stack size: 16 [bytes] register: %r4 , %r5 , %r10C14 , %alr work register %r6 argument out_data0 %r7 argument in_data0 %r8 argument out_data1 %r9 argument in_data1 [%sp+1] argument is_pos [%sp+2] argument sblimit [%sp+3] argument ms_stereo [%sp+4] argument io [reference] x. 1.5.11 c33mp3calcstereoprocess()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.13 c33mp3calcantialias anti alias process [category] low-level function [declaration] void c33mp3calcantialias(long *in_data, long *out_data, int sblimit) [argument] in_data[sblimit][18] array of input sub-band data one sub-band data consists of 18 samples (one sample = 32 bits). out_data[sblimit][18] array of output sub-band data one sub-band data consists of 18 samples (one sample = 32 bits). sblimit number of sub-band - 1 ( sblimit = 1C31) for example, if there are 32 sub-bands, this parameter is 31. [return value] (none) [restriction] the operation of this function cannot be guaranteed if the sblimit is out of the valid range. [description] performs butterfly calculation processing to plural sub-band data. the butterfly calculation method is shown below. . . . . . . long in_data [0][18] in_data [j][17-i] cs [i] ca [i] -ca [i] cs [i] out_data [j][17-i] out_data[j][17-j]=(in_data[j][17-i]*cs[i])-(in_data[j+1][i]*ca[i]) out_data[j+1][j]=(in_data[j][17-i]*ca[i])+(in_data[j+1][i]*cs[i]) (i = 0,...,7) out_data[j][17-j] = in_data[j][17-i] out_data[j+1][j] = in_data[j+1][i] (i = 8) sub-band 1 long in_data [1][18] long out_data[0][18] long in_data[n-2][18] sub-band n-1 long out_data[n-2][18] long in_data[n-1][18] sub-band n long out_data[n-1][18] long out_data [1][18] . . . sub-band 2 . . . . . . in_data [j+1][i] formula out_data [j+1][i] cs [ i ] = c [ i] = {-0.6, -0.535, -0.33, -0.185, -0.095, -0.041, -0.0142, -0.0037} 1 1 + (c[ i ]) 2 , ca [ i] = c [ i] 1 + (c[ i]) 2 figure x.1.5.13.1 diagram of anti alias processing resource requirements stack size: 12 [bytes] register: %r4 , %r5 , %r9 work register %r6 argument in_data %r7 argument out_data %r8 argument sblimit [reference] (none)
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-34 epson s1c33e08 technical manual x. 1 . 5 . 14 c 33 mp 3 calcidctlong inverse mdct calculation for long block [category] low-level function [declaration] void c33mp3calcidctlong(long in_data[18], long out_data[18]) [argument] in_data[18] input sub-band data out_data[18] output sub-band data [return value] (none) [description] performs inverse mdct calculation processing to one sub-band data of a long block. this calculation is based on lee 84 ' fct. (reference) inverse mdct k = 0 for i = 0, 1, ... , n -1 ( n = 36) x i = x k cos ( ( 2 i + 1 + ) (2 k + 1) ) 2 n n 2 n - 1 2 generally, this function is used with the c33mp3calcidctwindow() function. an example is shown below. example: usage of c33mp3calcidctlong() and c33mp3calcidctwindow() unsigned long in_data[18]; // input subband data unsigned long tmp[36]; unsigned long out_data[36]; // output subband data c33mp3calcidctlong(in_data, tmp); c33mp3calcidctwindow(out_data, tmp, 0); // window table is type '0' resource requirements stack size: 104 [bytes] register: %r4 , %r5 , %r8 , %r9 work register %r6 argument in_data %r7 argument out_data [reference] x. 1.5.15 c33mp3calcidctwindow(), x.1.5.16 c33mp3calcidctshort()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.15 c33mp3 calcidctwindow window calculation [category] low-level function [declaration] void c33mp3calcidctwindow(long out_data[36], long in_data[18], int block_type) [argument] out_data[36] output sub-band data in_data[18] input sub-band data block_type block table no. (no. = 0C3) [return value] (none) [description] performs window calculation processing after inverse mdct to one sub-band data for a long block. the window calculation method is shown below. block type 0 long block data block type 1 start block data block type 2 short block data block type 3 stop block data figure x.1.5.15.1 diagram of window function after inverse mdct resource requirements stack size: 0 [bytes] register: %r4 , %r5 , %alr work register %r6 argument out_data %r7 argument in_data %r8 argument block_type [reference] x. 1.5.14 c33mp3calcidctlong(), x.1.5.16 c33mp3calcidctshort()
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-36 epson s1c33e08 technical manual x. 1 . 5 . 16 c 33 mp 3 calcidctshort inverse mdct calculation for short block [category] low-level function [declaration] void c33mp3calcidctshort(long in_data[18], long out_data[36]) [argument] in_data[18] input sub-band data out_data[36] output sub-band data [return value] (none) [description] performs inverse mdct calculation processing to one sub-band data of a short block. this calculation is based on lee 84 ' fct. resource requirements stack size: 72 [bytes] register: %r4 , %r5 , %r8 , %r9 work register %r6 argument in_data %r7 argument out_data [reference] x. 1.5.14 c33mp3calcidctlong(), x.1.5.15 c33mp3calcidctwindow()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.17 c33mp3calcsubbandsynthesisfdct fast-dct calculation [category] low-level function [declaration] void c33mp3calcsubbandsynthesisfdct(long in_data[32], long out_data_even[16], long out_data_odd[16]) [argument] in_data[32] a block data on a sample. the block data has elements of 32 sub-bands. out_data_even[16] even dct output coefficients out_data_odd[16] odd dct output coefficients [return value] (none) [description] performs fast-dct calculation processing to block data on one sample. this calculation is based on a 32 point idct as derived by lee ' 84 & konstantinedes. resource requirements stack size: 104 [bytes] register: %r4 , %r5 work register %r6 argument in_data %r7 argument out_data_even %r8 argument out_data_odd [reference] x. 1.5.18 c33mp3calcsubbandsynthesiswindow() , x. 1.5.19 c33mp3calcsubbandsynthesiswindow2/4/8()
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-38 epson s1c33e08 technical manual x.1.5.18 c33mp3 calcsubbandsynthesiswindow window calculation for sub-band synthesis [category] low-level function [declaration] void c33mp3calcsubbandsynthesiswindow(long *in_ptr, short out_data[32], long in_data[512]) [argument] in_ptr current position on in_data out_data[32] output pcm data in_data[512] input data [return value] (none) in the case of c33mp3calcsubbandsynthesiswindow() [description] performs window calculation for sub-band synthesis. resource requirements stack size: 0 [bytes] register: %r4 , %r5 work register %r6 argument in_ptr %r7 argument out_data %r8 argument in_data [reference] x. 1.5.17 c33mp3calcsubbandsynthesisfdct()
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.5.19 c33mp3 calcsubbandsynthesiswindow2/4/8 window calculation for sub-band synthesis 2/4/8 [category] low-level function [declaration] short c33mp3calcsubbandsynthesiswindow2(long *in_ptr, short out_data[32], long in_data[512], short carry_in) short c33mp3calcsubbandsynthesiswindow4(long *in_ptr, short out_data[32], long in_data[512], short carry_in) short c33mp3calcsubbandsynthesiswindow8(long *in_ptr, short out_data[32], long in_data[512], short carry_in) [argument] in_ptr current position on in_data out_data[32] output pcm data in_data[512] input data carry_in a value that was carried on the last time. set 0 at the first time. [return value] carry_out carried value to set into carry_in at the next time [description] performs window calculation for sub-band synthesis. the c33mp3calcsubbandsynthesiswindow2/4/8() functions are compatible with the c33mp3calc subbandsynthesiswindow() function. however, the c33mp3calcsubbandsynthesiswindow2/ 4/8() functions decrease calculation quantity by thinning and interpolation. the c33mp3calcsubbandsynthesiswindow2() , c33mp3calcsubbandsynthesiswindow4() , and c33mp3calcsubbandsynthesiswindow8() functions perform thinning and interpolation with 2 , 4 , and 8 multiples, respectively. resource requirements stack size: 0 [bytes] register: %r4 , %r5 work register %r6 argument in_ptr %r7 argument out_data %r8 argument in_data %r9 argument carry_in [reference] x. 1.5.17 c33mp3calcsubbandsynthesisfdct()
x peripheral modules 8 (mp3): mp3 decoder (mp3) x-1-40 epson s1c33e08 technical manual x.1.6 performance x.1.6.1 support formats the following shows the mp 3 formats supported in the mp3 decoder bios: mpeg1 layer iii sampling frequency [khz] bit-rate [kbps] 32 40 48 56 64 80 96 112 128 160 192 224 256 320 48 ok ok ok ok ok ok ok ok ok ok ok ok ok ok 44.1 ok ok ok ok ok ok ok ok ok ok ok ok ok ok 32 ok ok ok ok ok ok ok ok ok ok ok ok ok ok ? all bit rates support vbr. mpeg2 layer iii (lsf) sampling frequency [khz] bit-rate [kbps] 8 16 24 32 40 48 56 64 80 96 112 128 144 160 24 ok ok ok ok ok ok ok ok ok ok ok ok ok ok 22.05 ok ok ok ok ok ok ok ok ok ok ok ok ok ok 16 ok ok ok ok ok ok ok ok ok ok ok ok ok ok ? all bit rates support vbr. mpeg2.5 sampling frequency [khz] bit-rate [kbps] 8 16 24 32 40 48 56 64 80 96 112 128 144 160 12 C C C C C C C C C C C C C C 11.025 C C C C C C C C C C C C C C 8 C C C C C C C C C C C C C C ? this is the fraunhofer-gesellschaft original format. ok: supported. ?: not tested. C: not supported.
x peripheral modules 8 (mp3): mp3 decoder (mp3) s1c33e08 technical manual epson x-1-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock x.1.6.2 cpu occupancy ratio the cpu time shared by the decoder (hsdma interrupt process) depends on the sampling frequency and bit rate of the mp3 data to be played back. for example, when the cpu/sdram clock is 48 mhz and the decoder is playing back 44 . 1 khz sampled 128 -kbps mp3 data in middle quality mode, the cpu time shared by the decoder is about 70% in 26.1 ms periods (*). * ( 1 /sampling frequency) (number of samples in an mp3 data frame) number of samples: 576 when sampling frequency = 16C24 khz 1152 when sampling frequency = 32C48 khz example: when the sampling frequency = 44.1 khz and the bit rate = 128 kbps 1/441000 1152 = 22.6 s 1152 = 26.1 ms user application decoder (hsdma interrupt process) 26.1 ms 70% 30% 44.1 khz, 128 kbps, middle quality mode (cpu/sdram clock = 48 mhz) figure x.1.6.2.1 cpu occupancy ratio system clock: 60 [mhz], sdram clock: 60 [mhz] sampling frequency = 48 [khz] 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0 32 64 128 160 bit-rate [kbps] high quality mode middle quality mode low quality mode cpu occupancy ratio [%] 192 224 256 320 sampling frequency = 24 [khz] 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0 8 3 2 6 4 128 144 160 bit-rate [kbps] high quality mode middle quality mode low quality mode cpu occupancy ratio [%] system clock: 48 [mhz], sdram clock: 48 [mhz] sampling frequency = 48 [khz] 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0 32 64 128 160 bit-rate [kbps] high quality mode middle quality mode low quality mode cpu occupancy ratio [%] 192 224 256 320 sampling frequency = 24 [khz] 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0 8 3 2 6 4 128 144 160 bit-rate [kbps] high quality mode middle quality mode low quality mode cpu occupancy ratio [%]
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i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock s1c33e08 technical manual appendix

appendix a i/o map s1c33e08 technical manual epson ap-a-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock appendix a i/o map 0x300010C0x300020 misc register (1) .......................................................................... ap-a-2 0x300260C0x3002 af interrupt controller ....................................................................... ap-a-3 0x300300C0x30031 b card interface .............................................................................. ap-a-11 0x300380C0x3003d5 i/o ports ....................................................................................... ap-a-13 0x300520C0x30055 e a/d converter .............................................................................. ap-a-24 0x300660C0x30066 c watchdog timer ........................................................................... ap-a-27 0x300780C0x3007ea 16 -bit timer .................................................................................. ap-a-29 0x300900C0x30099 f usb function controller .............................................................. ap-a-37 0x300b00C0x300b4 f serial interface ............................................................................. ap-a-47 0x300c00C0x300c25 extended ports ............................................................................. ap-a-52 0x300c40C0x300c4 d misc register (2) .......................................................................... ap-a-54 0x301100C0x301105 intelligent dma ............................................................................. ap-a-56 0x301120C0x30119 e high-speed dma ......................................................................... ap-a-57 0x301500C0x301510 sram controller .......................................................................... ap-a-70 0x301600C0x301610 sdram controller ........................................................................ ap-a-71 0x301700C0x30171 c spi ............................................................................................... ap -a-72 0x301800C0x30181 c dcsio .......................................................................................... ap-a-73 0x301900C0x301928 real time clock ........................................................................... ap-a-74 0x301a00C0x301 aac lcd controller ............................................................................. ap-a-76 0x301b00C0x301b24 clock management unit ............................................................... ap-a-83 0x301c00C0x301c20 i 2 s interface ................................................................................. ap-a-87 note : (b), (hw), and (w) in [address] indicate an 8 -bit register, a 16 -bit register, and a 32 -bit register, respectively. the meaning of the symbols described in [init.] are listed below: 0, 1 : initial values that are set at initial reset. (however, the registers for the bus and input/output ports are not initialized at hot start.) x: not initialized at initial reset. C: not set in the circuit.
appendix a i/o map ap-a-2 epson s1c33e08 technical manual 0x300010C0x300020 misc register name address register name bit function setting init. r/w remarks C rtcwt2 rtcwt1 rtcwt0 d7C3 d2 d1 d0 reserved rtc register access wait control C 1 1 1 C r/w 0 when being read. 00300010 (b) rtc wait control register (pmisc_rtcwt) protected 0 to 7 (cycles) C C usbsnz C usbwt2 usbwt1 usbwt0 d7C6 d5 d4C3 d2 d1 d0 reserved usb snooze control reserved usb register access wait control C 0 C 1 1 1 C r/w C r/w 0 when being read. 0 when being read. 00300012 (b) usb wait control register (pmisc_usbwt) protected 0 to 7 (cycles) C C 1 enabled 0 disabled C trcmux d7C1 d0 reserved p15C17, p34C36 debug function selection C 1 C r/w 0 when being read. 00300014 (b) debug port mux register (pmisc_pmux) protected C 1 debug 0 gpio, etc. C parun paclr d7C2 d1 d0 reserved test bit test bit C C C C C C do not access in the user program. 00300016 (b) performance analyzer control register (pmisc_pac) protected C C C boot3 boot2 boot1 boot0 C boot_ena ce10_size d7 d6 d5 d4 d3C2 d1 d0 boot mode indicator reserved #ce10 area boot enable #ce10 area size x x x x C 1 1 r/w C r/w r/w depend on the boot1 and boot0 pin status at initial reset 0 when being read. 00300018 (b) boot register (pmisc_boot) protected C 1 1 internal 16 bits 0 0 external 8 bits boot[3:0] boot mode spi nor flash/rom reserved nand flash 1000 0100 0010 0001 C corom_sw d7C1 d0 reserved test bit C C C C do not access in the user program. 0030001a (b) corom switch register (pmisc_corom) protected C C wr iting 10010110 (0x96) remo v es the wr ite protection of the misc registers (0x300010C0x30001a). wr iting another v alue set the wr ite protection. prot7 prot6 prot5 prot4 prot3 prot2 prot1 prot0 d7 d6 d5 d4 d3 d2 d1 d0 misc register protect flag 0 0 0 0 0 0 0 0 r/w 00300020 (b) misc protect register (pmisc_prot)
appendix a i/o map s1c33e08 technical manual epson ap-a-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300260C0x300268 interrupt controller name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp1l2 pp1l1 pp1l0 C pp0l2 pp0l1 pp0l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 1 interrupt level reserved port input 0 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300260 (b) port input 0C1 interrupt priority register (pint_pp01l) C 0 to 7 0 to 7 C C pp3l2 pp3l1 pp3l0 C pp2l2 pp2l1 pp2l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 3 interrupt level reserved port input 2 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300261 (b) port input 2C3 interrupt priority register (pint_pp23l) C 0 to 7 0 to 7 C C pk1l2 pk1l1 pk1l0 C pk0l2 pk0l1 pk0l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved key input 1 interrupt level reserved key input 0 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300262 (b) key input interrupt priority register (pint_pk01l) C 0 to 7 0 to 7 C C phsd1l2 phsd1l1 phsd1l0 C phsd0l2 phsd0l1 phsd0l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved hsdma ch.1 interrupt level reserved hsdma ch.0 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300263 (b) hsdma ch.0C1 interrupt priority register (pint_phsd01l) C 0 to 7 0 to 7 C C phsd3l2 phsd3l1 phsd3l0 C phsd2l2 phsd2l1 phsd2l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved hsdma ch.3 interrupt level reserved hsdma ch.2 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300264 (b) hsdma ch.2C3 interrupt priority register (pint_phsd23l) C 0 to 7 C pdm2 pdm1 pdm0 d7C3 d2 d1 d0 reserved idma interrupt level C x x x C r/w 0 when being read. 00300265 (b) idma interrupt priority register (pint_pdm) C 0 to 7 0 to 7 C C p16t12 p16t11 p16t10 C p16t02 p16t01 p16t00 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 1 interrupt level reserved 16-bit timer 0 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300266 (b) 16-bit timer 0C1 interrupt priority register (pint_p16t01) C 0 to 7 0 to 7 C C p16t32 p16t31 p16t30 C p16t22 p16t21 p16t20 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 3 interrupt level reserved 16-bit timer 2 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300267 (b) 16-bit timer 2C3 interrupt priority register (pint_p16t23) C 0 to 7 0 to 7 C C p16t52 p16t51 p16t50 C p16t42 p16t41 p16t40 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 5 interrupt level reserved 16-bit timer 4 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300268 (b) 16-bit timer 4C5 interrupt priority register (pint_p16t45)
appendix a i/o map ap-a-4 epson s1c33e08 technical manual 0x300269C0x300272 interrupt controller name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C psio02 psio01 psio00 C plcdc2 plcdc1 plcdc0 d7 d6 d5 d4 d3 d2 d1 d0 reserved serial interface ch.0 interrupt level reserved lcdc interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 00300269 (b) lcdc, serial i/f ch.0 interrupt priority register (pint_plcdc_ psi00) C 0 to 7 0 to 7 C C pad2 pad1 pad0 C psio12 psio11 psio10 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d converter interrupt level reserved serial interface ch.1 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 0030026a (b) serial i/f ch.1, a/d interrupt priority register (pint_psi01_pad) C 0 to 7 C prtc2 prtc1 prtc0 d7C3 d2 d1 d0 reserved rtc interrupt level C x x x C r/w writing 1 not allowed. 0030026b (b) rtc interrupt priority register (pint_prtc) C 0 to 7 0 to 7 C C pp5l2 pp5l1 pp5l0 C pp4l2 pp4l1 pp4l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 5 interrupt level reserved port input 4 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 0030026c (b) port input 4C5 interrupt priority register (pint_pp45l) C 0 to 7 0 to 7 C C pp7l2 pp7l1 pp7l0 C pp6l2 pp6l1 pp6l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 7 interrupt level reserved port input 6 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 0030026d (b) port input 6C7 interrupt priority register (pint_pp67l) C 0 to 7 0 to 7 C C pspi2 pspi1 pspi0 C psio22 psio21 psio20 d7 d6 d5 d4 d3 d2 d1 d0 reserved spi interrupt level reserved serial interface ch.2 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 0030026e (b) serial i/f ch.2, spi interrupt priority register (pint_psi02_pspi) C ek1 ek0 ep3 ep2 ep1 ep0 d7C6 d5 d4 d3 d2 d1 d0 reserved key input 1 key input 0 port input 3 port input 2 port input 1 port input 0 C C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300270 (b) 1 enabled 0 disabled key input, port input 0C3 interrupt enable register (pint_ek01_ep03) C eidma ehdm3 ehdm2 ehdm1 ehdm0 d7C5 d4 d3 d2 d1 d0 reserved idma hsdma ch.3 hsdma ch.2 hsdma ch.1 hsdma ch.0 C C 0 0 0 0 0 C r/w r/w r/w r/w r/w 0 when being read. 00300271 (b) 1 enabled 0 disabled dma interrupt enable register (pint_edma) e16tc1 e16tu1 C e16tc0 e16tu0 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 1 comparison a 16-bit timer 1 comparison b reserved 16-bit timer 0 comparison a 16-bit timer 0 comparison b reserved 0 0 C 0 0 C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300272 (b) 1 enabled 0 disabled 16-bit timer 0C1 interrupt enable register (pint_e16t01) C 1 enabled 0 disabled C
appendix a i/o map s1c33e08 technical manual epson ap-a-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300273C0x300283 interrupt controller name address register name bit function setting init. r/w remarks e16tc3 e16tu3 C e16tc2 e16tu2 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 3 comparison a 16-bit timer 3 comparison b reserved 16-bit timer 2 comparison a 16-bit timer 2 comparison b reserved 0 0 C 0 0 C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300273 (b) 1 enabled 0 disabled 16-bit timer 2C3 interrupt enable register (pint_e16t23) C 1 enabled 0 disabled C e16tc5 e16tu5 C e16tc4 e16tu4 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 5 comparison a 16-bit timer 5 comparison b reserved 16-bit timer 4 comparison a 16-bit timer 4 comparison b reserved 0 0 C 0 0 C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300274 (b) 1 enabled 0 disabled 16-bit timer 4C5 interrupt enable register (pint_e16t45) C 1 enabled 0 disabled C C estx1 esrx1 eserr1 estx0 esrx0 eserr0 d7C6 d5 d4 d3 d2 d1 d0 reserved sif ch.1 transmit buffer empty sif ch.1 receive buffer full sif ch.1 receive error sif ch.0 transmit buffer empty sif ch.0 receive buffer full sif ch.0 receive error C C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300276 (b) 1 enabled 0 disabled serial i/f ch.0C1 interrupt enable register (pint_esif01) C ep7 ep6 ep5 ep4 ertc eade eadc d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 7 port input 6 port input 5 port input 4 rtc a/d conversion completion a/d out-of-range C C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300277 (b) 1 enabled 0 disabled port input 4C7, rtc, a/d interrupt enable register (pint_ep47_ertc _ead) C elcdc C d7C2 d1 d0 reserved lcdc frame end reserved C 0 C C r/w C 0 when being read. do not write 1. 00300278 (b) lcdc interrupt enable register (pint_elcdc) C C 1 enabled 0 disabled C espitx espirx C estx2 esrx2 eserr2 d7C6 d5 d4 d3 d2 d1 d0 reserved spi transmit dma spi receive dma reserved sif ch.2 transmit buffer empty sif ch.2 receive buffer full sif ch.2 receive error C C 0 0 C 0 0 0 C r/w r/w C r/w r/w r/w 0 when being read. do not write 1. 00300279 (b) 1 enabled 0 disabled 1 enabled 0 disabled serial i/f ch.2, spi interrupt enable register (pint_esif2_espi) C C fk1 fk0 fp3 fp2 fp1 fp0 d7C6 d5 d4 d3 d2 d1 d0 reserved key input 1 key input 0 port input 3 port input 2 port input 1 port input 0 C C x x x x x x C r/w r/w r/w r/w r/w r/w 0 when being read. 00300280 (b) 1 occurred 0 not occurred key input, port input 0C3 interrupt cause flag register (pint_fk01_fp03) C fidma fhdm3 fhdm2 fhdm1 fhdm0 d7C5 d4 d3 d2 d1 d0 reserved idma hsdma ch.3 hsdma ch.2 hsdma ch.1 hsdma ch.0 C C x x x x x C r/w r/w r/w r/w r/w 0 when being read. 00300281 (b) dma interrupt cause flag register (pint_fdma) 1 occurred 0 not occurred f16tc1 f16tu1 C f16tc0 f16tu0 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 1 comparison a 16-bit timer 1 comparison b reserved 16-bit timer 0 comparison a 16-bit timer 0 comparison b reserved x x C x x C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300282 (b) 1 occurred 0 not occurred 16-bit timer 0C1 interrupt cause flag register (pint_f16t01) C 1 occurred 0 not occurred C f16tc3 f16tu3 C f16tc2 f16tu2 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 3 comparison a 16-bit timer 3 comparison b reserved 16-bit timer 2 comparison a 16-bit timer 2 comparison b reserved x x C x x C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300283 (b) 1 occurred 0 not occurred 16-bit timer 2C3 interrupt cause flag register (pint_f16t23) C 1 occurred 0 not occurred C
appendix a i/o map ap-a-6 epson s1c33e08 technical manual 0x300284C0x300293 interrupt controller name address register name bit function setting init. r/w remarks f16tc5 f16tu5 C f16tc4 f16tu4 C d7 d6 d5C4 d3 d2 d1C0 16-bit timer 5 comparison a 16-bit timer 5 comparison b reserved 16-bit timer 4 comparison a 16-bit timer 4 comparison b reserved x x C x x C r/w r/w C r/w r/w C 0 when being read. 0 when being read. 00300284 (b) 1 occurred 0 not occurred 16-bit timer 4C5 interrupt cause flag register (pint_f16t45) C 1 occurred 0 not occurred C C fstx1 fsrx1 fserr1 fstx0 fsrx0 fserr0 d7C6 d5 d4 d3 d2 d1 d0 reserved sif ch.1 transmit buffer empty sif ch.1 receive buffer full sif ch.1 receive error sif ch.0 transmit buffer empty sif ch.0 receive buffer full sif ch.0 receive error C C x x x x x x C r/w r/w r/w r/w r/w r/w 0 when being read. 00300286 (b) 1 occurred 0 not occurred serial i/f ch.0C1 interrupt cause flag register (pint_fsif01) C fp7 fp6 fp5 fp4 frtc fade fadc d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 7 port input 6 port input 5 port input 4 rtc a/d conversion completion a/d out-of-range C C x x x x x x x C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300287 (b) 1 occurred 0 not occurred port input 4C7, rtc, a/d interrupt cause flag register (pint_fp47_frtc _fad) C flcdc C d7C2 d1 d0 reserved lcdc frame end reserved C x C C r/w C 0 when being read. 0 when being read. 00300288 (b) lcdc interrupt cause flag register (pint_flcdc) C 1 occurred 0 not occurred C C fspitx fspirx C fstx2 fsrx2 fserr2 d7C6 d5 d4 d3 d2 d1 d0 reserved spi transmit dma spi receive dma reserved sif ch.2 transmit buffer empty sif ch.2 receive buffer full sif ch.2 receive error C C x x C x x x C r/w r/w C r/w r/w r/w 0 when being read. 0 when being read. 00300289 (b) 1 occurred 0 not occurred serial i/f ch.2, spi interrupt cause flag register (pint_fsif2_fspi) C 1 occurred 0 not occurred r16tc0 r16tu0 rhdm1 rhdm0 rp3 rp2 rp1 rp0 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 0 comparison a 16-bit timer 0 comparison b hsdma ch.1 hsdma ch.0 port input 3 port input 2 port input 1 port input 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300290 (b) 1 idma request 0 interrupt request port input 0C3, hsdma ch.0C1, 16-bit timer 0 idma request register (pidmareq_rp03 _rhs_r16t0) r16tc4 r16tu4 r16tc3 r16tu3 r16tc2 r16tu2 r16tc1 r16tu1 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 4 comparison a 16-bit timer 4 comparison b 16-bit timer 3 comparison a 16-bit timer 3 comparison b 16-bit timer 2 comparison a 16-bit timer 2 comparison b 16-bit timer 1 comparison a 16-bit timer 1 comparison b 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300291 (b) 1 idma request 0 interrupt request 16-bit timer 1C4 idma request register (pidmareq _r16t14) rstx0 rsrx0 C r16tc5 r16tu5 d7 d6 d5C2 d1 d0 sif ch.0 transmit buffer empty sif ch.0 receive buffer full reserved 16-bit timer 5 comparison a 16-bit timer 5 comparison b 0 0 C 0 0 r/w r/w C r/w r/w 0 when being read. 00300292 (b) 1 idma request 0 interrupt request 1 idma request 0 interrupt request 16-bit timer 5, serial i/f ch.0 idma request register (pidmareq_r16t5 _rsif0) C rp7 rp6 rp5 rp4 C rade rstx1 rsrx1 d7 d6 d5 d4 d3 d2 d1 d0 port input 7 port input 6 port input 5 port input 4 reserved a/d conversion completion sif ch.1 transmit buffer empty sif ch.1 receive buffer full 0 0 0 0 C 0 0 0 r/w r/w r/w r/w C r/w r/w r/w 0 when being read. 00300293 (b) 1 idma request 0 interrupt request 1 idma request 0 interrupt request C serial i/f ch.1, a/d, port input 4C7 idma request register (pidmareq_rsif1 _rad_rp47)
appendix a i/o map s1c33e08 technical manual epson ap-a-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300294C0x300298 interrupt controller name address register name bit function setting init. r/w remarks de16tc0 de16tu0 dehdm1 dehdm0 dep3 dep2 dep1 dep0 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 0 comparison a 16-bit timer 0 comparison b hsdma ch.1 hsdma ch.0 port input 3 port input 2 port input 1 port input 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300294 (b) 1 idma enabled 0 idma disabled port input 0C3, hsdma ch.0C1, 16-bit timer 0 idma enable register (pidmaen_dep03 _dehs_de16t0) de16tc4 de16tu4 de16tc3 de16tu3 de16tc2 de16tu2 de16tc1 de16tu1 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 4 comparison a 16-bit timer 4 comparison b 16-bit timer 3 comparison a 16-bit timer 3 comparison b 16-bit timer 2 comparison a 16-bit timer 2 comparison b 16-bit timer 1 comparison a 16-bit timer 1 comparison b 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300295 (b) 1 idma enabled 0 idma disabled 16-bit timer 1C4 idma enable register (pidmaen _de16t14) destx0 desrx0 C de16tc5 de16tu5 d7 d6 d5C2 d1 d0 sif ch.0 transmit buffer empty sif ch.0 receive buffer full reserved 16-bit timer 5 comparison a 16-bit timer 5 comparison b 0 0 C 0 0 r/w r/w C r/w r/w 0 when being read. 00300296 (b) 1 idma enabled 0 idma disabled 1 idma enabled 0 idma disabled 16-bit timer 5, serial i/f ch.0 idma enable register (pidmaen_de16t5 _desif0) C dep7 dep6 dep5 dep4 C deade destx1 desrx1 d7 d6 d5 d4 d3 d2 d1 d0 port input 7 port input 6 port input 5 port input 4 reserved a/d conversion completion sif ch.1 transmit buffer empty sif ch.1 receive buffer full 0 0 0 0 C 0 0 0 r/w r/w r/w r/w C r/w r/w r/w 0 when being read. 00300297 (b) 1 idma enabled 0 idma disabled 1 idma enabled 0 idma disabled C serial i/f ch.1, a/d, port input 4C7 idma enable register (pidmaen_desif1 _dead_dep47) hsd1s3 hsd1s2 hsd1s1 hsd1s0 hsd0s3 hsd0s2 hsd0s1 hsd0s0 d7 d6 d5 d4 d3 d2 d1 d0 hsdma ch.1 trigger set-up hsdma ch.0 trigger set-up 0 0 0 0 0 0 0 0 r/w r/w 00300298 (b) 0 1 2 3 4 5 6 7 8 9 a b c d e software trigger #dmareq1 input (falling edge) #dmareq1 input (rising edge) port 1 input port 5 input (reserved) 16-bit timer 1 compare b 16-bit timer 1 compare a 16-bit timer 5 compare b i 2 s right si/f ch.1 rx buffer full si/f ch.1 tx buffer empty a/d conversion completion port 9 input (usb pdreq) port 13 input 0 1 2 3 4 5 6 7 8 9 a b c d e software trigger #dmareq0 input (falling edge) #dmareq0 input (rising edge) port 0 input port 4 input (reserved) 16-bit timer 0 compare b 16-bit timer 0 compare a 16-bit timer 4 compare b i 2 s left si/f ch.0 rx buffer full si/f ch.0 tx buffer empty a/d conversion completion port 8 input (spi interrupt) port 12 input hsdma ch.0C1 trigger set-up register (phsdma_htgr1)
appendix a i/o map ap-a-8 epson s1c33e08 technical manual 0x300299C0x30029f interrupt controller name address register name bit function setting init. r/w remarks hsd3s3 hsd3s2 hsd3s1 hsd3s0 hsd2s3 hsd2s2 hsd2s1 hsd2s0 d7 d6 d5 d4 d3 d2 d1 d0 hsdma ch.3 trigger set-up hsdma ch.2 trigger set-up 0 0 0 0 0 0 0 0 r/w r/w 00300299 (b) 0 1 2 3 4 5 6 7 8 9 a b c d e software trigger #dmareq3 input (falling edge) #dmareq3 input (rising edge) port 3 input port 7 input (reserved) 16-bit timer 3 compare b 16-bit timer 3 compare a (reserved) spi rx (reserved) (reserved) a/d conversion completion port 11 input (dcsio interrupt) port 15 input 0 1 2 3 4 5 6 7 8 9 a b c d e software trigger #dmareq2 input (falling edge) #dmareq2 input (rising edge) port 2 input port 6 input (reserved) 16-bit timer 2 compare b 16-bit timer 2 compare a (reserved) spi tx si/f ch.2 rx buffer full si/f ch.2 tx buffer empty a/d conversion completion port 10 input (usb interrupt) port 14 input hsdma ch.2C3 trigger set-up register (phsdma_htgr2) C hst3 hst2 hst1 hst0 d7C4 d3 d2 d1 d0 reserved hsdma ch.3 software trigger hsdma ch.2 software trigger hsdma ch.1 software trigger hsdma ch.0 software trigger C 0 0 0 0 C w w w w 0 when being read. 0030029a (b) C 1 trigger 0 invalid hsdma software trigger register (phsdma _hsofttgr) C rspitx rspirx rstx2 rsrx2 rlcdc C d7C6 d5 d4 d3 d2 d1 d0 reserved spi transmit dma spi receive dma sif ch.2 transmit buffer empty sif ch.2 receive buffer full lcdc frame end reserved C C 0 0 0 0 0 C C r/w r/w r/w r/w r/w C 0 when being read. 0 when being read. 0030029b (b) 1 idma request 0 interrupt request lcdc, serial i/f ch.2, spi idma request register (pidmareq_rlcdc _rsif2_rspi ) C C despitx despirx destx2 desrx2 delcdc C d7C6 d5 d4 d3 d2 d1 d0 reserved spi transmit dma spi receive dma sif ch.2 transmit buffer empty sif ch.2 receive buffer full lcdc frame end reserved C C 0 0 0 0 0 C C r/w r/w r/w r/w r/w C 0 when being read. 0 when being read. 0030029c (b) 1 idma enabled 0 idma disabled lcdc, serial i/f ch.2, spi idma enable register (pidmaen_delcdc _desif2_despi) C C denonly idmaonly rstonly d7C3 d2 d1 d0 reserved idma enable register set method selection idma request register set method selection cause-of-interrupt flag reset method selection C C 1 1 1 C r/w r/w r/w 0 when being read. 0030029f (b) flag set/reset method select register (prst_reset) 1 set only 0 rd/wr 1 set only 0 rd/wr 1 reset only 0 rd/wr
appendix a i/o map s1c33e08 technical manual epson ap-a-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x3002a0C0x3002aa interrupt controller name address register name bit function setting init. r/w remarks C 0 to 7 0 to 7 C C pp9l2 pp9l1 pp9l0 C pp8l2 pp8l1 pp8l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 9/usb pdreq interrupt level reserved port input 8/spi interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 003002a0 (b) port input 8C9 interrupt priority register (pint_pp89l) C 0 to 7 0 to 7 C C pp11l2 pp11l1 pp11l0 C pp10l2 pp10l1 pp10l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 11/dcsio interrupt level reserved port input 10/usb interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 003002a1 (b) port input 10C11 interrupt priority register (pint_pp1011l) C 0 to 7 0 to 7 C C pp13l2 pp13l1 pp13l0 C pp12l2 pp12l1 pp12l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 13 interrupt level reserved port input 12 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 003002a2 (b) port input 12C13 interrupt priority register (pint_pp1213l) C 0 to 7 0 to 7 C C pp15l2 pp15l1 pp15l0 C pp14l2 pp14l1 pp14l0 d7 d6 d5 d4 d3 d2 d1 d0 reserved port input 15 interrupt level reserved port input 14 interrupt level C x x x C x x x C r/w C r/w 0 when being read. 0 when being read. 003002a3 (b) port input 14C15 interrupt priority register (pint_pp1415l) C 0 to 7 C pi2s2 pi2s1 pi2s0 d7C3 d2 d1 d0 reserved i 2 s interrupt level C x x x C r/w 0 when being read. 003002a4 (b) i 2 s interrupt priority register (pint_pi2s) ep15 ep14 ep13 ep12 ep11 ep10 ep9 ep8 d7 d6 d5 d4 d3 d2 d1 d0 port input 15 port input 14 port input 13 port input 12 port input 11/dcsio port input 10/usb port input 9/usb pdreq port input 8/spi 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 003002a6 (b) 1 enabled 0 disabled port input 8C15 interrupt enable register (pint_ep815) C ei2s C d7C3 d2 d1C0 reserved i 2 s reserved C 0 C C r/w C 0 when being read. 0 when being read. 003002a7 (b) i 2 s interrupt enable register (pint_ei2s) C 1 enabled 0 disabled C fp15 fp14 fp13 fp12 fp11 fp10 fp9 fp8 d7 d6 d5 d4 d3 d2 d1 d0 port input 15 port input 14 port input 13 port input 12 port input 11/dcsio port input 10/usb port input 9/usb pdreq port input 8/spi x x x x x x x x r/w r/w r/w r/w r/w r/w r/w r/w 003002a9 (b) 1 occurred 0 not occurred port input 8C15 interrupt cause flag register (pint_fp815) C fi2s C d7C3 d2 d1C0 reserved i 2 s reserved C x C C r/w C 0 when being read. 0 when being read. 003002aa (b) 1 occurred 0 not occurred i 2 s interrupt cause flag register (pint_fi2s) C C
appendix a i/o map ap-a-10 epson s1c33e08 technical manual 0x3002acC0x3002af interrupt controller name address register name bit function setting init. r/w remarks rp15 rp14 rp13 rp12 rp11 rp10 rp9 rp8 d7 d6 d5 d4 d3 d2 d1 d0 port input 15 port input 14 port input 13 port input 12 port input 11/dcsio port input 10/usb port input 9/usb pdreq port input 8/spi 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 003002ac (b) 1 idma request 0 interrupt request port input 8C15 idma request register (pidmareq _rp815) C ri2s d7C1 d0 reserved i 2 s C 0 C r/w C 0 when being read. 003002ad (b) 1 idma request 0 interrupt request i 2 s idma request register (pidmareq_ri2s) dep15 dep14 dep13 dep12 dep11 dep10 dep9 dep8 d7 d6 d5 d4 d3 d2 d1 d0 port input 15 port input 14 port input 13 port input 12 port input 11/dcsio port input 10/usb port input 9/usb pdreq port input 8/spi 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 003002ae (b) 1 idma enabled 0 idma disabled port input 8C15 idma enable register (pidmaen_dep815) C dei2s d7C1 d0 reserved i 2 s C 0 C r/w C 0 when being read. 003002af (b) 1 idma enabled 0 idma disabled i 2 s idma enable register (pidmaen_dei2s)
appendix a i/o map s1c33e08 technical manual epson ap-a-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300300C0x300318 card interface name address register name bit function setting init. r/w remarks cardpc21 cardpc20 cardpc11 cardpc10 cardcf1 cardcf0 cardsmt1 cardsmt0 d7 d6 d5 d4 d3 d2 d1 d0 pc card 2 area configuration pc card 1 area configuration cf area configuration smartmedia/nand flash area configuration 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300300 (b) card i/f area configuration register (pcardsetup) 11 10 01 00 bit[1:0] #ce area #ce11 (area 11, 12) #ce9 (area 9, 22) #ce7 (area 7, 19) #ce4 (area 4, 14) C cardio5 cardio4 cardio3 cardio2 cardio1 cardio0 d7C6 d5 d4 d3 d2 d1 d0 reserved card5 port function select card4 port function select card3 port function select card2 port function select card1 port function select card0 port function select C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300302 (b) card i/f output port configuration register (pcardfuncsel05) C 1 #cfce2 0 #we 1 #cfce1 0 #oe 1 #smwr 0 #iowr 1 #smrd 0 #iord 1 #cfce2 0 #smwr 1 #cfce1 0 #smrd C eccsel2 eccsel1 eccsel0 d7C3 d2 d1 d0 reserved external memory area select for triggering ecc C 0 0 0 C r/w 0 when being read. 00300310 (b) ecc trigger area select register (pecctrigsel) C eccsel[2:0] 111 110 101 100 011 010 001 000 #ce area #ce11 #ce10 #ce9 #ce8 #ce7 #ce6 #ce5 #ce4 C eccrdy1 eccrst eccrdy0 d7C2 d1 d0 reserved area 1 parity data ready status ecc circuit reset area 0 parity data ready status C 0 C 0 C r w r 0 when being read. 00300311 (b) ecc reset/ready register (peccrstrdy) C 1 ready 0 busy 1 reset 0 invalid 1 ready 0 busy C eccen d7C1 d0 reserved ecc circuit enable C 0 C r/w 0 when being read. 00300312 (b) ecc enable register (peccena) C 1 enabled 0 disabled C mode d7C1 d0 reserved card device mode C 0 C r/w 0 when being read. 00300313 (b) ecc mode register (peccmd) C 1 16 bits 0 8 bits 0x0 to 0x3f C C cp05 cp04 cp03 cp02 cp01 cp00 C C d7 d6 d5 d4 d3 d2 d1 d0 area 0 column parity data unused bit unused bit 1 1 1 1 1 1 1 1 r r r 1 when being read. 00300314 (b) area 0 ecc column parity data register (pecc0cp) 0x0 to 0xff (low-order 8 bits) lp07 lp06 lp05 lp04 lp03 lp02 lp01 lp00 d7 d6 d5 d4 d3 d2 d1 d0 area 0 ecc line parity lp00 = lsb 1 1 1 1 1 1 1 1 r 00300316 (b) area 0 ecc line parity register 0 (pecc0lpl) 0x0 to 0xff (high-order 8 bits) lp015 lp014 lp013 lp012 lp011 lp010 lp09 lp08 d7 d6 d5 d4 d3 d2 d1 d0 area 0 ecc line parity lp015 = msb 1 1 1 1 1 1 1 1 r 00300317 (b) area 0 ecc line parity register 1 (pecc0lph) 0x0 to 0x3f C C cp15 cp14 cp13 cp12 cp11 cp10 C C d7 d6 d5 d4 d3 d2 d1 d0 area 1 column parity data unused bit unused bit 1 1 1 1 1 1 1 1 r r r 1 when being read. 00300318 (b) area 1 ecc column parity data register (pecc1cp)
appendix a i/o map ap-a-12 epson s1c33e08 technical manual 0x30031aC0x30031b card interface name address register name bit function setting init. r/w remarks 0x0 to 0xff (low-order 8 bits) lp17 lp16 lp15 lp14 lp13 lp12 lp11 lp10 d7 d6 d5 d4 d3 d2 d1 d0 area 1 ecc line parity lp10 = lsb 1 1 1 1 1 1 1 1 r 0030031a (b) area 1 ecc line parity register 0 (pecc1lpl) 0x0 to 0xff (high-order 8 bits) lp115 lp114 lp113 lp112 lp111 lp110 lp19 lp18 d7 d6 d5 d4 d3 d2 d1 d0 area 1 ecc line parity lp115 = msb 1 1 1 1 1 1 1 1 r 0030031b (b) area 1 ecc line parity register 1 (pecc1lph)
appendix a i/o map s1c33e08 technical manual epson ap-a-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300380C0x300387 i/o ports name address register name bit function setting init. r/w remarks p07d p06d p05d p04d p03d p02d p01d p00d d7 d6 d5 d4 d3 d2 d1 d0 p07 i/o port data p06 i/o port data p05 i/o port data p04 i/o port data p03 i/o port data p02 i/o port data p01 i/o port data p00 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 00300380 (b) 1 high 0 low p0 port data register (pp0_p0d) ioc07 ioc06 ioc05 ioc04 ioc03 ioc02 ioc01 ioc00 d7 d6 d5 d4 d3 d2 d1 d0 p07 i/o control p06 i/o control p05 i/o control p04 i/o control p03 i/o control p02 i/o control p01 i/o control p00 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300381 (b) 1 output 0 input p0 i/o control register (pp0_ioc0) p17d p16d p15d p14d p13d p12d p11d p10d d7 d6 d5 d4 d3 d2 d1 d0 p17 i/o port data p16 i/o port data p15 i/o port data p14 i/o port data p13 i/o port data p12 i/o port data p11 i/o port data p10 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 00300382 (b) 1 high 0 low p1 port data register (pp1_p1d) ioc17 ioc16 ioc15 ioc14 ioc13 ioc12 ioc11 ioc10 d7 d6 d5 d4 d3 d2 d1 d0 p17 i/o control p16 i/o control p15 i/o control p14 i/o control p13 i/o control p12 i/o control p11 i/o control p10 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300383 (b) 1 output 0 input p1 i/o control register (pp1_ioc1) p27d p26d p25d p24d p23d p22d p21d p20d d7 d6 d5 d4 d3 d2 d1 d0 p27 i/o port data p26 i/o port data p25 i/o port data p24 i/o port data p23 i/o port data p22 i/o port data p21 i/o port data p20 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 00300384 (b) 1 high 0 low p2 port data register (pp2_p2d) ioc27 ioc26 ioc25 ioc24 ioc23 ioc22 ioc21 ioc20 d7 d6 d5 d4 d3 d2 d1 d0 p27 i/o control p26 i/o control p25 i/o control p24 i/o control p23 i/o control p22 i/o control p21 i/o control p20 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300385 (b) 1 output 0 input p2 i/o control register (pp2_ioc2) C p36d p35d p34d p33d p32d p31d p30d d7 d6 d5 d4 d3 d2 d1 d0 reserved p36 i/o port data p35 i/o port data p34 i/o port data p33 i/o port data p32 i/o port data p31 i/o port data p30 i/o port data C ext. ext. ext. ext. ext. ext. ext. C r/w r/w r/w r/w r/w r/w r/w 0 when being read. ext.: the initial value depends on the external pin status. 00300386 (b) 1 high 0 low p3 port data register (pp3_p3d) C C ioc36 ioc35 ioc34 ioc33 ioc32 ioc31 ioc30 d7 d6 d5 d4 d3 d2 d1 d0 reserved p36 i/o control p35 i/o control p34 i/o control p33 i/o control p32 i/o control p31 i/o control p30 i/o control C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300387 (b) 1 output 0 input p3 i/o control register (pp3_ioc3 C
appendix a i/o map ap-a-14 epson s1c33e08 technical manual 0x300388C0x300391 i/o ports name address register name bit function setting init. r/w remarks p47d p46d p45d p44d p43d p42d p41d p40d d7 d6 d5 d4 d3 d2 d1 d0 p47 i/o port data p46 i/o port data p45 i/o port data p44 i/o port data p43 i/o port data p42 i/o port data p41 i/o port data p40 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 00300388 (b) 1 high 0 low p4 port data register (pp4_p4d) ioc47 ioc46 ioc45 ioc44 ioc43 ioc42 ioc41 ioc40 d7 d6 d5 d4 d3 d2 d1 d0 p47 i/o control p46 i/o control p45 i/o control p44 i/o control p43 i/o control p42 i/o control p41 i/o control p40 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300389 (b) 1 output 0 input p4 i/o control register (pp4_ioc4) p57d p56d p55d p54d p53d p52d p51d p50d d7 d6 d5 d4 d3 d2 d1 d0 p57 i/o port data p56 i/o port data p55 i/o port data p54 i/o port data p53 i/o port data p52 i/o port data p51 i/o port data p50 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 0030038a (b) 1 high 0 low p5 port data register (pp5_p5d) ioc57 ioc56 ioc55 ioc54 ioc53 ioc52 ioc51 ioc50 d7 d6 d5 d4 d3 d2 d1 d0 p57 i/o control p56 i/o control p55 i/o control p54 i/o control p53 i/o control p52 i/o control p51 i/o control p50 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 0030038b (b) 1 output 0 input p5 i/o control register (pp5_ioc5) p67d p66d p65d p64d p63d p62d p61d p60d d7 d6 d5 d4 d3 d2 d1 d0 p67 i/o port data p66 i/o port data p65 i/o port data p64 i/o port data p63 i/o port data p62 i/o port data p61 i/o port data p60 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 0030038c (b) 1 high 0 low p6 port data register (pp6_p6d) ioc67 ioc66 ioc65 ioc64 ioc63 ioc62 ioc61 ioc60 d7 d6 d5 d4 d3 d2 d1 d0 p67 i/o control p66 i/o control p65 i/o control p64 i/o control p63 i/o control p62 i/o control p61 i/o control p60 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 0030038d (b) 1 output 0 input p6 i/o control register (pp6_ioc6) C p74d p73d p72d p71d p70d d7C5 d4 d3 d2 d1 d0 reserved p74 input port data p73 input port data p72 input port data p71 input port data p70 input port data C ext. ext. ext. ext. ext. C r r r r r 0 when being read. ext.: the initial value depends on the external pin status. 0030038e (b) 1 high 0 low p7 port data register (pp7_p7d) C C p85d p84d p83d p82d p81d p80d d7C6 d5 d4 d3 d2 d1 d0 reserved p85 i/o port data p84 i/o port data p83 i/o port data p82 i/o port data p81 i/o port data p80 i/o port data C ext. ext. ext. ext. ext. ext. C r/w r/w r/w r/w r/w r/w 0 when being read. ext.: the initial value depends on the external pin status. 00300390 (b) 1 high 0 low p8 port data register (pp8_p8d) C C ioc85 ioc84 ioc83 ioc82 ioc81 ioc80 d7C6 d5 d4 d3 d2 d1 d0 reserved p85 i/o control p84 i/o control p83 i/o control p82 i/o control p81 i/o control p80 i/o control C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300391 (b) 1 output 0 input p8 i/o control register (pp8_ioc8) C
appendix a i/o map s1c33e08 technical manual epson ap-a-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300392C0x3003a1 i/o ports name address register name bit function setting init. r/w remarks p97d p96d p95d p94d p93d p92d p91d p90d d7 d6 d5 d4 d3 d2 d1 d0 p97 i/o port data p96 i/o port data p95 i/o port data p94 i/o port data p93 i/o port data p92 i/o port data p91 i/o port data p90 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 00300392 (b) 1 high 0 low p9 port data register (pp9_p9d) ioc97 ioc96 ioc95 ioc94 ioc93 ioc92 ioc91 ioc90 d7 d6 d5 d4 d3 d2 d1 d0 p97 i/o control p96 i/o control p95 i/o control p94 i/o control p93 i/o control p92 i/o control p91 i/o control p90 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300393 (b) 1 output 0 input p9 i/o control register (pp9_ioc9) cfp031 cfp030 cfp021 cfp020 cfp011 cfp010 cfp001 cfp000 d7 d6 d5 d4 d3 d2 d1 d0 p03 port extended function p02 port extended function p01 port extended function p00 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a0 (b) p00Cp03 port function select register (pp0_03_cfp) cfp03[1:0] function reserved #dmaend3 #srdy0 p03 cfp02[1:0] function reserved #dmaend2 #sclk0 p02 cfp01[1:0] function reserved #dmaack3 sout0 p01 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp00[1:0] function reserved #dmaack2 sin0 p00 cfp071 cfp070 cfp061 cfp060 cfp051 cfp050 cfp041 cfp040 d7 d6 d5 d4 d3 d2 d1 d0 p07 port extended function p06 port extended function p05 port extended function p04 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a1 (b) p04Cp07 port function select register (pp0_47_cfp) cfp07[1:0] function reserved i2s_mclk #srdy1 p07 cfp06[1:0] function reserved i2s_sck #sclk1 p06 cfp05[1:0] function reserved i2s_ws sout1 p05 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp04[1:0] function reserved i2s_sdo sin1 p04
appendix a i/o map ap-a-16 epson s1c33e08 technical manual 0x3003a2C0x3003a4 i/o ports name address register name bit function setting init. r/w remarks cfp131 cfp130 cfp121 cfp120 cfp111 cfp110 cfp101 cfp100 d7 d6 d5 d4 d3 d2 d1 d0 p13 port extended function p12 port extended function p11 port extended function p10 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a2 (b) p10Cp13 port function select register (pp1_03_cfp) cfp13[1:0] function #dmaack1 #srdy0 tm3 p13 cfp12[1:0] function #dmaack0 #sclk0 tm2 p12 cfp11[1:0] function #dmaend1 sout0 tm1 p11 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp10[1:0] function #dmaend0 sin0 tm0 p10 cfp171 cfp170 cfp161 cfp160 cfp151 cfp150 cfp141 cfp140 d7 d6 d5 d4 d3 d2 d1 d0 p17 port extended function p16 port extended function p15 port extended function p14 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w when trcmux (d0/0x300014) is set to 1 (default), this register becomes ineffective and the port is configured for debugging. 003003a3 (b) p14Cp17 port function select register (pp1_47_cfp) cfp17[1:0] function tft_ctl2 #srdy1 dcsio1 p17 cfp16[1:0] function tft_ctl3 #sclk1 dcsio0 p16 cfp15[1:0] function tft_ctl0 sout1 tm5 p15 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp14[1:0] function reserved sin1 tm4 p14 cfp231 cfp230 cfp221 cfp220 cfp211 cfp210 cfp201 cfp200 d7 d6 d5 d4 d3 d2 d1 d0 p23 port extended function p22 port extended function p21 port extended function p20 port extended function 0 0 0 0 0 1 0 0 r/w r/w r/w r/w 003003a4 (b) p20Cp23 port function select register (pp2_03_cfp) cfp23[1:0] function reserved tft_ctl1 #sdras p23 cfp22[1:0] function reserved #sdcs p22 cfp21[1:0] function reserved sdclk p21 1 ? 01 00 1 ? 01 00 1 ? 01 00 11 10 01 00 cfp20[1:0] function reserved sdcke p20
appendix a i/o map s1c33e08 technical manual epson ap-a-17 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x3003a5C0x3003a8 i/o ports name address register name bit function setting init. r/w remarks cfp271 cfp270 cfp261 cfp260 cfp251 cfp250 cfp241 cfp240 d7 d6 d5 d4 d3 d2 d1 d0 p27 port extended function p26 port extended function p25 port extended function p24 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a5 (b) p24Cp27 port function select register (pp2_47_cfp) cfp27[1:0] function reserved dqmh p27 cfp26[1:0] function reserved dqml p26 cfp25[1:0] function reserved #sdwe p25 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp24[1:0] function reserved #sdcas p24 cfp331 cfp330 cfp321 cfp320 cfp311 cfp310 cfp301 cfp300 d7 d6 d5 d4 d3 d2 d1 d0 p33 port extended function p32 port extended function p31 port extended function p30 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a6 (b) p30Cp33 port function select register (pp3_03_cfp) cfp33[1:0] function reserved #dmareq3 card5 p33 cfp32[1:0] function reserved #dmareq2 card4 p32 cfp31[1:0] function reserved #dmareq1 card3 p31 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp30[1:0] function reserved #dmareq0 card2 p30 C cfp361 cfp360 cfp351 cfp350 cfp341 cfp340 d7C6 d5 d4 d3 d2 d1 d0 reserved p36 port extended function p35 port extended function p34 port extended function C 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. when trcmux (d0/0x300014) is set to 1 (default), this register becomes ineffective and the port is configured for debugging. 003003a7 (b) p34Cp36 port function select register (pp3_46_cfp) cfp36[1:0] function C reserved p36 dst2 cfp35[1:0] function reserved p35 dclk 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp34[1:0] function reserved p34 dsio cfp431 cfp430 cfp421 cfp420 cfp411 cfp410 cfp401 cfp400 d7 d6 d5 d4 d3 d2 d1 d0 p43 port extended function p42 port extended function p41 port extended function p40 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a8 (b) p40Cp43 port function select register (pp4_03_cfp) cfp43[1:0] function reserved fpdat9 p43 a21 cfp42[1:0] function reserved fpdat8 p42 a22 cfp41[1:0] function excl3 #sdras p41 a23 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp40[1:0] function excl4 #sdcas p40 a24
appendix a i/o map ap-a-18 epson s1c33e08 technical manual 0x3003a9C0x3003ab i/o ports name address register name bit function setting init. r/w remarks cfp471 cfp470 cfp461 cfp460 cfp451 cfp450 cfp441 cfp440 d7 d6 d5 d4 d3 d2 d1 d0 p47 port extended function p46 port extended function p45 port extended function p44 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003a9 (b) p44Cp47 port function select register (pp4_47_cfp) cfp47[1:0] function reserved p47 a11 cfp46[1:0] function reserved tft_ctl2 p46 a18 cfp45[1:0] function reserved fpdat11 p45 a19 11 10 01 00 11 10 01 00 11 10 01 00 1 ? 01 00 cfp44[1:0] function reserved fpdat10 p44 a20 cfp531 cfp530 cfp521 cfp520 cfp511 cfp510 cfp501 cfp500 d7 d6 d5 d4 d3 d2 d1 d0 p53 port extended function p52 port extended function p51 port extended function p50 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003aa (b) p50Cp53 port function select register (pp5_03_cfp) cfp53[1:0] function reserved sda10 p53 #ce7 cfp52[1:0] function cmu_clk #ce6 bclk p52 cfp51[1:0] function reserved card1 p51 #ce5 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp50[1:0] function reserved card0 p50 #ce4 cfp571 cfp570 cfp561 cfp560 cfp551 cfp550 cfp541 cfp540 d7 d6 d5 d4 d3 d2 d1 d0 p57 port extended function p56 port extended function p55 port extended function p54 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ab (b) p54Cp57 port function select register (pp5_47_cfp) cfp57[1:0] function reserved p57 #ce10 cfp56[1:0] function reserved p56 #ce11 cfp55[1:0] function reserved card0 p55 #ce9 11 10 01 00 11 10 01 00 1 ? 01 00 1 ? 01 00 cfp54[1:0] function reserved card1 p54 #ce8
appendix a i/o map s1c33e08 technical manual epson ap-a-19 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x3003acC0x3003af i/o ports name address register name bit function setting init. r/w remarks cfp631 cfp630 cfp621 cfp620 cfp611 cfp610 cfp601 cfp600 d7 d6 d5 d4 d3 d2 d1 d0 p63 port extended function p62 port extended function p61 port extended function p60 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ac (b) p60Cp63 port function select register (pp6_03_cfp) cfp63[1:0] function #wdt_nmi wdt_clk #srdy2 p63 cfp62[1:0] function cmu_clk #adtrg #sclk2 p62 cfp61[1:0] function excl1 dcsio1 sout2 p61 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp60[1:0] function excl0 dcsio0 sin2 p60 cfp671 cfp670 cfp661 cfp660 cfp651 cfp650 cfp641 cfp640 d7 d6 d5 d4 d3 d2 d1 d0 p67 port extended function p66 port extended function p65 port extended function p64 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ad (b) p64Cp67 port function select register (pp6_47_cfp) cfp67[1:0] function reserved fpdat10 spi_clk p67 cfp66[1:0] function reserved fpdat9 sdo p66 cfp65[1:0] function reserved fpdat8 sdi p65 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfp64[1:0] function reserved excl2 #wait p64 cfp731 cfp730 cfp721 cfp720 cfp711 cfp710 cfp701 cfp700 d7 d6 d5 d4 d3 d2 d1 d0 p73 port extended function p72 port extended function p71 port extended function p70 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003ae (b) p70Cp73 port function select register (pp7_03_cfp) cfp73[1:0] function reserved ain3 p73 cfp72[1:0] function reserved ain2 p72 cfp71[1:0] function reserved ain1 p71 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp70[1:0] function reserved ain0 p70 C cfp741 cfp740 d7C2 d1 d0 reserved p74 port extended function C 0 0 C r/w 0 when being read. 003003af (b) p74 port function select register (pp7_4_cfp) cfp74[1:0] function reserved excl5 ain4 p74 C 11 10 01 00
appendix a i/o map ap-a-20 epson s1c33e08 technical manual 0x3003b0C0x3003b3 i/o ports name address register name bit function setting init. r/w remarks cfp831 cfp830 cfp821 cfp820 cfp811 cfp810 cfp801 cfp800 d7 d6 d5 d4 d3 d2 d1 d0 p83 port extended function p82 port extended function p81 port extended function p80 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b0 (b) p80Cp83 port function select register (pp8_03_cfp) cfp83[1:0] function bclk tft_ctl1 fpdrdy p83 cfp82[1:0] function reserved fpshift p82 cfp81[1:0] function reserved fpline p81 1 ? 01 00 1 ? 01 00 1 ? 01 00 11 10 01 00 cfp80[1:0] function reserved fpframe p80 C cfp851 cfp850 cfp841 cfp840 d7C4 d3 d2 d1 d0 reserved p85 port extended function p84 port extended function C 0 0 0 0 C r/w r/w 0 when being read. 003003b1 (b) p84Cp85 port function select register (pp8_45_cfp) cfp85[1:0] function C reserved dcsio1 p85 cfp84[1:0] function reserved fpdat11 dcsio0 p84 11 10 01 00 1 ? 01 00 cfp931 cfp930 cfp921 cfp920 cfp911 cfp910 cfp901 cfp900 d7 d6 d5 d4 d3 d2 d1 d0 p93 port extended function p92 port extended function p91 port extended function p90 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b2 (b) p90Cp93 port function select register (pp9_03_cfp) cfp93[1:0] function reserved fpdat3 p93 cfp92[1:0] function reserved fpdat2 p92 cfp91[1:0] function reserved fpdat1 p91 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp90[1:0] function reserved fpdat0 p90 cfp971 cfp970 cfp961 cfp960 cfp951 cfp950 cfp941 cfp940 d7 d6 d5 d4 d3 d2 d1 d0 p97 port extended function p96 port extended function p95 port extended function p94 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003b3 (b) p94Cp97 port function select register (pp9_47_cfp) cfp97[1:0] function reserved fpdat7 p97 cfp96[1:0] function reserved fpdat6 p96 cfp95[1:0] function reserved fpdat5 p95 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfp94[1:0] function reserved fpdat4 p94
appendix a i/o map s1c33e08 technical manual epson ap-a-21 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x3003c0C0x3003c3 i/o ports name address register name bit function setting init. r/w remarks spt31 spt30 spt21 spt20 spt11 spt10 spt01 spt00 d7 d6 d5 d4 d3 d2 d1 d0 fpt3 interrupt input port selectio n fpt2 interrupt input port selectio n fpt1 interrupt input port selectio n fpt0 interrupt input port selectio n 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c0 (b) port input interrupt select register 1 (ppintsel _spt03) spt3[1:0] port p33 p13 p23 p03 spt2[1:0] port p32 p12 p22 p02 spt1[1:0] port p31 p11 p21 p01 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 spt0[1:0] port p30 p10 p20 p00 spt71 spt70 spt61 spt60 spt51 spt50 spt41 spt40 d7 d6 d5 d4 d3 d2 d1 d0 fpt7 interrupt input port selectio n fpt6 interrupt input port selectio n fpt5 interrupt input port selectio n fpt4 interrupt input port selectio n 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c1 (b) port input interrupt select register 2 (ppintsel _spt47) spt7[1:0] port p63 p17 p27 p07 spt6[1:0] port p62 p16 p26 p06 spt5[1:0] port p61 p15 p25 p05 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 spt4[1:0] port p60 p14 p24 p04 1 high level or rising edge 0 low level or falling edge sppt7 sppt6 sppt5 sppt4 sppt3 sppt2 sppt1 sppt0 d7 d6 d5 d4 d3 d2 d1 d0 fpt7 input polarity selection fpt6 input polarity selection fpt5 input polarity selection fpt4 input polarity selection fpt3 input polarity selection fpt2 input polarity selection fpt1 input polarity selection fpt0 input polarity selection 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 003003c2 (b) port input interrupt polarity select register 1 (ppintpol _spp07) 1 edge 0 level sept7 sept6 sept5 sept4 sept3 sept2 sept1 sept0 d7 d6 d5 d4 d3 d2 d1 d0 fpt7 edge/level selection fpt6 edge/level selection fpt5 edge/level selection fpt4 edge/level selection fpt3 edge/level selection fpt2 edge/level selection fpt1 edge/level selection fpt0 edge/level selection 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 003003c3 (b) port input interrupt edge/level select register 1 (ppintel _sept07)
appendix a i/o map ap-a-22 epson s1c33e08 technical manual 0x3003c4C0x3003c7 i/o ports name address register name bit function setting init. r/w remarks sptb1 sptb0 spta1 spta0 spt91 spt90 spt81 spt80 d7 d6 d5 d4 d3 d2 d1 d0 fpt11 interrupt input port selection fpt10 interrupt input port selection fpt9 interrupt input port selectio n fpt8 interrupt input port selectio n 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c4 (b) port input interrupt select register 3 (ppintsel _spt811) sptb[1:0] port p93 int_dcsio p83 p73 spta[1:0] port p92 int_usb p82 p72 spt9[1:0] port p91 usb_pdreq p81 p71 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 spt8[1:0] port p90 int_spi p80 p70 sptf1 sptf0 spte1 spte0 sptd1 sptd0 sptc1 sptc0 d7 d6 d5 d4 d3 d2 d1 d0 fpt15 interrupt input port selection fpt14 interrupt input port selection fpt13 interrupt input port selection fpt12 interrupt input port selection 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 003003c5 (b) port input interrupt select register 4 (ppintsel _spt1215) sptf[1:0] port p97 p67 p53 p43 spte[1:0] port p96 p66 p52 p42 sptd[1:0] port p95 p65 p51 p41 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 sptc[1:0] port p94 p64 p50 p40 1 high level or rising edge 0 low level or falling edge spptf sppte spptd spptc spptb sppta sppt9 sppt8 d7 d6 d5 d4 d3 d2 d1 d0 fpt15 input polarity selection fpt14 input polarity selection fpt13 input polarity selection fpt12 input polarity selection fpt11 input polarity selection fpt10 input polarity selection fpt9 input polarity selection fpt8 input polarity selection 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 003003c6 (b) port input interrupt polarity select register 2 (ppintpol _spp815) 1 edge 0 level septf septe septd septc septb septa sept9 sept8 d7 d6 d5 d4 d3 d2 d1 d0 fpt15 edge/level selection fpt14 edge/level selection fpt13 edge/level selection fpt12 edge/level selection fpt11 edge/level selection fpt10 edge/level selection fpt9 edge/level selection fpt8 edge/level selection 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 003003c7 (b) port input interrupt edge/level select register 2 (ppintel _sept815)
appendix a i/o map s1c33e08 technical manual epson ap-a-23 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x3003d0C0x3003d5 i/o ports name address register name bit function setting init. r/w remarks C sppk12 sppk11 sppk10 C sppk02 sppk01 sppk00 d7 d6 d5 d4 d3 d2 d1 d0 reserved fpk1 interrupt input port selectio n reserved fpk0 interrupt input port selectio n C 0 0 0 C 0 0 0 C r/w C r/w 0 when being read. 0 when being read. 003003d0 (b) key input interrupt select register (pkintsel _sppk01) sppk1[2:0] port p9[7:4] p8[5:4] p7[3:0] p6[7:4] p3[3:0] p2[7:4] p1[7:4] p0[7:4] 111 110 101 100 011 010 001 000 C sppk0[2:0] port p9[4:0] p8[4:0] p5[4:0] p6[4:0] p4[4:0] p2[4:0] p1[4:0] p0[4:0] 111 110 101 100 011 010 001 000 C C scpk04 scpk03 scpk02 scpk01 scpk00 d7C5 d4 d3 d2 d1 d0 reserved fpk04 input comparison fpk03 input comparison fpk02 input comparison fpk01 input comparison fpk00 input comparison C C 0 0 0 0 0 C r/w r/w r/w r/w r/w 0 when being read. 003003d2 (b) 1 high 0 low key input interrupt (fpk0) input comparison register (pkintcomp _scpk0) C scpk13 scpk12 scpk11 scpk10 d7C4 d3 d2 d1 d0 reserved fpk13 input comparison fpk12 input comparison fpk11 input comparison fpk10 input comparison C C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 003003d3 (b) 1 high 0 low key input interrupt (fpk1) input comparison register (pkintcomp _scpk1) C smpk04 smpk03 smpk02 smpk01 smpk00 d7C5 d4 d3 d2 d1 d0 reserved fpk04 input mask fpk03 input mask fpk02 input mask fpk01 input mask fpk00 input mask C C 0 0 0 0 0 C r/w r/w r/w r/w r/w 0 when being read. 003003d4 (b) 1 interrupt enabled 0 interrupt disabled key input interrupt (fpk0) input mask register (pkintcomp _smpk0) C smpk13 smpk12 smpk11 smpk10 d7C4 d3 d2 d1 d0 reserved fpk13 input mask fpk12 input mask fpk11 input mask fpk10 input mask C C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 003003d5 (b) 1 interrupt enabled 0 interrupt disabled key input interrupt (fpk1) input mask register (pkintcomp _smpk1)
appendix a i/o map ap-a-24 epson s1c33e08 technical manual 0x300520C0x300544 a/d converter name address register name bit function setting init. r/w remarks C C psonad psad2 psad1 psad0 d15C4 d3 d2 d1 d0 reserved a/d converter clock control a/d converter clock division ratio selection C 0 0 0 0 C r/w r/w 0 when being read. 00300520 (hw) 1 on 0 off psad[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/256 mclk/128 mclk/64 mclk/32 mclk/16 mclk/8 mclk/4 mclk/2 a/d clock control register (pad_clkctl) C add9 add8 add7 add6 add5 add4 add3 add2 add1 add0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d converted data add9 = msb add0 = lsb C 0x0 to 0x3ff C 0 0 0 0 0 0 0 0 0 0 C r 0 when being read. 00300540 (hw) a/d conversion result register (pad_add) C 0 to 4 0 to 4 0 to 4 C ce2 ce1 ce0 cs2 cs1 cs0 C ms ts1 ts0 ch2 ch1 ch0 d15C14 d13 d12 d11 d10 d9 d8 d7C6 d5 d4 d3 d2 d1 d0 reserved a/d converter end channel selection a/d converter start channel selection reserved a/d conversion mode selection a/d conversion trigger selection a/d conversion channel status C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w r/w C r/w r/w r 0 when being read. 0 when being read. 00300542 (hw) a/d trigger/ channel select register (pad_trig_chnl) 11 10 01 00 ts[1:0] C trigger #adtrg pin reserved 16-bit timer software 1 continuous 0 normal adcmpe adcmp2 adcmp1 adcmp0 aduprst adlwrst st1 st0 C intmode cmpinten cnvinten adf ade adst owe d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 upper/lower-limit comparison enable upper/lower-limit comparison channel selection upper-limit comparison status lower-limit comparison status input signal sampling time setup reserved interrupt signal mode out-of-range int. enable conversion-complete int. enable conversion-complete flag a/d enable a/d conversion control/status overwrite error flag 0 to 4 11 10 01 00 st[1:0] sampling time 9 clocks 7 clocks 5 clocks 3 clocks 0 0 0 0 0 0 1 1 C 0 0 1 0 0 0 0 r/w r/w r r r/w C r/w r/w r/w r r/w r/w r/w can be used when adcadv = "1". use with 9 clocks. 0 when being read. can be used when adcadv = "1". reset when add is read. reset by writing 0. 00300544 (hw) a/d control/ status register (pad_en_smpl _stat) 1 out of range 0 within range 1 enabled 0 disabled 1 out of range 0 within range C 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 complete only 0 or 1 completed 0 run/standby 1 start/run 0 stop 1 error 0 normal
appendix a i/o map s1c33e08 technical manual epson ap-a-25 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300546C0x300550 a/d converter name address register name bit function setting init. r/w remarks C owe4 owe3 owe2 owe1 owe0 C adf4 adf3 adf2 adf1 adf0 d15C13 d12 d11 d10 d9 d8 d7C5 d4 d3 d2 d1 d0 reserved ch.4 overwrite error flag ch.3 overwrite error flag ch.2 overwrite error flag ch.1 overwrite error flag ch.0 overwrite error flag reserved ch.4 conversion-complete flag ch.3 conversion-complete flag ch.2 conversion-complete flag ch.1 conversion-complete flag ch.0 conversion-complete flag C 0 0 0 0 0 C 0 0 0 0 0 C r/w r/w r/w r/w r/w C r r r r r 0 when being read. can be used when adcadv = "1". reset by writing 0. 0 when being read. can be used when adcadv = "1". reset when adbufx is read. 00300546 (hw) a/d channel status flag register (pad_end) 1 error 0 normal 1 completed 0 run/standby C C 0x0 to 0x3ff C ad0buf9 ad0buf8 ad0buf7 ad0buf6 ad0buf5 ad0buf4 ad0buf3 ad0buf2 ad0buf1 ad0buf0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d ch.0 converted data ad0buf9 = msb ad0buf0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r 0 when being read. can be used when adcadv = "1". 00300548 (hw) a/d ch.0 conversion result buffer register (pad_ch0_buf) C 0x0 to 0x3ff C ad1buf9 ad1buf8 ad1buf7 ad1buf6 ad1buf5 ad1buf4 ad1buf3 ad1buf2 ad1buf1 ad1buf0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d ch.1 converted data ad1buf9 = msb ad1buf0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r 0 when being read. can be used when adcadv = "1". 0030054a (hw) a/d ch.1 conversion result buffer register (pad_ch1_buf) C 0x0 to 0x3ff C ad2buf9 ad2buf8 ad2buf7 ad2buf6 ad2buf5 ad2buf4 ad2buf3 ad2buf2 ad2buf1 ad2buf0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d ch.2 converted data ad2buf9 = msb ad2buf0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r 0 when being read. can be used when adcadv = "1". 0030054c (hw) a/d ch.2 conversion result buffer register (pad_ch2_buf) C 0x0 to 0x3ff C ad3buf9 ad3buf8 ad3buf7 ad3buf6 ad3buf5 ad3buf4 ad3buf3 ad3buf2 ad3buf1 ad3buf0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d ch.3 converted data ad3buf9 = msb ad3buf0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r 0 when being read. can be used when adcadv = "1". 0030054e (hw) a/d ch.3 conversion result buffer register (pad_ch3_buf) C 0x0 to 0x3ff C ad4buf9 ad4buf8 ad4buf7 ad4buf6 ad4buf5 ad4buf4 ad4buf3 ad4buf2 ad4buf1 ad4buf0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d ch.4 converted data ad4buf9 = msb ad4buf0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r 0 when being read. can be used when adcadv = "1". 00300550 (hw) a/d ch.4 conversion result buffer register (pad_ch4_buf) C
appendix a i/o map ap-a-26 epson s1c33e08 technical manual 0x300558C0x30055e a/d converter name address register name bit function setting init. r/w remarks 0x0 to 0x3ff C adupr9 adupr8 adupr7 adupr6 adupr5 adupr4 adupr3 adupr2 adupr1 adupr0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d conversion upper limit value adupr9 = msb adupr0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. can be used when adcadv = "1". 00300558 (hw) a/d upper limit value register (pad_upper) C 0x0 to 0x3ff C adlwr9 adlwr8 adlwr7 adlwr6 adlwr5 adlwr4 adlwr3 adlwr2 adlwr1 adlwr0 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved a/d conversion lower limit value adlwr9 = msb adlwr0 = lsb C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. can be used when adcadv = "1". 0030055a (hw) a/d lower limit value register (pad_lower) C C intmask4 intmask3 intmask2 intmask1 intmask0 d15C5 d4 d3 d2 d1 d0 reserved ch.4 conversion-complete int. mask ch.3 conversion-complete int. mask ch.2 conversion-complete int. mask ch.1 conversion-complete int. mask ch.0 conversion-complete int. mask C 1 1 1 1 1 C r/w r/w r/w r/w r/w 0 when being read. can be used when adcadv = "1". 0030055c (hw) a/d conversion complete interrupt mask register (pad_ch04 _intmask) C 1 interrupt enabled 0 interrupt mask C adcadv C istate1 istate0 icounter3 icounter2 icounter1 icounter0 d15C9 d8 d7C6 d5 d4 d3 d2 d1 d0 reserved standard/advanced mode selection reserved internal status internal counter value C 0 C 0 0 0 0 0 0 C r/w C r r do not write 1. 0 when being read. 0030055e (hw) a/d converter mode select/ internal status register (pad_advmode) C 0 to 15 C 1 advanced 0 standar d 11 10 01 00 istate[1:0] status converting reserved sampling idle
appendix a i/o map s1c33e08 technical manual epson ap-a-27 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300660C0x300666 watchdog timer name address register name bit function setting init. r/w remarks wr iting 0x96 remo v es the wr ite protection of the w atchdog timer enab le and compar ison data registers (0x300662C0x300666). wr iting another v alue set the wr ite protection. wdptc15 wdptc14 wdptc13 wdptc12 wdptc11 wdptc10 wdptc9 wdptc8 wdptc7 wdptc6 wdptc5 wdptc4 wdptc3 wdptc2 wdptc1 wdptc0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 watchdog timer register write- protect x x x x x x x x x x x x x x x x w 0 when being read. 00300660 (hw) watchdog timer write- protect register (pwd_wp) C C C clksel clken runstp C nmien resen d15C7 d6 d5 d4 d3C2 d1 d0 reserved watchdog timer input clock select watchdog timer clock output contro l watchdog timer run/stop control reserved watchdog timer nmi enable watchdog timer reset enable C 0 0 0 C 0 0 C r/w r/w r/w C r/w r/w 0 when being read. 0 when being read. 00300662 (hw) 1 enabled 0 disabled watchdog timer enable register (pwd_en) 1 enabled 0 disabled 1 run 0 stop 1 on 0 off 1 external clock 0 internal cloc k 0x0 to 0x3fffffff (lo w-order 16 bits) cmpdt15 cmpdt14 cmpdt13 cmpdt12 cmpdt11 cmpdt10 cmpdt9 cmpdt8 cmpdt7 cmpdt6 cmpdt5 cmpdt4 cmpdt3 cmpdt2 cmpdt1 cmpdt0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 watchdog timer comparison data cmpdt0 = lsb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00300664 (hw) watchdog timer comparison data setup register 0 (pwd_comp_low) C 0x0 to 0x3fffffff (high-order 14 bits) C cmpdt29 cmpdt28 cmpdt27 cmpdt26 cmpdt25 cmpdt24 cmpdt23 cmpdt22 cmpdt21 cmpdt20 cmpdt19 cmpdt18 cmpdt17 cmpdt16 d15C14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved watchdog timer comparison data cmpdt29 = msb C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. 00300666 (hw) watchdog timer comparison data setup register 1 (pwd_comp_high)
appendix a i/o map ap-a-28 epson s1c33e08 technical manual 0x300668C0x30066c watchdog timer name address register name bit function setting init. r/w remarks 0x0 to 0x3fffffff (lo w-order 16 bits) ctrdt15 ctrdt14 ctrdt13 ctrdt12 ctrdt11 ctrdt10 ctrdt9 ctrdt8 ctrdt7 ctrdt6 ctrdt5 ctrdt4 ctrdt3 ctrdt2 ctrdt1 ctrdt0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 watchdog timer counter data ctrdt0 = lsb x x x x x x x x x x x x x x x x r 00300668 (hw) watchdog timer count register 0 (pwd_cnt_low) C 0x0 to 0x3fffffff (high-order 14 bits) C ctrdt29 ctrdt28 ctrdt27 ctrdt26 ctrdt25 ctrdt24 ctrdt23 ctrdt22 ctrdt21 ctrdt20 ctrdt19 ctrdt18 ctrdt17 ctrdt16 d15C14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved watchdog timer counter data ctrdt29 = msb C x x x x x x x x x x x x x x C r 0 when being read. 0030066a (hw) watchdog timer count register 1 (pwd_cnt_high) C C wdresen d15C1 d0 reserved watchdog timer reset C 0 C w 0 when being read. 0030066c (hw) watchdog timer control register (pwd_cntl) 1 reset 0 invalid
appendix a i/o map s1c33e08 technical manual epson ap-a-29 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300780C0x300786 16-bit timer name address register name bit function setting init. r/w remarks 0 to 65535 cr0a15 cr0a14 cr0a13 cr0a12 cr0a11 cr0a10 cr0a9 cr0a8 cr0a7 cr0a6 cr0a5 cr0a4 cr0a3 cr0a2 cr0a1 cr0a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 0 comparison data a cr0a15 = msb cr0a0 = lsb x x x x x x x x x x x x x x x x r/w 00300780 (hw) 16-bit timer 0 comparison data a setup register (pt16_cr0a) 0 to 65535 cr0b15 cr0b14 cr0b13 cr0b12 cr0b11 cr0b10 cr0b9 cr0b8 cr0b7 cr0b6 cr0b5 cr0b4 cr0b3 cr0b2 cr0b1 cr0b0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 0 comparison data b cr0b15 = msb cr0b0 = lsb x x x x x x x x x x x x x x x x r/w 00300782 (hw) 16-bit timer 0 comparison data b setup register (pt16_cr0b) 0 to 65535 tc015 tc014 tc013 tc012 tc011 tc010 tc09 tc08 tc07 tc06 tc05 tc04 tc03 tc02 tc01 tc00 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 0 counter data tc015 = msb tc00 = lsb x x x x x x x x x x x x x x x x r/w data can be written only in advanced mode. 00300784 (hw) 16-bit timer 0 counter data register (pt16_tc0) C initol0 (tmode0) selfm0 selcrb0 outinv0 cksl0 ptm0 preset0 prun0 d15C9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 0 initial output level (reserved for 16-bit timer 0 test) 16-bit timer 0 fine mode selection 16-bit timer 0 comparison buffer 16-bit timer 0 output inversion 16-bit timer 0 input clock selectio n 16-bit timer 0 clock output control 16-bit timer 0 reset 16-bit timer 0 run/stop control C 0 0 0 0 0 0 0 0 0 C r/w r r/w r/w r/w r/w r/w w r/w 0 when being read. advanced mode do not write 1. 0 when being read. 00300786 (hw) C 1 enabled 0 disabled 1 fine mode 0 normal 1 invert 0 normal 1 external clock 0 internal clock 1 on 0 off 1 reset 0 invalid 1 run 0 stop 16-bit timer 0 control register (pt16_ctl0) 1 test mode 0 normal 1 high 0 low
appendix a i/o map ap-a-30 epson s1c33e08 technical manual 0x300788C0x30078e 16-bit timer name address register name bit function setting init. r/w remarks 0 to 65535 cr1a15 cr1a14 cr1a13 cr1a12 cr1a11 cr1a10 cr1a9 cr1a8 cr1a7 cr1a6 cr1a5 cr1a4 cr1a3 cr1a2 cr1a1 cr1a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 1 comparison data a cr1a15 = msb cr1a0 = lsb x x x x x x x x x x x x x x x x r/w 00300788 (hw) 16-bit timer 1 comparison data a setup register (pt16_cr1a) 0 to 65535 cr1b15 cr1b14 cr1b13 cr1b12 cr1b11 cr1b10 cr1b9 cr1b8 cr1b7 cr1b6 cr1b5 cr1b4 cr1b3 cr1b2 cr1b1 cr1b0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 1 comparison data b cr1b15 = msb cr1b0 = lsb x x x x x x x x x x x x x x x x r/w 0030078a (hw) 16-bit timer 1 comparison data b setup register (pt16_cr1b) 0 to 65535 tc115 tc114 tc113 tc112 tc111 tc110 tc19 tc18 tc17 tc16 tc15 tc14 tc13 tc12 tc11 tc10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 1 counter data tc115 = msb tc10 = lsb x x x x x x x x x x x x x x x x r/w data can be written only in advanced mode. 0030078c (hw) 16-bit timer 1 counter data register (pt16_tc1) C initol1 (tmode1) selfm1 selcrb1 outinv1 cksl1 ptm1 preset1 prun1 d15C9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 1 initial output level (reserved for 16-bit timer 1 test) 16-bit timer 1 fine mode selection 16-bit timer 1 comparison buffer 16-bit timer 1 output inversion 16-bit timer 1 input clock selectio n 16-bit timer 1 clock output control 16-bit timer 1 reset 16-bit timer 1 run/stop control C 0 0 0 0 0 0 0 0 0 C r/w r r/w r/w r/w r/w r/w w r/w 0 when being read. advanced mode do not write 1. 0 when being read. 0030078e (hw) C 1 enabled 0 disabled 1 fine mode 0 normal 1 invert 0 normal 1 external clock 0 internal clock 1 on 0 off 1 reset 0 invalid 1 run 0 stop 16-bit timer 1 control register (pt16_ctl1) 1 test mode 0 normal 1 high 0 low
appendix a i/o map s1c33e08 technical manual epson ap-a-31 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300790C0x300796 16-bit timer name address register name bit function setting init. r/w remarks 0 to 65535 cr2a15 cr2a14 cr2a13 cr2a12 cr2a11 cr2a10 cr2a9 cr2a8 cr2a7 cr2a6 cr2a5 cr2a4 cr2a3 cr2a2 cr2a1 cr2a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 2 comparison data a cr2a15 = msb cr2a0 = lsb x x x x x x x x x x x x x x x x r/w 00300790 (hw) 16-bit timer 2 comparison data a setup register (pt16_cr2a) 0 to 65535 cr2b15 cr2b14 cr2b13 cr2b12 cr2b11 cr2b10 cr2b9 cr2b8 cr2b7 cr2b6 cr2b5 cr2b4 cr2b3 cr2b2 cr2b1 cr2b0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 2 comparison data b cr2b15 = msb cr2b0 = lsb x x x x x x x x x x x x x x x x r/w 00300792 (hw) 16-bit timer 2 comparison data b setup register (pt16_cr2b) 0 to 65535 tc215 tc214 tc213 tc212 tc211 tc210 tc29 tc28 tc27 tc26 tc25 tc24 tc23 tc22 tc21 tc20 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 2 counter data tc215 = msb tc20 = lsb x x x x x x x x x x x x x x x x 00300794 (hw) 16-bit timer 2 counter data register (pt16_tc2) r/w data can be written only in advanced mode. C initol2 (tmode2) selfm2 selcrb2 outinv2 cksl2 ptm2 preset2 prun2 d15C9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 2 initial output level (reserved for 16-bit timer 2 test) 16-bit timer 2 fine mode selection 16-bit timer 2 comparison buffer 16-bit timer 2 output inversion 16-bit timer 2 input clock selectio n 16-bit timer 2 clock output control 16-bit timer 2 reset 16-bit timer 2 run/stop control C 0 0 0 0 0 0 0 0 0 C r/w r r/w r/w r/w r/w r/w w r/w 0 when being read. advanced mode do not write 1. 0 when being read. 00300796 (hw) C 1 enabled 0 disabled 1 fine mode 0 normal 1 invert 0 normal 1 external clock 0 internal clock 1 on 0 off 1 reset 0 invalid 1 run 0 stop 16-bit timer 2 control register (pt16_ctl2) 1 test mode 0 normal 1 high 0 low
appendix a i/o map ap-a-32 epson s1c33e08 technical manual 0x300798C0x30079e 16-bit timer name address register name bit function setting init. r/w remarks 0 to 65535 cr3a15 cr3a14 cr3a13 cr3a12 cr3a11 cr3a10 cr3a9 cr3a8 cr3a7 cr3a6 cr3a5 cr3a4 cr3a3 cr3a2 cr3a1 cr3a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 3 comparison data a cr3a15 = msb cr3a0 = lsb x x x x x x x x x x x x x x x x r/w 00300798 (hw) 16-bit timer 3 comparison data a setup register (pt16_cr3a) 0 to 65535 cr3b15 cr3b14 cr3b13 cr3b12 cr3b11 cr3b10 cr3b9 cr3b8 cr3b7 cr3b6 cr3b5 cr3b4 cr3b3 cr3b2 cr3b1 cr3b0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 3 comparison data b cr3b15 = msb cr3b0 = lsb x x x x x x x x x x x x x x x x r/w 0030079a (hw) 16-bit timer 3 comparison data b setup register (pt16_cr3b) 0 to 65535 tc315 tc314 tc313 tc312 tc311 tc310 tc39 tc38 tc37 tc36 tc35 tc34 tc33 tc32 tc31 tc30 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 3 counter data tc315 = msb tc30 = lsb x x x x x x x x x x x x x x x x 0030079c (hw) 16-bit timer 3 counter data register (pt16_tc3) r/w data can be written only in advanced mode. C initol3 (tmode3) selfm3 selcrb3 outinv3 cksl3 ptm3 preset3 prun3 d15C9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 3 initial output level (reserved for 16-bit timer 3 test) 16-bit timer 3 fine mode selection 16-bit timer 3 comparison buffer 16-bit timer 3 output inversion 16-bit timer 3 input clock selectio n 16-bit timer 3 clock output control 16-bit timer 3 reset 16-bit timer 3 run/stop control C 0 0 0 0 0 0 0 0 0 C r/w r r/w r/w r/w r/w r/w w r/w 0 when being read. advanced mode do not write 1. 0 when being read. 0030079e (hw) C 1 enabled 0 disabled 1 fine mode 0 normal 1 invert 0 normal 1 external clock 0 internal clock 1 on 0 off 1 reset 0 invalid 1 run 0 stop 16-bit timer 3 control register (pt16_ctl3) 1 test mode 0 normal 1 high 0 low
appendix a i/o map s1c33e08 technical manual epson ap-a-33 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x3007a0C0x3007a6 16-bit timer name address register name bit function setting init. r/w remarks 0 to 65535 cr4a15 cr4a14 cr4a13 cr4a12 cr4a11 cr4a10 cr4a9 cr4a8 cr4a7 cr4a6 cr4a5 cr4a4 cr4a3 cr4a2 cr4a1 cr4a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 4 comparison data a cr4a15 = msb cr4a0 = lsb x x x x x x x x x x x x x x x x r/w 003007a0 (hw) 16-bit timer 4 comparison data a setup register (pt16_cr4a) 0 to 65535 cr4b15 cr4b14 cr4b13 cr4b12 cr4b11 cr4b10 cr4b9 cr4b8 cr4b7 cr4b6 cr4b5 cr4b4 cr4b3 cr4b2 cr4b1 cr4b0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 4 comparison data b cr4b15 = msb cr4b0 = lsb x x x x x x x x x x x x x x x x r/w 003007a2 (hw) 16-bit timer 4 comparison data b setup register (pt16_cr4b) 0 to 65535 tc415 tc414 tc413 tc412 tc411 tc410 tc49 tc48 tc47 tc46 tc45 tc44 tc43 tc42 tc41 tc40 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 4 counter data tc415 = msb tc40 = lsb x x x x x x x x x x x x x x x x 003007a4 (hw) 16-bit timer 4 counter data register (pt16_tc4) r/w data can be written only in advanced mode. C initol4 (tmode4) selfm4 selcrb4 outinv4 cksl4 ptm4 preset4 prun4 d15C9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 4 initial output level (reserved for 16-bit timer 4 test) 16-bit timer 4 fine mode selection 16-bit timer 4 comparison buffer 16-bit timer 4 output inversion 16-bit timer 4 input clock selectio n 16-bit timer 4 clock output control 16-bit timer 4 reset 16-bit timer 4 run/stop control C 0 0 0 0 0 0 0 0 0 C r/w r r/w r/w r/w r/w r/w w r/w 0 when being read. advanced mode do not write 1. 0 when being read. 003007a6 (hw) C 1 enabled 0 disabled 1 fine mode 0 normal 1 invert 0 normal 1 external clock 0 internal clock 1 on 0 off 1 reset 0 invalid 1 run 0 stop 16-bit timer 4 control register (pt16_ctl4) 1 test mode 0 normal 1 high 0 low
appendix a i/o map ap-a-34 epson s1c33e08 technical manual 0x3007a8C0x3007ae 16-bit timer name address register name bit function setting init. r/w remarks 0 to 65535 cr5a15 cr5a14 cr5a13 cr5a12 cr5a11 cr5a10 cr5a9 cr5a8 cr5a7 cr5a6 cr5a5 cr5a4 cr5a3 cr5a2 cr5a1 cr5a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 5 comparison data a cr5a15 = msb cr5a0 = lsb x x x x x x x x x x x x x x x x r/w 003007a8 (hw) 16-bit timer 5 comparison data a setup register (pt16_cr5a) 0 to 65535 cr5b15 cr5b14 cr5b13 cr5b12 cr5b11 cr5b10 cr5b9 cr5b8 cr5b7 cr5b6 cr5b5 cr5b4 cr5b3 cr5b2 cr5b1 cr5b0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 5 comparison data b cr5b15 = msb cr5b0 = lsb x x x x x x x x x x x x x x x x r/w 003007aa (hw) 16-bit timer 5 comparison data b setup register (pt16_cr5b) 0 to 65535 tc515 tc514 tc513 tc512 tc511 tc510 tc59 tc58 tc57 tc56 tc55 tc54 tc53 tc52 tc51 tc50 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit timer 5 counter data tc515 = msb tc50 = lsb x x x x x x x x x x x x x x x x 003007ac (hw) 16-bit timer 5 counter data register (pt16_tc5) r/w data can be written only in advanced mode. C initol5 (tmode5) selfm5 selcrb5 outinv5 cksl5 ptm5 preset5 prun5 d15C9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 5 initial output level (reserved for 16-bit timer 5 test) 16-bit timer 5 fine mode selection 16-bit timer 5 comparison buffer 16-bit timer 5 output inversion 16-bit timer 5 input clock selectio n 16-bit timer 5 clock output control 16-bit timer 5 reset 16-bit timer 5 run/stop control C 0 0 0 0 0 0 0 0 0 C r/w r r/w r/w r/w r/w r/w w r/w 0 when being read. advanced mode do not write 1. 0 when being read. 003007ae (hw) C 1 enabled 0 disabled 1 fine mode 0 normal 1 invert 0 normal 1 external clock 0 internal clock 1 on 0 off 1 reset 0 invalid 1 run 0 stop 16-bit timer 5 control register (pt16_ctl5) 1 test mode 0 normal 1 high 0 low
appendix a i/o map s1c33e08 technical manual epson ap-a-35 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x3007d0C0x3007de 16-bit timer name address register name bit function setting init. r/w remarks 0 to 65535 da0a15 da0a14 da0a13 da0a12 da0a11 da0a10 da0a9 da0a8 da0a7 da0a6 da0a5 da0a4 da0a3 da0a2 da0a1 da0a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 da16 ch.0 comparison data a da0a15 = msb da0a0 = lsb x x x x x x x x x x x x x x x x r/w advanced mode 003007d0 (hw) da16 ch.0 register (pda16_cr0a) 0 to 65535 da1a15 da1a14 da1a13 da1a12 da1a11 da1a10 da1a9 da1a8 da1a7 da1a6 da1a5 da1a4 da1a3 da1a2 da1a1 da1a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 da16 ch.1 comparison data a da1a15 = msb da1a0 = lsb x x x x x x x x x x x x x x x x r/w advanced mode 003007d2 (hw) da16 ch.1 register (pda16_cr1a) 0 to 65535 da2a15 da2a14 da2a13 da2a12 da2a11 da2a10 da2a9 da2a8 da2a7 da2a6 da2a5 da2a4 da2a3 da2a2 da2a1 da2a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 da16 ch.2 comparison data a da2a15 = msb da2a0 = lsb x x x x x x x x x x x x x x x x r/w advanced mode 003007d4 (hw) da16 ch.2 register (pda16_cr2a) C pause5 pause4 pause3 pause2 pause1 pause0 d15C6 d5 d4 d3 d2 d1 d0 reserved 16-bit timer 5 count pause 16-bit timer 4 count pause 16-bit timer 3 count pause 16-bit timer 2 count pause 16-bit timer 1 count pause 16-bit timer 0 count pause C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. advanced mode 003007dc (hw) C count pause register (pt16_cnt_pause) 1 pause 0 count C t16adv d15C1 d0 reserved standard mode/advanced mode select C 0 C r/w writing 1 not allowed. 003007de (hw) 16-bit timer std/adv mode select register (pt16_advmode) C 1 advanced mode 0 standar d mode
appendix a i/o map ap-a-36 epson s1c33e08 technical manual 0x3007e0C0x3007ea 16-bit timer name address register name bit function setting init. r/w remarks C C p16ton0 p16ts02 p16ts01 p16ts00 d15C4 d3 d2 d1 d0 reserved 16-bit timer 0 clock control 16-bit timer 0 clock division ratio select C 0 0 0 0 C r/w r/w 0 when being read. 003007e0 (hw) 1 on 0 off p16ts0[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 16-bit timer 0 clock control register (pt16_clkctl_0) C C p16ton1 p16ts12 p16ts11 p16ts10 d15C4 d3 d2 d1 d0 reserved 16-bit timer 1 clock control 16-bit timer 1 clock division ratio select C 0 0 0 0 C r/w r/w 0 when being read. 003007e2 (hw) 1 on 0 off p16ts1[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 16-bit timer 1 clock control register (pt16_clkctl_1) C C p16ton2 p16ts22 p16ts21 p16ts20 d15C4 d3 d2 d1 d0 reserved 16-bit timer 2 clock control 16-bit timer 2 clock division ratio select C 0 0 0 0 C r/w r/w 0 when being read. 003007e4 (hw) 1 on 0 off p16ts2[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 16-bit timer 2 clock control register (pt16_clkctl_2) C C p16ton3 p16ts32 p16ts31 p16ts30 d15C4 d3 d2 d1 d0 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio select C 0 0 0 0 C r/w r/w 0 when being read. 003007e6 (hw) 1 on 0 off p16ts3[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 16-bit timer 3 clock control register (pt16_clkctl_3) C C p16ton4 p16ts42 p16ts41 p16ts40 d15C4 d3 d2 d1 d0 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio select C 0 0 0 0 C r/w r/w 0 when being read. 003007e8 (hw) 1 on 0 off p16ts4[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 16-bit timer 4 clock control register (pt16_clkctl_4) C C p16ton5 p16ts52 p16ts51 p16ts50 d15C4 d3 d2 d1 d0 reserved 16-bit timer 5 clock control 16-bit timer 5 clock division ratio select C 0 0 0 0 C r/w r/w 0 when being read. 003007ea (hw) 1 on 0 off p16ts5[2:0] 111 110 101 100 011 010 001 000 division ratio mclk/4096 mclk/1024 mclk/256 mclk/64 mclk/16 mclk/4 mclk/2 mclk/1 16-bit timer 5 clock control register (pt16_clkctl_5)
appendix a i/o map s1c33e08 technical manual epson ap-a-37 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300900C0x30090b usb function controller name address register name bit setting init. r/w remarks sie_intstat eprintstat dma_intstat fifo_intstat C ep0intstat rcvep0setup d7 d6 d5 d4 d3C2 d1 d0 0 0 0 0 C 0 0 r r r r C r r(w) 0 when being read. 00300900 (b) 1 sie interrupts 0 none 1 epr interrupts 0 none 1 dma interrupts 0 none 1 fifo interrupts 0 none C 1 ep0 interrupts 0 none 1 receive ep0 setup 0 none mainintstat (main interrupt status) vbus_changed nonj detectreset detectsuspend rcvsof detectj C setaddresscmp d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 C 0 r(w) r(w) r(w) r(w) r(w) r(w) C r(w) 0 when being read. 00300901 (b) 1 vbus is changed 0 none 1 detect non j state 0 none 1 detect usb reset 0 none 1 detect usb suspend 0 none 1 receive sof token 0 none 1 detect j state 0 none C 1 autosetaddress complete 0 none sie_intstat (sie interrupt status) C epdintstat epcintstat epbintstat epaintstat d7C4 d3 d2 d1 d0 C 0 0 0 0 C r r r r 0 when being read. 00300902 (b) C 1 epc interrupt 0 none 1 epb interrupt 0 none 1 epa interrupt 0 none eprintstat (epr interrupt status) 1 epd interrupt 0 none C dma_countup dma_cmp d7C2 d1 d0 C 0 0 C r(w) r(w) 0 when being read. 00300903 (b) C 1 dma complete 0 none dma_intstat (dma interrupt status) 1 dma counter overflow 0 none descriptorcmp C fifo_in_cmp fifo_out_cmp d7 d6C2 d1 d0 0 C 0 0 r(w) C r(w) r(w) 0 when being read. 00300904 (b) C 1 out fifo complete 0 none 1 descriptor complete 0 none fifo_intstat (fifo interrupt status) 1 in fifo complete 0 none C in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7C6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 00300907 (b) 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none ep0intstat (ep0 interrupt status) C C out_shortack in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 00300908 (b) 1 out short packet ack 0 none 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none epaintstat (epa interrupt status) C C out_shortack in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 00300909 (b) 1 out short packet ack 0 none 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none epbintstat (epb interrupt status) C C out_shortack in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 0030090a (b) 1 out short packet ack 0 none 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none epcintstat (epc interrupt status) C C out_shortack in_tranack out_tranack in_trannak out_trannak in_tranerr out_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r(w) r(w) r(w) r(w) r(w) r(w) r(w) 0 when being read. 0030090b (b) 1 out short packet ack 0 none 1 in transaction ack 0 none 1 out transaction ack 0 none 1 in transaction nak 0 none 1 out transaction nak 0 none 1 in transaction error 0 none 1 out transaction error 0 none epdintstat (epd interrupt status) C
appendix a i/o map ap-a-38 epson s1c33e08 technical manual 0x300910C0x30091b usb function controller name address register name bit setting init. r/w remarks en sie_intstat en eprintstat endma_intstat enfifo_intstat C en ep0intstat en rcvep0setup d7 d6 d5 d4 d3C2 d1 d0 0 0 0 0 C 0 0 r/w r/w r/w r/w C r/w r/w 0 when being read. 00300910 (b) C 1 enabled 0 disabled 1 enabled 0 disabled mainintenb ( main interrupt enable ) envbus_changed ennonj endetectreset endetectsuspend enrcvsof endetectj C ensetaddresscmp d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 C 0 r/w r/w r/w r/w r/w r/w C r/w 0 when being read. 00300911 (b) C 1 enabled 0 disabled sie_intenb (sie interrupt enable ) 1 enabled 0 disabled C enepdintstat enepcintstat enepbintstat enepaintstat d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300912 (b) C eprintenb (epr interrupt enable ) 1 enabled 0 disabled C endma_countup endma_cmp d7C2 d1 d0 C 0 0 C r/w r/w 0 when being read. 00300913 (b) C dma_intenb (dma interrupt enable) 1 enabled 0 disabled endescriptorcmp C enfifo_in_cmp enfifo_out_cmp d7 d6C2 d1 d0 0 C 0 0 r/w C r/w r/w 0 when being read. 00300914 (b) C 1 enabled 0 disabled fifo_intenb (fifo interrupt enable) 1 enabled 0 disabled C enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7C6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 0 when being read. 00300917 (b) ep0intenb (ep0 interrupt enable) C 1 enabled 0 disabled C enout_shortack enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300918 (b) epaintenb (epa interrupt enable) C 1 enabled 0 disabled C enout_shortack enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00300919 (b) epbintenb (epb interrupt enable) C 1 enabled 0 disabled C enout_shortack enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0030091a (b) epcintenb (epc interrupt enable) C 1 enabled 0 disabled C enout_shortack enin_tranack enout_tranack enin_trannak enout_trannak enin_tranerr enout_tranerr d7 d6 d5 d4 d3 d2 d1 d0 C 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0030091b (b) epdintenb (epd interrupt enable) C 1 enabled 0 disabled
appendix a i/o map s1c33e08 technical manual epson ap-a-39 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300920C0x30092f usb function controller name address register name bit setting init. r/w remarks revisionnum[7] revisionnum[6] revisionnum[5] revisionnum[4] revisionnum[3] revisionnum[2] revisionnum[1] revisionnum[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 0 1 0 r 00300920 (b) revisionnum (revision number) revision number (0x12) disbusdetect enautonego insuspend startdetectj sendwakeup C activeusb d7 d6 d5 d4 d3 d2C1 d0 0 0 0 0 0 C 0 r/w r/w r/w r/w r/w C r/w 0 when being read. 00300921 (b) 1 disable bus detect 0 enable bus detect 1 enable auto negotiation 0 disable auto negotiation 1 monitor nonj C 0 do nothing 1 send remote wakeup signal 0 do nothing 1 start j-state detection 0 do nothing 1 activate usb 0 disactivate usb usb_control (usb control register) vbus fs C linestate[1] linestate[0] d7 d6 d5C2 d1 d0 x 1 C x x r r C r 0 when being read. 00300922 (b) 1 fs mode (fix ed) 0 C 1 vbus=high 0 vbus=low C linestate[1:0] dp/dm 1 1 0 0 1 0 1 0 se1 k j se0 usb_status (usb status register) rpuenb C opmode[1] opmode[0] d7 d6C2 d1 d0 0 C 0 1 r/w C r/w 0 when being read. 00300923 (b) 1 enable pull-up 0 disable pull-up C opmode[1:0] operation mode 1 1 0 0 1 0 1 0 reserved disable bitstuffing and nrzi encoding non-driving normal operation xcvrcontrol (xcvr control register) enusb_test C test_se0_nak test_j test_k test_packet d7 d6C4 d3 d2 d1 d0 0 C 0 0 0 0 r/w C r/w r/w r/w r/w 0 when being read. 00300924 (b) 1 enable usb test 0 do nothing C 1 test_se0_nak 0 do nothing 1 test_j 0 do nothing 1 test_k 0 do nothing 1 test_packet 0 do nothing usb_test (usb test) allforcenak eprforcestall allfifo_clr C ep0fifo_clr d7 d6 d5 d4C1 d0 0 0 0 C 0 w w w C w 0 when being read. 00300925 (b) 1 set all forcenak 0 do nothing 1 set ep's forcestall 0 do nothing 1 clear all fifo C 0 do nothing 1 clear ep0 fifo 0 do nothing epncontrol (endpoint control ) C epdfifo_clr epcfifo_clr epbfifo_clr epafifo_clr d7C4 d3 d2 d1 d0 C 0 0 0 0 C w w w w 0 when being read. 00300926 (b) C 1 clear epc fifo 0 do nothing 1 clear epb fifo 0 do nothing 1 clear epa fifo 0 do nothing eprfifo_clr (epr fifo clear) 1 clear epd fifo 0 do nothing fninvalid C framenumber[10] framenumber[9] framenumber[8] d7 d6C3 d2 d1 d0 1 C 0 0 0 r C r 0 when being read. 0030092e (b) 1 invalid frame number 0 valid frame number C frame number high framenumber_h (frame number high) framenumber[7] framenumber[6] framenumber[5] framenumber[4] framenumber[3] framenumber[2] framenumber[1] framenumber[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 0030092f (b) framenumber_l (frame number low) frame number low
appendix a i/o map ap-a-40 epson s1c33e08 technical manual 0x300930C0x300937 usb function controller name address register name bit setting init. r/w remarks ep0setup_0[7] ep0setup_0[6] ep0setup_0[5] ep0setup_0[4] ep0setup_0[3] ep0setup_0[2] ep0setup_0[1] ep0setup_0[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300930 (b) ep0setup_0 (ep0 set-up 0) endpoint 0 set-up data 0 ep0setup_1[7] ep0setup_1[6] ep0setup_1[5] ep0setup_1[4] ep0setup_1[3] ep0setup_1[2] ep0setup_1[1] ep0setup_1[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300931 (b) ep0setup_1 (ep0 set-up 1) endpoint 0 set-up data 1 ep0setup_2[7] ep0setup_2[6] ep0setup_2[5] ep0setup_2[4] ep0setup_2[3] ep0setup_2[2] ep0setup_2[1] ep0setup_2[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300932 (b) ep0setup_2 (ep0 set-up 2) endpoint 0 set-up data 2 ep0setup_3[7] ep0setup_3[6] ep0setup_3[5] ep0setup_3[4] ep0setup_3[3] ep0setup_3[2] ep0setup_3[1] ep0setup_3[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300933 (b) ep0setup_3 (ep0 set-up 3) endpoint 0 set-up data 3 ep0setup_4[7] ep0setup_4[6] ep0setup_4[5] ep0setup_4[4] ep0setup_4[3] ep0setup_4[2] ep0setup_4[1] ep0setup_4[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300934 (b) ep0setup_4 (ep0 set-up 4) endpoint 0 set-up data 4 ep0setup_5[7] ep0setup_5[6] ep0setup_5[5] ep0setup_5[4] ep0setup_5[3] ep0setup_5[2] ep0setup_5[1] ep0setup_5[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300935 (b) ep0setup_5 (ep0 set-up 5) endpoint 0 set-up data 5 ep0setup_6[7] ep0setup_6[6] ep0setup_6[5] ep0setup_6[4] ep0setup_6[3] ep0setup_6[2] ep0setup_6[1] ep0setup_6[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300936 (b) ep0setup_6 (ep0 set-up 6) endpoint 0 set-up data 6 ep0setup_7[7] ep0setup_7[6] ep0setup_7[5] ep0setup_7[4] ep0setup_7[3] ep0setup_7[2] ep0setup_7[1] ep0setup_7[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300937 (b) ep0setup_7 (ep0 set-up 7) endpoint 0 set-up data 7
appendix a i/o map s1c33e08 technical manual epson ap-a-41 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300938C0x300943 usb function controller name address register name bit setting init. r/w remarks autosetaddress usb_address[6] usb_address[5] usb_address[4] usb_address[3] usb_address[2] usb_address[1] usb_address[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w 00300938 (b) usb_address (usb address) usb address 1 auto set address 0 do nothing inxout C replydescriptor d7 d6C1 d0 0 C 0 r/w C w 0 when being read. 00300939 (b) 1 in 0 out 1 reply descriptor 0 do nothing C ep0control (ep0 control) d7 d6 d5 d4 d3 d2 d1 d0 C 0 C 0 0 0 0 0 C r/w C r r/w r/w r/w r/w 0 when being read. 0 when being read. 0030093a (b) 1 enable short packet 0 do nothing C C toggle sequence bit ep0controlin (ep0 control in) 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing C enshortpkt C togglestat toggleset toggleclr forcenak forcestall d7 d6C5 d4 d3 d2 d1 d0 0 C 0 0 0 0 0 r/w C r w w r/w r/w 0 when being read. 0 when being read. 0030093b (b) 1 auto force nak 0 do nothing C toggle sequence bit ep0controlout (ep0 control out ) autoforcenak C togglestat toggleset toggleclr forcenak forcestall 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing d7 d6 d5 d4 d3 d2C0 C 0 0 0 1 C C r/w C 0 when being read. 0 when being read. 0030093f (b) C C endpoint ep0 max pa ck et siz e ep0maxsiz e (ep0 max pac ket size) C ep0maxsize[6] ep0maxsize[5] ep0maxsize[4] ep0maxsize[3] C d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w r/w r w w r/w r/w 0 when being read. 00300940 (b) epacontrol (epa control) autoforcenak enshortpkt disaf_nak_short togglestat toggleset toggleclr forcenak forcestall toggle sequence bit 1 auto force nak 0 do nothing 1 enable short packet 0 do nothing 1 disable auto force 0 auto force nak short 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w r/w r w w r/w r/w 0 when being read. 00300941 (b) epbcontrol (epb control) autoforcenak enshortpkt disaf_nak_short togglestat toggleset toggleclr forcenak forcestall toggle sequence bit 1 auto force nak 0 do nothing 1 enable short packet 0 do nothing 1 disable auto force 0 auto force nak short 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w r/w r w w r/w r/w 0 when being read. 00300942 (b) epccontrol (epc control) autoforcenak enshortpkt disaf_nak_short togglestat toggleset toggleclr forcenak forcestall toggle sequence bit 1 auto force nak 0 do nothing 1 enable short packet 0 do nothing 1 disable auto force 0 auto force nak short 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w r/w r/w r w w r/w r/w 0 when being read. 00300943 (b) epdcontrol (epd control) autoforcenak enshortpkt disaf_nak_short togglestat toggleset toggleclr forcenak forcestall toggle sequence bit 1 auto force nak 0 do nothing 1 enable short packet 0 do nothing 1 disable auto force 0 auto force nak short 1 set toggle sequence bit 0 do nothing 1 clear toggle sequence bit 0 do nothing 1 force nak 0 do nothing 1 force stall 0 do nothing
appendix a i/o map ap-a-42 epson s1c33e08 technical manual 0x300950C0x30095a usb function controller name address register name bit setting init. r/w remarks C epamaxsize[9] epamaxsize[8] d7C2 d1 d0 C 0 0 C r/w 0 when being read. 00300950 (b) C endpoint epa max packet size epamaxsize_h (epa max packet size high) epamaxsize[7] epamaxsize[6] epamaxsize[5] epamaxsize[4] epamaxsize[3] epamaxsize[2] epamaxsize[1] epamaxsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 00300951 (b) epamaxsize_l (epa max packet size low) endpoint epa max packet size d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 C 0 0 0 0 r/w r/w r/w C r/w 0 when being read. 00300952 (b) C endpoint number (0x1 to 0xf) epaconfig_0 (epa configuration 0 ) inxout togglemode enendpoint C endpointnumber[3] endpointnumber[2] endpointnumber[1] endpointnumber[0] 1 in 0 out 1 enable endpoint 0 disable endpoint 1 always toggle 0 normal toggle d7 d6 d5C0 0 0 C r/w r/w C 0 when being read. 00300953 (b) C epaconfig_1 (epa configuration 1 ) iso iso_crcmode C 1 iso 0 non-iso 1 crc mode 0 normal iso C epbmaxsize[9] epbmaxsize[8] d7C2 d1 d0 C 0 0 C r/w 0 when being read. 00300954 (b) C endpoint epb max packet size epbmaxsize_h (epb max packet size high) epbmaxsize[7] epbmaxsize[6] epbmaxsize[5] epbmaxsize[4] epbmaxsize[3] epbmaxsize[2] epbmaxsize[1] epbmaxsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 00300955 (b) epbmaxsize_l (epb max packet size low) endpoint epb max packet size d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 C 0 0 0 0 r/w r/w r/w C r/w 0 when being read. 00300956 (b) C endpoint number (0x1 to 0xf) epbconfig_0 (epb configuration 0 ) inxout togglemode enendpoint C endpointnumber[3] endpointnumber[2] endpointnumber[1] endpointnumber[0] 1 in 0 out 1 enable endpoint 0 disable endpoint 1 always toggle 0 normal toggle d7 d6 d5C0 0 0 C r/w r/w C 0 when being read. 00300957 (b) C epbconfig_1 (epb configuration 1 ) iso iso_crcmode C 1 iso 0 non-iso 1 crc mode 0 normal iso C epcmaxsize[9] epcmaxsize[8] d7C2 d1 d0 C 0 0 C r/w 0 when being read. 00300958 (b) C endpoint epc max packet size epcmaxsize_h (epc max packet size high) epcmaxsize[7] epcmaxsize[6] epcmaxsize[5] epcmaxsize[4] epcmaxsize[3] epcmaxsize[2] epcmaxsize[1] epcmaxsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 00300959 (b) epcmaxsize_l (epc max packet size low) endpoint epc max packet size d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 C 0 0 0 0 r/w r/w r/w C r/w 0 when being read. 0030095a (b) C endpoint number (0x1 to 0xf) epcconfig_0 (epc configuration 0 ) inxout togglemode enendpoint C endpointnumber[3] endpointnumber[2] endpointnumber[1] endpointnumber[0] 1 in 0 out 1 enable endpoint 0 disable endpoint 1 always toggle 0 normal toggle
appendix a i/o map s1c33e08 technical manual epson ap-a-43 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x30095bC0x300976 usb function controller name address register name bit setting init. r/w remarks d7 d6 d5C0 0 0 C r/w r/w C 0 when being read. 0030095b (b) C epcconfig_1 (epc configuration 1 ) iso iso_crcmode C 1 iso 0 non-iso 1 crc mode 0 normal iso C epdmaxsize[9] epdmaxsize[8] d7C2 d1 d0 C 0 0 C r/w 0 when being read. 0030095c (b) C endpoint epd max packet size epdmaxsize_h (epd max packet size high) epdmaxsize[7] epdmaxsize[6] epdmaxsize[5] epdmaxsize[4] epdmaxsize[3] epdmaxsize[2] epdmaxsize[1] epdmaxsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030095d (b) epdmaxsize_l (epd max packet size low) endpoint epd max packet size d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 C 0 0 0 0 r/w r/w r/w C r/w 0 when being read. 0030095e (b) C endpoint number (0x1 to 0xf) epdconfig_0 (epd configuration 0 ) inxout togglemode enendpoint C endpointnumber[3] endpointnumber[2] endpointnumber[1] endpointnumber[0] 1 in 0 out 1 enable endpoint 0 disable endpoint 1 always toggle 0 normal toggle d7 d6 d5C0 0 0 C r/w r/w C 0 when being read. 0030095f (b) C epdconfig_1 (epd configuration 1 ) iso iso_crcmode C 1 iso 0 non-iso 1 crc mode 0 normal iso C epastartadrs[11] epastartadrs[10] epastartadrs[9] epastartadrs[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300970 (b) C endpoint epa start address epastartadrs_h (epa fifo start address high) epastartadrs[7] epastartadrs[6] epastartadrs[5] epastartadrs[4] epastartadrs[3] epastartadrs[2] C d7 d6 d5 d4 d3 d2 d1C0 0 0 0 0 0 0 C r/w C 0 when being read. 00300971 (b) C endpoint epa start address epastartadrs_l (epa fifo start address low) C epbstartadrs[11] epbstartadrs[10] epbstartadrs[9] epbstartadrs[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300972 (b) C endpoint epb start address epbstartadrs_h (epb fifo start address high) epbstartadrs[7] epbstartadrs[6] epbstartadrs[5] epbstartadrs[4] epbstartadrs[3] epbstartadrs[2] C d7 d6 d5 d4 d3 d2 d1C0 0 0 0 0 0 0 C r/w C 0 when being read. 00300973 (b) C endpoint epb start address epbstartadrs_l (epb fifo start address low) C epcstartadrs[11] epcstartadrs[10] epcstartadrs[9] epcstartadrs[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300974 (b) C endpoint epc start address epcstartadrs_h (epc fifo start address high) epcstartadrs[7] epcstartadrs[6] epcstartadrs[5] epcstartadrs[4] epcstartadrs[3] epcstartadrs[2] C d7 d6 d5 d4 d3 d2 d1C0 0 0 0 0 0 0 C r/w C 0 when being read. 00300975 (b) C endpoint epc start address epcstartadrs_l (epc fifo start address low) C epdstartadrs[11] epdstartadrs[10] epdstartadrs[9] epdstartadrs[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300976 (b) C endpoint epd start address epdstartadrs_h (epd fifo start address high)
appendix a i/o map ap-a-44 epson s1c33e08 technical manual 0x300977C0x300989 usb function controller name address register name bit setting init. r/w remarks epdstartadrs[7] epdstartadrs[6] epdstartadrs[5] epdstartadrs[4] epdstartadrs[3] epdstartadrs[2] C d7 d6 d5 d4 d3 d2 d1C0 0 0 0 0 0 0 C r/w C 0 when being read. 00300977 (b) C endpoint epd start address epdstartadrs_l (epd fifo start address low) C joinepdrd joinepcrd joinepbrd joinepard d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300980 (b) C 1 join epc fifo read 0 do nothing 1 join epb fifo read 0 do nothing 1 join epa fifo read 0 do nothing cpu_joinrd (cpu join fifo read) 1 join epd fifo read 0 do nothing C joinepdwr joinepcwr joinepbwr joinepawr d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300981 (b) C 1 join epc fifo write 0 do nothing 1 join epb fifo write 0 do nothing 1 join epa fifo write 0 do nothing cpu_joinwr (cpu join fifo write) 1 join epd fifo write 0 do nothing C enepnfifo_wr enepnfifo_rd d7C2 d1 d0 C 0 0 C r/w r/w 0 when being read. 00300982 (b) C 1 enable join epn fifo read 0 do nothing enepnfifo _access (enable epn fifo access) 1 enable join epn fifo write 0 do nothing epnfifodata[7] epnfifodata[6] epnfifodata[5] epnfifodata[4] epnfifodata[3] epnfifodata[2] epnfifodata[1] epnfifodata[0] d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x r/w 00300983 (b) epnfifoforcpu (epn fifo for cpu) endpoint ep0 fifo access from cpu d7C4 d3 d2 d1 d0 C 0 0 0 0 C r 0 when being read. 00300984 (b) epnrdremain_h (epn fifo read remain high) C endpoint n fifo read remain high C epnrdremain[11] epnrdremain[10] epnrdremain[9] epnrdremain[8] epnrdremain[7] epnrdremain[6] epnrdremain[5] epnrdremain[4] epnrdremain[3] epnrdremain[2] epnrdremain[1] epnrdremain[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300985 (b) epnrdremain_l (epn fifo read remain low) endpoint n fifo read remain low d7C4 d3 d2 d1 d0 C 0 0 0 0 C r 0 when being read. 00300986 (b) epnwrremain_h (epn fifo write remain high) C endpoint n fifo write remain high C epnwrremain[11] epnwrremain[10] epnwrremain[9] epnwrremain[8] epnwrremain[7] epnwrremain[6] epnwrremain[5] epnwrremain[4] epnwrremain[3] epnwrremain[2] epnwrremain[1] epnwrremain[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300987 (b) epnwrremain_l (epn fifo write remain low) endpoint n fifo write remain low d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300988 (b) descadrs_h (descriptor address high) C descriptor address C descadrs[11] descadrs[10] descadrs[9] descadrs[8] descadrs[7] descadrs[6] descadrs[5] descadrs[4] descadrs[3] descadrs[2] descadrs[1] descadrs[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 00300989 (b) descadrs_l (descriptor address low) descriptor address
appendix a i/o map s1c33e08 technical manual epson ap-a-45 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x30098aC0x300999 usb function controller name address register name bit setting init. r/w remarks d7C2 d1 d0 C 0 0 C r/w 0 when being read. 0030098a (b) descsize_h (descriptor size high) C descriptor size C descsize[9] descsize[8] descsize[7] descsize[6] descsize[5] descsize[4] descsize[3] descsize[2] descsize[1] descsize[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030098b (b) descsize_l (descriptor size low) descriptor size descmode[7] descmode[6] descmode[5] descmode[4] descmode[3] descmode[2] descmode[1] descmode[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030098f (b) descdoor (descriptor door) descriptor door d7 d6 d5C0 0 when being read. 00300990 (b) dma_fifo_control (dma fifo control) 0 0 C r r/w C C 1 fifo is running 0 fifo is not running 1 auto enable short packet 0 do nothing fifo_running autoenshort C C joinepddma joinepcdma joinepbdma joinepadma d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300991 (b) C 1 join epc to dma 0 do nothing 1 join epb to dma 0 do nothing 1 join epa to dma 0 do nothing dma_join (dma join fifo) 1 join epd to dma 0 do nothing d7 d6 d5 d4 d3 d2 d1 d0 0 when being read. 00300992 (b) dma_control (dma control) 0 0 0 C 0 C 0 0 r r r C w C w w C pdack signal logic pdreq signal logic C 1 dma is running 0 dma is not running 1 clear dma counter 0 do nothing 1 finish dma 0 do nothing 1 start dma 0 do nothing dma_running pdreq pdack C counterclr C dma_stop dma_go d7 d6C4 d3 d2 d1 d0 0 when being read. 0 when being read. 00300994 (b) dma_config_0 (dma configuration 0 ) 0 C 0 0 0 C r/w C r/w r/w r/w C C C 1 activate dma port 0 disactivate dma port 1 active-low 0 active-high 1 active-low 0 active-high 1 active-low 0 active-high activeport C pdreq_level pdack_level pdrdwr_level C d7 d6C4 d3 d2C1 d0 0 C 0 C 0 r/w C r/w C r/w 0 when being read. 0 when being read. 00300995 (b) dma_config_1 (dma configuration 1 ) rcvlimitmode C singleword C countmode C C 1 receive limit mode 0 normal 1 single word 0 multi word 1 count-down mode 0 free-run mode d7C4 d3 d2 d1 d0 C 0 0 0 0 C r/w 0 when being read. 00300997 (b) dma_latency (dma latency) C latency C dma_latency[3] dma_latency[2] dma_latency[1] dma_latency[0] C dma_remain[11] dma_remain[10] dma_remain[9] dma_remain[8] d7C4 d3 d2 d1 d0 C 0 0 0 0 C r 0 when being read. 00300998 (b) dma_remain_h (dma fifo remain high) dma fifo remain high C dma_remain[7] dma_remain[6] dma_remain[5] dma_remain[4] dma_remain[3] dma_remain[2] dma_remain[1] dma_remain[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r 00300999 (b) dma_remain_l (dma fifo remain low) dma fifo remain low
appendix a i/o map ap-a-46 epson s1c33e08 technical manual 0x30099cC0x30099f usb function controller name address register name bit setting init. r/w remarks dma_count[31] dma_count[30] dma_count[29] dma_count[28] dma_count[27] dma_count[26] dma_count[25] dma_count[24] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030099c (b) dma_count_hh (dma transfer byte counter high/high) dma transfer byte counter dma_count[23] dma_count[22] dma_count[21] dma_count[20] dma_count[19] dma_count[18] dma_count[17] dma_count[16] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030099d (b) dma_count_hl (dma transfer byte counter high/low) dma transfer byte counter dma_count[15] dma_count[14] dma_count[13] dma_count[12] dma_count[11] dma_count[10] dma_count[9] dma_count[8] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030099e (b) dma_count_lh (dma transfer byte counter low/high) dma transfer byte counter dma_count[7] dma_count[6] dma_count[5] dma_count[4] dma_count[3] dma_count[2] dma_count[1] dma_count[0] d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 r/w 0030099f (b) dma_count_ll (dma transfer byte counter low/low) dma transfer byte counter
appendix a i/o map s1c33e08 technical manual epson ap-a-47 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300b00C0x300b06 serial interface name address register name bit function setting init. r/w remarks 0x0 to 0xff(0x7f) txd07 txd06 txd05 txd04 txd03 txd02 txd01 txd00 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.0 transmit data txd07(06) = msb txd00 = lsb x x x x x x x x r/w 7-bit asynchronous mode does not use txd07. 00300b00 (b) serial i/f ch.0 transmit data register (pefsif0_txd) 0x0 to 0xff(0x7f) rxd07 rxd06 rxd05 rxd04 rxd03 rxd02 rxd01 rxd00 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.0 receive data rxd07(06) = msb rxd00 = lsb x x x x x x x x r 7-bit asynchronous mode does not use rxd07 (fixed at 0). 00300b01 (b) serial i/f ch.0 receive data register (pefsif0_rxd) rxd0num1 rxd0num0 tend0 fer0 per0 oer0 tdbe0 rdbf0 d7 d6 d5 d4 d3 d2 d1 d0 number of ch.0 receive data in fifo ch.0 transmit-completion flag ch.0 framing error flag ch.0 parity error flag ch.0 overrun error flag ch.0 transmit data buffer empty ch.0 receive data buffer full 0 0 0 0 0 0 1 0 r r r/w r/w r/w r r reset by writing 0. 00300b02 (b) 1 error 0 normal 1 transmittin g 0 end 1 error 0 normal 1 error 0 normal 1 empty 0 not empty 1 full 0 not full serial i/f ch.0 status register (pefsif0_status) rxd0num[1:0] number of data 4 3 2 1 or 0 11 10 01 00 txen0 rxen0 epr0 pmd0 stpb0 ssck0 smd01 smd00 d7 d6 d5 d4 d3 d2 d1 d0 ch.0 transmit enable ch.0 receive enable ch.0 parity enable ch.0 parity mode select ch.0 stop bit select ch.0 input clock select ch.0 transfer mode select 11 10 01 00 smd0[1:0] transfer mode 8-bit asynchronous 7-bit asynchronous clock sync. slave clock sync. maste r 0 0 x x x x x x r/w r/w r/w r/w r/w r/w r/w valid only in asynchronous mode. 00300b03 (b) 1 enabled 0 disabled 1 enabled 0 disabled 1 with parity 0 no parity 1 odd 0 even 1 2 bits 0 1 bit 1 #sclk0 0 internal clock serial i/f ch.0 control register (pefsif0_ctl) srdyctl0 fifoint01 fifoint00 divmd0 irtl0 irrl0 irmd01 irmd00 d7 d6 d5 d4 d3 d2 d1 d0 ch.0 #srdy control ch.0 receive buffer full interrupt timing ch.0 async. clock division ratio ch.0 irda i/f output logic inversion ch.0 irda i/f input logic inversion ch.0 interface mode select 0 0 0 x x x x x r/w r/w r/w r/w r/w r/w writing is disabled when sioadv (d0/0x300b4f) = "0". valid only in asynchronous mode. 00300b04 (b) 1 1/8 0 1/16 1 high mask 0 normal 1 inverted 0 direct 1 inverted 0 direct serial i/f ch.0 irda register (pefsif0_irda) irmd0[1:0] i/f mode reserved irda 1.0 reserved general i/f 11 10 01 00 11 10 01 00 fifoint0[1:0] receive level 4 3 2 1 C C brtrun0 d7C1 d0 reserved baud-rate timer run/stop control C 0 C r/w 0 when being read. 00300b05 (b) 1 run 0 stop serial i/f ch.0 baud-rate timer control register (pefsif0_brtrun) 0x0 to 0xff (brtrd0[11:0] = 0x0 to 0xfff) brtrd07 brtrd06 brtrd05 brtrd04 brtrd03 brtrd02 brtrd01 brtrd00 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.0 baud-rate timer reload data [7:0] 0 0 0 0 0 0 0 0 r/w 00300b06 (b) serial i/f ch.0 baud-rate timer reload data register (lsb) (pefsif0_brtrdl)
appendix a i/o map ap-a-48 epson s1c33e08 technical manual 0x300b07C0x300b13 serial interface name address register name bit function setting init. r/w remarks C 0x0 to 0xf (brtrd0[11:0] = 0x0 to 0xfff) C brtrd011 brtrd010 brtrd09 brtrd08 d7C4 d3 d2 d1 d0 reserved serial i/f ch.0 baud-rate timer reload data [11:8] C 0 0 0 0 C r/w 0 when being read. 00300b07 (b) serial i/f ch.0 baud-rate timer reload data register (msb) (pefsif0_brtrdm) 0x0 to 0xff (brtcd0[11:0] = 0x0 to 0xfff) brtcd07 brtcd06 brtcd05 brtcd04 brtcd03 brtcd02 brtcd01 brtcd00 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.0 baud-rate timer count data [7:0] 0 0 0 0 0 0 0 0 r 00300b08 (b) serial i/f ch.0 baud-rate timer count data register (lsb) (pefsif0_brtcdl) C 0x0 to 0xf (brtcd0[11:0] = 0x0 to 0xfff) C brtcd011 brtcd010 brtcd09 brtcd08 d7C4 d3 d2 d1 d0 reserved serial i/f ch.0 baud-rate timer count data [11:8] C 0 0 0 0 C r 0 when being read. 00300b09 (b) serial i/f ch.0 baud-rate timer count data register (msb) (pefsif0_brtcdm) 0x0 to 0xff(0x7f) txd17 txd16 txd15 txd14 txd13 txd12 txd11 txd10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 transmit data txd17(16) = msb txd10 = lsb x x x x x x x x r/w 7-bit asynchronous mode does not use txd17. 00300b10 (b) serial i/f ch.1 transmit data register (pefsif1_txd) 0x0 to 0xff(0x7f) rxd17 rxd16 rxd15 rxd14 rxd13 rxd12 rxd11 rxd10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 receive data rxd17(16) = msb rxd10 = lsb x x x x x x x x r 7-bit asynchronous mode does not use rxd17 (fixed at 0). 00300b11 (b) serial i/f ch.1 receive data register (pefsif1_rxd) rxd1num1 rxd1num0 tend1 fer1 per1 oer1 tdbe1 rdbf1 d7 d6 d5 d4 d3 d2 d1 d0 number of ch.1 receive data in fifo ch.1 transmit-completion flag ch.1 framing error flag ch.1 parity error flag ch.1 overrun error flag ch.1 transmit data buffer empty ch.1 receive data buffer full 0 0 0 0 0 0 1 0 r r r/w r/w r/w r r reset by writing 0. 00300b12 (b) 1 error 0 normal 1 transmittin g 0 end 1 error 0 normal 1 error 0 normal 1 empty 0 not empty 1 full 0 not full serial i/f ch.1 status register (pefsif1_status) rxd1num[1:0] number of data 4 3 2 1 or 0 11 10 01 00 txen1 rxen1 epr1 pmd1 stpb1 ssck1 smd11 smd10 d7 d6 d5 d4 d3 d2 d1 d0 ch.1 transmit enable ch.1 receive enable ch.1 parity enable ch.1 parity mode select ch.1 stop bit select ch.1 input clock select ch.1 transfer mode select smd1[1:0] transfer mode 8-bit asynchronous 7-bit asynchronous clock sync. slave clock sync. maste r 0 0 x x x x x x r/w r/w r/w r/w r/w r/w r/w valid only in asynchronous mode. 00300b13 (b) serial i/f ch.1 control register (pefsif1_ctl) 1 enabled 0 disabled 1 enabled 0 disabled 1 with parity 0 no parity 1 odd 0 even 1 2 bits 0 1 bit 1 #sclk1 0 internal clock 11 10 01 00
appendix a i/o map s1c33e08 technical manual epson ap-a-49 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300b14C0x300b1c serial interface name address register name bit function setting init. r/w remarks srdyctl1 fifoint11 fifoint10 divmd1 irtl1 irrl1 irmd11 irmd10 d7 d6 d5 d4 d3 d2 d1 d0 ch.1 #srdy control ch.1 receive buffer full interrupt timing ch.1 async. clock division ratio ch.1 irda i/f output logic inversion ch.1 irda i/f input logic inversion ch.1 interface mode select irmd1[1:0] i/f mode reserved irda 1.0 reserved general i/f 11 10 01 00 11 10 01 00 fifoint1[1:0] receive level 4 3 2 1 0 0 0 x x x x x r/w r/w r/w r/w r/w r/w writing is disabled when sioadv (d0/0x300b4f) = "0". valid only in asynchronous mode. 00300b14 (b) 1 1/8 0 1/16 1 high mask 0 normal 1 inverted 0 direct 1 inverted 0 direct serial i/f ch.1 irda register (pefsif1_irda) C C brtrun1 d7C1 d0 reserved baud-rate timer run/stop control C 0 C r/w 0 when being read. 00300b15 (b) 1 run 0 stop serial i/f ch.1 baud-rate timer control register (pefsif1_brtrun) 0x0 to 0xff (brtrd1[11:0] = 0x0 to 0xfff) brtrd17 brtrd16 brtrd15 brtrd14 brtrd13 brtrd12 brtrd11 brtrd10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 baud-rate timer reload data [7:0] 0 0 0 0 0 0 0 0 r/w 00300b16 (b) serial i/f ch.1 baud-rate timer reload data register (lsb) (pefsif1_brtrdl) C 0x0 to 0xf (brtrd1[11:0] = 0x0 to 0xfff) C brtrd111 brtrd110 brtrd19 brtrd18 d7C4 d3 d2 d1 d0 reserved serial i/f ch.1 baud-rate timer reload data [11:8] C 0 0 0 0 C r/w 0 when being read. 00300b17 (b) serial i/f ch.1 baud-rate timer reload data register (msb) (pefsif1_brtrdm) 0x0 to 0xff (brtcd1[11:0] = 0x0 to 0xfff) brtcd17 brtcd16 brtcd15 brtcd14 brtcd13 brtcd12 brtcd11 brtcd10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 baud-rate timer count data [7:0] 0 0 0 0 0 0 0 0 r 00300b18 (b) serial i/f ch.01 baud-rate timer count data register (lsb) (pefsif1_brtcdl) C 0x0 to 0xf (brtcd1[11:0] = 0x0 to 0xfff) C brtcd111 brtcd110 brtcd19 brtcd18 d7C4 d3 d2 d1 d0 reserved serial i/f ch.1 baud-rate timer count data [11:8] C 0 0 0 0 C r 0 when being read. 00300b19 (b) serial i/f ch.1 baud-rate timer count data register (msb) (pefsif1_brtcdm) rpnum12 rpnum11 rpnum10 clkoen1 clkol1 msbsel1 7816md11 7816md10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 number of transmit repetition ch.1 clock output enable ch.1 clock output forced low ch.1 msb first selection serial i/f ch.1 iso7816 mode selection 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w 00300b1a (b) serial i/f ch.1 iso7816 mode control register (pefsif1_7816ctl) 7816md1[1:0] mode reserved iso7816, t = 1 iso7816, t = 0 normal i/f 0x0 to 0x7 11 10 01 00 1 normal 0 forced low 1 enabled 0 disabled 1 msb first 0 lsb first C ter1 d7C1 d0 reserved ch.1 iso7816 transmit error flag C 0 C r/w 0 when being read. reset by writing 0. 00300b1b (b) serial i/f ch.1 iso7816 mode status register (pefsif1_7816sta ) C 1 error 0 normal 0x0 to 0xff (fidi1[13:0] = 0x0 to 0x3fff) fidi17 fidi16 fidi15 fidi14 fidi13 fidi12 fidi11 fidi10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 iso7816 mode fi/di ratio [7:0] 0 0 0 0 0 0 0 0 r/w valid only in iso7816 mode. 00300b1c (b) serial i/f ch.1 iso7816 mode fi/di ratio register (lsb) (pefsif1_fidil)
appendix a i/o map ap-a-50 epson s1c33e08 technical manual 0x300b1dC0x300b23 serial interface name address register name bit function setting init. r/w remarks C 0x0 to 0x3f (fidi1[13:0] = 0x0 to 0x3fff) C fidi113 fidi112 fidi111 fidi110 fidi19 fidi18 d7C6 d5 d4 d3 d2 d1 d0 reserved serial i/f ch.1 iso7816 mode fi/di ratio [13:8] C 0 0 0 0 0 0 C r/w 0 when being read. valid only in iso7816 mode. 00300b1d (b) serial i/f ch.1 iso7816 mode fi/di ratio register (msb) (pefsif1_fidim) 0x0 to 0xff ttgr17 ttgr16 ttgr15 ttgr14 ttgr13 ttgr12 ttgr11 ttgr10 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.1 transmit time guard 0 0 0 0 0 0 0 0 r/w 00300b1e (b) serial i/f ch.1 transmit time guard register (pefsif1_ttgr) 0x0 to 0x7f clknen1 clkn16 clkn15 clkn14 clkn13 clkn12 clkn11 clkn10 d7 d6 d5 d4 d3 d2 d1 d0 ch.1 clkn enable serial i/f ch.1 number of output clocks 0 0 0 0 0 0 0 0 r/w r/w 00300b1f (b) serial i/f ch.1 iso7816 mode output clock setup register (pefsif1_clknum) 1 enabled 0 disabled 0x0 to 0xff(0x7f) txd27 txd26 txd25 txd24 txd23 txd22 txd21 txd20 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.2 transmit data txd27(26) = msb txd20 = lsb x x x x x x x x r/w 7-bit asynchronous mode does not use txd27. 00300b20 (b) serial i/f ch.2 transmit data register (pefsif2_txd) 0x0 to 0xff(0x7f) rxd27 rxd26 rxd25 rxd24 rxd23 rxd22 rxd21 rxd20 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.2 receive data rxd27(26) = msb rxd20 = lsb x x x x x x x x r 7-bit asynchronous mode does not use rxd27 (fixed at 0). 00300b21 (b) serial i/f ch.2 receive data register (pefsif2_rxd) rxd2num1 rxd2num0 tend2 fer2 per2 oer2 tdbe2 rdbf2 d7 d6 d5 d4 d3 d2 d1 d0 number of ch.2 receive data in fifo ch.2 transmit-completion flag ch.2 framing error flag ch.2 parity error flag ch.2 overrun error flag ch.2 transmit data buffer empty ch.2 receive data buffer full 0 0 0 0 0 0 1 0 r r r/w r/w r/w r r reset by writing 0. 00300b22 (b) 1 error 0 normal 1 transmittin g 0 end 1 error 0 normal 1 error 0 normal 1 empty 0 not empty 1 full 0 not full serial i/f ch.2 status register (pefsif2_status) rxd2num[1:0] number of data 4 3 2 1 or 0 11 10 01 00 txen2 rxen2 epr2 pmd2 stpb2 ssck2 smd21 smd20 d7 d6 d5 d4 d3 d2 d1 d0 ch.2 transmit enable ch.2 receive enable ch.2 parity enable ch.2 parity mode select ch.2 stop bit select ch.2 input clock select ch.2 transfer mode select 11 10 01 00 smd2[1:0] transfer mode 8-bit asynchronous 7-bit asynchronous clock sync. slave clock sync. maste r 0 0 x x x x x x r/w r/w r/w r/w r/w r/w r/w valid only in asynchronous mode. 00300b23 (b) 1 enabled 0 disabled 1 enabled 0 disabled 1 with parity 0 no parity 1 odd 0 even 1 2 bits 0 1 bit 1 #sclk2 0 internal clock serial i/f ch.2 control register (pefsif2_ctl)
appendix a i/o map s1c33e08 technical manual epson ap-a-51 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300b24C0x300b4f serial interface name address register name bit function setting init. r/w remarks srdyctl2 fifoint21 fifoint20 divmd2 irtl2 irrl2 irmd21 irmd20 d7 d6 d5 d4 d3 d2 d1 d0 ch.2 #srdy control ch.2 receive buffer full interrupt timing ch.2 async. clock division ratio ch.2 irda i/f output logic inversion ch.2 irda i/f input logic inversion ch.2 interface mode select 0 0 0 x x x x x r/w r/w r/w r/w r/w r/w writing is disabled when sioadv (d0/0x300b4f) = "0". valid only in asynchronous mode. 00300b24 (b) 1 1/8 0 1/16 1 high mask 0 normal 1 inverted 0 direct 1 inverted 0 direct serial i/f ch.2 irda register (pefsif2_irda) irmd2[1:0] i/f mode reserved irda 1.0 reserved general i/f 11 10 01 00 11 10 01 00 fifoint2[1:0] receive level 4 3 2 1 C C brtrun2 d7C1 d0 reserved baud-rate timer run/stop control C 0 C r/w 0 when being read. 00300b25 (b) 1 run 0 stop serial i/f ch.2 baud-rate timer control register (pefsif2_brtrun) 0x0 to 0xff (brtrd2[11:0] = 0x0 to 0xfff) brtrd27 brtrd26 brtrd25 brtrd24 brtrd23 brtrd22 brtrd21 brtrd20 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.2 baud-rate timer reload data [7:0] 0 0 0 0 0 0 0 0 r/w 00300b26 (b) serial i/f ch.2 baud-rate timer reload data register (lsb) (pefsif2_brtrdl) C 0x0 to 0xf (brtrd2[11:0] = 0x0 to 0xfff) C brtrd211 brtrd210 brtrd29 brtrd28 d7C4 d3 d2 d1 d0 reserved serial i/f ch.2 baud-rate timer reload data [11:8] C 0 0 0 0 C r/w 0 when being read. 00300b27 (b) serial i/f ch.2 baud-rate timer reload data register (msb) (pefsif2_brtrdm) 0x0 to 0xff (brtcd2[11:0] = 0x0 to 0xfff) brtcd27 brtcd26 brtcd25 brtcd24 brtcd23 brtcd22 brtcd21 brtcd20 d7 d6 d5 d4 d3 d2 d1 d0 serial i/f ch.2 baud-rate timer count data [7:0] 0 0 0 0 0 0 0 0 r 00300b28 (b) serial i/f ch.2 baud-rate timer count data register (lsb) (pefsif2_brtcdl) C 0x0 to 0xf (brtcd2[11:0] = 0x0 to 0xfff) C brtcd211 brtcd210 brtcd29 brtcd28 d7C4 d3 d2 d1 d0 reserved serial i/f ch.2 baud-rate timer count data [11:8] C 0 0 0 0 C r 0 when being read. 00300b29 (b) serial i/f ch.2 baud-rate timer count data register (msb) (pefsif2_brtcdm) C sioadv d7C1 d0 reserved standard mode/advanced mode select C 0 C r/w writing 1 not allowed. 00300b4f (b) serial i/f std/adv mode select register (pefsif_adv) C 1 advanced mode 0 standar d mode
appendix a i/o map ap-a-52 epson s1c33e08 technical manual 0x300c00C0x300c21 extended ports name address register name bit function setting init. r/w remarks C ioca4 ioca3 ioca2 ioca1 ioca0 d7C5 d4 d3 d2 d1 d0 reserved pa4 i/o control pa3 i/o control pa2 i/o control pa1 i/o control pa0 i/o control C 0 0 0 0 0 C r/w r/w r/w r/w r/w 0 when being read. 00300c00 (b) 1 output 0 input pa i/o control register (ppa_ioc) C C pa4d pa3d pa2d pa1d pa0d d7C5 d4 d3 d2 d1 d0 reserved pa4 i/o port data pa3 i/o port data pa2 i/o port data pa1 i/o port data pa0 i/o port data C ext. ext. ext. ext. ext. C r/w r/w r/w r/w r/w 0 when being read. ext.: the initial value depends on the external pin status. 00300c01 (b) 1 high 0 low pa i/o port data register (ppa_data) C C iocb3 iocb2 iocb1 iocb0 d7C4 d3 d2 d1 d0 reserved pb3 i/o control pb2 i/o control pb1 i/o control pb0 i/o control C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300c02 (b) 1 output 0 input pb i/o control register (ppb_ioc) C C pb3d pb2d pb1d pb0d d7C4 d3 d2 d1 d0 reserved pb3 i/o port data pb2 i/o port data pb1 i/o port data pb0 i/o port data C ext. ext. ext. ext. C r/w r/w r/w r/w 0 when being read. ext.: the initial value depends on the external pin status. 00300c03 (b) 1 high 0 low pb i/o port data register (ppb_data) C iocc7 iocc6 iocc5 iocc4 iocc3 iocc2 iocc1 iocc0 d7 d6 d5 d4 d3 d2 d1 d0 pc7 i/o control pc6 i/o control pc5 i/o control pc4 i/o control pc3 i/o control pc2 i/o control pc1 i/o control pc0 i/o control 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c04 (b) 1 output 0 input pc i/o control register (ppc_ioc) pc7d pc6d pc5d pc4d pc3d pc2d pc1d pc0d d7 d6 d5 d4 d3 d2 d1 d0 pc7 i/o port data pc6 i/o port data pc5 i/o port data pc4 i/o port data pc3 i/o port data pc2 i/o port data pc1 i/o port data pc0 i/o port data ext. ext. ext. ext. ext. ext. ext. ext. r/w r/w r/w r/w r/w r/w r/w r/w ext.: the initial value depends on the external pin status. 00300c05 (b) 1 high 0 low pc i/o port data register (ppc_data) cfpa31 cfpa30 cfpa21 cfpa20 cfpa11 cfpa10 cfpa01 cfpa00 d7 d6 d5 d4 d3 d2 d1 d0 pa3 port extended function pa2 port extended function pa1 port extended function pa0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c20 (b) pa0Cpa3 port function select register (ppa_03_cfp) cfpa3[1:0] function card0 tft_ctl2 fpdat10 pa3 cfpa2[1:0] function reserved tft_ctl1 fpdat9 pa2 cfpa1[1:0] function reserved tft_ctl0 fpdat8 pa1 1 ? 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfpa0[1:0] function reserved tft_ctl0 pa0 C cfpa41 cfpa40 d7C2 d1 d0 reserved pa4 port extended function C 0 0 C r/w 0 when being read. 00300c21 (b) pa4 port function select register (ppa_4_cfp) cfpa4[1:0] function card1 tft_ctl3 fpdat11 pa4 11 10 01 00 function C
appendix a i/o map s1c33e08 technical manual epson ap-a-53 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300c22C0x300c25 extended ports name address register name bit function setting init. r/w remarks cfpb31 cfpb30 cfpb21 cfpb20 cfpb11 cfpb10 cfpb01 cfpb00 d7 d6 d5 d4 d3 d2 d1 d0 pb3 port extended function pb2 port extended function pb1 port extended function pb0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c22 (b) pb0Cpb3 port function select register (ppb_03_cfp) cfpb3[1:0] function card5 i2s_mclk fpdat11 pb3 cfpb2[1:0] function card4 i2s_sck fpdat10 pb2 cfpb1[1:0] function card3 i2s_ws fpdat9 pb1 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 cfpb0[1:0] function card2 i2s_sdo fpdat8 pb0 cfpc31 cfpc30 cfpc21 cfpc20 cfpc11 cfpc10 cfpc01 cfpc00 d7 d6 d5 d4 d3 d2 d1 d0 pc3 port extended function pc2 port extended function pc1 port extended function pc0 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c24 (b) pc0Cpc3 port function select register (ppc_03_cfp) cfpc3[1:0] function reserved pc3 d11 cfpc2[1:0] function reserved pc2 d10 cfpc1[1:0] function reserved pc1 d9 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfpc0[1:0] function reserved pc0 d8 cfpc71 cfpc70 cfpc61 cfpc60 cfpc51 cfpc50 cfpc41 cfpc40 d7 d6 d5 d4 d3 d2 d1 d0 pc7 port extended function pc6 port extended function pc5 port extended function pc4 port extended function 0 0 0 0 0 0 0 0 r/w r/w r/w r/w 00300c25 (b) pc4Cpc7 port function select register (ppc_47_cfp) cfpc7[1:0] function reserved pc7 d15 cfpc6[1:0] function reserved pc6 d14 cfpc5[1:0] function reserved pc5 d13 1 ? 01 00 1 ? 01 00 1 ? 01 00 1 ? 01 00 cfpc4[1:0] function reserved pc4 d12
appendix a i/o map ap-a-54 epson s1c33e08 technical manual 0x300c40C0x300c48 misc register name address register name bit function setting init. r/w remarks C d7C0 reserved C C 0 when being read. 00300c40 (b) bus signal pull-up control register (pmisc_buspup) C C ldrvdb ldrvce ldrvad ldrvrw d7C4 d3 d2 d1 d0 reserved d15Cd0 low drive #ce11C#ce4 low drive a24Ca0 low drive #rd,#wrl,#wrh,#bsl low driv e C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. 00300c41 (b) bus signal low drive control register (pmisc_buslow) 1 low drive 0 normal output C pup07 pup06 pup05 pup04 pup03 pup02 pup01 pup00 d7 d6 d5 d4 d3 d2 d1 d0 p07 pull-up p06 pull-up p05 pull-up p04 pull-up p03 pull-up p02 pull-up p01 pull-up p00 pull-up 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c42 (b) 1 pulled up 0 no pull-up p0 pull-up control register (pmisc_pup0) pup17 pup16 pup15 pup14 pup13 pup12 pup11 pup10 d7 d6 d5 d4 d3 d2 d1 d0 p17 pull-up p16 pull-up p15 pull-up p14 pull-up p13 pull-up p12 pull-up p11 pull-up p10 pull-up 1 1 1 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c43 (b) 1 pulled up 0 no pull-up p1 pull-up control register (pmisc_pup1) pup27 pup26 pup25 pup24 pup23 pup22 pup21 pup20 d7 d6 d5 d4 d3 d2 d1 d0 p27 pull-up p26 pull-up p25 pull-up p24 pull-up p23 pull-up p22 pull-up p21 pull-up p20 pull-up 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 00300c44 (b) 1 pulled up 0 no pull-up p2 pull-up control register (pmisc_pup2) C pup36 pup35 pup34 pup33 pup32 pup31 pup30 d7 d6 d5 d4 d3 d2 d1 d0 reserved p36 pull-up p35 pull-up p34 pull-up p33 pull-up p32 pull-up p31 pull-up p30 pull-up C 1 1 1 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 1 when being read. C 00300c45 (b) 1 pulled up 0 no pull-up p3 pull-up control register (pmisc_pup3) pup47 pup46 pup45 pup44 pup43 pup42 pup41 pup40 d7 d6 d5 d4 d3 d2 d1 d0 p47 pull-up p46 pull-up p45 pull-up p44 pull-up p43 pull-up p42 pull-up p41 pull-up p40 pull-up 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 00300c46 (b) 1 pulled up 0 no pull-up p4 pull-up control register (pmisc_pup4) pup57 pup56 pup55 pup54 pup53 pup52 pup51 pup50 d7 d6 d5 d4 d3 d2 d1 d0 p57 pull-up p56 pull-up p55 pull-up p54 pull-up p53 pull-up p52 pull-up p51 pull-up p50 pull-up 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w 00300c47 (b) 1 pulled up 0 no pull-up p5 pull-up control register (pmisc_pup5) pup67 pup66 pup65 pup64 pup63 pup62 pup61 pup60 d7 d6 d5 d4 d3 d2 d1 d0 p67 pull-up p66 pull-up p65 pull-up p64 pull-up p63 pull-up p62 pull-up p61 pull-up p60 pull-up 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c48 (b) 1 pulled up 0 no pull-up p6 pull-up control register (pmisc_pup6)
appendix a i/o map s1c33e08 technical manual epson ap-a-55 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x300c49C0x300c4d misc register name address register name bit function setting init. r/w remarks C pup74 pup73 pup72 pup71 pup70 d7C5 d4 d3 d2 d1 d0 reserved p74 pull-up p73 pull-up p72 pull-up p71 pull-up p70 pull-up C 0 0 0 0 0 C r/w r/w r/w r/w r/w 1 when being read. C 00300c49 (b) 1 pulled up 0 no pull-up p7 pull-up control register (pmisc_pup7) C pup85 pup84 pup83 pup82 pup81 pup80 d7C6 d5 d4 d3 d2 d1 d0 reserved p85 pull-up p84 pull-up p83 pull-up p82 pull-up p81 pull-up p80 pull-up C 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w 1 when being read. C 00300c4a (b) 1 pulled up 0 no pull-up p8 pull-up control register (pmisc_pup8) pup97 pup96 pup95 pup94 pup93 pup92 pup91 pup90 d7 d6 d5 d4 d3 d2 d1 d0 p97 pull-up p96 pull-up p95 pull-up p94 pull-up p93 pull-up p92 pull-up p91 pull-up p90 pull-up 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 00300c4b (b) 1 pulled up 0 no pull-up p9 pull-up control register (pmisc_pup9) C pupa4 pupa3 pupa2 pupa1 pupa0 d7C5 d4 d3 d2 d1 d0 reserved pa4 pull-up pa3 pull-up pa2 pull-up pa1 pull-up pa0 pull-up C 1 1 1 1 1 C r/w r/w r/w r/w r/w 1 when being read. C 00300c4c (b) 1 pulled up 0 no pull-up pa pull-up control register (pmisc_pupa) C pupb3 pupb2 pupb1 pupb0 d7C4 d3 d2 d1 d0 reserved pb3 pull-up pb2 pull-up pb1 pull-up pb0 pull-up C 1 1 1 1 C r/w r/w r/w r/w 1 when being read. C 00300c4d (b) 1 pulled up 0 no pull-up pb pull-up control register (pmisc_pupb)
appendix a i/o map ap-a-56 epson s1c33e08 technical manual 0x301100C0x301105 intelligent dma name address register name bit function setting init. r/w remarks dbasel15 dbasel14 dbasel13 dbasel12 dbasel11 dbasel10 dbasel9 dbasel8 dbasel7 dbasel6 dbasel5 dbasel4 dbasel3 dbasel2 dbasel1 dbasel0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idma base address low-order 16 bits (initial value: 0x200003a0) 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 r/w fix at 0. 00301100 (hw) idma base address register 0 (pidmabase) dbaseh15 dbaseh14 dbaseh13 dbaseh12 dbaseh11 dbaseh10 dbaseh9 dbaseh8 dbaseh7 dbaseh6 dbaseh5 dbaseh4 dbaseh3 dbaseh2 dbaseh1 dbaseh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idma base address high-order 16 bits (initial value: 0x200003a0) 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301102 (hw) idma base address register 1 0 to 127 dstart dchn6 dchn5 dchn4 dchn3 dchn2 dchn1 dchn0 d7 d6 d5 d4 d3 d2 d1 d0 idma start idma channel number 1 idma start 0 stop 0 0 r/w r/w 00301104 (b) idma start register (pidma_start) C C idmaen d7C1 d0 reserved idma enable (for software trigger) 1 enabled 0 disabled C 0 C r/w 0 when being read. 00301105 (b) idma enable register (pidma_en)
appendix a i/o map s1c33e08 technical manual epson ap-a-57 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301120C0x301126 high-speed dma name address register name bit function setting init. r/w remarks tc0_l7 tc0_l6 tc0_l5 tc0_l4 tc0_l3 tc0_l2 tc0_l1 tc0_l0 blklen07 blklen06 blklen05 blklen04 blklen03 blklen02 blklen01 blklen00 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch.0 transfer c ounter[7:0 ] (block transfer mode) ch.0 transfer counter[15:8] (single/successive transfer mode) ch.0 block lengt h (block transfer mode) ch.0 transfer counter[7:0] (single/successive transfer mode) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w 00301120 (hw) hsdma ch.0 transfer counter register (phs0_cnt) C C dualm0 d0dir C tc0_h7 tc0_h6 tc0_h5 tc0_h4 tc0_h3 tc0_h2 tc0_h1 tc0_h0 d15 d14 d13C8 d7 d6 d5 d4 d3 d2 d1 d0 ch.0 address mode selection d) invalid s) ch.0 transfer direction control reserved ch.0 transfer counter[15:8] (block transfer mode) ch.0 transfer counter[23:16] (single/successive transfer mode) 1 dual addr 0 single addr 1 memory wr 0 memory rd 0 C 0 C 0 0 0 0 0 0 0 0 r/w C r/w C r/w 0 when being read. 00301122 (hw) hsdma ch.0 control register note: d) dual address mode s) single address mode s0adrl15 s0adrl14 s0adrl13 s0adrl12 s0adrl11 s0adrl10 s0adrl9 s0adrl8 s0adrl7 s0adrl6 s0adrl5 s0adrl4 s0adrl3 s0adrl2 s0adrl1 s0adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.0 source address[15:0] s) ch.0 memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301124 (hw) hsdma ch.0 low-order source address setup register (phs0_sadr) note: d) dual address mode s) single address mode C datsize0 s0in1 s0in0 s0adrh11 s0adrh10 s0adrh9 s0adrh8 s0adrh7 s0adrh6 s0adrh5 s0adrh4 s0adrh3 s0adrh2 s0adrh1 s0adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved ch.0 transfer data size d) ch.0 source address control s) ch.0 memory address control d) ch.0 source address[27:16] s) ch.0 memory address[27:16] C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. 00301126 (hw) 1 half word 0 byte hsdma ch.0 high-order source address setup register note: d) dual address mode s) single address mode 11 10 01 00 s0in[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed C
appendix a i/o map ap-a-58 epson s1c33e08 technical manual 0x301128C0x301130 high-speed dma name address register name bit function setting init. r/w remarks d0adrl15 d0adrl14 d0adrl13 d0adrl12 d0adrl11 d0adrl10 d0adrl9 d0adrl8 d0adrl7 d0adrl6 d0adrl5 d0adrl4 d0adrl3 d0adrl2 d0adrl1 d0adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.0 destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301128 (hw) hsdma ch.0 low-order destination address setup register (phs0_dadr) note: d) dual address mode s) single address mode d0mod1 d0mod0 d0in1 d0in0 d0adrh11 d0adrh10 d0adrh9 d0adrh8 d0adrh7 d0adrh6 d0adrh5 d0adrh4 d0adrh3 d0adrh2 d0adrh1 d0adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch.0 transfer mode d) ch.0 destination address control s) invalid d) ch.0 destination address[27:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w 0030112a (hw) hsdma ch.0 high-order destination address setup register note: d) dual address mode s) single address mode d0mod[1:0] mode invalid block successive single d0in[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed 11 10 01 00 11 10 01 00 C C hs0_en d15C1 d0 reserved ch.0 enable 1 enable 0 disable C 0 C r/w 0 when being read. 0030112c (hw) hsdma ch.0 enable register (phs0_en) C C hs0_tf d15C1 d0 reserved ch.0 trigger flag clear (writing) ch.0 trigger flag status (reading) 1 clear 0 no operatio n 1 set 0 cleared C 0 C r/w 0 when being read. 0030112e (hw) hsdma ch.0 trigger flag register (phs0_tf) tc1_l7 tc1_l6 tc1_l5 tc1_l4 tc1_l3 tc1_l2 tc1_l1 tc1_l0 blklen17 blklen16 blklen15 blklen14 blklen13 blklen12 blklen11 blklen10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch.1 transfer c ounter[7:0 ] (block transfer mode) ch.1 transfer counter[15:8] (single/successive transfer mode) ch.1 block lengt h (block transfer mode) ch.1 transfer counter[7:0] (single/successive transfer mode) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w 00301130 (hw) hsdma ch.1 transfer counter register (phs1_cnt)
appendix a i/o map s1c33e08 technical manual epson ap-a-59 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301132C0x301138 high-speed dma name address register name bit function setting init. r/w remarks C C dualm1 d1dir C tc1_h7 tc1_h6 tc1_h5 tc1_h4 tc1_h3 tc1_h2 tc1_h1 tc1_h0 d15 d14 d13C8 d7 d6 d5 d4 d3 d2 d1 d0 ch.1 address mode selection d) invalid s) ch.1 transfer direction control reserved ch.1 transfer counter[15:8] (block transfer mode) ch.1 transfer counter[23:16] (single/successive transfer mode) 1 dual addr 0 single addr 1 memory wr 0 memory rd 0 C 0 C 0 0 0 0 0 0 0 0 r/w C r/w C r/w 0 when being read. 00301132 (hw) hsdma ch.1 control register note: d) dual address mode s) single address mode s1adrl15 s1adrl14 s1adrl13 s1adrl12 s1adrl11 s1adrl10 s1adrl9 s1adrl8 s1adrl7 s1adrl6 s1adrl5 s1adrl4 s1adrl3 s1adrl2 s1adrl1 s1adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.1 source address[15:0] s) ch.1 memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301134 (hw) hsdma ch.1 low-order source address setup register (phs1_sadr) note: d) dual address mode s) single address mode C datsize1 s1in1 s1in0 s1adrh11 s1adrh10 s1adrh9 s1adrh8 s1adrh7 s1adrh6 s1adrh5 s1adrh4 s1adrh3 s1adrh2 s1adrh1 s1adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved ch.1 transfer data size d) ch.1 source address control s) ch.1 memory address control d) ch.1 source address[27:16] s) ch.1 memory address[27:16] C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. 00301136 (hw) 1 half word 0 byte hsdma ch.1 high-order source address setup register note: d) dual address mode s) single address mode C 11 10 01 00 s1in[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed d1adrl15 d1adrl14 d1adrl13 d1adrl12 d1adrl11 d1adrl10 d1adrl9 d1adrl8 d1adrl7 d1adrl6 d1adrl5 d1adrl4 d1adrl3 d1adrl2 d1adrl1 d1adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.1 destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301138 (hw) hsdma ch.1 low-order destination address setup register (phs1_dadr) note: d) dual address mode s) single address mode
appendix a i/o map ap-a-60 epson s1c33e08 technical manual 0x30113aC0x301142 high-speed dma name address register name bit function setting init. r/w remarks d1mod1 d1mod0 d1in1 d1in0 d1adrh11 d1adrh10 d1adrh9 d1adrh8 d1adrh7 d1adrh6 d1adrh5 d1adrh4 d1adrh3 d1adrh2 d1adrh1 d1adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch.1 transfer mode d) ch.1 destination address control s) invalid d) ch.1 destination address[27:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w 0030113a (hw) hsdma ch.1 high-order destination address setup register note: d) dual address mode s) single address mode d1mod[1:0] mode invalid block successive single d1in[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed 11 10 01 00 11 10 01 00 C C hs1_en d15C1 d0 reserved ch.1 enable 1 enable 0 disable C 0 C r/w 0 when being read. 0030113c (hw) hsdma ch.1 enable register (phs1_en) C C hs1_tf d15C1 d0 reserved ch.1 trigger flag clear (writing) ch.1 trigger flag status (reading) 1 clear 0 no operatio n 1 set 0 cleared C 0 C r/w 0 when being read. 0030113e (hw) hsdma ch.1 trigger flag register (phs1_tf) tc2_l7 tc2_l6 tc2_l5 tc2_l4 tc2_l3 tc2_l2 tc2_l1 tc2_l0 blklen27 blklen26 blklen25 blklen24 blklen23 blklen22 blklen21 blklen20 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch.2 transfer c ounter[7:0 ] (block transfer mode) ch.2 transfer counter[15:8] (single/successive transfer mode) ch.2 block lengt h (block transfer mode) ch.2 transfer counter[7:0] (single/successive transfer mode) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w 00301140 (hw) hsdma ch.2 transfer counter register (phs2_cnt) C C dualm2 d2dir C tc2_h7 tc2_h6 tc2_h5 tc2_h4 tc2_h3 tc2_h2 tc2_h1 tc2_h0 d15 d14 d13C8 d7 d6 d5 d4 d3 d2 d1 d0 ch.2 address mode selection d) invalid s) ch.2 transfer direction control reserved ch.2 transfer counter[15:8] (block transfer mode) ch.2 transfer counter[23:16] (single/successive transfer mode) 1 dual addr 0 single addr 1 memory wr 0 memory rd 0 C 0 C 0 0 0 0 0 0 0 0 r/w C r/w C r/w 0 when being read. 00301142 (hw) hsdma ch.2 control register note: d) dual address mode s) single address mode
appendix a i/o map s1c33e08 technical manual epson ap-a-61 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301144C0x301148 high-speed dma name address register name bit function setting init. r/w remarks s2adrl15 s2adrl14 s2adrl13 s2adrl12 s2adrl11 s2adrl10 s2adrl9 s2adrl8 s2adrl7 s2adrl6 s2adrl5 s2adrl4 s2adrl3 s2adrl2 s2adrl1 s2adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.2 source address[15:0] s) ch.2 memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301144 (hw) hsdma ch.2 low-order source address setup register (phs2_sadr) note: d) dual address mode s) single address mode C datsize2 s2in1 s2in0 s2adrh11 s2adrh10 s2adrh9 s2adrh8 s2adrh7 s2adrh6 s2adrh5 s2adrh4 s2adrh3 s2adrh2 s2adrh1 s2adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved ch.2 transfer data size d) ch.2 source address control s) ch.2 memory address control d) ch.2 source address[27:16] s) ch.2 memory address[27:16] C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. 00301146 (hw) 1 half word 0 byte hsdma ch.2 high-order source address setup register note: d) dual address mode s) single address mode C 11 10 01 00 s2in[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed d2adrl15 d2adrl14 d2adrl13 d2adrl12 d2adrl11 d2adrl10 d2adrl9 d2adrl8 d2adrl7 d2adrl6 d2adrl5 d2adrl4 d2adrl3 d2adrl2 d2adrl1 d2adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.2 destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301148 (hw) hsdma ch.2 low-order destination address setup register (phs2_dadr) note: d) dual address mode s) single address mode
appendix a i/o map ap-a-62 epson s1c33e08 technical manual 0x30114aC0x301152 high-speed dma name address register name bit function setting init. r/w remarks d2mod1 d2mod0 d2in1 d2in0 d2adrh11 d2adrh10 d2adrh9 d2adrh8 d2adrh7 d2adrh6 d2adrh5 d2adrh4 d2adrh3 d2adrh2 d2adrh1 d2adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch.2 transfer mode d) ch.2 destination address control s) invalid d) ch.2 destination address[27:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w 0030114a (hw) hsdma ch.2 high-order destination address setup register note: d) dual address mode s) single address mode d2mod[1:0] mode invalid block successive single d2in[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed 11 10 01 00 11 10 01 00 C C hs2_en d15C1 d0 reserved ch.2 enable 1 enable 0 disable C 0 C r/w 0 when being read. 0030114c (hw) hsdma ch.2 enable register (phs2_en) C C hs2_tf d15C1 d0 reserved ch.2 trigger flag clear (writing) ch.2 trigger flag status (reading) 1 clear 0 no operatio n 1 set 0 cleared C 0 C r/w 0 when being read. 0030114e (hw) hsdma ch.2 trigger flag register (phs2_tf) tc3_l7 tc3_l6 tc3_l5 tc3_l4 tc3_l3 tc3_l2 tc3_l1 tc3_l0 blklen37 blklen36 blklen35 blklen34 blklen33 blklen32 blklen31 blklen30 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch.3 transfer c ounter[7:0 ] (block transfer mode) ch.3 transfer counter[15:8] (single/successive transfer mode) ch.3 block lengt h (block transfer mode) ch.3 transfer counter[7:0] (single/successive transfer mode) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w 00301150 (hw) hsdma ch.3 transfer counter register (phs3_cnt) C C dualm3 d3dir C tc3_h7 tc3_h6 tc3_h5 tc3_h4 tc3_h3 tc3_h2 tc3_h1 tc3_h0 d15 d14 d13C8 d7 d6 d5 d4 d3 d2 d1 d0 ch.3 address mode selection d) invalid s) ch.3 transfer direction control reserved ch.3 transfer counter[15:8] (block transfer mode) ch.3 transfer counter[23:16] (single/successive transfer mode) 1 dual addr 0 single addr 1 memory wr 0 memory rd 0 C 0 C 0 0 0 0 0 0 0 0 r/w C r/w C r/w 0 when being read. 00301152 (hw) hsdma ch.3 control register note: d) dual address mode s) single address mode
appendix a i/o map s1c33e08 technical manual epson ap-a-63 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301154C0x301158 high-speed dma name address register name bit function setting init. r/w remarks s3adrl15 s3adrl14 s3adrl13 s3adrl12 s3adrl11 s3adrl10 s3adrl9 s3adrl8 s3adrl7 s3adrl6 s3adrl5 s3adrl4 s3adrl3 s3adrl2 s3adrl1 s3adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.3 source address[15:0] s) ch.3 memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301154 (hw) hsdma ch.3 low-order source address setup register (phs3_sadr) note: d) dual address mode s) single address mode C datsize3 s3in1 s3in0 s3adrh11 s3adrh10 s3adrh9 s3adrh8 s3adrh7 s3adrh6 s3adrh5 s3adrh4 s3adrh3 s3adrh2 s3adrh1 s3adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved ch.3 transfer data size d) ch.3 source address control s) ch.3 memory address control d) ch.3 source address[27:16] s) ch.3 memory address[27:16] C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w r/w r/w 0 when being read. 00301156 (hw) 1 half word 0 byte hsdma ch.3 high-order source address setup register note: d) dual address mode s) single address mode C 11 10 01 00 s3in[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed d3adrl15 d3adrl14 d3adrl13 d3adrl12 d3adrl11 d3adrl10 d3adrl9 d3adrl8 d3adrl7 d3adrl6 d3adrl5 d3adrl4 d3adrl3 d3adrl2 d3adrl1 d3adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.3 destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301158 (hw) hsdma ch.3 low-order destination address setup register (phs3_dadr) note: d) dual address mode s) single address mode
appendix a i/o map ap-a-64 epson s1c33e08 technical manual 0x30115aC0x301164 high-speed dma name address register name bit function setting init. r/w remarks d3mod1 d3mod0 d3in1 d3in0 d3adrh11 d3adrh10 d3adrh9 d3adrh8 d3adrh7 d3adrh6 d3adrh5 d3adrh4 d3adrh3 d3adrh2 d3adrh1 d3adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch.3 transfer mode d) ch.3 destination address control s) invalid d) ch.3 destination address[27:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w 0030115a (hw) hsdma ch.3 high-order destination address setup register note: d) dual address mode s) single address mode d3mod[1:0] mode invalid block successive single d3in[1:0] inc/dec inc.(no init) inc.(init) dec.(no init) fixed 11 10 01 00 11 10 01 00 C C hs3_en d15C1 d0 reserved ch.3 enable 1 enable 0 disable C 0 C r/w 0 when being read. 0030115c (hw) hsdma ch.3 enable register (phs3_en) C C hs3_tf d15C1 d0 reserved ch.3 trigger flag clear (writing) ch.3 trigger flag status (reading) 1 clear 0 no operatio n 1 set 0 cleared C 0 C r/w 0 when being read. 0030115e (hw) hsdma ch.3 trigger flag register (phs3_tf) C C C d0id s0id C wordsize0 d15C6 d5 d4 d3C1 d0 reserved d) ch.0 destination address control s) invalid d) ch.0 source address control s) ch.0 memory address control reserved ch.0 transfer data size 1 decrement (with init.) 0 d0in[1:0] setting 1 decrement (with init.) 0 s0in[1:0] setting C 0 0 C 0 C r/w r/w C r/w 0 when being read. 0 when being read. 00301162 (hw) hsdma ch.0 control register (phs0_advmode) for adv mode note: d) dual mode s) single mode 1 word 0 datsize0 setting s0adrl15 s0adrl14 s0adrl13 s0adrl12 s0adrl11 s0adrl10 s0adrl9 s0adrl8 s0adrl7 s0adrl6 s0adrl5 s0adrl4 s0adrl3 s0adrl2 s0adrl1 s0adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.0 source address[15:0] s) ch.0 memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301164 (hw) hsdma ch.0 low-order source address setup register (phs0_adv_sadr) for adv mode note: d) dual address mode s) single address mode
appendix a i/o map s1c33e08 technical manual epson ap-a-65 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301166C0x301172 high-speed dma name address register name bit function setting init. r/w remarks s0adrh15 s0adrh14 s0adrh13 s0adrh12 s0adrh11 s0adrh10 s0adrh9 s0adrh8 s0adrh7 s0adrh6 s0adrh5 s0adrh4 s0adrh3 s0adrh2 s0adrh1 s0adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.0 source address[31:16] s) ch.0 memory address[31:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301166 (hw) hsdma ch.0 high-order source address setup register for adv mode note: d) dual address mode s) single address mode d0adrl15 d0adrl14 d0adrl13 d0adrl12 d0adrl11 d0adrl10 d0adrl9 d0adrl8 d0adrl7 d0adrl6 d0adrl5 d0adrl4 d0adrl3 d0adrl2 d0adrl1 d0adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.0 destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301168 (hw) hsdma ch.0 low-order destination address setup register (phs0_adv_dadr) for adv mode note: d) dual address mode s) single address mode d0adrh15 d0adrh14 d0adrh13 d0adrh12 d0adrh11 d0adrh10 d0adrh9 d0adrh8 d0adrh7 d0adrh6 d0adrh5 d0adrh4 d0adrh3 d0adrh2 d0adrh1 d0adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.0 destination address[31:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 0030116a (hw) hsdma ch.0 high-order destination address setup register for adv mode note: d) dual address mode s) single address mode C C C d1id s1id C wordsize1 d15C6 d5 d4 d3C1 d0 reserved d) ch.1 destination address control s) invalid d) ch.1 source address control s) ch.1 memory address control reserved ch.1 transfer data size 1 decrement (with init.) 0 d1in[1:0] setting 1 decrement (with init.) 0 s1in[1:0] setting C 0 0 C 0 C r/w r/w C r/w 0 when being read. 0 when being read. 00301172 (hw) hsdma ch.1 control register (phs1_advmode) for adv mode note: d) dual mode s) single mode 1 word 0 datsize1 setting
appendix a i/o map ap-a-66 epson s1c33e08 technical manual 0x301174C0x30117a high-speed dma name address register name bit function setting init. r/w remarks s1adrl15 s1adrl14 s1adrl13 s1adrl12 s1adrl11 s1adrl10 s1adrl9 s1adrl8 s1adrl7 s1adrl6 s1adrl5 s1adrl4 s1adrl3 s1adrl2 s1adrl1 s1adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.1 source address[15:0] s) ch.1 memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301174 (hw) hsdma ch.1 low-order source address setup register (phs1_adv_sadr) for adv mode note: d) dual address mode s) single address mode s1adrh15 s1adrh14 s1adrh13 s1adrh12 s1adrh11 s1adrh10 s1adrh9 s1adrh8 s1adrh7 s1adrh6 s1adrh5 s1adrh4 s1adrh3 s1adrh2 s1adrh1 s1adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.1 source address[31:16] s) ch.1 memory address[31:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301176 (hw) hsdma ch.1 high-order source address setup register for adv mode note: d) dual address mode s) single address mode d1adrl15 d1adrl14 d1adrl13 d1adrl12 d1adrl11 d1adrl10 d1adrl9 d1adrl8 d1adrl7 d1adrl6 d1adrl5 d1adrl4 d1adrl3 d1adrl2 d1adrl1 d1adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.1 destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301178 (hw) hsdma ch.1 low-order destination address setup register (phs1_adv_dadr) for adv mode note: d) dual address mode s) single address mode d1adrh15 d1adrh14 d1adrh13 d1adrh12 d1adrh11 d1adrh10 d1adrh9 d1adrh8 d1adrh7 d1adrh6 d1adrh5 d1adrh4 d1adrh3 d1adrh2 d1adrh1 d1adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.1 destination address[31:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 0030117a (hw) hsdma ch.1 high-order destination address setup register for adv mode note: d) dual address mode s) single address mode
appendix a i/o map s1c33e08 technical manual epson ap-a-67 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301182C0x301188 high-speed dma name address register name bit function setting init. r/w remarks C C C d2id s2id C wordsize2 d15C6 d5 d4 d3C1 d0 reserved d) ch.2 destination address control s) invalid d) ch.2 source address control s) ch.2 memory address control reserved ch.2 transfer data size 1 decrement (with init.) 0 d2in[1:0] setting 1 decrement (with init.) 0 s2in[1:0] setting C 0 0 C 0 C r/w r/w C r/w 0 when being read. 0 when being read. 00301182 (hw) hsdma ch.2 control register (phs2_advmode) for adv mode note: d) dual mode s) single mode 1 word 0 datsize2 setting s2adrl15 s2adrl14 s2adrl13 s2adrl12 s2adrl11 s2adrl10 s2adrl9 s2adrl8 s2adrl7 s2adrl6 s2adrl5 s2adrl4 s2adrl3 s2adrl2 s2adrl1 s2adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.2 source address[15:0] s) ch.2 memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301184 (hw) hsdma ch.2 low-order source address setup register (phs2_adv_sadr) for adv mode note: d) dual address mode s) single address mode s2adrh15 s2adrh14 s2adrh13 s2adrh12 s2adrh11 s2adrh10 s2adrh9 s2adrh8 s2adrh7 s2adrh6 s2adrh5 s2adrh4 s2adrh3 s2adrh2 s2adrh1 s2adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.2 source address[31:16] s) ch.2 memory address[31:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301186 (hw) hsdma ch.2 high-order source address setup register for adv mode note: d) dual address mode s) single address mode d2adrl15 d2adrl14 d2adrl13 d2adrl12 d2adrl11 d2adrl10 d2adrl9 d2adrl8 d2adrl7 d2adrl6 d2adrl5 d2adrl4 d2adrl3 d2adrl2 d2adrl1 d2adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.2 destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301188 (hw) hsdma ch.2 low-order destination address setup register (phs2_adv_dadr) for adv mode note: d) dual address mode s) single address mode
appendix a i/o map ap-a-68 epson s1c33e08 technical manual 0x30118aC0x301196 high-speed dma name address register name bit function setting init. r/w remarks d2adrh15 d2adrh14 d2adrh13 d2adrh12 d2adrh11 d2adrh10 d2adrh9 d2adrh8 d2adrh7 d2adrh6 d2adrh5 d2adrh4 d2adrh3 d2adrh2 d2adrh1 d2adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.2 destination address[31:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 0030118a (hw) hsdma ch.2 high-order destination address setup register for adv mode note: d) dual address mode s) single address mode C C C d3id s3id C wordsize3 d15C6 d5 d4 d3C1 d0 reserved d) ch.3 destination address control s) invalid d) ch.3 source address control s) ch.3 memory address control reserved ch.3 transfer data size 1 decrement (with init.) 0 d3in[1:0] setting 1 decrement (with init.) 0 s3in[1:0] setting C 0 0 C 0 C r/w r/w C r/w 0 when being read. 0 when being read. 00301192 (hw) hsdma ch.3 control register (phs3_advmode) for adv mode note: d) dual mode s) single mode 1 word 0 datsize3 setting s3adrl15 s3adrl14 s3adrl13 s3adrl12 s3adrl11 s3adrl10 s3adrl9 s3adrl8 s3adrl7 s3adrl6 s3adrl5 s3adrl4 s3adrl3 s3adrl2 s3adrl1 s3adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.3 source address[15:0] s) ch.3 memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301194 (hw) hsdma ch.3 low-order source address setup register (phs3_adv_sadr) for adv mode note: d) dual address mode s) single address mode s3adrh15 s3adrh14 s3adrh13 s3adrh12 s3adrh11 s3adrh10 s3adrh9 s3adrh8 s3adrh7 s3adrh6 s3adrh5 s3adrh4 s3adrh3 s3adrh2 s3adrh1 s3adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.3 source address[31:16] s) ch.3 memory address[31:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301196 (hw) hsdma ch.3 high-order source address setup register for adv mode note: d) dual address mode s) single address mode
appendix a i/o map s1c33e08 technical manual epson ap-a-69 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301198C0x30119e high-speed dma name address register name bit function setting init. r/w remarks d3adrl15 d3adrl14 d3adrl13 d3adrl12 d3adrl11 d3adrl10 d3adrl9 d3adrl8 d3adrl7 d3adrl6 d3adrl5 d3adrl4 d3adrl3 d3adrl2 d3adrl1 d3adrl0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.3 destination address[15:0] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 00301198 (hw) hsdma ch.3 low-order destination address setup register (phs3_adv_dadr) for adv mode note: d) dual address mode s) single address mode d3adrh15 d3adrh14 d3adrh13 d3adrh12 d3adrh11 d3adrh10 d3adrh9 d3adrh8 d3adrh7 d3adrh6 d3adrh5 d3adrh4 d3adrh3 d3adrh2 d3adrh1 d3adrh0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d) ch.3 destination address[31:16] s) invalid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 0030119a (hw) hsdma ch.3 high-order destination address setup register for adv mode note: d) dual address mode s) single address mode C hsdmaadv d15C1 d0 reserved standard mode/advanced mode select C 0 C r/w 0 when being read. 0030119c (hw) hsdma std/adv mode select register (phs_cntlmode) C 1 advanced mode 0 standar d mode C dmaacctime3 dmaacctime2 dmaacctime1 dmaacctime0 d15C4 d3 d2 d1 d0 reserved idma and hsdma sequential access time setup C 0 0 0 0 C r/w 0 when being read. 0030119e (hw) dma sequential access time register (phs_acctime) C 0 1 2 3 4 5 6 7 unlimited 64 cycles 128 cycles 192 cycles 256 cycles 320 cycles 384 cycles 448 cycles 8 9 a b c d e f 512 cycles 576 cycles 640 cycles 704 cycles 768 cycles 832 cycles 896 cycles 960 cycles
appendix a i/o map ap-a-70 epson s1c33e08 technical manual 0x301500C0x301510 sram controller name address register name bit function setting init. r/w remarks C ce9bclk ce9hold2 ce9hold1 ce9hold0 C ce11stup ce4stup bclk d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce9 area bclk divide control #ce9 area output disable time reserved #ce11 setup time #ce4 setup time bclk divide control C 1 0 0 0 C 0 0 1 C r/w r/w C r/w r/w r/w 0 when being read. 0 when being read. 00301500 (w) bclk and setup time control register (psramc_bclk _setup) 1 no setup tim e 0 +1 bclk C 0 to 7 C 1 no setup tim e 0 +1 bclk 1 sramc_clk 1/2 0 sramc_clk 1 1 sramc_clk 1/2 0 sramc_clk 1 C ce11wait2 ce11wait1 ce11wait0 ce10wait3 ce10wait2 ce10wait1 ce10wait0 ce9wait3 ce9wait2 ce9wait1 ce9wait0 ce8wait3 ce8wait2 ce8wait1 ce8wait0 ce7wait3 ce7wait2 ce7wait1 ce7wait0 ce6wait3 ce6wait2 ce6wait1 ce6wait0 ce5wait3 ce5wait2 ce5wait1 ce5wait0 ce4wait3 ce4wait2 ce4wait1 ce4wait0 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved number of #ce11 static wait cycles reserved number of #ce10 static wait cycles reserved number of #ce9 static wait cycles reserved number of #ce8 static wait cycles reserved number of #ce7 static wait cycles reserved number of #ce6 static wait cycles reserved number of #ce5 static wait cycles reserved number of #ce4 static wait cycles C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C 1 1 1 C r/w C r/w C r/w C r/w C r/w C r/w C r/w C r/w 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301504 (w) wait control register (psramc_swait) C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C 0 to 7 C ce11size1 ce11size0 C ce9size1 ce9size0 ce8size1 ce8size0 ce7size1 ce7size0 ce6size1 ce6size0 ce5size1 ce5size0 ce4size1 ce4size0 d31C16 d15 d14 d13C12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce11 device size reserved #ce9 device size #ce8 device size #ce7 device size #ce6 device size #ce5 device size #ce4 device size C 0 1 C 0 1 0 1 0 1 0 1 0 1 0 1 C r/w C r/w r/w r/w r/w r/w r/w 0 when being read. 0 when being read. 00301508 (w) device size setup register (psramc_slv _size) C (see below) C ce xsize[1:0] size reserved 8 bits 16 bits reserved 11 10 01 00 C ce11type ce10type ce9type ce8type ce7type ce6type ce5type ce4type d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved #ce11 device type #ce10 device type #ce9 device type #ce8 device type #ce7 device type #ce6 device type #ce5 device type #ce4 device type C 0 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0030150c (w) device type setup register (psramc_a0_bsl) C 1 bsl 0 a0 C a6loc d31C1 d0 reserved area 6 location setup C 0 C r/w 0 when being read. 00301510 (w) area location setup register (psramc_als) C 1 external 0 internal
appendix a i/o map s1c33e08 technical manual epson ap-a-71 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301600C0x301610 sdram controller name address register name bit function setting init. r/w remarks C C sdon sden inimrs inipre iniref d31C5 d4 d3 d2 d1 d0 reserved sdram controller enable sdram initialize flag mrs command enable for init. pall command enable for init. ref command enable for init. C 0 0 0 0 0 C r/w r r/w r/w r/w 0 when being read. 00301600 (w) 1 initialized 0 not initialized 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled sdram initial register (psdramc_ini) C t24ns[1:0] = 0 to 3 1 to 4 cycles C t60ns[2:0] = 0 to 7 1 to 8 cycles t80ns[3:0] = 0 to 15 1 to 16 cycles C C t24ns1 t24ns0 C t60ns2 t60ns1 t60ns0 t80ns3 t80ns2 t80ns1 t80ns0 C addrc2 addrc1 addrc0 d31C14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved number of sdram t rp and t rcd cycles reserved number of sdram t ras cycles number of sdram t rc , t rfc and t xsr cycles reserved sdram address configuration C 0 0 C 0 0 0 1 1 1 0 C 0 0 0 C r/w C r/w r/w C r/w 0 when being read. 0 when being read. 0 when being read. 00301604 (w) 111 110 101 100 011 010 001 000 addrc[2:0] configuration 32m x 16 bits x 1 16m x 8 bits x 2 8m x 8 bits x 2 2m x 8 bits x 2 16m x 16 bits x 1 8m x 16 bits x 1 4m x 16 bits x 1 1m x 16 bits x 1 sdram configuration register (psdramc_ctl) C 0x0 to 0x7f C seldo sckon selen selco6 selco5 selco4 selco3 selco2 selco1 selco0 C aurco11 aurco10 aurco9 aurco8 aurco7 aurco6 aurco5 aurco4 aurco3 aurco2 aurco1 aurco0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved sdram self-refresh status sdram clock during self-refresh sdram self-refresh enable sdram self-refresh counter reserved sdram auto-refresh counter C 0 0 0 1 1 1 1 1 1 1 C 0 0 0 0 1 0 0 0 1 1 0 0 C r r/w r/w r/w C r/w 0 when being read. 0 when being read. 00301608 (w) 1 refresh mode 0 done 1 enabled 0 disabled 1 enabled 0 disabled sdram refresh register (psdramc_ref) C 0x0 to 0xfff C arbon C dbf incr cas1 cas0 appon iqb d31 d30C6 d5 d4 d3 d2 d1 d0 arbiter enable reserved double frequency mode enable incr transfer enable cas latency setup sdapp control instruction queue buffer enable 0 C 0 0 1 0 0 0 r/w C r/w r/w r/w r/w r/w 0 when being read. 00301610 (w) 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled sdram application configuration register (psdramc_app) 1 on 0 off 1 enabled 0 disabled cas[1:0] cas latency 3 2 1 reserved 11 10 01 00
appendix a i/o map ap-a-72 epson s1c33e08 technical manual 0x301700C0x30171c spi name address register name bit function setting init. r/w remarks 0x0 to 0xffffffff spirxd31 | spirxd0 d31 | d0 spi receive data spirxd31 = msb spirxd0 = lsb 0x0 r 00301700 (w) spi receive data register (pspi_rxd) 0x0 to 0xffffffff spitxd31 | spitxd0 d31 | d0 spi transmit data spitxd31 = msb spitxd0 = lsb 0x0 r/w 00301704 (w) spi transmit data register (pspi_txd) C bpt4 bpt3 bpt2 bpt1 bpt0 cpha cpol mwen mcbr2 mcbr1 mcbr0 txde rxde mode ena d31C15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved number of data bits per transfer spi_clk phase selection spi_clk polarity selection reserved master clock bit rate (in master mode only) transmit dma enable receive dma enable spi mode selection spi enable C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C r/w r/w r/w C r/w r/w r/w r/w r/w 0 when being read. 00301708 (w) spi control register 1 (pspi_ctl1) C number of data bits per transfer = bpt + 1 fix at 0. master clock divided value = 4 2 mcbr 1 phase 1 0 0 phase 0 1 enabled disabled 0 1 master slave 0 1 enabled disabled 0 1 enabled disabled 1 active low 0 active high C ssa ss ssp ssc C rdyp rdys rdye d31C12 d11 d10 d9 d8 d7C3 d2 d1 d0 reserved reserved slave select control reserved reserved reserved reserved reserved reserved C 0 0 0 0 C 0 0 0 C C r/w C C C C C C 0 when being read. master mode slave mode 0 when being read. 0030170c (w) spi control register 2 (pspi_ctl2) C fix at 0. fix at 0. fix at 0. fix at 0. fix at 0. fix at 0. fix at 0. C 1 0 spi select spi deselect number of wait cycles = spiw[31:0] + 1 (1 to 65536) spiw31 | spiw0 d31 | d0 wait cycle control spiw31 = msb spiw0 = lsb 0x0 r/w 00301710 (w) spi wait register (pspi_wait) C C C C bsyf mfef tdef rdof rdff C d31C7 d6 d5 d4 d3 d2 d1C0 reserved transfer busy flag reserved transmit data empty flag receive data overflow flag receive data full flag reserved C 0 C 1 0 0 C C r C r r r C 0 when being read. master mode 0 when being read. 0 when being read. 00301714 (w) 1 busy 0 idle 1 occurred 0 not occurred 1 empty 0 not empty 1 full 0 not full spi status register (pspi_stat) C fix at 0. C mfie teie roie rfie mirq irqe d31C6 d5 d4 d3 d2 d1 d0 reserved reserved transmit data empty int. enable receive overflow interrupt enable receive data full interrupt enable manual irq set/clear interrupt request enable C 0 0 0 0 0 0 C C r/w r/w r/w r/w r/w 0 when being read. 00301718 (w) 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 set 0 clear 1 enabled 0 disabled spi interrupt control register (pspi_int) C 0x0 to 0x1f C C C rxmask4 rxmask3 rxmask2 rxmask1 rxmask0 C rxme C d31C15 d14 d13 d12 d11 d10 d9C2 d1 d0 reserved bit mask for reading received data reserved receive data mask enable reserved C 0 0 0 0 0 C 0 C C r/w C r/w C 0 when being read. 0 when being read. do not write 1. 0030171c (w) 1 enabled 0 disabled spi receive data mask register (pspi_rxmk)
appendix a i/o map s1c33e08 technical manual epson ap-a-73 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301800C0x30181c dcsio name address register name bit function setting init. r/w remarks C divrt7 divrt6 divrt5 divrt4 divrt3 divrt2 divrt1 divrt0 C advrate basesel lsbfirst dcsioen d31C16 d15 d14 d13 d12 d11 d10 d9 d8 d7C4 d3 d2 d1 d0 reserved dcsio system clock baud rate setup (divrt must be 2 or more.) reserved non-base line transfer rate setup base line selection lsb first selection dcsio enable C 0 0 0 0 0 0 0 0 C 0 0 0 0 C r/w C r/w r/w r/w r/w 0 when being read. 0 when being read. 00301800 (w) dcsio control register (pdcsio_ctl) C baud rate = f mclk /(divrt 2) C 0 1 a b 0 1 base 1/8 = base line 0 1 lsb first msb first 0 1 enabled disabled C txda7 txda6 txda5 txda4 txda3 txda2 txda1 txda0 C txdb7 txdb6 txdb5 txdb4 txdb3 txdb2 txdb1 txdb0 d31C24 d23 d22 d21 d20 d19 d18 d17 d16 d15C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved line a transmit data reserved line b transmit data C 1 1 1 1 1 1 1 1 C 1 1 1 1 1 1 1 1 C r/w C r/w 0 when being read. 0 when being read. 00301804 (w) dcsio data load register (pdcsio_load) C 0x0 to 0xff C 0x0 to 0xff C rxda7 rxda6 rxda5 rxda4 rxda3 rxda2 rxda1 rxda0 C rxdb7 rxdb6 rxdb5 rxdb4 rxdb3 rxdb2 rxdb1 rxdb0 d31C24 d23 d22 d21 d20 d19 d18 d17 d16 d15C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved line a receive data reserved line b receive data C 1 1 1 1 1 1 1 1 C 1 1 1 1 1 1 1 1 C r C r 0 when being read. 0 when being read. 00301808 (w) dcsio receive data register (pdcsio_rcv) C 0x0 to 0xff C 0x0 to 0xff C C rxbfen txbeen inten d31C3 d2 d1 d0 reserved receive data full interrupt enable transmit data empty int. enable dcsio interrupt request enable C 0 0 0 C r/w r/w r/w 0 when being read. 00301814 (w) 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled dcsio interrupt control register (pdcsio_int) C C rxbf txbe busy d31C3 d2 d1 d0 reserved receive data full flag transmit data empty flag dcsio busy flag C 0 0 0 C r r r 0 when being read. 00301818 (w) 1 empty 0 not empty 1 full 0 not full 1 busy 0 idle dcsio status register (pdcsio_stat) C dira1 dira0 dirb1 dirb0 d31C4 d3 d2 d1 d0 reserved line a direction select line b direction select C 0 0 0 0 C r/w r/w 0 when being read. 0030181c (w) 1 ? 01 00 dira[1:0] i/o input only input/push-pull output input/open-drain output 1 ? 01 00 dirb[1:0] i/o input only input/push-pull output input/open-drain output dcsio port direction control register (pdcsio_dir) C
appendix a i/o map ap-a-74 epson s1c33e08 technical manual 0x301900C0x301924 real time clock name address register name bit function setting init. r/w remarks C rtcirq d31C 1 d0 reserved interrupt status C x C r/w 0 when being read. reset by writing 1. 00301900 (w) rtc interrupt status register (prtcintstat) C 1 occurred 0 not occurred C rtct1 rtct0 rtcimd rtcien d31C4 d3 d2 d1 d0 reserved rtc interrupt cycle setup rtc interrupt mode select rtc interrupt enable C x x x x C r/w r/w r/w 0 when being read. 00301904 (w) rtc interrupt mode register (prtcintmode) C 1 level sense 0 edge trigger 1 enabled 0 disabled 11 10 01 00 rtct[1:0] cycle 1 hour 1 minute 1 second 1/64 second C rtc24h C rtcadj rtcstp rtcrst d31C5 d4 d3 d2 d1 d0 reserved 24h/12h mode select reserved 30-second adjustment counter run/stop control software reset C x C x x x C r/w C r/w r/w r/w 0 when being read. 00301908 (w) rtc control register (prtc_cntl0) C C 1 24h 0 12h 1 stop 0 run 1 adjust 0 C 1 reset 0 C C rtcbsy rtchld d31C 2 d1 d0 reserved counter busy flag counter hold control C x x C r r/w 0 when being read. 0030190c (w) rtc access control register (prtc_cntl1) C 1 busy 0 r/w possibl e 1 hold 0 running C rtcsh2 rtcsh1 rtcsh0 rtcsl3 rtcsl2 rtcsl1 rtcsl0 d31C7 d6 d5 d4 d3 d2 d1 d0 reserved rtc 10-second counter rtc 1-second counter C x x x x x x x C r/w r/w 0 when being read. 00301910 (w) rtc second register (prtcsec) 0 to 5 C 0 to 9 C rtcmih2 rtcmih1 rtcmih0 rtcmil3 rtcmil2 rtcmil1 rtcmil0 d31C7 d6 d5 d4 d3 d2 d1 d0 reserved rtc 10-minute counter rtc 1-minute counter C x x x x x x x C r/w r/w 0 when being read. 00301914 (w) rtc minute register (prtcmin) 0 to 5 C 0 to 9 C rtcap rtchh1 rtchh0 rtchl3 rtchl2 rtchl1 rtchl0 d31C7 d6 d5 d4 d3 d2 d1 d0 reserved am/pm indicator rtc 10-hour counter rtc 1-hour counter C x x x x x x x C r/w r/w r/w 0 when being read. 00301918 (w) rtc hour register (prtchour) 0 to 2 or 0 to 1 C 1 pm 0 am 0 to 9 C rtcdh1 rtcdh0 rtcdl3 rtcdl2 rtcdl1 rtcdl0 d31C6 d5 d4 d3 d2 d1 d0 reserved rtc 10-day counter rtc 1-day counter C x x x x x x C r/w r/w 0 when being read. 0030191c (w) rtc day register (prtcday) 0 to 3 C 0 to 9 C rtcmoh rtcmol3 rtcmol2 rtcmol1 rtcmol0 d31C5 d4 d3 d2 d1 d0 reserved rtc 10-month counter rtc 1-month counter C x x x x x C r/w r/w 0 when being read. 00301920 (w) rtc month register (prtcmonth) 0 or 1 C 0 to 9 C rtcyh3 rtcyh2 rtcyh1 rtcyh0 rtcyl3 rtcyl2 rtcyl1 rtcyl0 d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved rtc 10-year counter rtc 1-year counter C x x x x x x x x C r/w r/w 0 when being read. 00301924 (w) rtc year register (prtcyear) 0 to 9 C 0 to 9
appendix a i/o map s1c33e08 technical manual epson ap-a-75 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301928 real time clock name address register name bit function setting init. r/w remarks C rtcwk2 rtcwk1 rtcwk0 d31C 3 d2 d1 d0 reserved rtc days of week counter C x x x C r/w 0 when being read. 00301928 (w) rtc days of week register (prtcdayweek) C 111 110 101 100 011 010 001 000 rtcwk[2:0] days of week C saturday friday thursday wednesday tuesday monday sunday
appendix a i/o map ap-a-76 epson s1c33e08 technical manual 0x301a00C0x301a20 lcd controller name address register name bit function setting init. r/w remarks C inten d31C1 d0 reserved frame interrupt enable C 0 C r/w 0 when being read. 00301a00 (w) 1 enabled 0 disabled frame interrupt register (plcdc_int) C C C intf C vndpf C psave1 psave0 d31 d30C8 d7 d6C2 d1 d0 frame interrupt flag reserved vertical display status reserved power save mode 0 C 1 C 0 0 r/w C r C r/w reset by writing 1. 0 when being read. 0 when being read. 00301a04 (w) 1 generated 0 not generated status and power save configuration register (plcdc_ps) 1 1 0 0 1 0 1 0 psave[1:0] mode normal operation doze mode reserved power save mode 1 vndp 0 vdp C htcnt6 htcnt5 htcnt4 htcnt3 htcnt2 htcnt1 htcnt0 C hdpcnt6 hdpcnt5 hdpcnt4 hdpcnt3 hdpcnt2 hdpcnt1 hdpcnt0 d31C23 d22 d21 d20 d19 d18 d17 d16 d15C7 d6 d5 d4 d3 d2 d1 d0 reserved horizontal total period (ht) setup ht = hdp + hndp ht > hdps + hdp (for hr-tft) reserved horizontal display period (hdp) setup C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. 0 when being read. 00301a10 (w) horizontal display register (plcdc_hd) C ht = (htcnt + 1) 8 [ts] hndp = (htcnt - hdpcnt) 8 [ts] C hdp = (hdpcnt + 1) 8 [ts] C vtcnt9 vtcnt8 vtcnt7 vtcnt6 vtcnt5 vtcnt4 vtcnt3 vtcnt2 vtcnt1 vtcnt0 C vdpcnt9 vdpcnt8 vdpcnt7 vdpcnt6 vdpcnt5 vdpcnt4 vdpcnt3 vdpcnt2 vdpcnt1 vdpcnt0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved vertical total period (vt) setup vt = vdp + vndp vt > vdps + vdp (for hr-tft) reserved vertical display period (vdp) setup C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. 0 when being read. 00301a14 (w) vertical display register (plcdc_vd) C vt = vtcnt + 1 [lines] vndp = htcnt - hdpcnt [lines] C vdp = vdpcnt + 1 [lines] C mod5 mod4 mod3 mod2 mod1 mod0 d31C6 d5 d4 d3 d2 d1 d0 reserved lcd mod rate mod5 = msb mod0 = lsb C 0 0 0 0 0 0 C r/w 0 when being read. 00301a18 (w) mod rate register (plcdc_mr) C 0x0 to 0x3f C hdpscnt9 hdpscnt8 hdpscnt7 hdpscnt6 hdpscnt5 hdpscnt4 hdpscnt3 hdpscnt2 hdpscnt1 hdpscnt0 d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved horizontal display period start position for hr-tft ht > hdps + hdp C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. 0x0 must be set for stn panels. 00301a20 (w) horizontal display start position register (plcdc_hdps) C hdps = hdpscnt + 1 [pixels]
appendix a i/o map s1c33e08 technical manual epson ap-a-77 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301a24C0x301a2c lcd controller name address register name bit function setting init. r/w remarks C vdpscnt9 vdpscnt8 vdpscnt7 vdpscnt6 vdpscnt5 vdpscnt4 vdpscnt3 vdpscnt2 vdpscnt1 vdpscnt0 d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved vertical display period start position for hr-tft vt > vdps + vdp C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. 0x0 must be set for stn panels. 00301a24 (w) vertical display start position register (plcdc_vdps) C vdps = vdpscnt [lines] C fplst9 fplst8 fplst7 fplst6 fplst5 fplst4 fplst3 fplst2 fplst1 fplst0 C fplpol fplwd6 fplwd5 fplwd4 fplwd3 fplwd2 fplwd1 fplwd0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved fpline pulse start position reserved fpline pulse polarity fpline pulse width C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 C r/w C r/w r/w 0 when being read. ? 1: for hr-tft 0x0 must be set for stn panels. 0 when being read. ( ? 1) 00301a28 (w) fpline pulse setup register (plcdc_l) C start position = fplst + 1 [pixels] C pulse width = fplwd + 1 [pixels] 0 1 active high active low C fpfst9 fpfst8 fpfst7 fpfst6 fpfst5 fpfst4 fpfst3 fpfst2 fpfst1 fpfst0 C fpfpol C fpfwd2 fpfwd1 fpfwd0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C8 d7 d6C3 d2 d1 d0 reserved fpframe pulse start position reserved fpframe pulse polarity reserved fpframe pulse width C 0 0 0 0 0 0 0 0 0 0 C 0 C 0 0 0 C r/w C r/w C r/w 0 when being read. ? 1: for hr-tft 0x0 must be set for stn panels. 0 when being read. ( ? 1) 0 when being read. ( ? 1) 00301a2c (w) fpframe pulse setup register (plcdc_f) C start position = fpfst ht [pixels] C C pulse width = (fpfwd+1) ht [pixels] 0 1 active high active low
appendix a i/o map ap-a-78 epson s1c33e08 technical manual 0x301a30C0x301a48 lcd controller name address register name bit function setting init. r/w remarks C fpfstpo9 fpfstpo8 fpfstpo7 fpfstpo6 fpfstpo5 fpfstpo4 fpfstpo3 fpfstpo2 fpfstpo1 fpfstpo0 C fpfsto9 fpfsto8 fpfsto7 fpfsto6 fpfsto5 fpfsto4 fpfsto3 fpfsto2 fpfsto1 fpfsto0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved fpframe pulse stop offset reserved fpframe pulse start offset C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. ? 1: for hr-tft 0x0 must be set for stn panels. 0 when being read. ( ? 1) 00301a30 (w) fpframe pulse offset register (plcdc_fo) C stop offset = fpfstpo [pixels] C start offset = fpfsto [pixels] C ctl1ctl preset fpspol ctlswap d31C4 d3 d2 d1 d0 reserved tft_ctl1 control tft_ctl0C2 preset enable fpshift polarity tft_ctl0/tft_ctl1 swap C 0 0 0 0 C r/w r/w r/w r/w 0 when being read. for hr-tft 0x0 must be set for stn panels. 00301a40 (w) hr-tft special output register (plcdc_tso) C 0 1 program toggle/line 0 1 program preset 0 1 falling rising 0 1 swap not swap C ctl1stp9 ctl1stp8 ctl1stp7 ctl1stp6 ctl1stp5 ctl1stp4 ctl1stp3 ctl1stp2 ctl1stp1 ctl1stp0 C ctl1st9 ctl1st8 ctl1st7 ctl1st6 ctl1st5 ctl1st4 ctl1st3 ctl1st2 ctl1st1 ctl1st0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved tft_ctl1 pulse stop offset tft_ctl1 pulse width = (ctl1stp - ctl1st +1) ts reserved tft_ctl1 pulse start offset C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. ? 2: for hr-tft this register is enabled when preset = 1. 0 when being read. ( ? 2) 00301a44 (w) tft_ctl1 pulse register (plcdc_tc1) C stop offset = ctl1stp + 1 [pixels] C start offset = ctl1st [pixels] C ctl0stp9 ctl0stp8 ctl0stp7 ctl0stp6 ctl0stp5 ctl0stp4 ctl0stp3 ctl0stp2 ctl0stp1 ctl0stp0 C ctl0st9 ctl0st8 ctl0st7 ctl0st6 ctl0st5 ctl0st4 ctl0st3 ctl0st2 ctl0st1 ctl0st0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved tft_ctl0 pulse stop offset tft_ctl0 pulse width = (ctl0stp - ctl0st +1) ts reserved tft_ctl0 pulse start offset C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. ? 2: for hr-tft this register is enabled when preset = 1. 0 when being read. ( ? 2) 00301a48 (w) tft_ctl0 pulse register (plcdc_tc0) C stop offset = ctl0stp + 1 [pixels] C start offset = ctl0st [pixels]
appendix a i/o map s1c33e08 technical manual epson ap-a-79 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301a4cC0x301a80 lcd controller name address register name bit function setting init. r/w remarks C ctl2dly9 ctl2dly8 ctl2dly7 ctl2dly6 ctl2dly5 ctl2dly4 ctl2dly3 ctl2dly2 ctl2dly1 ctl2dly0 d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved tft_ctl2 delay C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. for hr-tft this register is enabled when preset = 1. 00301a4c (w) tft_ctl2 register (plcdc_tc2) C delay = ctl2dly [pixels] C C C C tftsel color fpsmask C dwd1 dwd0 swinv blank C frmrpt dithen C lutpass C bpp2 bpp1 bpp0 d31 d30 d29 d28 d27 d26 d25 d24 d23C8 d7 d6 d5 d4 d3 d2C0 hr-tft panel selection color/mono selection fpshift mask enable reserved lcd panel data width software video invert display blank enable reserved frame repeat for el panel dither mode enable reserved lut bypass mode reserved bit-per-pixel select 0 0 0 C 0 0 0 0 C 0 0 C 0 C 0 0 0 r/w r/w r/w C r/w r/w r/w C r/w r/w C r/w C r/w 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301a60 (w) 1 blank 0 normal lcdc display mode register (plcdc_dmd) 1 inverted 0 normal 1 color 0 mono 1 hr-tft 0 stn dwd[1:0] 11 10 01 00 data format 8-bit (format2) reserved 8-bit (format1) 4-bit 1 enabled 0 disabled 1 repeated 0 not repeated bpp[2:0] 101 100 011 010 001 000 other bpp (color/gray) 16 bpp (64kc) 12 bpp (4kc) 8 bpp (256c) 4 bpp (16c/16gr) 2 bpp (4c/4gr) 1 bpp (2c/2gr) reserved 1 enabled 0 disabled 1 bypassed 0 used C C iram d31C1 d0 reserved iram assignment C 0 C r/w 0 when being read. 00301a64 (w) iram select register (plcdc_iram) 1 a0ram 0 ivram 0x0 to 0xfffffffc mwadr31 mwadr30 | mwadr1 mwadr0 d31 d30 | d1 d0 main window start address mwadr31 = msb mwadr0 = lsb 0x0 r/w 00301a70 (w) main window display start address register (plcdc_madd) C mwladr9 mwladr8 mwladr7 mwladr6 mwladr5 mwladr4 mwladr3 mwladr2 mwladr1 mwladr0 d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved main window line address offset C 0 0 0 0 0 0 0 0 0 0 C r/w 0 when being read. 00301a74 (w) main window line address offset register (plcdc_mladd) C main window width (pixels) bpp/32 0x0 to 0xfffffffc swadr31 swadr30 | swadr1 swadr0 d31 d30 | d1 d0 sub-window start address swadr31 = msb swadr0 = lsb 0x0 r/w 00301a80 (w) sub-window display start address register (plcdc_sadd)
appendix a i/o map ap-a-80 epson s1c33e08 technical manual 0x301a88C0x301a8c lcd controller name address register name bit function setting init. r/w remarks pipen C pipyst9 pipyst8 pipyst7 pipyst6 pipyst5 pipyst4 pipyst3 pipyst2 pipyst1 pipyst0 C pipxst9 pipxst8 pipxst7 pipxst6 pipxst5 pipxst4 pipxst3 pipxst2 pipxst1 pipxst0 d31 d30C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pip sub-window enable reserved sub-window vertical (y) start position reserved sub-window horizontal (x) start position 0 C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 r/w C r/w C r/w 0 when being read. ? 3: this register is enabled when pipen = 1. 0 when being read. ( ? 3) 00301a88 (w) sub-window start position register (plcdc_ssp) C y start position = pipyst (lines) from the origin C x start position = pipxst (pixels) from the origin (word units) 0 1 enabled disabled C pipyend9 pipyend8 pipyend7 pipyend6 pipyend5 pipyend4 pipyend3 pipyend2 pipyend1 pipyend0 C pipxend9 pipxend8 pipxend7 pipxend6 pipxend5 pipxend4 pipxend3 pipxend2 pipxend1 pipxend0 d31C26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved sub-window vertical (y) end position reserved sub-window horizontal (x) end position C 0 0 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 C r/w C r/w 0 when being read. ? 3: this register is enabled when pipen = 1. 0 when being read. ( ? 3) 00301a8c (w) sub-window end position register (plcdc_sep) C y end position = pipyend (lines) from the origin C x end position = pipxend (pixels) from the origin (word units)
appendix a i/o map s1c33e08 technical manual epson ap-a-81 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301aa0C0x301aa4 lcd controller name address register name bit function setting init. r/w remarks lut35 lut34 lut33 lut32 lut31 lut30 C lut25 lut24 lut23 lut22 lut21 lut20 C lut15 lut14 lut13 lut12 lut11 lut10 C lut05 lut04 lut03 lut02 lut01 lut00 C d31 d30 d29 d28 d27 d26 d25C24 d23 d22 d21 d20 d19 d18 d17C16 d15 d14 d13 d12 d11 d10 d9C8 d7 d6 d5 d4 d3 d2 d1C0 look-up table entry 3 data reserved look-up table entry 2 data reserved look-up table entry 1 data reserved look-up table entry 0 data reserved 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w C r/w C r/w C r/w C 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301aa0 (w) look-up table data register 0 (plcdc_lut_03) 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C lut75 lut74 lut73 lut72 lut71 lut70 C lut65 lut64 lut63 lut62 lut61 lut60 C lut55 lut54 lut53 lut52 lut51 lut50 C lut45 lut44 lut43 lut42 lut41 lut40 C d31 d30 d29 d28 d27 d26 d25C24 d23 d22 d21 d20 d19 d18 d17C16 d15 d14 d13 d12 d11 d10 d9C8 d7 d6 d5 d4 d3 d2 d1C0 look-up table entry 7 data reserved look-up table entry 6 data reserved look-up table entry 5 data reserved look-up table entry 4 data reserved 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w C r/w C r/w C r/w C 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301aa4 (w) look-up table data register 1 (plcdc_lut_47) 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C
appendix a i/o map ap-a-82 epson s1c33e08 technical manual 0x301aa8C0x301aac lcd controller name address register name bit function setting init. r/w remarks lutb5 lutb4 lutb3 lutb2 lutb1 lutb0 C luta5 luta4 luta3 luta2 luta1 luta0 C lut95 lut94 lut93 lut92 lut91 lut90 C lut85 lut84 lut83 lut82 lut81 lut80 C d31 d30 d29 d28 d27 d26 d25C24 d23 d22 d21 d20 d19 d18 d17C16 d15 d14 d13 d12 d11 d10 d9C8 d7 d6 d5 d4 d3 d2 d1C0 look-up table entry 11 data reserved look-up table entry 10 data reserved look-up table entry 9 data reserved look-up table entry 8 data reserved 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w C r/w C r/w C r/w C 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301aa8 (w) look-up table data register 2 (plcdc_lut_8b) 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C lutf5 lutf4 lutf3 lutf2 lutf1 lutf0 C lute5 lute4 lute3 lute2 lute1 lute0 C lutd5 lutd4 lutd3 lutd2 lutd1 lutd0 C lutc5 lutc4 lutc3 lutc2 lutc1 lutc0 C d31 d30 d29 d28 d27 d26 d25C24 d23 d22 d21 d20 d19 d18 d17C16 d15 d14 d13 d12 d11 d10 d9C8 d7 d6 d5 d4 d3 d2 d1C0 look-up table entry 15 data reserved look-up table entry 14 data reserved look-up table entry 13 data reserved look-up table entry 12 data reserved 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C 0 0 0 0 0 0 C r/w C r/w C r/w C r/w C 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301aac (w) look-up table data register 3 (plcdc_lut_cf) 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C 0x0 to 0x3f C
appendix a i/o map s1c33e08 technical manual epson ap-a-83 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301b00C0x301b04 clock management unit name address register name bit function setting init. r/w remarks C usbsapb_cke usb_cke sdapcpu_hcke sdapcpu_cke sdaplcdc_cke sdsapb_cke dstram_cke lcdcahbif_cke lcdcsapb_cke lcdc_cke d31C10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved usb sapb i/f clock control usb ip 48 mhz clock control sdramc cpu app clock control (halt) sdramc cpu app clock control sdramc lcdc app clock control sdramc sapb i/f clock control dst ram clock control lcdc ahb i/f clock control lcdc sapb i/f clock control lcdc main clock control 1 on 0 off C 0 0 0 0 0 0 1 0 0 0 C r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00301b00 (w) gated clock control register 0 (pcmu _gatedclk0) protected C C cpuahb_hcke lcdcahb_hcke gpionstp_hcke sramc_hcke efsiobr_hcke misc_hcke C ivramarb_cke tm5_cke tm4_cke tm3_cke tm2_cke tm1_cke tm0_cke egpio_cke i2s_cke dcsio_cke wdt_cke gpio_cke sramsapb_cke spi_cke efsiosapb_cke card_cke adc_cke itc_cke dma_cke rtcsapb_cke d31C30 d29 d28 d27 d26 d25 d24 d23C20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved cpu_ahb bus clk control (halt) lcdc_ahb bus clk control (halt) gpio no stop clock control (halt) sramc clock control (halt) efsio baud rate clk control (halt) misc clock control (halt) reserved ivram arbiter clock control 16-bit timer 5 clock control 16-bit timer 4 clock control 16-bit timer 3 clock control 16-bit timer 2 clock control 16-bit timer 1 clock control 16-bit timer 0 clock control egpio clock control i 2 s clock control dcsio clock control watchdog timer clock control gpio normal clock control sramc sapb i/f clock control spi clock control efsio sapb i/f clock control card i/f clock control adc clock control itc clock control dmac clock control rtc sapb i/f clock control 1 on 0 off C 1 1 1 1 1 1 C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C r/w r/w r/w r/w r/w r/w C r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 when being read. 0 when being read. 00301b04 (w) gated clock control register 1 (pcmu _gatedclk1) protected C 1 on 0 off C
appendix a i/o map ap-a-84 epson s1c33e08 technical manual 0x301b08 clock management unit name address register name bit function setting init. r/w remarks C cmu_clksel4 cmu_clksel3 cmu_clksel2 cmu_clksel1 cmu_clksel0 pllindiv3 pllindiv2 pllindiv1 pllindiv0 lcdcdiv3 lcdcdiv2 lcdcdiv1 lcdcdiv0 C mclkdiv C osc3div2 osc3div1 osc3div0 C oscsel1 oscsel0 sosc3 sosc1 d31C29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15C13 d12 d11 d10 d9 d8 d7C4 d3 d2 d1 d0 reserved cmu_clk output clock source selection pll input clock source divider selection lcdc clock divider selection reserved mclk clock divider selection reserved osc3 clock divider selection reserved osc clock selection high-speed oscillation (osc3) on/of f low-speed oscillation (osc1) on/of f 1 1/2 0 1/1 1 on 0 off 1 on 0 off C 0 0 0 0 0 0 1 1 1 0 1 1 1 C 0 C 0 0 0 C 0 0 1 1 C r/w r/w r/w C r/w C r/w C r/w r/w r/w 0 when being read. 0 when being read. 0 when being read. 0 when being read. 00301b08 (w) system clock control register (pcmu_clkcntl) protected C C C C cmu_clksel[4:0] other 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 clock source reserved osc3_div*1/32 osc3_div*1/16 osc3_div*1/8 osc3_div*1/4 osc3_div*1/2 osc3_div*1/1 lcdc_clk mclk pll osc1 osc3 pllindiv[3:0] other 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 divider osc3*1/8 osc3*1/10 osc3*1/9 osc3*1/8 osc3*1/7 osc3*1/6 osc3*1/5 osc3*1/4 osc3*1/3 osc3*1/2 osc3*1/1 lcdcdiv[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 divider osc3*1/16 osc3*1/15 osc3*1/14 osc3*1/13 osc3*1/12 osc3*1/11 osc3*1/10 osc3*1/9 osc3*1/8 osc3*1/7 osc3*1/6 osc3*1/5 osc3*1/4 osc3*1/3 osc3*1/2 osc3*1/1 osc3div[2:0] 111 110 101 100 011 010 001 000 divider osc3*1/1 osc3*1/1 osc3*1/32 osc3*1/16 osc3*1/8 osc3*1/4 osc3*1/2 osc3*1/1 oscsel[1:0] 11 10 01 00 clock source pll osc3 osc1 osc3
appendix a i/o map s1c33e08 technical manual epson ap-a-85 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301b0cC0x301b14 clock management unit name address register name bit function setting init. r/w remarks C pllcs1 pllcs0 pllbyp pllcp4 pllcp3 pllcp2 pllcp1 pllcp0 pllvc3 pllvc2 pllvc1 pllvc0 pllrs3 pllrs2 pllrs1 pllrs0 plln3 plln2 plln1 plln0 pllv1 pllv0 C pllpowr d31C24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved pll lpf capacitance setup pll bypass mode setup pll charge pump current setup pll vco kv setup pll lpf resistance setup pll multiplication rate setup pll v-divider setup reserved pll on/off control C 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 C 0 C r/w r/w r/w r/w r/w r/w r/w C r/w 0 when being read. 0 when being read. 00301b0c (w) pll control register (pcmu_pll) protected fixed at "0" (default) C fixed at "00" (default) fixed at "10000" (default) pllvc[3:0] 1000 0111 0110 0101 0100 0011 0010 0001 other f vco [mhz] 360 < f vco 400 320 < f vco 360 280 < f vco 320 240 < f vco 280 200 < f vco 240 160 < f vco 200 120 < f vco 160 100 f vco 120 not allowed pllrs[3:0] 1010 1000 other f refck [mhz] 5 f refck < 20 20 f refck 150 not allowed 1 on 0 off plln[3:0] 1111 1110 : 0001 0000 multiplication rate x16 x15 : x2 x1 pllv[1:0] 11 10 01 00 w 8 4 2 not allowed C C ssmcitm3 ssmcitm2 ssmcitm1 ssmcitm0 ssmcidt3 ssmcidt2 ssmcidt1 ssmcidt0 C ssmcon d31C16 d15 d14 d13 d12 d11 d10 d9 d8 d7C1 d0 reserved sscg macro interval timer (itm) setting sscg macro maximum frequency change width setting reserved sscg macro on/off C 1 1 1 1 0 0 0 0 C 0 C r/w r/w C r/w 0 when being read. 0 when being read. 00301b10 (w) sscg macro control register (pcmu_sscg) protected C 0 to 0xf 0 to 0xf C 1 on 0 off C osctm7 osctm6 osctm5 osctm4 osctm3 osctm2 osctm1 osctm0 C osc3off tmhsp C wakeupwt d31C16 d15 d14 d13 d12 d11 d10 d9 d8 d7C4 d3 d2 d1 d0 reserved osc oscillation stabilization-wait timer reserved osc3 disable during sleep wait-timer high-speed mode reserved wakeup-wait function enable 1 wait interrupt 0 no wait 1 high speed 0 normal 1 stop 0 run C 0 0 0 0 0 0 0 0 C 0 0 C 0 C r/w C r/w r/w C r/w 0 when being read. 0 when being read. 0 when being read. 00301b14 (w) C C clock option register (pcmu_opt) protected C 0 to 255
appendix a i/o map ap-a-86 epson s1c33e08 technical manual 0x301b24 clock management unit name address register name bit function setting init. r/w remarks C wr iting 10010110 (0x96) remo v es the wr ite protection of the cloc k control registers (0x301b00C0x301b14). wr iting another v alue set the wr ite protection. C clgp7 clgp6 clgp5 clgp4 clgp3 clgp2 clgp1 clgp0 d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved clock control register protect flag C 0 0 0 0 0 0 0 0 C r/w 0 when being read. 00301b24 (w) clock control protect register (pcmu_protect)
appendix a i/o map s1c33e08 technical manual epson ap-a-87 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock 0x301c00C0x301c20 i 2 s interface name address register name bit function setting init. r/w remarks C i2sen i2souten chmd1 chmd0 wclkmd bclkpol dttmg dtform d31C8 d7 d6 d5 d4 d3 d2 d1 d0 reserved i 2 s module enable i 2 s output enable i 2 s output channel mode i 2 s output word clock mode i 2 s output bit clock polarity i 2 s output data timing i 2 s output data format 1 enabled 0 disabled 1 enabled 0 disabled 1 l: high r: low 0 l: low r: high 1 negative 0 positive 1 not delayed 0 delayed 1 lsb first 0 msb first C 0 0 0 0 0 0 0 0 C r/w r/w r/w r/w r/w r/w r/w 0 when being read. 00301c00 (w) 11 10 01 00 chmd[1:0] mode mute mono left mono right stereo i 2 s control register (pi2s_contrl) C C i2smclk5 i2smclk4 i2smclk3 i2smclk2 i2smclk1 i2smclk0 d31C6 d5 d4 d3 d2 d1 d0 reserved i2s_mclk divide ratio selection C 0 0 0 0 0 0 C r/w 0 when being read. 00301c04 (w) 111111 111110 | 000001 000000 i2smclk[5:0] i2s_mclk mclk (cmu) /64 mclk (cmu) /63 | mclk (cmu) /2 mclk (cmu) /1 i 2 s mclk divide ratio register (pi2s_dv_mclk) C C lrclk2 lrclk1 lrclk0 d31C3 d2 d1 d0 reserved lrclk divide ratio selection C 0 0 0 C r/w 0 when being read. 00301c08 (w) 111 110 101 100 011 010 001 000 lrclk[2:0] lrclk i2s_mclk/512 i2s_mclk/448 i2s_mclk/384 i2s_mclk/320 i2s_mclk/256 i2s_mclk/192 i2s_mclk/128 i2s_mclk/64 i 2 s audio clock divide ratio register (pi2s_dv_lrclk) C C i2sbusy C i2sstart d31C8 d7 d6C1 d0 reserved i 2 s module busy flag reserved i 2 s start/stop 1 busy 0 idle 1 start 0 stop C 0 C 0 C r C r/w 0 when being read. 0 when being read. 00301c0c (w) i 2 s start register (pi2s_start) C C C i2shsdma d31C1 d0 reserved i 2 s hsdma mode selection 1 16 bits 2 ch. 0 32 bits 1 ch. C 0 C r/w 0 when being read. 00301c10 (w) i 2 s hsdma mode select register (pi2s_hsdmamd) C C i2sfifoef d31C1 d0 reserved i 2 s fifo empty flag 1 empty 0 not empty C 0 C r 0 when being read. 00301c14 (w) i 2 s fifo status register (pi2s_fifo_empty) C i2sfifo[31:0] d31C0 pcm data for writing to fifo 0 w 0 when being read. 00301c20 (w) i 2 s fifo register (pi2s_fifo)
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appendix b differences between c33 pe core and other c33 core s1c33e08 technical manual epson ap-b-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock appendix b differences between c 33 pe core and other c 33 core the functions below have been added to or changed for the c 33 pe core, based on functions of the c33 std core cpu (s1c33000 ). for details, see the s1c33 family c33 pe core manual. b.1 instructions the c 33 pe core instruction set is compatible with the c33 std core cpu, note, however, that some existing instructions have been function extended or removed and new instructions have been added for high-performance operations and cost reduction. function-extended instructions the c 33 pe core has the following function-extended instructions. 1 . the number of bits shifted by shift/rotate instructions has bee n increased from 8 to 32. shift %rd , imm5 0C8 bits shift 0C32 bits shift, shift = srl, sll , sra , sla , rr , rl shift %rd , %rs 0C8 bits shift 0C32 bits shift, shift = srl , sll , sra , sla , rr , rl 2 . the data transfer instructions between a general-purpose register and a special register have been modified to support newly added special registers. ld.w %sd , %rs special register specifiable in %sd added ld.w %rd , %ss special register specifiable in %ss added added instructions the instructions added to the c 33 pe core are listed below. 1 . instructions specifically designed to save and restore single or special registers have been added. push %rs pushes single register pop %rd pops single register pushs %ss pushes special registers successively pops %sd pops special registers successively 2 . instructions specifically designed for use with the coprocessor interface have been added. ld.c %rd , imm4 coprocessor data transfer ld.c imm4 , %rs coprocessor data transfer do.c imm6 coprocessor execution ld.cf coprocessor flag transfer 3 . other special instructions have been added. swaph %rd , %rs switches between big and little endians psrset imm5 sets the psr bit psrclr imm5 clears the psr bit jpr %rb register indirect unconditional relative branch instructions removed in the c 33 pe core, the instructions listed below have been removed from the instruction set of the c33 std core cpu. div0s preprocessing for signed step division div0u preprocessing for unsigned step division div1 step division div2s correction of the result of signed step division, 1 div3s correction of the result of signed step division, 2 mac multiply-accumulate operation scan0 scan bits for 0 scan1 scan bits for 1 mirror mirroring these functions can be realized using the software library provided or by other means.
appendix b differences between c33 pe core and other c33 core ap-b-2 epson s1c33e08 technical manual b.2 registers the general-purpose registers (r 0 to r15) are basically the same as in the c33 std core cpu. the special registers have been functionally extended as described below. pc all 32 bits can now be used. moreover, the pc can now be read out to enable high-speed leaf calls. trap table base register a trap table base register (ttbr) has been added. ttbr, which was mapped at address 0x48134 in the c33 std core cpu, is incorporated in the c33 pe core as a special register. the initial value (boot address) has not changed from 0xc00000. processor identification register a processor identification register (idir) has been added for identifying the core type and version. debug base register a debug base register (dbbr) has been added. this register indicates the start address of the debug area. it normally is fixed to 0x60000. processor status register the following flags in psr have been removed as have the related instructions: mo flag (bit 7 ) mac overflow flag ds flag (bit 6 ) divide sign b.3 address space and other address space the c 33 pe core supports a 4g-byte space based on a 32 -bit address bus. other 1 . interrupt/exception processing the trap table base register (ttbr) now serves as an internal special register of the processor. furthermore, this processor has come to generate an exception when an undefined instruction (an object code not defined in the instruction set) is executed or more than two ext instructions are described. 2. pipeline the 3 -stage pipeline in the c33 std core cpu has been modified to a 2 -stage pipeline in the c33 pe core (consisting of fetch/decode and execute/access/write back).
appendix c development tools s1c33e08 technical manual epson ap-c-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock appendix c development tools c.1 major development tools the following shows the major development tools that support the s 1c33e08: 1 . s1c33 family c/c++ compiler package (s5u1c33001c) the s 1c33 family c/c++ compiler package includes software development tools for compiling c/c++ source files, assembling assembly source files, linking object files, debugging executable files, making mask data and other utilities. also included in the package is the gnu 33 ide workbench that provides an integrated development environment from creating source files to debugging. these tools run on windows 2000 or windows xp. 2 . in-circuit debugger (s5u1c3300xh) the in-circuit debugger (icd) is a hardware tool used for debugging. by using an icd with a target board, various debug functions can be executed from the debugger on a personal computer. 3 . s1c33 family middleware packages various kinds of middleware packages, such as real-time os, file system middleware, audio and jpeg codec middleware, music play middleware, are provided.
appendix c development tools ap-c-2 epson s1c33e08 technical manual c.2 precautions on use of s5u1c33001c this section describes the precautions to develop an s 1c33e08 application using the s1c33 family c/c++ compiler package (s 5u1c33001 c). for common precautions and details of tools, see the s5u1c33001c manual. version of s 5u1c33001c use the s 5u1c33001 c (ver. 3 ) or later. precautions on use of c/c++ compiler and assembler compiler and assembler options ? when executing the compiler or assembler (or when creating a makefile), specify the -mc33pe option to generate the codes for the c33 pe core. ? in gnu33 ide, be sure to select c33 pe core for the target cpu (select pe from [properties] dialog for the project > [gnu33 general] > [target cpu macro type]). cpu registers table c. 2.1 general-purpose register usage register %r0 %r1 %r2 %r3 %r4 %r5 %r6 %r7 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 method of use register used as a frame pointer register that need has to their v alues sa v ed when calling a function registers that need ha ve to their v alues sa v ed when calling a function register f or stor ing retur ned v alues (8/16/32-bit data, 32 lo w-order bits of doub le-type data) register f or stor ing retur ned v alues (32 high-order bits of doub le-type data) register f or passing argument (1st word) register f or passing argument (2nd word) register f or passing argument (3rd word) register f or passing argument (4th word) scratch register/unused def ault data area pointer register * ? when the -medda32 option (def ault data area is not used) is not specified ? the c33 pe core does not include the %dp register. do not describe the %dp register in sources and do not specify functions that use the %dp register. ? before the %r0 to %r3 registers can be used, the contents must be saved to the stack using the pushn instruction. also, the saved contents must be restored from the stack using the popn instruction. ? the %r4 and %r5 registers can be used without saving/restoring the contents until a returned value is set in the register before returning. ? the %r6 to %r9 registers can be used after the stored arguments are used. it is not necessary to restore the contents before returning. ? the %r10 to %r15 registers are reserved by the as assembler and ld linker for referencing symbols. try to use these registers as little as possible. ? passing arguments to the function that returns a structure data if the length of the structure data that is returned from a function is 8 bytes or less, the structure data is stored in the %r4 and %r5 registers used for storing returned values. in this case, the pointer to the structure that is normally sent as the 1 st argument is not passed to the function.
appendix c development tools s1c33e08 technical manual epson ap-c-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock libraries the s 5u1c33001 c package contains different library files for each c33 core. specify the c 33 pe core library files for the libraries to be linked. precautions on use of debugger ? use the s 5 u 1 c 33001 h 1100 (icd 33 ver. 3 . 0 ) or later when debugging an s 1 c 33 e 08 application using an icd. earlier versions of icd do not support the s 1 c 33 e 08 . furthermore, it is necessary to update the icd firmware when using the s 5 u 1 c 33001 h 1100 (icd 33 ver. 3 . 0 ), since its standard specification does not support the s 1 c 33 e 08 . the following s 1 c 33 e 08 pins are used for debugging. dsio (p 34 ) dclk (p 35 ) dst2 (p 36 ) these pins must be configured for debugging. fix the debug port mux register ( 0 x 300014 ) at 0 x 1 or the p 34 Cp 36 port function select register ( 0 x 3003 a 7 ) at 0 x 0 and do not switch the pin function. when pc tracing is not performed, disable the pc trace function in the icd by setting the dip switch (sw 5 : on). ? the pc trace function of the icd uses the s 1 c 33 e 08 pins listed below. dst0 (p 15 /tm 5 /sout 1 /tft_ctl 0 ) dst1 (p 16 /dcsio 0 /#sclk 1 /tft_ctl 3 ) dpco (p 17 /dcsio 1 /#srdy 1 /tft_ctl 2 ) dsio (p 34 ) dclk (p 35 ) dst2 (p 36 ) these pins must be configured for debugging. fix the debug port mux register ( 0 x 300014 ) at 0 x 1 and do not switch the pin function. ? when debugging a c33 pe core application with the icd, execute the c33 das command as shown below before executing the target command. (gdb) c33 das 0x60000 0x84780 1 (gdb) target icd usb (0x60000 = debug rom address, 0x84780 = debug ram address, 1 = c33 pe core) ? the areas listed below are reserved for debugging or system use. do not access these areas during debugging. - area 0, addresses 0x0 to 0 xf (when the debug monitor is used) - area 1 (reserved for system) - area 2 (reserved for debugging) - area 3, addresses 0x84700 to 0x847ff and 0x90000 to 0 xfffff (reserved for debugging/system) ? setting dstram_cke (d3/0x301b00) when the debug tools (icd 33 and gnu33 ) are used, addresses 0x846 ff to 0x847 ff in the dst ram are used as the debug area. therefore, set dstram_cke (d 3/0x301b00 ) to 1 to supply the operating clock to the dst ram before debugging can be started. dstram_cke (d 3/0x301b00 ) can be set to 0 to stop the dst ram operation when the debug tool and the dst ram are not used. ? dstram_cke : dstram clock control bit in the gated clock control register 0 (d3/0x301b00)
appendix c development tools ap-c-4 epson s1c33e08 technical manual ? writing boot program using the debugger the following shows the procedure to write a program to the boot device using the debugger and to start up the system from the boot device. 1 . make sure that the target board (s1c33e08) and icd33 are off. 2 . configure the s1c33e08 boot[1: 0 ] pins, as you want. 3 . turn the target board (s1c33e08) and icd33 on and start up the debugger on the pc. 4 . execute a command file to disable the boot sequence and to write a boot program to the boot device (nand flash, nor flash, spi flash, etc.) from the debugger. 5 . terminate the debugger and turn the target board (s1c33e08) and icd33 off. 6 . configure the s1c33e08 boot[1:0 ] pins according to the boot device. 7 . disconnect the icd33 and turn the target board (s1c33e08) on. the s 1c33e08 boots up by the boot program written in the device specified. the following shows an example command file to write the boot program in step 4 . set the boot register (0x300018) to 0x01 to disable the boot sequence before erasing the flash and writing the program. example: to write the boot program test.elf to the nor flash located in the #ce 10 area # gwb33.cmd command file made by gwb33 c33 das 0x60000 0x84780 # set the map in the debugger # c33 rpf c33e08.par # load symbol information file am29f800.elf # decide debugger mode and port target icd com1 # target icd usb # load to memory load am29f800.elf # boot disable, ce10 = 16 bits set {char} 0x300020 = 0x96 set {char} 0x300018 = 0x01 # flash set command c33 fls 0xc00000 0xcfffff flash_erase flash_load # 0xc00000 = flash area start address # 0xcfffff = flash area end address # flash_erase = flash erase routine top address # flash_load = flash load routine top address #flash erase command c33 fle 0xc00000 0x0 0x0 # 0xc00000 = flash control register # 0x0 = erase start block (0: erase all areas 1-19) # 0x0 = erase end block (this parameter is ignored as the start block is 0) file test.elf target icd com1 #target icd usb # boot disable, ce10 = 16 bits set {char} 0x300020 = 0x96 set {char} 0x300018 = 0x01 load test.elf
appendix d boot s1c33e08 technical manual epson ap-d-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock appendix d boot d. 1 boot mode the s1c33e08 supports the five boot modes listed below. ? large-page nand flash boot (large page: 2048 + 64, 4096 + 128 bytes/page) ? small-page nand flash boot (small page: 512 + 16, 1024 + 32 bytes/page) ? nor flash/external rom boot (either 8 bits or 16 bits) ? spi-eeprom boot ? pc rs232c boot the s 1c33e08 boots up in the boot mode that can be selected with the boot and #ce10 pin configuration at initial reset. table d. 1.1 setting boot mode (pfbga-180pin or die model) boo t1 pin 1 1 0 0 boot mode spi-eepr om pc rs232c nor flash/e xter nal ro m reser ve d large-page nand flash (> 1024 + 32 b ytes/page) small-page nand flash ( 1024 + 32 b ytes/page) boo t0 pin 1 0 1 0 #ce10 1 (input) 0 (input) output C 1 (input) 0 (input) boot code star t address 0x20010 in the inter nal r om (area 1) 0x2000c in the inter nal r om (area 1) C 0x20004 in the inter nal r om (area 1) mbr ex ecution address 0x0 in a0ram depending on the contents in 0xc00000 C 0x0 in a0ram table d. 1.2 setting boot mode (qfp-144pin model) boo t1 pin 1 0 boot mode nor flash/e xter nal ro m large-page nand flash (> 1024 + 32 b ytes/page) small-page nand flash ( 1024 + 32 b ytes/page) #ce10 output 1 (input) 0 (input) boot code star t address 0x2000c in the inter nal r om (area 1) 0x20004 in the inter nal r om (area 1) mbr ex ecution address depending on the contents in 0xc00000 0x0 in a0ram ? the qfp- 144 pin model provides the boot1 pin only due to the limitation of number of pins (the boot0 pin is pulled down to v ss inside the ic). when the power is turned on or the chip is reset, the boot address is set to 0xc00000 in area 10 (ttbr initial value) due to the c 33 pe core specification. in the s1c33e08 , a 4 -word gate rom is located at area 10 (address 0xc00000 in the internal area). it contains vectors to jump to the boot sequence (boot code start address) for the boot mode specified by the pins above. the boot sequence is programmed in the specific rom in area 1.
appendix d boot ap-d-2 epson s1c33e08 technical manual d. 2 nand flash boot d. 2.1 configuration of nand flash boot system when the s 1c33e08 is turned on or reset with both the boot1 and boot0 pins set to 0 (v ss ), the s 1c33e08 boots up by executing the mbr after loading it from the nand flash in the #ce 11 area to a0ram. the nand flash conditions supported by the s 1c33e08 are as follows: ? data size: 8 bits or 16 bits ? memory size: 1g bits max. (small page) 128 g bits max. (large page) ? page size: 512 + 16 bytes/page 1024 + 32 bytes/page 2048 + 64 bytes/page 4096 + 128 bytes/page figure d.2.1.1 shows a nand flash boot system connection diagram. s1c33e08 nand flash d[15:0] or d[7:0] cle ale #ce #re #we r y/#by #wp pre #ce10 (p57) boo t1 boo t0 v ddh 100 k ? 4.7 k ? p02 p03 (p56) #ce11 (p30) #smrd (p31) #smwr (a24) p40 p xx io[15:0] (16 -bit flash ) or io[7:0] (8 -bit flash ) figure d. 2.1.1 nand flash boot system table d. 2.1.1 pins used for nand flash boot s1c33e08 pins #ce11 /p56 p02 /#sclk0/#dmaend2 p03 /#srd y0/#dmaend3 p30/ card2 ? 1 /#dmareq0 p31/ card3 ? 1 /#dmareq1 a24/ p40 /#sdcas/excl4 d[7:0] d[15:8] /pc[7:0] p xx ? 2 #ce10/ p57 ? 3 nand flash pins #ce cle ale #re #we r y/#by io[7:0] io[15:8] #wp C pin status before booting high output input (hi-z) input (hi-z) input (hi-z) input (hi-z) lo w output input (with b us latch) input (with b us latch) (input) input (pulled up inter nally) pin status after booting high output lo w output lo w output high output high output input (pulled up inter nally) input (with b us latch) input (with b us latch) (input) input ? 1: ? 2: ? 3: card2 is set to #smrd and card3 is set to #smwr. it should be controlled according to the application by the user program after booting. used to specify the page siz e dur ing boot mode configuration with the boo t pins . the pins listed in the table are configured for nand flash devices (pin names in boldface ) in the boot sequence. therefore, these pins cannot be used for general-purpose i/o or other peripheral functions.
appendix d boot s1c33e08 technical manual epson ap-d-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock d. 2.2 nand flash boot sequence figure d.2.2.1 shows the nand flash boot flowchart. st ar t j umps to address 0x0 configures card i/f and por t functions initializ es nand flash page inde x (ra = 0) loads and ve r ifies 4-b yte configuration data (resets de vice siz e) loads 512-b yte ex ecutab le code/ ecc chec k r y/#by detection small/ large page detection issues reset command (0xff) issues read command (0x00) outputs 4-cycle address issues read command 1 (0x00) issues read command 2 (0x30) outputs 5-cycle address p40 = l r y/#by detection p40 = l end of p age no ve r ify error p57(#ce10) = h p57(#ce10) = l ye s p40 = h or timeout p40 = h or timeout no error ye s no ye s increments nand flash page (ra = +1) figure d. 2.2.1 nand flash boot flowchart
appendix d boot ap-d-4 epson s1c33e08 technical manual (1 ) when the boot1 and boot0 pins are set to 0 at power-on or reset, the nand flash boot sequence programmed in the specific rom (area 1 ) is executed. (2 ) the boot sequence configures the port and the card interface. (3 ) issues the reset command to reset the nand flash. (4 ) reads the p57 (#ce10) pin status and issues a read command according to the page size determined by the read pin level. when p 57 (#ce10 ) pin = 0 , a read command for small page (1 -cycle command with a 4 -cycle address) is issued. when p 57 (#ce10 ) pin = 1 , a read command for large page (2 -cycle command with a 5 -cycle address) is issued. (5 ) reads 512 + 16 bytes of data from the first page. the first 4 bytes are configuration data that indicates the nand flash bus size and page size. the subsequent contents are executable codes and ecc. (see section d. 2.3 for details.) according to the read configuration data, read operation continues until the end of the page. the executable codes are loaded from the beginning of a 0ram (0x0C). the read process performs an error check every 512 bytes using an 8 -byte ecc that follows. if an error is detected, read operation from the current page is aborted. in this case, the sequence returns to step ( 3 ) and reads mbr again from the next page. (6 ) when all the data in a page has been read, the sequence jumps t o address 0x0 to execute the loaded codes. figures d.2.2.2 and d.2.2.3 show mbr reading start sequences for a small-page and a large-page nand flash. #ce (#ce11) cle (p02) ale (p03) #we (p31) #re (p30) ry/#by (a24) i/o[7:0] (d[7:0]) 0x00 0x00 data1 data2 data3 data4 data5 data6 data7 data8 data9 0x00 0x00 0x00 read command configuration data * mbr data executable codes 4-cycle address * read in 2 cycles for 16-bit nand flash figure d. 2.2.2 small-page nand flash read (8 -bit device) #ce (#ce11) cle (p02) ale (p03) #we (p31) #re (p30) ry/#by (a24) i/o[7:0] (d[7:0]) 0x00 0x00 0x30 data1 data2 data3 data4 data5 data6 0x00 0x00 0x00 0x00 1st read command 2nd read command configuration data * mbr data executable code 5-cycle address * read in 2 cycles for 16-bit nand flash figure d. 2.2.3 large-page nand flash read (8 -bit device)
appendix d boot s1c33e08 technical manual epson ap-d-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock d. 2.3 nand flash data mbr code layout figure d. 2.3.1 shows the mbr code layout according to the page size. configuration data byte 1 byte 2 byte 3 byte 4 executable code (1) byte 5 : byte 516 ecc (1) byte 517 : byte 524 unused byte 525 : byte 528 mbr data 512 + 16 bytes/page 512 bytes 8 bytes (8-bit nand flash) configuration data byte 2 byte 4 executable code (1) byte 6 : byte 516 ecc (1) byte 518 : byte 524 unused byte 526 byte 528 byte 1 byte 3 byte 5 : byte 515 byte 517 : byte 523 byte 525 byte 527 mbr data 512 bytes 8 bytes (16-bit nand flash) configuration data byte 1 byte 2 byte 3 byte 4 executable code (1) byte 5 : byte 516 ecc (1) byte 517 : byte 524 unused byte 1045 : byte 1056 mbr data 1024 + 32 bytes/page 512 bytes 8 bytes (8-bit nand flash) configuration data byte 2 byte 4 executable code (1) byte 6 : byte 516 ecc (1) byte 518 : byte 524 unused byte 1046 : byte 1056 byte 1 byte 3 byte 5 : byte 515 byte 517 : byte 523 byte 1045 : byte 1055 mbr data 512 bytes 8 bytes (16-bit nand flash) executable code (2) byte 525 : byte 1036 ecc (2) byte 1037 : byte 1044 512 bytes 8 bytes configuration data byte 1 byte 2 byte 3 byte 4 executable code (1) byte 5 : byte 516 ecc (1) byte 517 : byte 524 unused byte 2085 : byte 2112 mbr data 512 bytes 8 bytes (8-bit nand flash) 512 bytes 8 bytes 512 bytes 8 bytes 512 bytes 8 bytes executable code (2) byte 525 : byte 1036 ecc (2) byte 1037 : byte 1044 executable code (3) byte 1045 : byte 1556 ecc (3) byte 1557 : byte 1564 executable code (4) byte 1565 : byte 2076 ecc (4) byte 2077 : byte 2084 executable code (2) byte 526 : byte 1036 ecc (2) byte 1038 : byte 1044 byte 525 : byte 1035 byte 1037 : byte 1043 512 bytes 8 bytes configuration data byte 2 byte 4 executable code (1) byte 6 : byte 516 ecc (1) byte 518 : byte 524 unused byte 2086 : byte 2112 byte 1 byte 3 byte 5 : byte 515 byte 517 : byte 523 byte 2085 : byte 2111 mbr data 512 bytes 8 bytes (16-bit nand flash) 512 bytes 8 bytes 512 bytes 8 bytes 512 bytes 8 bytes executable code (2) byte 526 : byte 1036 ecc (2) byte 1038 : byte 1044 byte 525 : byte 1035 byte 1037 : byte 1043 executable code (3) byte 1046 : byte 1556 ecc (3) byte 1558 : byte 1564 byte 1045 : byte 1555 byte 1557 : byte 1563 executable code (4) byte 1566 : byte 2076 ecc (4) byte 2078 : byte 2084 byte 1565 : byte 2075 byte 2077 : byte 2083 2048 + 64 bytes/page figure d. 2.3.1 mbr code layout configuration data a 4 -byte configuration data, which represents the nand flash bus size and page size, must be written at the beginning of the mbr code. figure d. 2.3.2 below shows the bit configuration of the first byte. bit 7 user id bus size page size bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure d. 2.3.2 first byte of configuration data bits 7C6 : user id, or any user defined contents this is a free-field allowing the user to define any id. these 2 bits do not affect the boot up operation. bits 5C4 : nand flash bus size 01: 16 bits 10: 8 bits other: invalid bits 3C0 : nand flash page size 0001: 512 + 16 bytes 0010: 1024 + 32 bytes 0100: 2048 + 64 bytes 1000: 4096 + 128 bytes other: invalid
appendix d boot ap-d-6 epson s1c33e08 technical manual the second to fourth bytes are redundant data used to check the configuration data. table d. 2.3.1 shows the logical equations for expressing the second to fourth bytes and configuration data samples. table d. 2.3.1 configuration data samples byte no. 1st b yte 2nd b yte 3rd b yte 4th b yte equation C [ d ata ] 1st b yte [d ata ] 1st b yte 2nd b yte [d ata d ata ] 2nd b yte ^ 3rd b yte [d ata ^ (d ata d at a)] ? 8 bits ? 512 + 8 0x21 0xde 0x9e 0x40 ^: indicates xor. ? 16 bits ? 512 + 8 0x11 0xee 0xce 0x20 ? 8 bits ? 2048 + 64 0x24 0xdb 0xcc 0x17 ? 16 bits ? 2048 + 64 0x14 0xeb 0x5c 0xb7 ecc data an ecc (error correction code) generator is embedded in the card interface module. the ecc generator generates a 22 -bit ecc parity data, which consists of a 6 -bit column parity code (cp) and a 16 -bit line parity code (lp), for each 256 bytes (in the case of 8 -bit devices) or 128 words (in the case of 16 -bit devices) of nand flash data area. so two 22 -bit ecc parity data are generated per 512 -byte data. when reading data from a nand flash, software can compare the ecc data read from the nand flash with the data generated by the ecc generator. it makes it possible to detect two bit errors and correct one bit errors. the ecc check is performed in the boot sequence. if an error occurs, read operation from the current page is aborted and the sequence reads mbr again from the next page. for this comparison, an 8 -byte ecc data must be written for every 512 bytes of nand flash data. figure d. 2 . 3 . 3 shows the configuration of 8-byte ecc. ecc byte 1 cp0[5:0] 0x00 lp0[7:0] lp0[15:8] cp1[5:0] 0x00 lp1[7:0] lp1[15:8] ecc byte 2 ecc byte 3 ecc byte 4 ecc byte 5 ecc byte 6 ecc byte 7 ecc byte 8 figure d. 2.3.3 ecc data in nand flash for the ecc algorithm, see section v. 4.6, ecc generator.
appendix d boot s1c33e08 technical manual epson ap-d-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock d. 3 nor flash/external rom boot d. 3.1 configuration of nor flash/external rom boot system when the s 1c33e08 is turned on or reset with the boot1 pin set to 1 (v ddh ) and boot 0 pin set to 0 (v ss ), the s1c33e08 reads the reset vector from address 0xc00000 in the external nor flash or external rom and jumps to the user reset handler routine. this boot sequence is similar to the standard function of the c 33 pe core. however, the s 1c33e08 supports booting from an 8 -bit nor flash in contrast to the c33 pe core that supports only a 16-bit device. the s 1c33e08 reads the reset vector by executing the boot program written in the specific rom (area 1 ), and configures the #ce10 device size to 8 or 16 bits according to the lsb of the reset vector that is ignored in 16 -bit boot. then it jumps to the reset handler routine. figure d.3.1.1 shows a nor flash/external rom boot system connection diagram. s1c33e08 8-bit nor flash (exter nal r om) (1) 8-bit nor flash/exter nal ro m a[23:0] d[7:0] #rd #wrl #ce a[23:0] dq[7:0] #oe #we #ce10 boo t1 boo t0 v ddh 100 k ? 4.7 k ? s1c33e08 16-bit nor flash (exter nal r om) (2) 16-bit nor flash/exter nal ro m a[23:1] d[15:0] #rd #wrl #ce a[22:0] dq[15:0] #oe #we #ce10 boo t1 boo t0 v ddh 100 k ? 4.7 k ? figure d. 3.1.1 nor flash/external rom boot system this system uses only the external bus signals for #ce 10 that are configured by default. d. 3.2 nor flash/external rom boot sequence figure d.3.2.1 shows the nor flash/external rom boot flowchart. st ar t j umps to reset v ector configures area 10 f or 8-bit de vices configures area 10 f or 16-bit de vices loads reset v ector lsb of 0xc00000 1 0 figure d. 3.2.1 nor flash/external rom boot flowchart
appendix d boot ap-d-8 epson s1c33e08 technical manual (1 ) when the boot1 pin is set to 1 and boot0 pin is set to 0 at power-on or reset, the nor flash/external rom boot sequence programmed in the specific rom (area 1 ) is executed. (2 ) the boot sequence configures the sramc for setting the #ce10 area device size to 8 bits. (3 ) checks the lsb of the reset vector written at address 0xc00000. (4 ) sets the #ce10 area device size back to 16 bits if the lsb of the reset vector is 0. leaves it unchanged ( 8 bits) if the lsb of the reset vector is 1. (5 ) reads the reset vector again and jumps to that address. figures d.3.2.2 and d.3.2.3 show 16-bit and 8-bit nor flash boot sequences. #ce10 #rd a[23:0] d[15:0] c00000 c00002 c00000 c00002 p[15:0] p[31:16 ] c0000 0 c00002 p[15:0] p[31:16] p p + 2 p[15:0 ] p[31:16] dummy read reset vector read jump to p lsb check bus size configuration figure d. 3.2.2 16-bit nor flash boot #ce10 #rd a[23:0] d[7:0] c00000 c00002 c00000 c00002 p[7:0] p[23:16 ] c0000 0 c00003 p[7:0 ] c0000 1 p[15:8 ] c00002 p[23:16] p[31:24 ] p p + 2 p[7:0] p[23:16] dummy read reset vector read jump to p lsb check bus size configuration figure d. 3.2.3 8-bit nor flash boot d. 3.3 reset vector for nor flash/external rom boot to boot up the system from a 16 -bit nor flash/external rom, write a reset vector in which the lsb is set to 0 to address 0xc00000. to boot up the system from an 8 -bit nor flash/external rom, write a reset vector in which the lsb is set to 1 to address 0xc00000. bit 31 reset vector 0 bit 30 bit 29 bit 3 bit 2 bit 1 bit 0 16-bit device reset vector 1 8-bit device 0xc00000 figure d. 3.3.1 reset vector for nor flash/external rom boot the lsb of the reset vector is ignored when the program jumps to the user reset handler routine. therefore, the jump destination is always a 16 -bit boundary address even if the lsb is set to 1 for 8-bit boot.
appendix d boot s1c33e08 technical manual epson ap-d-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock d. 4 spi-eeprom boot d. 4.1 configuration of spi-eeprom boot system when the s 1c33e08 is turned on or reset with all the boot1 , boot0 , and #ce10 pins set to 1 (v ddh ), the s1c33e08 boots up by executing the mbr after loading it from the eeprom, fram, or serial flash connected to the spi bus to a 0ram. figure d.4.1.1 shows an spi-eeprom boot system connection diagram. s1c33e08 eepr om (spi) reset signal #cs clk d q #hold #wp #reset #ce10 (p57) boo t1 boo t0 v ddh 100 k ? 4.7 k ? p52 (p67) spi_clk (p66) sdo (p65) sdi p xx #reset v ddh figure d. 4.1.1 spi-eeprom boot system note : the qfp24-144pin package model does not support spi-eeprom boot. table d. 4.1.1 pins used for spi-eeprom boot s1c33e08 pins p52 /bclk/#ce6/cmu_clk p65/ sdi /fpd at 8 p66/ sdo /fpd at 9 p67/ spi_clk /fpd a t10 p xx ? 1 #ce10/ p57 ? 2 eeprom pins #cs q d clk #wp C pin status before booting input (pulled up inter nally) input (hi-z) input (hi-z) input (hi-z) (input) input (pulled up inter nally) pin status after booting high output input (hi-z) output lo w output (input) input ? 1: ? 2: it should be controlled according to the application by the user program after booting. used to select spi-eepr om boot or pc rs232c boot dur ing boot mode configuration with the boo t pins . the pins listed in the table are configured for spi (pin names in boldface ) in the boot sequence. therefore, these pins cannot be used for general-purpose i/o or other peripheral functions. this boot sequence supports up to 4 gb (4 -cycle address) of spi-bus eeprom. the spi module is configured as below in the boot sequence. bit rate: osc 3 / 16 (e.g., 3 mhz when osc3 = 48 mhz) spi mode: cpol = 0, cpha = 0 data bit length: 8 bits master/slave mode: master mode spi_clk (cpol = 0, cpha = 0) sdi/sdo fetching receive data into shift register 8 bits msb lsb figure d. 4.1.2 spi mode
appendix d boot ap-d-10 epson s1c33e08 technical manual d. 4.2 spi-eeprom boot sequence figure d.4.2.1 shows the spi-eeprom boot flowchart. st ar t j umps to address 0x0 configures spi (cpha = 0, cpol = 0) issues rdsr command (0x05) issues read command (0x03) configures the por t functions wip bit 1 0 p57 (#ce10) 0 t o pc rs232c boot sequence 1 loads 512-b yte ex ecutab le code outputs 32-bit address figure d. 4.2.1 spi-eeprom boot flowchart (1 ) when the boot1 , boot0 , and p57 (#ce10 ) pins are set to 1 at power-on or reset, the spi-eeprom boot sequence programmed in the specific rom (area 1 ) is executed. (2 ) the boot sequence configures the port and the spi module. (3 ) issues the rdsr (read status register) command (0x05 ) to the eeprom and reads the wip (write in progress) bit to check the eeprom status. waits for the eeprom be ready status if it is busy. (4 ) issues the read command (0x03) with a 32-bit address (0x00 4 bytes) to the eeprom. (5 ) reads 512 bytes of executable codes. the executable codes are loaded from the beginning of a 0ram (0x0C). (6 ) jumps to address 0x0 to execute the loaded codes. figure d.4.2.2 shows mbr reading start sequences for a spi-eeprom. #cs (p52) clk (p67) d (p66) q (p65) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 read command (0x03) 32-bit address (0x00 4 bytes) mbr data 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 invalid data data 1 data 2 figure d. 4.2.2 eeprom read
appendix d boot s1c33e08 technical manual epson ap-d-11 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock d. 4.3 eeprom data the spi-eeprom boot sequence issues a 32 -bit address regardless of the eeprom size. depending on the eeprom size, data may be output during an address output period. therefore, mbr codes must be followed by an appropriate offset. the boot sequence ignores the offset bytes. table d. 4.3.1 and figure d.4.3.1 show the data locations according to the eeprom size. table d. 4.3.1 eeprom size and address size eeprom size 1 to 256 b ytes 0.25k to 64k b ytes 64k to 16m b ytes 16m to 4g b ytes address size 1 b yte 2 b ytes 3 b ytes 4 b ytes mbr data location byte 4 to byte 256 byte 3 to byte 514 byte 2 to byte 513 byte 1 to byte 512 byte 1 253-byte executable code invalid byte 2 byte 3 byte 4 byte 5 byte 255 byte 256 1-cycle address eeprom byte 1 512-byte executable code invalid byte 2 byte 3 byte 4 byte 5 byte 514 2-cycle address eeprom byte 1 512-byte executable code invalid byte 2 byte 3 byte 4 byte 5 byte 513 3-cycle address eeprom byte 1 512-byte executable code byte 2 byte 3 byte 4 byte 5 byte 512 4-cycle address eeprom figure d. 4.3.1 data location according to the eeprom size
appendix d boot ap-d-12 epson s1c33e08 technical manual d. 5 pc rs232c boot d. 5.1 configuration of pc rs232c boot system when the s 1c33e08 is turned on or reset with the boot1 and boot0 pins set to 1 (v ddh ) and the #ce 10 pin set to 0 (v ss ), the s 1c33e08 boots up by executing the mbr after loading it from the pc (rs232 c) to a0 ram via the serial interface ch. 0. figure d.5.1.1 shows a pc rs232c boot system connection diagram. s1c33e08 txd rxd gnd comx #ce10 (p57) boo t1 boo t0 v ddh 100 k ? 4.7 k ? (p00) sin0 (p01) sout0 v ss figure d. 5.1.1 pc rs232c boot system note : the qfp24-144pin package model does not supports pc rs232c boot. table d. 5.1.1 pins used for pc rs232c boot s1c33e08 pins p00/ sin0 /#dmaack2 p01/ sout0 /#dmaa ck3 #ce10/ p57 ? 1 rs232c pins txd rxd C pin status before booting input (hi-z) input (hi-z) input (pulled up inter nally) pin status after booting input (hi-z) output input ? 1: used to select spi-eepr om boot or pc rs232c boot dur ing boot mode configuration with the boo t pins . the pins listed in the table are configured for the serial interface ch. 0 (pin names in boldface ) in the boot sequence. therefore, these pins cannot be used for general-purpose i/o or other peripheral functions. the baud rate and rs232 c parameters are configured as below in the boot sequence. baud rate: automatically detected, 9600 bps typ. (note) data bit length: 8 bits start bit: 1 bit stop bit: 1 bit parity: none note : table d.5.1.2 shows the maximum baud rate that can be set according to the s1c33e08 system clock (osc3) frequency. the baud rate values in the vicinity of maximum frequency may have an error on the order of 5 percent. use a lower baud rate to reduce an error. table d. 5.1.2 system clock frequency and baud rate osc3 frequency maximum baud rate (bps) > 500 khz 1200 > 4 mhz 9600 > 7 mhz 19200 > 15 mhz 38400 > 20 mhz 57600 > 40 mhz 115200
appendix d boot s1c33e08 technical manual epson ap-d-13 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock d. 5.2 pc rs232c boot sequence figure d.5.2.1 shows the pc rs232 c boot flowchart. st ar t j umps to address 0x0 initializ es the 16-bit timer counts lo w pulses with the 16-bit timer calculates the baud rate from the 16- bit timer count v alue configures the por t functions 0x80 4 b ytes receiv ed star t/stop bit detection no no ye s ye s p57 (#ce10) 1 t o spi boot sequence 0 uploads the chip id do wnloads 512-b yte ex ecutab le code uploads 512-b yte ex ecutab le code (f or ve r ification) initializ es the ser ial interf ace figure d. 5.2.1 pc rs232 c boot flowchart (1 ) when the boot1 and boot0 pins are set to 1 and the p57 (#ce10 ) pin is set to 0 at power-on or reset, the pc rs232 c boot sequence programmed in the specific rom (area 1 ) is executed. (2 ) the boot sequence configures the port and the 16 -bit timer. (3 ) waits for the p00 (sin0 ) input pulled-down to 0 (start bit). when a start bit is input, the boot sequence starts the 16 -bit timer to measure the low level width. (4 ) after 4 bytes of 0x80 sent from the pc have been input, the baud rate is calculated from the 16 -bit timer count value, and the serial interface is enabled with the calculated baud rate. (5 ) the s1c33e08 uploads a 4-byte chip id code to the pc. the pc sends 512 bytes of executable codes to the s1c33e08 after the chip id is verified. (6 ) the s1c33e08 downloads the 512 bytes of executable codes. the executable codes are loaded from the beginning of a 0ram (0x0C). (7 ) the s1c33e08 uploads the downloaded 512 bytes of executable codes to the pc. the pc verifies the codes with the original data for checking error. (8 ) the boot sequence jumps to address 0x0 to execute the loaded codes.
appendix d boot ap-d-14 epson s1c33e08 technical manual d. 5.3 transfer data first the pc sends 4 bytes of 0x80 to the s1c33e08 . then the pc sends 512 -byte mbr data after verifying the 4 -byte chip id code received from the s1c33e08. the s 1c33e08 calculates the baud rate by counting the 4 bytes of 0x80 received from the pc and configures its serial interface. then the s 1c33e08 sends the 4 -byte chip id code to the pc. after the 512 -byte mbr data is received, the s 1c33e08 returns it to the pc for verification. figure d.5.3.1 shows the transfer data. byte 1 512-byte executable code byte 2 byte 3 byte 4 0x80 0x80 0x80 0x80 byte 5 byte 516 (first 4 bytes are used for baud rate measurement.) pc s1c33e08 byte 1 512-byte executable code byte 2 byte 3 byte 4 0x00 0x0e 0x07 0x00 byte 5 byte 516 (first 4 bytes are chip id.) figure d. 5.3.1 transfer data for pc rs232c boot
appendix d boot s1c33e08 technical manual epson ap-d-15 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock d. 6 precautions the s1c33e08 supports various boot modes as described above. in these boot modes, the following modes use the specific sequencer built into the s 1c33e08. ? small/large-page nand flash boot ? spi-eeprom boot the function and operation of the specific sequencer have been checked using the devices listed below, note, however, that we cannot guarantee that all nand flash and spi-eeprom products work. therefore, be sure to evaluate the function and check the operation of the boot sequence on the product system. < reference > nand flash and spi-eeprom models that have completed the basic operation check for the s1c33e08 8-bit large page nand flash toshiba tc58 nvg1s3btg00 samsung k9f2g08u0 m-y,p 8-bit small page nand flash stmicroelectronics nand512w3a2bn6 16-bit small page nand flash samsung k9f1216u0a spi-eeprom stmicroelectronics st m 45pe80 winbond nx25p16
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appendix e summary of precautions s1c33e08 technical manual epson ap-e-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock appendix e summary of precautions memory the areas listed below are reserved for debugging or system use. do not access these areas from the user program or the debugger during debugging. - area 0, addresses 0x0 to 0 xf (when the debug monitor is used) - area 1 (reserved for system) - area 2 (reserved for debugging) - area 3, addresses 0x84700 to 0x847ff and 0x90000 to 0 xfffff (reserved for debugging/system) high-speed dma (hsdma) ? when setting the transfer conditions, always make sure the dma controller is inactive (hs x _en (d 0/ 0x30112c + 0x10? x) = 0). ? hs x _en : ch. x enable bit in the hsdma ch. x enable register (d0/0x30112c + 0x10? x ) ? after an initial reset, the cause-of-interrupt flag (fhdm x (d x/0x300281 )) becomes indeterminate. always be sure to reset the flag to prevent interrupts or idma requests from being generated inadvertently. ? fhdm x : hsdma ch. x cause-of-interrupt flag in the dma interrupt cause flag register (d x /0x300281) ? to prevent an interrupt from being generated repeatedly for the same source, be sure to reset the cause-of- interrupt flag before setting up the psr again or executing the reti instruction. ? hsdma is given higher priority over idma (intelligent dma) and the cpu. however, since hsdma and idma share the same circuit, hsdma cannot gain the bus ownership while an idma transfer is under way. requests for hsdma invocation that have occurred during an idma transfer are kept pending until the idma transfer is completed. a request for idma invocation or an interrupt request that has occurred during a hsdma transfer are accepted after completion of the hsdma transfer. ? in dual-address mode, a0 ram (area 0 ), specific rom (area 1 ), and ivram (area 0 ) cannot be specified as the source or destination for dma transfer. while ivram (area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) can be used for dual-address transfer. ? in single-address mode, a0 ram (area 0 ), specific rom (area 1 ), area 2 , ivram (area 0 or area 3 ), dst ram (area 3 ) and the internal peripheral i/o registers (area 6 ) cannot be used for dma transfer. ? single-address mode does not allow data transfer between memory devices. an external logic circuit is required to perform single-address transfer between memory devices. ? single-address mode does not support the external memory area that is configured for sdram. ? be sure to disable the hsdma before setting the chip in sleep mode (executing the slp instruction). halt mode can be set even if the hsdma is enabled. intelligent dma (idma) ? the control information must be placed in dst ram (area 3 ) or an external ram. area 0 (a0 ram) and area 2 cannot be used for idma transfer and storing control information. ? the address you set in the idma base address registers must always be 4 -word units boundary address. ? be sure to disable dma transfers (idmaen (d0/0x301105 ) = 0 ) before setting the base address. writing to the idma base address register is ignored when the dma transfer is enabled (idmaen (d 0 / 0 x 301105 ) = 1 ). when the register is read, the read data is indeterminate. ? idmaen : idma enable bit in the idma enable register (d0/0x301105) ? do not start an idma transfer and change the idma channel number simultaneously. when setting dchn[6:0] (d[6:0]/0x301104), write 0 to dstart (d7/0x301104). ? dchn[6:0] : idma channel number set-up bits in the idma start register (d[6:0]/0x301104) ? dstart : idma start control bit in the idma start register (d7/0x301104)
appendix e summary of precautions ap-e-2 epson s1c33e08 technical manual ? since the control information is placed in ram, it can be rewritten. however, before rewriting the content of this information, make sure that no dma transfer is generated in the channel whose information you are going to rewrite. ? since the c33 pe core performs look-ahead operations, do not specify another channel immediately after a software trigger has invoked a channel. ? be sure to disable the idma before setting the chip in sleep mode (executing the slp instruction). halt mode can be set even if the idma is enabled. sram controller (sramc) the bclk pin output clock will not be divided regardless of how the bclk divide-by ratio is set using bclk (d0/0x301500 ); it is always the same as the sramc_clk clock. ? bclk : bclk divide control bit in the bclk and setup time control register (d0/0x301500) sdram controller (sdramc) if the operating clock (sdclk) is stopped while the sdram is being accessed, a system failure may occur due to stoppage of the sdram operation in uncontrolled status. the following operations stop the sdclk, therefore, do not perform these operations when the sdram may be accessed. ? setting the s1c33e08 in sleep status ? switching the p21 port function from sdclk output to general-purpose input/output ? disabling the clock supply to the sdramc module besides the cpu, the dma controller (when dma transfer from/to the sdram is enabled) and the lcd controller (when sdram is configured as the vram for the lcdc) access the sdram. in this case, before performing an above operation, disable the dma transfer and the lcdc so that the sdram will not be accessed. clock management unit (cmu) ? the clock control registers ( 0 x 301 b 00 C 0 x 301 b 14 ) are write-protected. before these registers can be rewritten, write protection must be removed by writing data 0 x 96 to the clock control protect register ( 0 x 301 b 24 ). once write protection is removed, the clock control registers can be written to any number of times until the protect register is reset to other than 0 x 96 . note that since unnecessary rewriting of the clock control registers could lead to erratic system operation, the clock control protect register ( 0 x 301 b 24 ) should be set to other than 0 x 96 unless the clock control registers must be rewritten. ? when clock sources are changed, the clock control registers must be set so that the cmu is supplied with a clock from the selected clock source upon returning from sleep mode immediately after the change. otherwise, the chip may not restart after return from sleep mode. furthermore, note that the timer, which generates an oscillation stabilization wait time after the sleep mode is released, operates with the clock after switching over. be sure to use the correct clock frequency for calculating the wait time to be set to osctm[ 7:0] (d[15:8]/0x301b14 ) and tmhsp (d2/0x301b14). ? osctm[7:0] : osc oscillation stabilization-wait timer in the clock option register (d[15:8]/0x301b14) ? tmhsp : stabilization-wait timer high-speed mode select bit in the clock option register (d2/0x301b14) ? when sosc3 (d1/0x301b08 ) or sosc1 (d0/0x301b08 ) is set from 0 to 1 for initiating oscillation by the oscillator, a finite time is required until the oscillation stabilizes (e.g., 25 ms for osc3 and 3 seconds for osc 1 in the s1c33e08 ). to prevent erratic operation, do not use the oscillator-derived clock until the oscillation start time stipulated in the electrical characteristics table elapses. ? sosc3 : high-speed oscillation (osc3) on/off control bit in the system clock control register (d1/0x301b08) ? sosc1 : low-speed oscillation (osc1) on/off control bit in the system clock control register (d0/0x301b08) ? immediately after the pll is started by setting pllpowr (d 0 / 0 x 301 b 0 c) to 1 , an output clock stabilization wait time is required (e.g., 200 s in the s1c33e08 ). when the clock source for the system is switched over to the pll, allow for this wait time after the pll has turned on. ? pllpowr : pll on/off control bit in the pll control register (d0/0x301b0c)
appendix e summary of precautions s1c33e08 technical manual epson ap-e-3 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock ? the frequency multiplication rate of the pll that can be set depends on the upper-limit operating clock frequency ( 90 mhz) and the osc3 oscillation frequency. when setting the frequency multiplication rate, be sure not to exceed the upper-limit operating clock frequency. ? the pll can only be set up when the pll is turned off (pllpowr (d0/0x301b0 c) = 0 ) and the clock source is other than the pll (oscsel[ 1:0 ] (d[3:2]/0x301b08 ) = 0C2 ). if settings are changed while the system is operating with the pll clock, the system may operate erratically. ? oscsel[1:0] : osc clock select bits in the system clock control register (d[3:2]/0x301b08) ? even if the #reset pin is pulled low (= 0 ), the chip may not be reset unless supplied with a clock. to reset the chip for sure, #reset should be held low for at least 3 osc3 clock cycles. however, the input/output port pins will be initialized by reset regardless of whether the chip is supplied with a clock. ? the oscillation start time of the high-speed (osc3 ) oscillator circuit varies with the device used, board patterns, and operating environment. therefore, a sufficient time should be provided before the reset signal is deasserted. ? nmi cannot be nested. the cpu keeps nmi input masked out until the reti instruction is executed after an nmi exception occurred. ? when using the sscg, always set ssmcitm[3:0] (d[15:12]/0x301b10) to 0b0001. ? ssmcitm[3:0] : sscg macro interval timer setting bits in the sscg macro control register (d[15:12]/0x301b10) ? ssmcidt[3:0 ] (d[11:8]/0x301b10 ) must be set according to the pll output clock frequency as shown in table iii. 1.7.2.1. using the sscg with an improper setting may cause a malfunction of the ic. ? ssmcidt[3:0] : sscg macro maximum frequency change width setting bits in the sscg macro control register (d[11:8]/0x301b10) ? when the pll is off, the initial values and the written values cannot be read correctly from ssmcidt[3:0] (d[11:8]/0x301b10 ) and ssmcitm[3:0 ] (d[15:12]/0x301b10 ) since the source clock is not supplied from the pll (different values are read out). the correct values can be read out when the pll is on. ? a stabilized clock must be supplied to the sscg module when turning the sscg on and off. the following shows the operation procedure. to turn the sscg on to turn the sscg off 1 . turn the pll on. 1 . turn the sscg off. 2 . wait more than the pll stabilization time. 2 . turn the pll off. 3 . turn the sscg on. ? the ss modulation is effective only for the pll output clock, and is not performed for other source clocks. when the pll output clock is not used for the system clock, tur n the sscg off. interrupt controller (itc) ? in sleep mode, there is a time lag between input of an interrupt signal for wakeup and the start of the clock supply to the itc, so a delay will occur until the itc sets the cause-of-interrupt flag. therefore, no interrupt will occur if the interrupt signal is deasserted before the clock is supplied to the itc, as the cause-of-interrupt flag in the itc is not set. furthermore, additional time is needed for the cpu to accept the interrupt request from the itc, the cpu may execute a few instructions that follow the slp instruction before it starts the interrupt processing. the same problem may occur when the cpu wakes up from sleep mode by nmi. no interrupt will occur if the #nmi signal is deasserted before the clock is supplied, as the nmi flag is not set. ? if the cause of interrupt used to restart from the standby mode has been set to invoke the idma, the idma is started up by that interrupt. if an interrupt to be generated upon completion of idma is disabled at the setting of the idma side, no interrupt request is signaled to the cpu. therefore, the cpu remains idle until the next interrupt request is generated. ? as the c33 pe core function, the il allows interrupt levels to be set in the range of 0 to 15 . however, since the interrupt priority register in the itc consists of three bits, interrupt levels in each interrupt system can only be set for up to 8.
appendix e summary of precautions ap-e-4 epson s1c33e08 technical manual ? when the reset-only method is used to reset the cause-of-interrupt flag (by writing 1 ), if a read-modify-write instruction (e.g., bset, bclr, or bnot) is executed, the other cause-of-interrupt flags at the same address that have been set to 1 are reset by a write. this requires caution. in cases when the read/write method is used to reset the cause-of-interrupt flag (by writing 0 ), all cause-of-interrupt flags for which 0 has been written are reset. when a read-modify-write operation is performed, a cause of interrupt may occur between reads and writes, so be careful when using this method. the same applies to the set-only method and read/write method for the idma request and idma enable registers. ? after an initial reset, the cause-of-interrupt flags and interrupt priority registers all become indeterminate. to prevent unwanted interrupts or idma requests from being generated inadvertently, be sure to reset these flags and registers in the software application. ? to prevent another interrupt from being generated for the same cause again after generation of an interrupt, be sure to reset the cause-of-interrupt flag before enabling interrupts and setting the psr again or executing the reti instruction. ? there is a time lag between latching the interrupt signal and latching the interrupt vector and level signals caused by the interface specifications between the cpu and the itc. 1 . the cpu latches the interrupt signal sent from the itc. 2 . the cpu latches the interrupt vector and level signals sent from the itc. 3 . the cpu executes the interrupt handler. an illegal interrupt exception (vector no. 11 ) occurs when a register related to the interrupt signal (itc s interrupt enable and cause-of-interrupt flag registers) is altered before the cpu latches the interrupt vector and level signals (between steps 1 and 2). therefore, it is very rare but an illegal interrupt exception may occur if an interrupt related register is altered when interrupts to the cpu are in enabled status (ie bit in psr = 1). however, the illegal interrupt exception that occurs does not affect the program execution if any processing is not performed in the exception handler. to avoid an illegal interrupt exception occurring, disable interrupts to the cpu (set ie bit in psr = 0 ) before altering an interrupt related register. real-time clock (rtc) ? the contents of all rtc control registers are indeterminate when power is turned on and are not initialized to specific values by initial reset. be sure to initialize these registers in software. ? while 1 is being carried over to the next-digit counter, the correct counter value may not be read out. moreover, attempting to write to the counters or other control registers may corrupt the counter value. therefore, do not write to the counters while 1 is being carried over. for the correct method of operation, see section iii. 3.3.5, counter hold and busy flag, and section iii.3.3.6, reading from and writing to counters in operation. ? note that rewriting rtc 24 h (d 4 / 0 x 301908 ) to switch between 12 -hour mode and 24 -hour mode may corrupt the count data for hours, days, months, years, or days of the week. therefore, after changing the rtc 24h (d4/0x301908 ) setting, be sure to set data in these counters back again. ? rtc24h : 24h/12h mode select bit in the rtc control register (d4/0x301908) ? avoid the settings below that may cause timekeeping errors. - settings exceeding the effective range do not set count data exceeding 60 seconds, 60 minutes, 12 or 24 hours, 31 days, 12 months, or 99 years. - settings nonexistent in the calendar do not set nonexistent dates such as april 31 or february 29, 2006 . even if such settings are made, the counters operate normally, so that when 1 is carried over from the hour counter to the 1 -day counter, the day counter counts up to the first day of the next month. (for april 31 , the day counter counts up to may 1; for february 29, 2006, the day counter counts up to march 1, 2006.)
appendix e summary of precautions s1c33e08 technical manual epson ap-e-5 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock ? the contents of all rtc interrupt control bits are indeterminate when power is turned on, and are not initialized to specific values by initial reset. after power-on, be sure to set rtcien (d 0 / 0 x 301904 ) to 0 (interrupt disabled) for preventing the occurrence of unwanted rtc interrupts. also be sure to write 1 to rtcirq (d0/0x301900) to reset it. ? rtcien : rtc interrupt enable bit in the rtc interrupt mode register (d0/0x301904) ? rtcirq : interrupt status bit in the rtc interrupt status register (d0/0x301900) ? immediately after the osc1 oscillator circuit is activated (as at power-on), a finite time (of about 3 seconds) is required for osc1 oscillation to stabilize. do not let the rtc start counting until this time elapses. misc registers ? the misc registers at addresses 0x300010C0x30001 a are write-protected. before the misc registers can be rewritten, write protection of these registers must be removed by writing data 0x96 to the misc protect register ( 0x300020 ). note that since unnecessary rewrites to addresses 0x300010C0x30001 a could lead to erratic system operation, the misc protect register ( 0x300020 ) should be set to other than 0x96 unless said misc registers must be rewritten. ? the low-drive control bit is disabled when the pin is used as the general-purpose i/o port (p xx). ? if the bus signals are forcibly driven low when the cpu is running by the instructions fetched from an external memory, the cpu will not be able to run after that point. to drive the signals low, the cpu must be running with the program stored in the internal ram. 16 -bit timers (t16) ? when setting the count clock or operation mode, make sure the 16 -bit timer is turned off. ? if a same value is set to the comparison data a and b registers, a hazard may be generated in the output signal. therefore, do not set the comparison registers as a = b. there is no problem when the interrupt function only is used. ? when using the output clock, set the comparison data registers as a 0 and b 1 . the minimum settings are a = 0 and b = 1 . in this case, the timer output clock cycle is the input clock 1/2. ? when the comparison data registers are set as a > b in normal mode, no comparison a interrupt is generated. in this case, the output signal is fixed at the off level. in fine mode, no comparison a interrupt is generated when the comparison data registers are set as a > 2 b + 1. ? after an initial reset, the cause-of-interrupt flag becomes indeterminate. to prevent generation of an unwanted interrupt or idma request, be sure to reset this flag and register in the software. ? to prevent another interrupt from being generated by the same cause of interrupt after an interrupt has occurred, be sure to reset the cause-of-interrupt flag before setting the psr again or executing the reti instruction. watchdog timer (wdt) ? when nmi or reset signal output by the watchdog timer is enabled, the watchdog timer must be reset within the set nmi/reset generation cycle. ? do not set a value equal to or less than 0x0000001 f in the comparison data register. ? depending on the counter and comparison register values, an nmi or reset signal may be generated after the nmi or reset function is enabled, or immediately after the watchdog timer starts. always be sure to set comparison data and reset the watchdog timer before writing 1 to nmien (d1/0x300662 ), resen (d0/ 0x300662 ), or runstp (d4/0x300662). ? nmien : watchdog timer nmi enable bit in the watchdog timer enable register (d1/0x300662) ? resen : watchdog timer reset enable bit in the watchdog timer enable register (d0/0x300662) ? runstp : watchdog timer run/stop control bit in the watchdog timer enable register (d4/0x300662)
appendix e summary of precautions ap-e-6 epson s1c33e08 technical manual general-purpose serial interface (efsio) ? before setting various serial-interface parameters, make sure the transmit and receive operations are disabled (txen x = rxen x = 0). ? txen x : serial i/f ch. x transmit enable bit in the serial i/f ch. x control register (d7/0x300b x 3) ? rxen x : serial i/f ch. x receive enable bit in the serial i/f ch. x control register (d6/0x300b x 3) ? when the serial interface is transmitting or receiving data, do not set txen x or rxen x to 0 , and do not execute the slp instruction. ? in clock-synchronized transfers, the mode of communication is half-duplex, in which the clock line is shared between the transmit and receive units. therefore, rxen x and txen x cannot be enabled simultaneously. ? after an initial reset, the cause-of-interrupt flags become indeterminate. to prevent generation of an unwanted interrupt or idma request, reset these flags in the program. ? if a receive error occurs, the receive-error interrupt and receive-buffer full interrupt causes occur simultaneously. however, since the receive-error interrupt has priority over the receive-buffer full interrupt, the receive-error interrupt is processed first. therefore, it is necessary to reset the receive-buffer full interrupt cause flag through the use of the receive-error interrupt processing routine. ? to prevent the regeneration of interrupts due to the same cause of interrupt following the occurrence of an interrupt, always be sure to reset the cause-of-interrupt flag before setting the psr again or executing the reti instruction. ? follow the procedure described below to initialize the serial interface. set irmd x [1:0] set smd x [1:0] other settings enable transmitting/receiving 00(normal i/f) or 10(irda i/f) transfer mode setting data format and clock selection internal division ratio, irda i/o logic and other settings enable transmitting, receiving or both figure e.1 serial interface initialize procedure ? when transmitting data in clock-synchronized master mode, transmit data is written to the transmit data register after the initial setting is performed following the flow above. however, the clock generated by the baud-rate timer must be supplied to the serial interface (at least one underflow has had to have occurred in the baud-rate timer) before this writing. otherwise, 0xff will be transmitted prior to the written data. ? the maximum transfer rate of the serial interface is limited to 8 mbps in clock-synchronized mode or 1 mbps in asynchronous mode. do not set a transfer rate (baud rate) t hat exceeds the limit. ? if the receive circuit is stopped during reception, set both transmission and reception to the disabled status. ? when performing data transfer in the clock-synchronized mode, the division ratio of the reload data for the baud-rate timer should be set so that the baud-rate is 1/4 of the system clock frequency or lower. ? when the transmit-enable bit txen x is set to 0 to disable transmit operations, the transmit data buffer (fifo) is cleared (initialized). similarly, when the receive-enable bit rxen x is set to 0 to disable receive operations, the receive data buffer (fifo) is cleared (initialized). therefore, make sure that the buffer does not contain any data waiting for transmission or reading before writing 0 to these bits. ? during irda receive operations, the rzi circuit recognizes low pulses by means of the signal edge (rising edge when irrl x = 0 ; falling edge when irrl x = 1). note that noise may cause a malfunction. ? irrl x : serial i/f ch. x irda i/f input logic inversion bit in the serial i/f ch. x irda register (d2/0x300b x 4)
appendix e summary of precautions s1c33e08 technical manual epson ap-e-7 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock serial peripheral interface (spi) ? be sure to use 32 -bit access instructions for reading/writing from/to the spi control registers (0x301700 to 0x30171 c). the spi control registers do not allow reading/writing using 16-bit and 8-bit access instructions. ? do not access the spi control register 1 (0x301708 ), spi control register 2 (0x30170 c), and spi wait register ( 0x301710) while the bsyf (d6/0x301714) is set to 1 (during data transfer). ? bsyf : transfer busy flag in the spi status register (d6/0x301714) ? to prevent malfunctions, write 0x0 to the spi interrupt control register (0x301718 ) to disable all the spi interrupt requests, before disabling the spi circuit (before se tting ena (d0/0x301708) to 0). ? ena : spi enable bit in the spi control register 1 (d0/0x301708) direction control serial interface (dcsio) ? be sure to use 32 -bit access instructions for reading/writing from/to the dcsio data load register (0x301804 ). transmit data for line a and line b must be written simultaneously. ? to prevent malfunctions, write 0x0 to the dcsio interrupt control register (0x301814 ) to disable all the dcsio interrupt requests, before disabling the dcsio circuit (before setting dcsioen (d 0 / 0 x 301800 ) to 0 ). ? dcsioen : dcsio enable bit in the dcsio control register (d0/0x301800) ? when using the dcsio ports as input/open-drain output ports (default configuration), be sure to enable the internal pull-up resistor (refer to section iii. 4.4, pin control registers ) or to connect an external pull-up resistor to the pin. card interface (card) ? the interface supports 16 -bit pc cards, such as ata (cf), lan (ethernet, wireless), or modem connected as an i/o card. sram cards, etc. are not supported. ? live or hot-line card insertion and removal are not supported. power must be turned off before inserting or removing a card. the automatic recognition of cards is also not supported. ? dma, zv, and cardbus are also not supported. ? to accommodate differences in power supply voltage between the pc card (5 v or 3.3 v) and the s1c33e08, use a buffer ic (e.g., s 1c37120). ? the ecc generator supports two data organization modes: 512-byte 8 -bit mode and 256 -word 16-bit mode. 256-byte 8-bit mode is not supported as it is a seldom-used feature. ? the card i/o signals must be connected to the d[15:0] pins when using the ecc function. ? eccrst (d0/0x300311) should be set before using the ecc function. ? eccrst : ecc circuit reset bit in the ecc reset/ready register (d0/0x300311) ? the eccen (d0/0x300312 ) should be set only while reading or writing card data. it should be disabled during command input, address input or status reading. ? eccen : ecc circuit enable bit in the ecc enable register (d0/0x300312) general-purpose i/o ports (gpio) ? after an initial reset, the cause-of-interrupt flags become indeterminate. to prevent generation of an unwanted interrupt or idma request, be sure to reset the flags in a program. ? to prevent regeneration of interrupts due to the same cause of interrupt following the occurrence of an interrupt, always be sure to reset the cause-of-interrupt flag before resetting the psr or executing the reti instruction. ? when using an port input interrupt as the trigger to restart from the sleep mode, an interrupt will occur due to the input signal level even if edge interrupt is specified as an interrupt condition. the signal level to restart the cpu is as follows according to the signal edge selected: if a rising-edge interrupt is set, the cpu restarts when the i nput signal goes to a high level. if a falling-edge interrupt is set, the cpu restarts when the input signal goes to a low level.
appendix e summary of precautions ap-e-8 epson s1c33e08 technical manual when a falling edge interrupt is selected to restart after the slp instruction is executed, the operation is as follows. if the interrupt port is already at a low level when the slp instruction is executed, the cpu enters sleep mode instantaneously and restarts immediately afterward. if the interrupt port is at a high level when the slp instruction is executed, the sleep mode continues until the port goes low. therefore, design the system assuming that the cpu can restart normally due to the signal level at the interrupt port, not an edge interrupt, when restarting the cpu from sleep mode using a port input interrupt. ? to use the p15Cp17 and p34Cp36 pins that are configured as the debug interface pins by default for general- purpose inputs/outputs, clear trcmux (d 0/0x300014) to 0. ? trcmux : p15C17, p34C36 debug function select bit in the debug port mux register (d0/0x300014) note, however, that the pc trace function of the debugger cannot be used when trcmux (d 0/0x300014 ) is set to 0. ? even if the port input interrupt condition is set to falling edge, the input pulse width must be longer than 1 cycle of the port operating clock (= mclk) to be certain an interrupt will be generated. a/d converter (adc) ? before setting the conversion mode, start/end channels, etc. for the a/d converter, be sure to disable ade (d2/0x300544 ). a change in settings while the a/d converter is enabled could cause it to operate erratically. ? ade : a/d enable bit in the a/d control/status register (d2/0x300544) ? in consideration of the conversion accuracy, we recommend that the a/d conversion clock be min. 16 khz to max. 2 mhz. ? do not start an a/d conversion when the clock supplied from the prescaler to the a/d converter is turned off, and do not turn off the prescaler's clock output when an a/d conversion is underway, as doing so could cause the a/d converter to operate erratically. ? after an initial reset, fade (d1/0x300287 ) and fadc (d0/0x300287 ) become indeterminate. to prevent generation of an unwanted interrupt or idma request, be sure to reset these flags in a program. ? fade : a/d conversion completion interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d1/0x300287) ? fadc : a/d out-of-range interrupt cause flag in the port input 4C7, rtc, a/d interrupt cause flag register (d0/0x300287) ? to prevent the regeneration of interrupts due to the same cause of interrupt following the occurrence an interrupt, always be sure to reset the cause-of-interrupt flag before setting the psr again or executing the reti instruction. ? when the a/d converter is set to enabled state, a current flows between av dd and v ss , and power is consumed, even when a/d operations are not performed. therefore, when the a/d converter is not used, it must be set to the disabled state (default 0 setting of ade (d2/0x300544)). ? when the 16 -bit timer 0 compare match b signal is used as a trigger factor, the division ratio of the prescaler in the 16-bit timer module must not be set to mclk/1. ? when using an external trigger to start a/d conversion, the low period of the trigger signal to be applied to the #adtrg pin must be two or more cpu operating clock cycles. furthermore, return the #adtrg input level to high within 20 cycles of the a/d input clock set. otherwise, it will be detected as the trigger for the next a/d conversion. ? software controllable pull-up resistors are provided for the input ports. disable the pull-up resistors of the ports used for analog inputs. ? when in break mode during icd-based debugging, the operating clock for the a/d converter is turned off due to the internal chip design. therefore, the a/d converter stops operating and registers cannot be accessed for write (but can be accessed for read).
appendix e summary of precautions s1c33e08 technical manual epson ap-e-9 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock lcd controller (lcdc) ? the lcdc clock supply cannot be stopped while the lcd displays a screen. before the lcdc clock supply can be stopped, the lcdc must enter power save mode. ? when using an stn panel, the registers for setting the hr-tft timing parameters must be set to 0x0. ? display addresses and positions are specified with a word boundary address or in word units, therefore the main window line address offset register (d[ 9:0]/0x301a74 ) must be set to a multiple of (32 bits bpp). depending on the lcd horizontal resolution and the bpp mode selected, it may be necessary to reserve a larger image area than the lcd panel resolution and set the appropriate line address offset even if the application does not need a lager image than the lcd panel to be displayed. for example, if the lcd width and image width are 240 pixels in 1-bpp mode, line address offset = 240 1 / 32 = 7.5 [words] in this case, mwladr[ 9:0 ] (d[9:0]/0x301a74 ) must be set to 8 . furthermore, the image must be prepared in 256 (8 32 ) pixels wide. ? mwladr[9:0] : main window line address offset bits in the main window line address offset register (d[9:0]/0x301a74) ? when a tft lcd panel is used with the s1c33e08 tft lcd interface selected (tftsel (d31/0x301a60) = 1 ), the vndpf flag (d7/0x301a04 ) may be fixed at 1 (vertical non-display period) in some rare cases depending on the timing. this means that the flag cannot normally indicate the vertical display and vertical non-display periods in the tft interface. ? tftsel : hr-tft panel select bit in the lcdc display mode register (d31/0x301a60) ? vndpf : vertical display status flag in the status and power save configuration register (d7/0x301a04) how to solve this problem for example, when the application needs to know a vertical non-display period to perform the following processing (switching the system clock in a vertical non-display period): (1 ) the system clock is 60 mhz (using the pll) and the tft lcd is displaying. (2 ) the program detects a vertical non-display period and switches the system clock to 12 mhz while keeping the tft lcd displayed. (3 ) the program sets the cpu to enter halt mode. to realize the above processing, use the following procedure to detect a vertical non-display period: (1 ) the system clock is 60 mhz (using the pll) and the tft lcd is displaying. (2 ) set the clock control register of a 16 -bit timer. (3 ) set the comparison data b setup register of the 16 -bit timer. (4 ) clear the 16-bit timer compare-match b interrupt flag. (5 ) detect the fpframe signal by reading the data register of the i/o port that has been configured for the fpframe output and run the 16 -bit timer when the fpframe signal is asserted (high level is detected when fpframe is configured to high active, or low level is detected when it is configured to low active). (6 ) detect that the 16 -bit timer compare-match b interrupt flag is set (it means that a vertical non-display period is detected). (7 ) switch the system clock to 12 mhz. (8 ) enter halt mode. use the following equation to calculate the comparison data b to be set to the 16-bit timer: 1 comparison data b = ((vdps + vdp) ht - vps) f t16 f fpshift f fpshift : lcdc fpshift clock frequency [hz] vdps: vertical display period start position (vdps = vdpscnt[ 9:0 ] [lines]) vdpscnt[9:0 ]: d[9:0]/0x301a24 vdp: vertical display period (vdp = vdpcnt[ 9:0] +1 [lines]) vdpcnt[9:0 ]: d[9:0]/0x301a14 ht: horizontal total period (ht = (htcnt[ 6:0] +1) 8 [ts]) htcnt[6:0 ]: d[22:16]/0x301a10 vps : vertical sync pulse start position (vps = fpfst[9:0] ht + fpfsto[9:0] [ts]) fpfst[9:0 ]: d[25:16]/0x301a2c fpfsto[ 9:0 ]: d[9:0]/0x301a30 f t16 : 16-bit timer x clock frequency [hz]
appendix e summary of precautions ap-e-10 epson s1c33e08 technical manual ? the lcdc does not support the frame interrupt (inten (d0/0x301a00 ), intf (d31/0x301a04 )) when tft interface is selected (tftsel (d 31/0x301a60) = 1). ? intf : frame interrupt flag in the status and power save configuration register (d31/0x301a04) ? inten : frame interrupt enable bit in the frame interrupt register (d0/0x301a00)
appendix f supplementary description for clock control s1c33e08 technical manual epson ap-f-1 i overview block pin power cpu map e char wiring mount ii hsdma idma sramc sdramc iii cmu itc rtc misc iv t16 wdt v efsio spi dcsio card i 2 s vi gpio egpio vii adc viii lcdc ivram ix usb x mp3 ap i/omap c33pe dev boot notes clock appendix f supplementary description for clock control notes on clock control ? use the gated clock control register 0 (0x301b00 ) and the gated clock control register 1 (0x301b04 ) to control the clock supply to the peripheral modules. ? the clocks must be supplied to operate the peripheral modules. ? the clocks are also required for accessing the control registers in the peripheral modules, in addition to operating the peripheral module. ? be aware that the default clock supply status (supplied or not supplied) is not the same for all peripheral modules (see the table below). list of clock control functions module rt c dma itc adc card efsio spi sramc gpio wdt dcsio i 2 s egpio t16 t16 t16 t16 t16 t16 lcdc misc efsio sramc gpio lcdc cpu lcdc lcdc lcdc lcdc sdramc sdramc sdramc sdramc usb usb control bit name r tcsapb_cke dma_cke itc_cke adc_cke card_cke efsiosapb_cke spi_cke sramsapb_cke gpio_cke wdt_cke dcsio_cke i2s_cke egpio_cke tm0_cke tm1_cke tm2_cke tm3_cke tm4_cke tm5_cke ivramarb_cke misc_hcke efsiobr_hcke sramc_hcke gpionstp_hcke lcdcahb_hcke cpu ahb_hcke lcdc_cke lcdcsapb_cke lcdcahbif_cke dstram_cke sdsapb_cke sd aplcdc_cke sd apcpu_cke sd apcpu_hcke usb_cke usbsapb_cke function r tc sapb b us interf ace cloc k (mclk) supply control dma controller cloc k (mclk) supply control itc cloc k (mclk) supply control a/d con ve r ter cloc k (mclk) supply control card interf ace cloc k (mclk) supply control efsio sapb b us interf ace cloc k (mclk) supply control spi cloc k (mclk) supply control sramc sapb b us interf ace cloc k (mclk) supply control gpio cloc k (mclk) supply control w atchdog timer cloc k (mclk) supply control dcsio cloc k (mclk) supply control i 2 s interf ace cloc k (mclk) supply control egpio cloc k (mclk) supply control 16-bit timer 0 cloc k (mclk) supply control 16-bit timer 1 cloc k (mclk) supply control 16-bit timer 2 cloc k (mclk) supply control 16-bit timer 3 cloc k (mclk) supply control 16-bit timer 4 cloc k (mclk) supply control 16-bit timer 5 cloc k (mclk) supply control ivram arbiter cloc k (mclk) supply control misc register cloc k (mclk) supply control in hal t mode efsio baud-rate timer cloc k (mclk) supply control in hal t mode sramc cloc k (mclk) supply control in hal t mode gpio input/interr upt circuit cloc k (mclk) supply control in hal t mode lcdc_ahb b us cloc k (mclk) supply control in hal t mode cpu_ahb b us cloc k (mclk) supply control in hal t mode lcdc module cloc k (lcdc_clk) supply control ? 1 lcdc sapb b us interf ace cloc k (mclk) supply control ? 1 lcdc_ahb b us interf ace cloc k (mclk) supply control ? 1 area 3 dst ram cloc k (mclk) supply control sdramc sapb b us interf ace cloc k (mclk) supply control sdramc lcdc_ahb b us interf ace cloc k (mclk) supply control sdramc cpu_ahb b us interf ace cloc k (mclk) supply control sdramc cpu_ahb b us interf ace cloc k (mclk) supply control in hal t mode usb module cloc k (osc3 = 48mhz) supply control usb sapb b us interf ace cloc k (mclk) supply control address : bit 0x301b04 : d0 0x301b04 : d1 0x301b04 : d2 0x301b04 : d3 0x301b04 : d4 0x301b04 : d5 0x301b04 : d6 0x301b04 : d7 0x301b04 : d8 0x301b04 : d9 0x301b04 : d10 0x301b04 : d11 0x301b04 : d12 0x301b04 : d13 0x301b04 : d14 0x301b04 : d15 0x301b04 : d16 0x301b04 : d17 0x301b04 : d18 0x301b04 : d19 0x301b04 : d24 0x301b04 : d25 0x301b04 : d26 0x301b04 : d27 0x301b04 : d28 0x301b04 : d29 0x301b00 : d0 0x301b00 : d1 0x301b00 : d2 0x301b00 : d3 0x301b00 : d4 0x301b00 : d5 0x301b00 : d6 0x301b00 : d7 0x301b00 : d8 0x301b00 : d9 ? 1: these bits must be set to 1 when s witching ivram to/from a0ram (see ne xt page).
appendix f supplementary description for clock control ap-f-2 epson s1c33e08 technical manual clock control when relocating the ivram (a 0ram) area the ivram, which is located in area 3 as the display memory for the lcdc by default, can be relocated to area 0 to use it as a0ram by setting the control bit in the lcdc module. the lcdc module clocks must be supplied when relocating the i vram even if the lcdc module is not used. the following shows the procedure to relocate the ivram from area 3 to area 0. 1 . enabling clock supply to the lcdc module before iram (d 0/0x301a64 ) can be accessed, set the control bits listed below to 1 to supply the clocks to the lcdc module. ? lcdc_cke : lcdc main clock control bit in the gated clock control register 0 (d0/0x301b00) ? lcdcsapb_cke : lcdc sapb bus interface clock control bit in the gated clock control register 0 (d1/0x301b00) ? lcdcahbif_cke : lcdc ahb bus interface clock control bit in the gated clock control register 0 (d2/0x301b00) these bits are set to 1 by default. 2 . relocating area 3 (ivram) to area 0 (a0ram) use the control bit iram (d 0/0x301a64) in the lcdc module to relocate the ivram. ? iram : iram assignment bit in the iram select register (d0/0x301a64) set iram (d 0/0x301a64) to 1 to relocate the ivram to area 0 (a0ram). iram = 0: ivram/area 3 (default) iram = 1 : a0ram/area 0 3 . disabling clock supply to the lcdc module set the control bits listed in step 1 to 0 to stop the clocks for the lcdc module. 4 . disabling clock supply to the ivram arbiter the ivram arbiter is not required when the ivram is used as the a 0 ram. set ivramarb_cke (d19/0x301b04) to 0 to stop the clock for the ivram arbiter. ? ivramarb_cke : ivram arbiter clock control bit in the gated clock control register 1 (d19/0x301b04) this bit is set to 1 by default.
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epson electronic devices website semiconductor operations division issue january, 2007 printed in japan b l technical manual s1c33e08 http://www.epson.jp/device/semicon_e document code: 410865100

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